Active voltage balancing device and control method thereof

Abstract

The application relates to an active voltage balancing device and a control method thereof. The device comprises: a connection node of a first capacitor and a second capacitor of a DC bus capacitor unit is a bus midpoint; a first switch tube and a second switch tube of a main power circuit are connected in series with an energy storage inductor between a positive end of a DC bus and a negative end of the DC bus, and the energy storage inductor and the second switch tube are connected to the bus midpoint; a voltage sampling circuit is connected to the positive end of the DC bus, the bus midpoint and the negative end of the DC bus, and an input end of a differential operational amplifier is connected to an output end of a voltage dividing resistor network; an ADC input end of a controller is connected to an output end of the differential operational amplifier to receive a voltage sampling signal, and is connected to an output end of a current sampling circuit to receive a current sampling signal; and a driving circuit is connected between a PWM output end and control ends of the first switch tube and the second switch tube. The application can realize accurate balancing of capacitor voltage and has the ability of rapid dynamic response.

Description

Technical Field

[0001] This application relates to the field of power electronics technology, and in particular to active voltage balancing devices and their control methods. Background Technology

[0002] In high-voltage DC bus applications, the withstand voltage of a single capacitor is often insufficient to meet system requirements. Therefore, a topology of two or more capacitors connected in series is typically used to improve the overall withstand voltage capability of the DC bus. However, due to unavoidable capacitance deviations (tolerance) and differences in equivalent series resistance (ESR) during the manufacturing process, an imbalance occurs in the voltage distribution on the DC bus among the series-connected capacitors. This means that one capacitor experiences a voltage higher than its rated value, while another experiences a voltage lower than its rated value. This voltage imbalance can cause a series of problems: capacitors subjected to overvoltage age faster and have a shorter lifespan; in severe cases, it may lead to capacitor breakdown, which in turn can cause cascading failures such as overvoltage damage to the main switching transistor, seriously affecting the safe and reliable operation of the system.

[0003] To address the aforementioned voltage equalization problem of series capacitors, existing technologies mainly employ the following two solutions: The first is a passive voltage equalization scheme, where a voltage equalization resistor is connected in parallel across each series capacitor. The resistor's bypass effect dissipates the voltage difference between the capacitors, thus balancing their voltages. This scheme has a simple circuit structure and low cost, but it has significant drawbacks: the voltage equalization resistor continuously consumes power, especially under light load conditions, resulting in a high proportion of losses and reduced overall system efficiency. Furthermore, passive voltage equalization is an open-loop control method, unable to handle voltage imbalances caused by differences in capacitor parameters (tolerance, ESR), resulting in almost zero dynamic response capability. The second solution is a simple active voltage equalization scheme, which clamps the capacitor voltage by controlling an auxiliary switch with a fixed duty cycle. This solution improves the voltage equalization effect to some extent compared to passive voltage equalization, but it still has the following shortcomings: the fixed duty cycle control cannot track the voltage imbalance caused by load changes and input voltage fluctuations, and is prone to over-compensation or under-compensation; the voltage equalization circuit is separated from the main converter control, and the influence of the main circuit switching state on the capacitor voltage is not considered, resulting in a delayed voltage equalization response; it lacks fault diagnosis function, does not monitor capacitor undervoltage faults, and cannot provide timely protection when the voltage of a capacitor exceeds the safety threshold.

[0004] In view of this, there is an urgent need to propose an active voltage balancing device and its control method to solve the defects of the existing DC bus series capacitor voltage equalization scheme of BUCK-BOOST converter, such as low efficiency, poor dynamic response, poor coordination with the main circuit and lack of fault protection. The device should achieve accurate capacitor voltage equalization, have rapid dynamic response capability, and realize the circuit fault protection function. Summary of the Invention

[0005] To overcome the problems existing in related technologies, this application provides an active voltage balancing device and its control method. The active voltage balancing device and its control method can solve the defects of the existing BUCK-BOOST converter DC bus series capacitor voltage equalization scheme, such as low efficiency, poor dynamic response, poor coordination with the main circuit, and lack of fault protection. It can achieve precise capacitor voltage equalization, has rapid dynamic response capability, and realize the circuit fault protection function.

[0006] The first aspect of this application provides an active voltage balancing device, comprising: The DC bus capacitor unit, main power circuit, voltage sampling circuit, current sampling circuit, controller and drive circuit are electrically connected to each other; The DC bus capacitor unit includes a first capacitor and a second capacitor connected in series between the positive terminal and the negative terminal of the DC bus, and the connection node between the first capacitor and the second capacitor is the midpoint of the bus. The main power circuit includes a first switching transistor, a second switching transistor, and an energy storage inductor; the first switching transistor and the second switching transistor are connected in series between the positive terminal and the negative terminal of the DC bus through the energy storage inductor, and the connection node between the energy storage inductor and the second switching transistor is connected to the midpoint of the bus. The voltage sampling circuit includes a voltage divider resistor network and a differential operational amplifier. The voltage divider resistor network is connected to the positive terminal, the midpoint of the DC bus, and the negative terminal of the DC bus. The input terminal of the differential operational amplifier is connected to the output terminal of the voltage divider resistor network. The current sampling circuit is used to collect the current of the energy storage inductor and output the current sampling signal; The controller's ADC input is connected to the output of the differential operational amplifier to receive voltage sampling signals, and to the output of the current sampling circuit to receive current sampling signals. The controller's PWM output is used to output PWM control signals. The driving circuit is connected between the PWM output terminal and the control terminals of the first and second switching transistors, and is used to drive the first and second switching transistors according to the PWM control signal.

[0007] In one embodiment, the voltage sampling circuit further includes: The voltage divider resistor network includes at least one first voltage divider resistor connected between the positive terminal of the DC bus and the midpoint of the bus, and at least one second voltage divider resistor connected between the midpoint of the bus and the negative terminal of the DC bus. The non-inverting and inverting inputs of the differential operational amplifier are connected to the corresponding nodes of the first and second voltage divider resistors, respectively, to convert the voltage divided signal into a differential sampling voltage signal and output it to the controller.

[0008] In one embodiment, the driving circuit includes: a first isolation driving chip, a second isolation driving chip, and a driving power transformer; The input terminal of the first isolation driver chip is connected to the first PWM output terminal of the controller, and the output terminal of the first isolation driver chip is connected to the control terminal of the first switching transistor. The input terminal of the second isolation driver chip is connected to the second PWM output terminal of the controller, and the output terminal of the second isolation driver chip is connected to the control terminal of the second switching transistor. The drive power transformer is used to provide operating power to the first isolation drive chip and the second isolation drive chip.

[0009] In one embodiment, the active voltage balancing device further includes a fault protection circuit, which includes a first voltage comparator and a second voltage comparator. The non-inverting and inverting inputs of the first voltage comparator receive the first reference voltage and the positive bus sampling voltage output by the current sampling circuit, respectively. The output of the first voltage comparator is connected to the controller. The non-inverting and inverting inputs of the second voltage comparator receive the second reference voltage and the negative bus sampling voltage output by the voltage sampling circuit, respectively. The output of the second voltage comparator is connected to the controller. The controller is used to perform protection actions based on the output signals of the first voltage comparator and / or the second voltage comparator.

[0010] A second aspect of this application provides a control method for an active voltage balancing device, characterized in that the method for controlling the active voltage balancing device as described in the first aspect includes: The first voltage of the first capacitor and the second voltage of the second capacitor are collected by the voltage sampling circuit, and the current value flowing through the energy storage inductor is collected by the current sampling circuit. The voltage difference between the positive and negative busbars is determined based on the first voltage and the second voltage. The voltage difference between the positive and negative busbars is input into the voltage PI controller to generate a current reference value. The current reference value is compared with the current value and then input to the current PI controller to generate a PWM modulation signal; Based on the PWM modulation signal, the first and second switching transistors are controlled by the drive circuit to enable the main power circuit to transfer energy bidirectionally between the first and second capacitors, thereby achieving active voltage balance of the DC bus series capacitors.

[0011] In one embodiment, after acquiring the current value flowing through the energy storage inductor via a current sampling circuit, the method further includes: When the current value exceeds the first current threshold, the controller sets the PWM control signal to zero and turns off the first and second switching transistors.

[0012] In one embodiment, after acquiring the first voltage of the first capacitor and the second voltage of the second capacitor through the voltage sampling circuit, the method further includes: When the first voltage or the second voltage exceeds the voltage threshold, the controller performs a shutdown protection action.

[0013] In one implementation, the parameter tuning steps for the voltage PI controller and the current PI controller include: Disconnect the voltage loop, set the current reference value of the current PI controller to a fixed value, adjust the proportional coefficient of the current PI controller until the current waveform shows a slight overshoot, and then adjust the integral coefficient of the current PI controller until the current static error is zero. Close the voltage loop and set the target bus voltage. Adjust the proportional coefficient of the voltage PI controller until the bus voltage response speed meets the requirements. Then adjust the integral coefficient of the voltage PI controller until the static error of the bus voltage is zero.

[0014] A third aspect of this application provides an electronic device, comprising: Processor; and A memory that stores executable code, which, when executed by the processor, causes the processor to perform the method described above.

[0015] A fourth aspect of this application provides a non-transitory machine-readable storage medium having executable code stored thereon, which, when executed by a processor of an electronic device, causes the processor to perform the method described above.

[0016] The technical solution provided in this application may include the following beneficial effects: The active voltage balancing device and its control method provided in this application replace the traditional passive voltage equalization scheme with an active control strategy. By adjusting the PWM duty cycle in real time through a controller, the main power circuit bidirectionally transfers energy between the first and second capacitors, achieving precise voltage equalization of the capacitors. Simultaneously, it eliminates the continuous power loss of the voltage equalization resistors, significantly improving system efficiency. Furthermore, by employing a dual closed-loop control architecture with an outer voltage loop and an inner current loop, combined with voltage and current feedforward control, it can quickly respond to load changes and input voltage fluctuations, greatly improving the dynamic response speed and steady-state accuracy of the voltage equalization control. In addition, the voltage equalization control is deeply integrated with the main converter control, utilizing the main power circuit itself to achieve voltage equalization, eliminating the need for an additional independent voltage equalization converter. This results in a compact circuit structure and low cost. Moreover, the device is equipped with a fault protection circuit that can monitor the voltage state of the series capacitors in real time. In the event of overvoltage or overcurrent faults, it promptly executes protective actions to prevent device damage, improving the safety and reliability of the system.

[0017] In summary, this application can solve the defects of existing BUCK-BOOST converter DC bus series capacitor voltage equalization schemes, such as low efficiency, poor dynamic response, poor coordination with the main circuit, and lack of fault protection. It can achieve precise capacitor voltage equalization, has rapid dynamic response capability, and realize the circuit fault protection function.

[0018] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and do not limit this application. Attached Figure Description

[0019] The above and other objects, features and advantages of this application will become more apparent from the more detailed description of exemplary embodiments thereof in conjunction with the accompanying drawings, wherein the same reference numerals generally represent the same components in the exemplary embodiments thereof.

[0020] Figure 1 This is a schematic diagram of the circuit structure of the main power circuit in the active voltage balancing device shown in the embodiments of this application; Figure 2 This is a schematic diagram of the connection topology between the main power circuit and the DC bus capacitor unit of the active voltage balancing device shown in the embodiments of this application; Figure 3 This is a schematic diagram of the circuit structure for comparison and protection after current sampling in the active voltage balancing device shown in the embodiments of this application; Figure 4 This is a schematic diagram of the circuit structure of the drive circuit in the active voltage balancing device shown in the embodiments of this application; Figure 5 This is a schematic diagram of the first circuit structure of the voltage divider resistor network in the active voltage balancing device shown in the embodiments of this application; Figure 6 This is a schematic diagram of the second circuit structure of the voltage divider resistor network in the active voltage balancing device shown in the embodiments of this application; Figure 7 This is a schematic diagram of the circuit structure of the voltage sampling circuit and the fault protection circuit in the active voltage balancing device shown in the embodiments of this application; Figure 8 This is a schematic flowchart illustrating the control method of the active voltage balancing device shown in the embodiments of this application; Figure 9 This is a schematic diagram of the structure of an electronic device shown in an embodiment of this application. Detailed Implementation

[0021] Preferred embodiments of the present application will now be described in more detail with reference to the accompanying drawings. While preferred embodiments of the present application are shown in the drawings, it should be understood that the present application may be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided to make the present application more thorough and complete, and to fully convey the scope of the present application to those skilled in the art.

[0022] The terminology used in this application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. The singular forms “a,” “the,” and “the” used in this application and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used herein refers to and includes any or all possible combinations of one or more of the associated listed items.

[0023] It should be understood that although the terms "first," "second," "third," etc., may be used in this application to describe various information, this information should not be limited to these terms. These terms are only used to distinguish information of the same type from one another. For example, without departing from the scope of this application, first information may also be referred to as second information, and similarly, second information may also be referred to as first information. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0024] In high-voltage DC bus applications, the withstand voltage of a single capacitor is often insufficient to meet system requirements. Therefore, a topology of two or more capacitors connected in series is typically used to improve the overall withstand voltage capability of the DC bus. However, due to unavoidable capacitance deviations (tolerance) and differences in equivalent series resistance (ESR) during the manufacturing process, an imbalance occurs in the voltage distribution on the DC bus among the series-connected capacitors. This means that one capacitor experiences a voltage higher than its rated value, while another experiences a voltage lower than its rated value. This voltage imbalance can cause a series of problems: capacitors subjected to overvoltage age faster and have a shorter lifespan; in severe cases, it may lead to capacitor breakdown, which in turn can cause cascading failures such as overvoltage damage to the main switching transistor, seriously affecting the safe and reliable operation of the system.

[0025] To address the aforementioned voltage equalization problem of series capacitors, existing technologies mainly employ the following two solutions: The first is a passive voltage equalization scheme, where a voltage equalization resistor is connected in parallel across each series capacitor. The resistor's bypass effect dissipates the voltage difference between the capacitors, thus balancing their voltages. This scheme has a simple circuit structure and low cost, but it has significant drawbacks: the voltage equalization resistor continuously consumes power, especially under light load conditions, resulting in a high proportion of losses and reduced overall system efficiency. Furthermore, passive voltage equalization is an open-loop control method, unable to handle voltage imbalances caused by differences in capacitor parameters (tolerance, ESR), resulting in almost zero dynamic response capability. The second solution is a simple active voltage equalization scheme, which clamps the capacitor voltage by controlling an auxiliary switch with a fixed duty cycle. This solution improves the voltage equalization effect to some extent compared to passive voltage equalization, but it still has the following shortcomings: the fixed duty cycle control cannot track the voltage imbalance caused by load changes and input voltage fluctuations, and is prone to over-compensation or under-compensation; the voltage equalization circuit is separated from the main converter control, and the influence of the main circuit switching state on the capacitor voltage is not considered, resulting in a delayed voltage equalization response; it lacks fault diagnosis function, does not monitor capacitor undervoltage faults, and cannot provide timely protection when the voltage of a capacitor exceeds the safety threshold.

[0026] In view of this, this application proposes an active voltage balancing device and its control method to solve the defects of existing BUCK-BOOST converter DC bus series capacitor voltage equalization schemes, such as low efficiency, poor dynamic response, poor coordination with the main circuit, and lack of fault protection. It achieves accurate capacitor voltage equalization, has rapid dynamic response capability, and realizes circuit fault protection function.

[0027] The technical solutions of the embodiments of this application are described in detail below with reference to the accompanying drawings.

[0028] Please see Figures 1 to 7 The active voltage balancing device shown in the embodiments of this application may include: The system comprises an interconnected DC bus capacitor unit, a main power circuit, a voltage sampling circuit, a current sampling circuit, a controller, and a drive circuit. The DC bus capacitor unit includes a first capacitor and a second capacitor connected in series between the positive and negative terminals of the DC bus. The connection point between the first and second capacitors is the midpoint of the bus. Figure 2 ( Figure 1 The energy storage inductor L1, the first capacitor C1, and the second capacitor C2 are not shown. Figure 2 As shown in the supplementary illustration, the positive terminal of the first capacitor C1 (positive bus capacitor) is connected to the positive terminal of the DC bus (BUS+), the negative terminal of the first capacitor and the positive terminal of the second capacitor C2 (negative bus capacitor) are connected to the midpoint (M) of the bus, and the negative terminal of the second capacitor is connected to the negative terminal (BUS-) of the DC bus.

[0029] In this embodiment, the main power circuit can adopt a BUCK-BOOST converter topology, including a first switch Q5, a second switch Q12, and an energy storage inductor L1. The first terminal (collector) of the first switch Q5 is connected to the positive terminal (BUS+) of the DC bus, and the second terminal (emitter) of the first switch Q5 is connected to the first terminal (collector) of the second switch Q12 via the energy storage inductor L1. The second terminal (emitter) of the second switch Q12 is connected to the negative terminal (BUS-) of the DC bus. The connection node between the energy storage inductor L1 and the second switch Q12 (i.e., the common node between the second terminal of the energy storage inductor L1 and the collector of Q12) is connected to the midpoint M of the bus. In this embodiment, the first switch Q5 and the second switch Q12 are IGBTs (e.g., Infineon IKW40N120H3), but MOSFETs or other fully controllable switching devices can also be used.

[0030] Through the above connections, the main power circuit constitutes a BUCK-BOOST converter capable of bidirectional energy transfer between the first and second capacitors. The specific operating modes are as follows: In BUCK mode (energy transfer from the first capacitor to the second capacitor), the system operates in BUCK mode when the voltage of the first capacitor is higher than that of the second capacitor. In this mode, the first switch Q5 is controlled to turn on and off using PWM, while the second switch Q12 remains off. When the first switch Q5 is on, energy flows from the first capacitor through the first switch Q5, the energy storage inductor L1, and the midpoint M of the bus into the second capacitor, simultaneously storing energy in inductor L1. When Q5 is off, the energy storage inductor L1 continues to release energy to the second capacitor through the body diode of the second switch Q12. By adjusting the PWM duty cycle of the first switch Q5, the amount of energy transferred from the first capacitor to the second capacitor can be precisely controlled.

[0031] In BOOST mode (energy transfer from the second capacitor to the first capacitor), the system operates in BOOST mode when the voltage of the second capacitor is higher than that of the first capacitor. In this mode, the second switch Q12 is controlled to turn on and off using PWM, while the first switch Q5 remains off. When the second switch Q12 is on, energy flows from the second capacitor through the bus midpoint M, the energy storage inductor L1, and the second switch Q12, forming a loop to store energy in the energy storage inductor L1. When the second switch Q12 is off, the energy stored in the energy storage inductor L1 is released to the first capacitor through the body diode of the first switch Q5. By adjusting the PWM duty cycle of the second switch Q12, the amount of energy transferred from the second capacitor to the first capacitor can be precisely controlled.

[0032] Through the coordinated operation of the above-mentioned BUCK and BOOST modes, the dynamic deviation of the positive and negative bus capacitor voltages can be gradually converged to zero, thereby achieving active voltage balance of the DC bus series capacitors.

[0033] In this embodiment, the voltage sampling circuit includes a voltage divider resistor network and a differential operational amplifier U4 (including U4A and U4C). Figures 5 to 7 As shown, the voltage divider resistor network consists of multiple series resistors connected between the positive terminal and the midpoint of the DC bus, and between the midpoint and the negative terminal of the DC bus. Specifically, the positive bus side voltage divider resistor network includes resistors R255~R260 (i.e., at least one first voltage divider resistor, for example, a combination of 510kΩ / 1206 and 200kΩ / 1206 packages), and the negative bus side voltage divider resistor network includes resistors R288~R293 (i.e., at least one second voltage divider resistor, also a combination of 510kΩ / 1206 and 200kΩ / 1206 packages). The non-inverting and inverting inputs of the differential operational amplifier U4 (in this embodiment, a TI TL074 or upgraded model TL074C / TL074I) are connected to the corresponding nodes of the voltage divider resistor network, converting the voltage-divided high-voltage bus voltage signal into a low-voltage differential signal, which is then output to the ADC input of the controller.

[0034] In this embodiment, the current sampling circuit is used to acquire the current of the energy storage inductor and output a current sampling signal. For example... Figures 1 to 3 As shown, the current sampling circuit includes a current sensor CT2 (in this embodiment, a Hishik STB-25HA with a range of 25A can be used) to detect the current flowing through the energy storage inductor L1. The output of the current sensor CT2 is connected to the ADC input of the controller, sending the current sampling signal to the controller for current loop control.

[0035] In this embodiment, a driving circuit is connected between the PWM output terminal and the control terminals of the first and second switching transistors, and is used to drive the first and second switching transistors according to the PWM control signal. The driving circuit may include a first isolation driving chip U3, a second isolation driving chip U6, and a driving power transformer T5. The input terminal of the first isolation driving chip U3 is connected to the first PWM output terminal of the controller, and its output terminal is connected to the gate (control terminal) of the first switching transistor Q5. The input terminal of the second isolation driving chip U6 is connected to the second PWM output terminal of the controller, and its output terminal is connected to the gate (control terminal) of the second switching transistor Q12. The driving power transformer T5 (a high-frequency transformer, such as an EE13 core, with an inductance of 1mH and a turns ratio of 40:75:75) provides isolated operating power to the first isolation driving chip U3 and the second isolation driving chip U6. In this embodiment, the isolation driver chip can be a Toshiba TLP350 (D4-TP5, F package). The output of the driver power transformer T5 is rectified by rectifier diodes D9 and D11 and regulated by Zener diodes ZD79 and ZD82 before being supplied to the driver chip.

[0036] In this embodiment, the controller's ADC input is connected to the output of a differential operational amplifier to receive voltage sampling signals, and to the output of a current sampling circuit to receive current sampling signals. The controller's PWM output is used to output PWM control signals. A digital signal processor (DSP) can be used (e.g., a TI TMS320F28377SPTPS, 200MHz clock frequency, HLQFP-176 package), which integrates an ADC module and a PWM module. The controller receives voltage and current sampling signals through its ADC module and outputs two complementary PWM control signals with dead time to the drive circuit through its PWM module, achieving precise control of the first switch Q5 and the second switch Q12.

[0037] In some embodiments, the active voltage balancing device further includes a fault protection circuit, which includes: a first voltage comparator U7 (including U7C and U7D) and a second voltage comparator U17 (including U17C and U7B). In this embodiment, for example, a TI LM339 or an upgraded model LM339A / LM339B can be used. The non-inverting input terminal of the first voltage comparator U7 ( Figure 3 Pin 11 of the circuit receives the first reference voltage, and its inverting input is connected to the positive bus sampling voltage output by the current sampling circuit CT2 to achieve overcurrent protection; the non-inverting input of the second voltage comparator U17 ( Figure 7 pin 9) and inverting input ( Figure 7 Pin 7 of the first voltage comparator (U7) receives the second reference voltage and the output voltage (negative bus sampling voltage) of the voltage sampling circuit, respectively, to achieve overvoltage protection. The outputs of the first voltage comparator U7 and the second voltage comparator U17 are connected to the controller, which executes the corresponding protection action based on the comparison result.

[0038] Figure 8 This is a schematic flowchart illustrating the control method of the active voltage balancing device according to an embodiment of this application. Figure 8 As shown, in some embodiments, the control method for the active voltage balancing device may include: S801 acquires the first voltage of the first capacitor and the second voltage of the second capacitor through a voltage sampling circuit, and acquires the current value flowing through the energy storage inductor through a current sampling circuit. After the system is powered on, the control loop parameters are first initialized, including the initial values ​​of the proportional and integral coefficients of the voltage PI controller and the current PI controller. In this embodiment, the voltage loop can be disconnected first, the current reference value of the current PI controller can be set to a fixed value, the current waveform can be monitored through an oscilloscope or the internal observation variable of the controller, and the proportional coefficient of the current PI controller can be adjusted until the current waveform shows a slight overshoot (about 5%~10%). Then, the integral coefficient of the current PI controller can be adjusted until the current static error is zero. Then, the voltage loop is closed and the target bus voltage (i.e., the desired positive and negative bus voltage balance value) is set. The proportional coefficient of the voltage PI controller is adjusted until the bus voltage response speed meets the requirements (monitoring the response speed of the bus voltages V+ and V-). Then, the integral coefficient of the voltage PI controller can be adjusted until the bus voltage static error is zero. It should be noted that, due to the coupling relationship between the voltage outer loop and the current inner loop in this device, after completing the above preliminary tuning, a small amount of joint fine-tuning is still required to ensure the stability and dynamic performance when the inner and outer loops work together.

[0039] Furthermore, the first voltage V+ of the first capacitor (positive bus capacitor) and the second voltage V- of the second capacitor (negative bus capacitor) are acquired through a voltage sampling circuit, and the bridge arm current flowing through the energy storage inductor L1 is acquired through a current sampling circuit.

[0040] S802 determines the voltage difference between the positive and negative buses based on the first voltage and the second voltage. The controller calculates the voltage difference ΔV = V+ - V- based on the acquired first voltage V+ and second voltage V-. This voltage difference ΔV reflects the degree of voltage imbalance between the positive and negative bus capacitors. When ΔV is positive, it indicates that the positive bus voltage is too high; when ΔV is negative, it indicates that the negative bus voltage is too high. The control objective is to make ΔV approach zero.

[0041] S803, the voltage difference between the positive and negative busbars is input to the voltage PI controller to generate a current reference value. In this embodiment, the voltage PI controller in the controller can perform proportional-integral calculations on the voltage difference between the positive and negative busbars to generate a current reference value. The control objective of the outer voltage loop is to make the voltage difference ΔV between the positive and negative busbars converge to zero, and the output of the voltage PI controller serves as the reference input for the inner current loop.

[0042] S804: The current reference value is compared with the current value and then input to the current PI controller to generate a PWM modulation signal. In this embodiment, the current feedforward value can also be superimposed on the current reference value to generate a composite current reference value. The current feedforward value can be calculated based on the rate of change of the bus voltage or the rate of change of the load current. Its function is to predict changes in current demand in advance before the outer voltage loop responds, thereby accelerating the dynamic response process of the system. Then, the composite current reference value is compared with the current value to obtain the current error. The current error is input to the current PI controller for proportional-integral calculation to generate the initial PWM modulation signal.

[0043] To improve the response accuracy of the inner current loop, the voltage feedforward can be superimposed on the initial PWM modulation signal to form a composite PWM modulation signal as the final PWM modulation signal. The voltage feedforward can be calculated based on the rate of change of the DC bus voltage, and its function is to compensate for the influence of bus voltage fluctuations on the current loop control.

[0044] S805, based on the PWM modulation signal, controls the on / off state of the first and second switching transistors via a drive circuit. The controller's PWM module generates two complementary PWM control signals with dead time, which are isolated and amplified by the drive circuit to drive the first switching transistor Q5 and the second switching transistor Q12. By adjusting the PWM duty cycle, the magnitude and direction of bidirectional energy transfer between the first and second capacitors in the main power circuit are controlled, causing the dynamic difference between the positive bus voltage V+ and the negative bus voltage V- to gradually converge to zero, thus achieving active voltage balance of the DC bus series capacitors.

[0045] It is understandable that the above S801 to S805 can be executed periodically, and the control frequency is determined by the PWM switching frequency. The typical value setting range is 10kHz~50kHz, which enables the main power circuit to transfer energy bidirectionally between the first capacitor and the second capacitor, so as to achieve active voltage balance of the DC bus series capacitor.

[0046] In some embodiments, during each control cycle of the controller, the absolute value of the bridge arm current sampled by the current sampling circuit can be monitored in real time. When the current value exceeds a first current threshold, the controller sets the PWM control signal to zero and turns off the first and second switching transistors. Simultaneously, the integral terms of the voltage PI controller and the current PI controller are reset to zero to prevent inrush current during system restart after fault clearing. Additionally, during each control cycle of the controller, the first voltage V+ and the second voltage V- sampled by the voltage sampling circuit can be monitored in real time. When V+ or V- exceeds a preset overvoltage threshold, the controller executes shutdown logic, sets the PWM duty cycle to zero, turns off the first switching transistor Q5 and the second switching transistor Q12, and latches the fault status output through voltage comparators U7 and U17 in the fault protection circuit for reading by the host computer or maintenance personnel.

[0047] Furthermore, a hardware-level protection channel can be incorporated into the fault protection circuit. Voltage comparator U7 compares the current sampling signal with a first reference voltage. When the current exceeds a hardware-set threshold, the U7 output flips, directly pulling the PWM drive signal low via hardware logic, achieving nanosecond-level response hardware-based fast protection. Similarly, voltage comparator U17 compares the voltage sampling signal with a second reference voltage, implementing hardware-level overvoltage protection. This dual redundancy of software and hardware protection significantly improves the system's safety and reliability.

[0048] Corresponding to the aforementioned application function implementation method embodiments, this application also provides an electronic device and corresponding embodiments for executing a control method of an active voltage balancing device.

[0049] Figure 9 This is a schematic diagram of the structure of an electronic device shown in an embodiment of this application.

[0050] See Figure 9 The electronic device 1000 includes a memory 1010 and a processor 1020.

[0051] The processor 1020 can be a Central Processing Unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor can be a microprocessor or any conventional processor.

[0052] Memory 1010 may include various types of storage units, such as system memory, read-only memory (ROM), and permanent storage devices. ROM may store static data or instructions required by the processor 1020 or other modules of the computer. Permanent storage devices may be read-write storage devices. Permanent storage devices may be non-volatile storage devices that retain stored instructions and data even when the computer is powered off. In some embodiments, permanent storage devices use mass storage devices (e.g., magnetic or optical disks, flash memory) as permanent storage devices. In other embodiments, permanent storage devices may be removable storage devices (e.g., floppy disks, optical drives). System memory may be a read-write storage device or a volatile read-write storage device, such as dynamic random access memory. System memory may store some or all of the instructions and data required by the processor during operation. Furthermore, memory 1010 may include any combination of computer-readable storage media, including various types of semiconductor memory chips (DRAM, SRAM, SDRAM, flash memory, programmable read-only memory), and disks and / or optical disks may also be used. In some implementations, memory 1010 may include a removable storage device that is readable and / or writable, such as a laser disc (CD), a read-only digital multifunction optical disc (e.g., DVD-ROM, dual-layer DVD-ROM), a read-only Blu-ray disc, an ultra-high density optical disc, a flash memory card (e.g., SD card, mini SD card, Micro-SD card, etc.), a magnetic floppy disk, etc. Computer-readable storage media do not contain carrier waves or transient electronic signals transmitted wirelessly or via wired connections.

[0053] The memory 1010 stores executable code, which, when processed by the processor 1020, can cause the processor 1020 to execute part or all of the methods described above.

[0054] The solution of this application has been described in detail above with reference to the accompanying drawings. In the above embodiments, the descriptions of each embodiment have different emphases; for parts not described in detail in a certain embodiment, please refer to the relevant descriptions of other embodiments. Those skilled in the art should also understand that the actions and modules involved in the specification are not necessarily essential to this application. Furthermore, it is understood that the steps in the method of this application's embodiments can be adjusted, combined, and deleted according to actual needs, and the modules in the device of this application's embodiments can be combined, divided, and deleted according to actual needs.

[0055] Furthermore, the method according to this application can also be implemented as a computer program or computer program product, which includes computer program code instructions for performing some or all of the steps in the method described above.

[0056] Alternatively, this application may be implemented as a non-transitory machine-readable storage medium (or computer-readable storage medium, or machine-readable storage medium) storing executable code (or computer program, or computer instruction code) thereon, which, when executed by a processor of an electronic device (or electronic device, server, etc.), causes the processor to perform part or all of the steps of the methods described above according to this application.

[0057] Those skilled in the art will also understand that the various exemplary logic blocks, modules, circuits, and algorithm steps described in connection with the present application can be implemented as electronic hardware, computer software, or a combination of both.

[0058] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems and methods according to various embodiments of this application. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the blocks may occur in a different order than those marked in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, can be implemented using a dedicated hardware-based system that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions.

[0059] The various embodiments of this application have been described above. These descriptions are exemplary and not exhaustive, nor are they limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen to best explain the principles, practical application, or improvement of the technology in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. An active voltage balancing device, characterized in that, include: The DC bus capacitor unit, main power circuit, voltage sampling circuit, current sampling circuit, controller and drive circuit are electrically connected to each other; The DC bus capacitor unit includes a first capacitor and a second capacitor connected in series between the positive end and the negative end of the DC bus, and the connection node between the first capacitor and the second capacitor is the midpoint of the bus. The main power circuit includes a first switching transistor, a second switching transistor, and an energy storage inductor; the first switching transistor and the second switching transistor are connected in series between the positive terminal and the negative terminal of the DC bus through the energy storage inductor, and the connection node between the energy storage inductor and the second switching transistor is connected to the midpoint of the bus. The voltage sampling circuit includes a voltage divider resistor network and a differential operational amplifier. The voltage divider resistor network is connected to the positive terminal of the DC bus, the midpoint of the bus, and the negative terminal of the DC bus. The input terminal of the differential operational amplifier is connected to the output terminal of the voltage divider resistor network. The current sampling circuit is used to collect the current of the energy storage inductor and output a current sampling signal; The ADC input terminal of the controller is connected to the output terminal of the differential operational amplifier to receive voltage sampling signals, and is also connected to the output terminal of the current sampling circuit to receive current sampling signals. The PWM output terminal of the controller is used to output PWM control signals. The driving circuit is connected between the PWM output terminal and the control terminal of the first switch and the control terminal of the second switch, and is used to drive the first switch and the second switch according to the PWM control signal.

2. The active voltage balancing device according to claim 1, characterized in that, The voltage sampling circuit further includes: The voltage divider resistor network includes at least one first voltage divider resistor connected between the positive terminal of the DC bus and the midpoint of the bus, and at least one second voltage divider resistor connected between the midpoint of the bus and the negative terminal of the DC bus. The non-inverting and inverting input terminals of the differential operational amplifier are respectively connected to the corresponding nodes of the first and second voltage divider resistors to convert the voltage divided signal into a differential sampling voltage signal and output it to the controller.

3. The active voltage balancing device according to claim 1, characterized in that, The driving circuit includes: a first isolation driving chip, a second isolation driving chip, and a driving power transformer; The input terminal of the first isolation driver chip is connected to the first PWM output terminal of the controller, and the output terminal of the first isolation driver chip is connected to the control terminal of the first switching transistor. The input terminal of the second isolation driver chip is connected to the second PWM output terminal of the controller, and the output terminal of the second isolation driver chip is connected to the control terminal of the second switching transistor. The drive power transformer is used to provide operating power to the first isolation drive chip and the second isolation drive chip.

4. The active voltage balancing device according to claim 1, characterized in that, The device further includes a fault protection circuit, which includes a first voltage comparator and a second voltage comparator. The non-inverting input and inverting input of the first voltage comparator receive the first reference voltage and the positive bus sampling voltage output by the current sampling circuit, respectively, and the output of the first voltage comparator is connected to the controller. The non-inverting input and inverting input of the second voltage comparator receive the second reference voltage and the negative bus sampling voltage output by the voltage sampling circuit, respectively, and the output of the second voltage comparator is connected to the controller. The controller is used to perform protection actions based on the output signals of the first voltage comparator and / or the second voltage comparator.

5. A control method for an active voltage balancing device, characterized in that, For controlling the active voltage balancing device as described in claims 1-4, comprising: The first voltage of the first capacitor and the second voltage of the second capacitor are collected by the voltage sampling circuit, and the current value flowing through the energy storage inductor is collected by the current sampling circuit. The voltage difference between the positive and negative busbars is determined based on the first voltage and the second voltage. The voltage difference between the positive and negative busbars is input into the voltage PI controller to generate a current reference value; The current reference value is compared with the current value and then input to the current PI controller to generate a PWM modulation signal; According to the PWM modulation signal, the first and second switching transistors are controlled by the driving circuit to enable the main power circuit to transmit energy bidirectionally between the first and second capacitors, thereby achieving active voltage balance of the DC bus series capacitors.

6. The control method for the active voltage balancing device according to claim 5, characterized in that, After acquiring the current value flowing through the energy storage inductor via the current sampling circuit, the method further includes: When the current value exceeds the first current threshold, the controller sets the PWM control signal to zero and turns off the first and second switching transistors.

7. The control method for the active voltage balancing device according to claim 5, characterized in that, After acquiring the first voltage of the first capacitor and the second voltage of the second capacitor through the voltage sampling circuit, the method further includes: When the first voltage or the second voltage exceeds the voltage threshold, the controller performs a shutdown protection action.

8. The control method for the active voltage balancing device according to claim 5, characterized in that, The parameter tuning steps for the voltage PI controller and the current PI controller include: Disconnect the voltage loop, set the current reference value of the current PI controller to a fixed value, adjust the proportional coefficient of the current PI controller until the current waveform shows a slight overshoot, and then adjust the integral coefficient of the current PI controller until the current static error is zero. Close the voltage loop and set the target bus voltage. Adjust the proportional coefficient of the voltage PI controller until the bus voltage response speed meets the requirements. Then adjust the integral coefficient of the voltage PI controller until the static error of the bus voltage is zero.

9. An electronic device, characterized in that, include: processor; as well as A memory having executable code stored thereon, which, when executed by the processor, causes the processor to perform the method as described in any one of claims 5-8.

10. A non-transitory machine-readable storage medium, characterized in that, It stores executable code that, when executed by a processor of an electronic device, causes the processor to perform the method as described in any one of claims 5-8.

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