A power pin ESD protection circuit, protection method and full-bridge protection circuit of a half-bridge driving chip

Abstract

The application discloses a power pin ESD protection circuit of a half-bridge driving chip, a protection method and a full-bridge protection circuit, which comprises a power tube MNH1, a power tube MNL1, a high-end pre-driving, a jump detection module and an auxiliary starting module. The jump detection module is connected with a power supply VCC, detects the jump of the power supply VCC and outputs a jump driving signal ng2. The auxiliary starting module is connected with the power supply VCC, the jump detection module and the gate of the power tube MNL1, and obtains the jump driving signal ng2. The auxiliary starting module is externally connected with an input logic signal lson1 and an enable signal en. When the voltage of the power supply VCC suddenly increases, the jump detection module outputs the jump driving signal ng2 with a high level, and drives the power tube MNL1 to be turned on by using the auxiliary starting module. Meanwhile, the power supply VCC with the suddenly increased voltage is coupled to the gate of the power tube MNH1, and the power tube MNH1 is turned on. By the above scheme, the application has the advantages of simple structure, reliable protection and the like.

Description

Technical Field

[0001] This invention relates to the field of power management and motor drive chip technology, and in particular to an ESD protection circuit, protection method and full-bridge protection circuit for the power supply pins of a half-bridge drive chip. Background Technology

[0002] The power supply pin ESD protection circuit of the existing half-bridge driver chip is as follows: Figure 1 As shown, the VCC pin is the power supply pin, responsible for providing power to the half-bridge drive structure. The input logic signal hson1 drives the power transistor MNH1 to turn on and off through the high-side pre-drive module, and the input logic signal lson1 drives the power transistor MNL1 to turn on and off through the low-side pre-drive module. Here, power transistors MNH1 and MNL1 are connected to the output terminal out1, and output terminal out1 is connected to the drive load. The input logic signal hson1, input logic signal lson1, high-side pre-drive, low-side pre-drive, power transistors MNH1 and MNL1 are connected in sequence... Figure 1 When connected, they together form a half-bridge drive structure.

[0003] To address ESD (Electrostatic Discharge) events, in the ESD protection circuit of traditional half-bridge driver chips, an ESD protection device is connected between the VCC and GND pins. This device provides a discharge path for the VCC pin and protects the internal circuitry and half-bridge driver structure from ESD damage. These ESD protection devices are typically PNP ESD or GGMOS ESD devices. As the supply voltage of the driver chip increases, the withstand voltage of the ESD device also increases linearly. If a high ESD rating is required for the VCC pin, this ESD protection device, due to its high withstand voltage and high ESD rating requirements, needs to occupy a larger area of ​​the chip.

[0004] Therefore, there is an urgent need to propose a simple, safe and reliable ESD protection circuit, protection method and full-bridge protection circuit for the power supply pin of a half-bridge driver chip, which can eliminate the need for traditional ESD devices and enhance the ESD withstand voltage level of the VCC pin. Summary of the Invention

[0005] To address the aforementioned problems, the present invention aims to provide an ESD protection circuit, protection method, and full-bridge protection circuit for the power supply pins of a half-bridge driver chip. The technical solution adopted by the present invention is as follows: The first part of this technology provides an ESD protection circuit for the power supply pins of a half-bridge driver chip, including: power transistor MNH1, power transistor MNL1, and a high-side pre-drive; the source of power transistor MNH1 is connected to the drain of power transistor MNL1; the gate of power transistor MNH1 is externally connected to the high-side pre-drive via an input logic signal hson1, and the drain of power transistor MNH1 is externally connected to the power supply VCC, further including: The transition detection module is connected to the power supply VCC, detects the transition of the power supply VCC, and outputs the transition drive signal ng2. And an auxiliary power-on module, which is connected to the power supply VCC, the transition detection module, and the gate of the power transistor MNL1 to obtain the transition drive signal ng2; the auxiliary power-on module is externally connected to the input logic signal lson1 and the enable signal en; When the voltage of the power supply VCC suddenly increases, the jump detection module outputs a high-level jump drive signal ng2 and uses the auxiliary turn-on module to drive the power transistor MNL1 to turn on; at the same time, the voltage of the power supply VCC suddenly increases and couples the gate of the power transistor MNH1, and the power transistor MNH1 turns on.

[0006] Furthermore, the transition detection module includes a high-pass filter consisting of a capacitor C1 and a resistor R1 connected in series, a Zener diode D1 and a transistor MN4 connected in series with one end between the capacitor C1 and the resistor R1 and the other end grounded; the capacitor C1 is connected to the power supply VCC.

[0007] Further, the auxiliary power-on module includes PMOS transistor MP1, PMOS transistor MP2, NMOS transistor MN5, NMOS transistor MN3, NMOS transistor MN6, NMOS transistor MN7, NAND gate I1, inverter I2, inverter I3, and resistor R2; NAND gate I1, inverter I2, and inverter I3 are connected in series and then connected to the gate of PMOS transistor MP1 and the gate of NMOS transistor MN3; the NAND gate I1 is externally connected to the input logic signal lson1 and the enable signal en; the gates of PMOS transistor MP2, NMOS transistor MN5, and NMOS transistor MN6 are all connected between capacitor C1 and resistor R1; the gate of NMOS transistor MN7 is connected to the drain of PMOS transistor MP1 via resistor R2; PMOS transistor MP1, PMOS transistor MP2, NMOS transistor MN7, and NMOS transistor MN3 are connected sequentially; the gate of power transistor MNL1 is connected between PMOS transistor MP2 and NMOS transistor MN7.

[0008] The second part of this technology provides a power supply pin ESD protection method, which uses the power supply pin ESD protection circuit of the half-bridge driver chip for detection and protection. The protection method includes the following steps: When the voltage of the power supply VCC suddenly increases, the voltage of the power supply VCC that suddenly increases couples to the gate of the power transistor MNH1 and drives the power transistor MNH1 to turn on. Simultaneously, the jump detection module acquires the power supply VCC with a sudden voltage increase and outputs a high-level jump drive signal ng2, which drives the power transistor MNL1 to conduct using the auxiliary turn-on module; at the same time, the power transistors MNH1 and MNL1 conduct electrostatic discharge to the power supply VCC.

[0009] Thirdly, this technology provides a full-bridge protection circuit, which is equipped with two sets of ESD protection circuits for the power supply pins of the half-bridge driver chip.

[0010] Compared with the prior art, the present invention has the following beneficial effects: This invention replaces ESD devices and low-side pre-drive by incorporating a transition detection module and an auxiliary enable module. When the power supply VCC is subjected to a positive ESD pulse, the voltage of VCC rises rapidly. The transition detection module detects the VCC transition and outputs a high-level transition drive signal ng2 to the auxiliary enable module. The auxiliary enable module then outputs a high-level ng1 signal, turning on the source and drain of power transistor MNL1. Simultaneously, the rapid rise in VCC voltage couples to the gate of power transistor MNH1, causing it to turn on. Thus, power transistors MNH1 and MNL1 are simultaneously turned on, providing an electrostatic discharge path to the VCC pin. Furthermore, the strong self-protection capabilities of power transistors MNH1 and MNL1 significantly enhance the ESD protection level of the VCC pin, improving chip reliability. Attached Figure Description

[0011] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation on the scope of protection. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0012] Figure 1 This is a schematic diagram of the ESD protection circuit for the power supply pins of a half-bridge driver chip in the prior art.

[0013] Figure 2 This is a schematic diagram illustrating the protection principle of the present invention.

[0014] Figure 3This is a schematic diagram of the specific circuit structure for ESD protection in this invention.

[0015] Figure 4 for Figure 3 Waveform diagram of key nodes in the process.

[0016] Figure 5 This is a schematic diagram of the ESD protection principle for the VCC pin of the full-bridge circuit in this invention. Detailed Implementation

[0017] To make the objectives, technical solutions, and advantages of this application clearer, the present invention will be further described below with reference to the accompanying drawings and embodiments. The embodiments of the present invention include, but are not limited to, the following embodiments. All other embodiments obtained by those skilled in the art based on the embodiments in this application without inventive effort are within the scope of protection of this application.

[0018] In this embodiment, the term "and / or" is merely a description of the relationship between related objects, indicating that there can be three relationships. For example, A and / or B can represent three situations: A exists alone, A and B exist simultaneously, and B exists alone.

[0019] The terms "first" and "second," etc., used in the specification and claims of this embodiment are used to distinguish different objects, not to describe a specific order of objects. For example, "first target object" and "second target object," etc., are used to distinguish different target objects, not to describe a specific order of target objects.

[0020] In the embodiments of this application, the terms "exemplary" or "for example" are used to indicate that something is an example, illustration, or description. Any embodiment or design that is described as "exemplary" or "for example" in the embodiments of this application should not be construed as being more preferred or advantageous than other embodiments or design. Specifically, the use of the terms "exemplary" or "for example" is intended to present the relevant concepts in a specific manner.

[0021] In the description of the embodiments in this application, unless otherwise stated, "multiple" means two or more. For example, multiple processing units means two or more processing units; multiple systems means two or more systems.

[0022] like Figures 2 to 5As shown, this embodiment provides a power pin ESD protection circuit for a half-bridge driver chip, including power transistors MNH1 and MNL1, a high-side pre-drive, a transition detection module, and an auxiliary enable module. The power pin ESD protection circuit detects a positive ESD pulse on the VCC pin (i.e., power supply VCC) and turns on power transistor MNL1. Due to the presence of its gate-drain parasitic capacitance CGD, a positive transition of VCC will cause the gate voltage of power transistor MNH1 to rise and conduct through the CGD capacitor coupling. This embodiment utilizes the simultaneous conduction of power transistors MNL1 and MNH1 to provide an ESD current discharge path. In this embodiment, since the on-resistance of power transistors MNH1 and MNL1 is generally between tens of mΩ and hundreds of mΩ, their self-protection capability can often pass tests at levels above HBM6KV. Therefore, this embodiment eliminates the need for ESD devices while significantly enhancing the ESD rating of the VCC pin. It should also be noted that the high-side pre-drive in this embodiment is an existing mature circuit and will not be described in detail here.

[0023] like Figure 2 As shown, when the power supply VCC is subjected to a positive ESD pulse, the voltage of VCC rises rapidly. The transition detection module detects the VCC transition and outputs a high-level transition drive signal ng2 to the auxiliary turn-on module. The auxiliary turn-on module then outputs a signal ng1 to turn on the power transistor MNL1. Normally, the transition drive signal ng2 is low. When VCC rises rapidly, it couples to the gate of the power transistor MNH1, causing MNH1 to turn on. Both power transistors MNH1 and MNL1 will be turned on simultaneously, providing an electrostatic discharge path to the VCC pin.

[0024] In this embodiment, after the driver chip is powered on normally, the input enable signal en will change from low to high. The auxiliary enable module will normally receive the input logic signal lson1 to control the switching of the power transistor MNL1. Therefore, this embodiment can eliminate the need for ESD devices and improve the ESD withstand voltage level of the VCC pin through the strong self-protection capabilities of the power transistors MNH1 and MNL1.

[0025] exist Figure 3 In the middle, the vdrv terminal is responsible for providing power to the gate drive of the power transistor MNL1. The input enable signal en is the power-on enable signal. After VCC is powered on and stabilized, the input signal en changes from low level to high level after a delay time. That is, the input enable signal en changing from low level to high level indicates that VCC is powered on.

[0026] The transition detection module in this embodiment consists of capacitor C1, resistor R1, Zener diode D1, and transistor MN4. Capacitor C1 and resistor R1 form a high-pass filter. One end of capacitor C1 is connected to one end of resistor R1, simultaneously outputting the ng2 signal to the auxiliary turn-on module. The rising edge transition of VCC will couple through capacitor C1, causing the ng2 node voltage to rise. Zener diode D1 is used to clamp the ng2 node voltage, preventing it from exceeding the gate voltage limit of transistor MN5. Transistor MN4 is used to pull the ng2 node voltage to ground after VCC power-on is complete (i.e., the en signal changes from low to high), to prevent VCC transitions from affecting the normal turn-on and turn-off of power transistor MNL1.

[0027] Additionally, the auxiliary power-on module consists of NAND gate I1, inverters I2 and I3, PMOS transistors MP1 and MP2, NMOS transistors MN5, MN3, MN6, and MN7, and resistor R2. PMOS transistors MP1 and MP2 are both N-well PMOS transistors, with their sources and wells connected. Furthermore, the drain of PMOS transistor MP1 is connected to the drive power supply Vdrv, the sources of PMOS transistors MP1 and MP2 are connected, and the drain of PMOS transistor MP2 is connected to the gate of power transistor MNL1.

[0028] In this embodiment, when VCC jumps upward, the gate of PMOS transistor MP2 goes high, causing MP2 to be in the off state. This prevents the branches containing PMOS transistors MP1 and MP2 from conducting, thus clamping the gate of power transistor MNL1 at a lower voltage level. When the voltage at node ng2 increases, transistor MN6 turns on and pulls the gate of transistor MN7 to ground, causing MN7 to be in the off state. This prevents the branches containing transistors MN7 and MN3 from conducting, thus clamping the gate of power transistor MNL1 at a lower voltage level.

[0029] When the voltage ng2 increases, transistor MN5 turns on. The subsequent conduction of MN5 charges the gate of power transistor MNL1, turning it on as well. Due to its gate-drain parasitic capacitance CGD, when VCC rises rapidly, it couples to the gate of power transistor MNH1 through CGD, causing MNH1 to turn on. Thus, both power transistors MNL1 and MNH1 are turned on simultaneously, providing an ESD discharge path for the VCC pin.

[0030] In this embodiment, the transition time of VCC under a positive ESD pulse is within a few hundred ns, while the power-on time of the VCC pin during normal operation is on the order of milliseconds. Therefore, it is necessary to design the values ​​of C1 and R1 reasonably so that the rapid transition of VCC triggering ESD can be detected and the power transistor MNL1 can be turned on, while avoiding the detection of a slow rise in VCC and the accidental turning on of the power transistor MNL1.

[0031] Set the rise rate of the VCC pin to SR. SR represents the rate of change of the VCC pin voltage over time, and its expression is: SR = dvcc / dt; Additionally, SR_F is set as the rapid rate of change when the VCC pin is subjected to a positive ESD pulse, and SR_L is set as the slow rate of change when the VCC pin is powered on.

[0032] In order for transistor MN5 and power transistor MNL1 to be turned on simultaneously when VCC is subjected to a positive pulse, the following condition must be met: SR_F*C1*R1>(VGS_MN5+VGS_MNL1); Where C1 represents the capacitance value of capacitor C1, R1 represents the resistance value of resistor R1, VGS_MN5 represents the gate-source drive voltage of transistor MN5, and VGS_MNL1 represents the gate-source drive voltage of power transistor MNL1.

[0033] Meanwhile, to avoid the misleading turn-on of transistor MN5 and power transistor MNL1 caused by slow power-up, it is necessary to satisfy: SR_L*C1*R1<(VTH_MN5+VTH_MNL1); Where VTH_MN5 represents the threshold voltage of transistor MN5, and VTH_MNL1 represents the threshold voltage of power transistor MNL1.

[0034] Here, after VCC is powered on, the input signal en will change from low to high. Transistor MN4 will turn on the gate of transistor MN5 to ground, turning it off.

[0035] like Figure 4 As shown, when the input signal en is low, the output of NAND gate I1 is high, and the output of inverters I2 and I3 is also high. When the input signal en is high, the input signal lson1 can drive the power transistor MNL1 to turn on and off through NAND gate I1, inverter I2, inverter I3, PMOS transistor MP1, and NMOS transistor MN3. Since node ng2 is low when en is high, PMOS transistor MP2 will be turned on, and NMOS transistor MN6 will be turned off. Therefore, the gate of transistor MN7 is pulled up to vdrv by resistor R2 and turned on.

[0036] Furthermore, this embodiment can derive a full-bridge VCC pin ESD protection circuit from the power supply pin ESD protection circuit of the half-bridge driver chip, as follows: Figure 5 As shown, the full-bridge VCC pin ESD protection circuit shares a common transition detection module, and each half-bridge driver chip has an auxiliary turn-on module. When VCC experiences a rapid rise due to a positive ESD event, the transition detection module detects the VCC transition output ng2 signal and drives power transistors MNL1 and MNL2 to conduct through the auxiliary turn-on module. Simultaneously, the VCC transition couples through the gate-drain parasitic capacitance of power transistors MNH1 and MNH2, causing their gate voltages to rise and turn them on. The simultaneous conduction of power transistors MNL1 and MNH1 provides one ESD discharge path, while the simultaneous conduction of power transistors MNL2 enhances another ESD discharge path. Thus, the simultaneous action of the two discharge paths significantly enhances the ESD voltage level of the VCC pin in the full-bridge scheme.

[0037] The above embodiments are merely preferred embodiments of the present invention and are not intended to limit the scope of protection of the present invention. Any changes made based on the design principles of the present invention, or any non-creative modifications made thereon, shall fall within the scope of protection of the present invention.

Claims

1. An ESD protection circuit for the power supply pins of a half-bridge driver chip, comprising: The system comprises power transistors MNH1 and MNL1, and a high-side pre-drive; the source of power transistor MNH1 is connected to the drain of power transistor MNL1; the gate of power transistor MNH1 is externally connected to an input logic signal hson1 via the high-side pre-drive, and the drain of power transistor MNH1 is externally connected to a power supply VCC; characterized in that it further comprises: The transition detection module is connected to the power supply VCC, detects the transition of the power supply VCC, and outputs the transition drive signal ng2. And an auxiliary power-on module, which is connected to the power supply VCC, the transition detection module, and the gate of the power transistor MNL1 to obtain the transition drive signal ng2; the auxiliary power-on module is externally connected to the input logic signal lson1 and the enable signal en; When the voltage of the power supply VCC suddenly increases, the jump detection module outputs a high-level jump drive signal ng2 and uses the auxiliary turn-on module to drive the power transistor MNL1 to turn on; at the same time, the voltage of the power supply VCC suddenly increases and couples the gate of the power transistor MNH1, and the power transistor MNH1 turns on.

2. The power supply pin ESD protection circuit for a half-bridge driver chip according to claim 1, characterized in that, The transition detection module includes a high-pass filter consisting of a capacitor C1 and a resistor R1 connected in series, a Zener diode D1 and a transistor MN4 connected in series with one end between the capacitor C1 and the resistor R1 and the other end grounded; the capacitor C1 is connected to the power supply VCC.

3. The power supply pin ESD protection circuit for a half-bridge driver chip according to claim 2, characterized in that, The auxiliary power-on module includes PMOS transistors MP1, MP2, MN5, MN3, MN6, and MN7, a NAND gate I1, an inverter I2, an inverter I3, and a resistor R2. The NAND gate I1, inverter I2, and inverter I3 are connected in series and then connected to the gates of PMOS transistor MP1 and NMOS transistor MN3. The NAND gate I1 is externally connected to the input logic signal lson1 and the enable signal en. The gates of PMOS transistor MP2, NMOS transistor MN5, and NMOS transistor MN6 are all connected between capacitor C1 and resistor R1. The gate of NMOS transistor MN7 is connected to the drain of PMOS transistor MP1 via resistor R2. PMOS transistors MP1, MP2, MN7, and MN3 are connected sequentially. The gate of power transistor MNL1 is connected between PMOS transistor MP2 and NMOS transistor MN7.

4. A method for ESD protection of a power supply pin, characterized in that, The protection method employs the power supply pin ESD protection circuit of the half-bridge driver chip according to any one of claims 1 to 3 for detection and protection, and includes the following steps: When the voltage of the power supply VCC suddenly increases, the voltage of the power supply VCC that suddenly increases couples to the gate of the power transistor MNH1 and drives the power transistor MNH1 to turn on. Simultaneously, the jump detection module acquires the power supply VCC with a sudden voltage increase and outputs a high-level jump drive signal ng2, which drives the power transistor MNL1 to conduct using the auxiliary turn-on module; at the same time, the power transistors MNH1 and MNL1 conduct electrostatic discharge to the power supply VCC.

5. A full-bridge protection circuit, characterized in that, The half-bridge driver chip described in any one of claims 1 to 3 is provided with two sets of ESD protection circuits for the power supply pins.

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