Buffer circuit, voltage converter, and vehicle

Abstract

The application provides a buffer circuit, a voltage converter and a vehicle, and belongs to the technical field of electronics. A first buffer module in the buffer circuit is configured to receive a reference drive signal and output a first drive signal. A second buffer module in the buffer circuit is configured to receive the first drive signal and the reference drive signal, and output the first drive signal or a second drive signal to a power tube based on a rate of change of a gate-source voltage of the power tube and the reference drive signal. The drive capability of the reference drive signal, the first drive signal and the second drive signal increases in turn. Thus, the buffer circuit, the voltage converter and the vehicle provided by the application can dynamically control the drive capability of the drive signal output to the power tube according to the reference drive signal and the rate of change of the gate-source voltage of the power tube, and can reduce the switching loss of the power tube and the overvoltage failure risk of the power tube.

Description

Technical Field

[0001] This application relates to the field of electronic technology, and in particular to a buffer circuit, a voltage converter, and a vehicle. Background Technology

[0002] The voltage converter includes a driver, a buffer circuit, and a power transistor. The buffer circuit buffers the reference drive signal output by the driver and outputs the buffered reference drive signal to the power transistor to drive the power transistor to switch alternately, converting the input voltage of the power transistor into an output voltage to supply power to the load.

[0003] In related technologies, the buffered reference drive signal has a strong driving capability, which can reduce the switching loss of the power transistor. However, during the power transistor turn-off process, the buffered reference drive signal with a strong driving capability may cause the voltage across the power transistor to rise rapidly, resulting in overvoltage damage to the power transistor. Summary of the Invention

[0004] This application provides a buffer circuit, a voltage converter, and a vehicle that can balance the switching losses of power transistors and the risk of overvoltage damage. The technical solution of this application is as follows.

[0005] In a first aspect, this application provides a buffer circuit, which includes a first buffer module and a second buffer module. The first buffer module is connected to the driver of the power transistor and the second buffer module, and the second buffer module is connected to the power transistor and the driver. The first buffer module is used to receive the reference drive signal output by the driver and output the first drive signal to the second buffer module. The second buffer module is used to receive the first drive signal and the reference drive signal, and output the first drive signal or the second drive signal to the power transistor based on the reference drive signal and the rate of change of the gate-source voltage of the power transistor. The driving capabilities of the reference drive signal, the first drive signal and the second drive signal increase sequentially.

[0006] In one implementation, the second buffer module is used to output a first drive signal to the power transistor when the reference drive signal indicates that the power transistor is turned off and the rate of change of the gate-source voltage is greater than a first threshold.

[0007] In one implementation, the second buffer module is used to output a first drive signal to the power transistor when the reference drive signal indicates that the power transistor is turned on.

[0008] In one implementation, a second buffer module is used to buffer the first drive signal when the reference drive signal indicates that the power transistor is turned off and the rate of change of the gate-source voltage is less than or equal to a first threshold, thereby obtaining and outputting a second drive signal to the power transistor.

[0009] In one implementation, the second buffer module includes a switch and a switch controller, wherein the switch controller, the switch, and the power transistor are connected in sequence; the switch controller is used to receive a reference drive signal and output a control signal to the switch based on the reference drive signal and the rate of change of the gate-source voltage; A switch is used to receive power supply current, control signal and first drive signal, and output the first drive signal to the power transistor based on the control signal, or increase the current of the first drive signal based on the power supply current to obtain and output the second drive signal to the power transistor.

[0010] In one implementation, the switch controller includes a filtering unit and a control unit, which are connected in sequence. The filtering unit is used to receive the gate-source voltage of the power transistor and a reference drive signal, and outputs a first filtered signal to the control unit. The first filtered signal indicates the rate of change of the gate-source voltage of the power transistor. The control unit is used to receive the first filtered signal and output a control signal to the switch.

[0011] In one implementation, the filtering unit includes a filter, a negative channel metal-oxide-semiconductor NMOS transistor, a Schmitt trigger, and an AND gate, which are connected in sequence. The filter is used to receive the gate-source voltage of the power transistor, filter the gate-source voltage to obtain a second filtered signal; the NMOS transistor is used to receive the second filtered signal and output a level signal to the Schmitt trigger; the Schmitt trigger is used to invert the level signal to obtain and output an inverted signal to the AND gate; the AND gate is used to receive the inverted signal and the reference drive signal, perform an AND operation on the inverted signal and the reference drive signal to obtain and output a first filtered signal to the control unit.

[0012] In one implementation, the control unit includes a metal-oxide-semiconductor (MOS) transistor group and a first inverter, and a filter unit, the MOS transistor group and the first inverter are connected in sequence; the MOS transistor group is used to receive a drive inverting signal and a first filter signal, and output a first voltage to the first inverter, wherein the drive inverting signal is inverted with a reference drive signal; the first inverter is used to receive the first voltage and output a control signal to the switch.

[0013] Secondly, this application provides a voltage converter, which includes a driver, a power transistor, and a buffer circuit in any implementation of the first aspect. The buffer circuit is used to output a first driving signal or a second driving signal to the power transistor based on a reference driving signal output by the driver. The first driving signal or the second driving signal is used to drive the power transistor to convert the input voltage into an output voltage, and the driving capabilities of the reference driving signal, the first driving signal, and the second driving signal increase sequentially.

[0014] Thirdly, this application provides a vehicle that includes a voltage converter as described in any implementation of the second aspect.

[0015] The beneficial effects of this application are at least as follows.

[0016] The second buffer module in the buffer circuit dynamically controls the driving capability of the driving signal output to the power transistor based on the reference driving signal and the gate-source voltage change rate of the power transistor. For example, when outputting the first driving signal to the power transistor, the driving capability of the first driving signal is relatively weak, thereby reducing the overvoltage risk of the power transistor during the turn-off process. Conversely, when outputting the second driving signal to the power transistor, the driving capability of the second driving signal is relatively strong, thereby reducing the switching losses of the power transistor. In other words, the buffer circuit can simultaneously reduce the switching losses of the power transistor and reduce the overvoltage failure risk of the power transistor. Attached Figure Description

[0017] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application. It is obvious that the drawings described below are merely some embodiments of this application, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0018] Figure 1 This is a schematic diagram of a voltage converter in related technologies; Figure 2 This is a schematic diagram of the power transistor's turn-on and turn-off process; Figure 3 This is a schematic diagram of a buffer circuit provided in an embodiment of this application; Figure 4 This is a schematic diagram of a second buffer module provided in an embodiment of this application; Figure 5 This is a schematic diagram of a switch controller provided in an embodiment of this application; Figure 6 This is a circuit diagram of a filtering unit provided in an embodiment of this application; Figure 7 This is a circuit diagram of a control unit provided in an embodiment of this application; Figure 8 This is a circuit diagram of a first buffer module provided in an embodiment of this application; Figure 9 This is a flowchart of a power transistor driving method provided in an embodiment of this application. Detailed Implementation

[0019] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided to make this application more comprehensive and complete, and to fully convey the concept of the exemplary embodiments to those skilled in the art.

[0020] Furthermore, the described features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. Numerous specific details are provided in the following description to give a thorough understanding of embodiments of this application. However, those skilled in the art will recognize that the technical solutions of this application can be practiced without one or more of the specific details, or other methods, apparatuses, steps, etc., can be employed. In other instances, well-known methods, apparatuses, implementations, or operations are not shown or described in detail to avoid obscuring various aspects of this application.

[0021] With the development of electronic technology, the application of power management integrated circuits (PMICs) has become more widespread. For example, in the vehicle's electronic system, PMICs are integrated into microcontroller units (MCUs), system-on-chips (SoCs), camera sensors, radar modules, and various high-speed interface circuits. By uniformly managing and distributing power, PMICs effectively improve the integration level of the entire vehicle's electronic system.

[0022] Taking PMICs, including DC-DC voltage converters, as an example, improving the conversion efficiency of DC-DC voltage converters can not only effectively reduce heat loss during system operation and reduce thermal management pressure, but also improve energy utilization efficiency, thereby helping to extend the battery life of vehicles or reduce the energy consumption of the whole vehicle.

[0023] For example, such as Figure 1 As shown, the DC-DC voltage converter 10 includes a driver 11, a buffer 12, a series-connected positive channel metal-oxide-semiconductor (PMOS) transistor P1 and a negative channel metal-oxide-semiconductor (NMOS) transistor N1, parasitic inductance Lp1, parasitic inductance Lp2, inductance L1, and capacitor C1. Figure 1In this context, VIN_INT refers to the source voltage of PMOS transistor P1, PGND_INT refers to the source voltage of NMOS transistor N1, and PGND refers to the ground voltage.

[0024] The reference drive signal output by driver 11 is buffered by buffer 12 and then output to PMOS transistor P1 and NMOS transistor N1 to drive PMOS transistor P1 and NMOS transistor N1 to switch alternately. Based on the input voltage VIN, inductor L1 and capacitor C1 are charged and discharged, thereby converting the input voltage VIN into the output voltage VOUT.

[0025] In addition, improving the conversion efficiency of DC-DC voltage converters can enable PMICs to support a wider range of operating voltage and temperature conditions, expanding their application scenarios in harsh automotive environments, such as maintaining stable power supply in situations with high temperature, high vibration, or large transient load fluctuations.

[0026] The conversion efficiency of a DC-DC voltage converter is negatively correlated with the losses of the power transistor (e.g., PMOS transistor P1 or NMOS transistor N1) in the DC-DC voltage converter. The losses of the power transistor mainly include conduction losses and switching losses. Among them, conduction losses are related to the on-resistance of the power transistor and the load current flowing through the power transistor, while switching losses are determined based on factors such as the switching frequency, voltage-current overlap region, and parasitic parameters during the switching transient process of the power transistor.

[0027] Since conduction loss is positively correlated with the on-resistance of the power transistor, reducing the on-resistance of the power transistor can reduce its conduction loss. However, methods for optimizing conduction loss are relatively limited and their effectiveness is nearing its limit. For example, in one related technique, adding a resistor in parallel with the original on-resistance can effectively reduce the on-resistance of the power transistor. However, in this technique, adding the resistor increases the area and cost of the PMIC.

[0028] Furthermore, reducing the switching losses of the power transistor can also reduce its overall power loss. Switching losses are essentially the energy losses generated during the transient process of the power transistor turning on and off. These energy losses mainly include gate drive losses and current-voltage overlap losses. Gate drive losses refer to the losses caused by the periodic charging and discharging of the power transistor's gate capacitance and other parasitic capacitances by the drive signal. Current-voltage overlap losses refer to the losses generated when the voltage and current on the power transistor overlap during switching.

[0029] Since current-voltage overlap loss occurs during the transition time when the power transistor is neither fully turned off nor fully turned on, the faster the switching speed of the power transistor, the shorter this transition time, and the smaller the current-voltage overlap loss. Since switching speed is positively correlated with the driving capability of the power transistor's drive signal, another related technique improves the switching speed of the power transistor by enhancing the driving capability of its drive signal, resulting in steeper current and voltage waveforms and reduced overlap.

[0030] However, the faster the switching speed of the power transistor, the more significant the switching noise (such as voltage overshoot and ringing) caused by parasitic inductance of the package and printed circuit board (PCB) traces in the voltage converter becomes. In the harsh power supply environment of automotive electronics, this switching noise not only degrades electromagnetic compatibility (EMC) performance but also generates peak voltages across the power transistor. These peak voltages may exceed the rated voltage of the power transistor, leading to power transistor breakdown or the generation of hot carrier effects, resulting in permanent damage to the power transistor.

[0031] by Figure 1 Taking P1 as an example, the conduction and turn-off processes of the PMOS transistor are explained. (See attached document.) Figure 2 , Figure 2 In this context, IL refers to the current flowing through inductor L1, VIN_INT refers to the source voltage of PMOS transistor P1, PGND_INT refers to the source voltage of NMOS transistor N1, and VGS_P refers to the absolute value of the gate-source voltage of PMOS transistor P1.

[0032] In the first stage of the conduction process, the drive signal is low, indicating that the PMOS transistor P1 is turned on. At this time, VGS_P continues to rise.

[0033] In the second stage, VGS_P rises to the turn-on threshold VTH1 of PMOS transistor P1, causing PMOS transistor P1 to turn on. The current flowing through PMOS transistor P1 increases, leading to a larger voltage difference across the parasitic inductor Lp1, which in turn lowers VIN_INT. Conversely, the current flowing through NMOS transistor N1 decreases, causing PGND_INT to increase. Since buffer 12 is powered by both VIN_INT and PGND_INT, the difference between them is the supply voltage of buffer 12. This supply voltage is positively correlated with the driving capability of the drive signal output by buffer 12. Therefore, in this stage, as the difference between VIN_INT and PGND_INT decreases, the driving capability of the drive signal output by buffer 12 also decreases.

[0034] The third stage is the Miller plateau stage, in which VGS_P remains stable, while VIN_INT and PGND_INT gradually oscillate to zero.

[0035] In the fourth stage, VGS_P continues to rise to a constant value, but its rise rate is slower than that in the first stage. Once the constant value is reached, PMOS transistor P1 is fully turned on.

[0036] In the fifth stage of the turn-off process, the drive signal is high, indicating that PMOS transistor P1 is turned off. At this time, VGS_P continues to decrease.

[0037] The sixth stage is the Miller plateau stage, during which VGS_P remains stable. The seventh stage is the stage where the current of PMOS transistor P1 decreases rapidly. In this stage, VGS_P drops to the turn-on threshold VTH1 of PMOS transistor P1, the current flowing through PMOS transistor P1 decreases rapidly, the voltage difference across parasitic inductance Lp1 becomes negative, VIN_INT is greater than VIN, the current flowing through NMOS transistor N1 also decreases, and PGND_INT decreases to be lower than PGND.

[0038] Since the driving capability of the drive signal is positively correlated with the switching speed of the power transistor, and the switching speed of the power transistor is positively correlated with the rate of change of the current flowing through the PMOS transistor P1, and this rate of change of current is positively correlated with the voltage difference between VIN_INT and PGND_INT, that is, the stronger the driving capability of the drive signal, the greater the voltage difference between VIN_INT and PGND_INT. The voltage difference between VIN_INT and PGND_INT, as the power supply voltage of buffer 12, also affects the driving capability of the drive signal, thus forming a positive feedback until the end of the seventh stage.

[0039] The voltage difference between VIN_INT and PGND_INT is also the drain-source voltage of PMOS transistor P1. When the voltage difference between VIN_INT and PGND_INT is greater than the breakdown voltage of PMOS transistor P1, PMOS transistor P1 will fail due to overvoltage.

[0040] Based on this, in one related technology, the buffer 12 adopts a "segmented drive" strategy, dynamically adjusting the drive capability according to the state of the power transistor. For example, a strong drive is used in the initial stage of the power transistor's on / off switching to quickly cross the linear region, and then a weak drive is switched to smoothly complete the subsequent process, thereby suppressing voltage and current overshoot while ensuring speed. However, this segmented drive scheme has a drawback: the "detection point" for state switching is difficult to set precisely. In practical applications, due to the influence of process corner, process-voltage-temperature (PVT) changes, and load current fluctuations, fixed detection points are prone to deviation, leading to "overdrive" or "slow drive" phenomena. Overdrive exposes the power transistor to the risk of voltage overshoot, while slow drive unnecessarily increases switching losses. Both can cause local hot spots or even burnout of the PMIC, limiting the efficiency and reliability of the segmented drive technology.

[0041] In another related technique, buffer 12 weakens the driving capability of the drive signal after a fixed period of time after the power transistor begins to turn off, thereby reducing the voltage difference between VIN_INT and PGND_INT. However, due to parameter differences between different power transistors, a single fixed period cannot be applied to every power transistor. Therefore, buffer 12 has low precision in controlling the driving capability of the drive signal, resulting in a poor balance between reducing the risk of overvoltage failure of the power transistor and switching losses.

[0042] This application provides a buffer circuit that can dynamically control the driving capability of the drive signal output to the power transistor, thereby reducing both the switching losses of the power transistor and the risk of overvoltage failure.

[0043] For example, such as Figure 3 As shown, a buffer circuit 100 provided in this embodiment includes a first buffer module 101 and a second buffer module 102. The first buffer module 101 is connected to the driver of the power transistor and the second buffer module 102, and the second buffer module 102 is connected to the power transistor and the driver. Here, a PMOS transistor is used as an example for the description.

[0044] The first buffer module 101 is used to receive the reference drive signal output by the driver and output the first drive signal to the second buffer module 102. The second buffer module 102 is used to receive the first drive signal and the reference drive signal, and output the first drive signal or the second drive signal to the power transistor based on the reference drive signal and the rate of change of the gate-source voltage of the power transistor. The driving capabilities of the reference drive signal, the first drive signal and the second drive signal increase sequentially.

[0045] In this embodiment, a reference drive signal indicates whether the power transistor is turned on or off. For example, a first-level reference drive signal indicates that the power transistor is on, and a second-level reference drive signal indicates that the power transistor is off. Since the gate-source voltage of the power transistor changes according to a certain pattern during the turn-off process, this pattern directly reflects the actual turn-off process. For example, the rate of change of the gate-source voltage is different at each stage of the turn-on or turn-off process, thus the rate of change of the gate-source voltage can indicate the stage of the turn-on or turn-off process.

[0046] It is understood that the buffer circuit 100 provided in this application can determine the on / off state of the power transistor and the stage in the on or off process based on the reference drive signal and the gate-source voltage change rate of the power transistor, thereby dynamically controlling the driving capability of the drive signal output to the power transistor for different stages.

[0047] For example, in the fifth and sixth stages, the second buffer module 102 outputs a second drive signal with stronger drive capability to the power transistor to reduce the switching losses of the power transistor; as another example, in the seventh stage, the second buffer module 102 outputs a first drive signal with weaker drive capability to the power transistor, thereby reducing the voltage difference between VIN_INT and PGND_INT to reduce the overvoltage risk of the power transistor. That is, the buffer circuit 100 provided in this application can simultaneously reduce the switching losses of the power transistor and reduce the overvoltage failure risk of the power transistor.

[0048] Furthermore, compared to the use of a fixed duration as the adjustment time for the driving capability of the driving signal in related technologies, the buffer circuit 100 provided in this application embodiment performs stage identification based on the actual gate-source voltage change characteristics of the power transistor, so that the adjustment time of the driving capability of the driving signal can dynamically change with the actual working state of the power transistor, thereby improving the accuracy and adaptability of stage identification.

[0049] In one implementation, the second buffer module 102 is used to output a first drive signal to the power transistor when the reference drive signal indicates that the power transistor is turned off and the rate of change of the gate-source voltage is greater than a first threshold.

[0050] The first threshold is a value that can distinguish different stages. For example, the first threshold is the value between the simulated value of the rate of change of the gate-source voltage in the third stage and the simulated value of the rate of change of the gate-source voltage in the seventh stage under the condition of the second drive signal. It is easy to see that the rate of change of the gate-source voltage in the fifth stage is less than that in the seventh stage. That is, when the reference drive signal indicates that the power transistor is turned off and the rate of change of the gate-source voltage is greater than the first threshold, the power transistor is in the seventh stage. The second buffer module 102 outputs the first drive signal to the power transistor, which can reduce the risk of overvoltage failure of the power transistor.

[0051] In one implementation, the second buffer module 102 is used to output a first drive signal to the power transistor when the reference drive signal indicates that the power transistor is turned on.

[0052] In one implementation, the second buffer module 102 is used to buffer the first drive signal when the reference drive signal indicates that the power transistor is turned off and the rate of change of the gate-source voltage is less than or equal to a first threshold, so as to obtain and output the second drive signal to the power transistor.

[0053] Obviously, when the reference drive signal indicates that the power transistor is turned off and the rate of change of the gate-source voltage is less than or equal to the first threshold, the power transistor is in the fifth or sixth stage. The second buffer module 102 can increase the driving capability of the first drive signal by buffering the first drive signal, that is, obtain the second drive signal and output the second drive signal to the power transistor, thereby reducing the switching loss of the power transistor.

[0054] For example, see Figure 4 The second buffer module 102 includes a switch M1 and a switch controller 1021, with the switch controller 1021, switch M1 and power transistor connected in sequence.

[0055] Among them, the switch controller 1021 is used to receive the reference drive signal and output the control signal to the switch M1 based on the reference drive signal and the rate of change of the gate-source voltage; the switch M1 is used to receive the supply current, the control signal and the first drive signal, and output the first drive signal to the power transistor based on the control signal, or increase the current of the first drive signal based on the supply current to obtain and output the second drive signal to the power transistor.

[0056] Optionally, the switch controller 1021 can perform signal processing on the gate-source voltage to obtain the rate of change of the gate-source voltage. For example, the switch controller 1021 can perform high-pass filtering on the gate-source voltage, and the filtered signal can indicate the rate of change of the gate-source voltage.

[0057] In one implementation, if the reference drive signal indicates that the power transistor is off and the rate of change of the gate-source voltage is greater than a first threshold, the switch controller 1021 outputs a first-level control signal; if the reference drive signal indicates that the power transistor is on, or if the reference drive signal indicates that the power transistor is off and the rate of change of the gate-source voltage is less than or equal to the first threshold, the switch controller 1021 outputs a second-level control signal. The first-level control signal indicates that switch M1 is off, and the second-level control signal indicates that switch M1 is on.

[0058] For example, switch M1 is a PMOS transistor. The source of switch M1 receives the supply current, and the gate of switch M1 is connected to switch controller 1021. The drain of switch M1, the power transistor, and the first buffer module 101 are interconnected. When switch M1 is on, the supply current is injected into the first drive signal through the drain of switch M1. That is, switch M1 increases the current of the first drive signal based on the supply current, thereby buffering the first drive signal to obtain the second drive signal and outputting it to the power transistor. When switch M1 is off, the supply current cannot be injected into the first drive signal through the drain of switch M1. In this case, switch M1 outputs the first drive signal to the power transistor.

[0059] It is easy to see that the switch controller 1021 and the switch M1 together selectively amplify the current of the first drive signal, thereby achieving buffering of the first drive signal. Compared with buffering achieved by increasing the number of inverter stages, increasing the transistor size in the buffer, or setting a dedicated drive stage, this embodiment does not require adding inverters or buffers. Instead, it uses switch M1 to selectively inject the supply current into the first drive signal, amplifying the drive current of the first drive signal when needed. Therefore, switch M1 not only enhances the driving capability of the first drive signal but also helps to reduce the number of transistors, circuit area, and power consumption in the buffer circuit 100.

[0060] like Figure 5 As shown, a switch controller 1021 provided in this application embodiment includes a filter unit 1022 and a control unit 1023, and the filter unit 1022, the control unit 1023 and the switch M1 are connected in sequence.

[0061] The filtering unit 1022 is used to receive the gate-source voltage of the power transistor and the reference drive signal, and output a first filtered signal to the control unit 1023. The first filtered signal indicates the rate of change of the gate-source voltage of the power transistor. The control unit 1023 is used to receive the first filtered signal and output a control signal to the switch M1.

[0062] For example, see Figure 6 The filter unit 1022 includes a filter, an NMOS transistor N2, a Schmitt trigger U1, and an AND gate U2. The filter includes a resistor R1 and a capacitor C2. One end of the resistor R1 and the capacitor C2 and the gate of the NMOS transistor N2 are connected to each other. The drain of the NMOS transistor N2, the Schmitt trigger U1, and the AND gate U2 are connected in series.

[0063] In this embodiment, a filter is used to receive the gate-source voltage of the power transistor, filter the gate-source voltage, and obtain a second filtered signal; an NMOS transistor N2 is used to receive the second filtered signal and output a level signal to a Schmitt trigger U1; a Schmitt trigger U1 is used to invert the level signal and obtain an inverted signal to be output to an AND gate U2; an AND gate U2 is used to receive the inverted signal and a reference drive signal, perform an AND operation on the inverted signal and the reference drive signal, obtain a first filtered signal to be output to the control unit 1023.

[0064] For example, resistor R1 and capacitor C2 form a high-pass filter to achieve high-pass filtering of the gate-source voltage, resulting in a second filtered signal. The voltage of the second filtered signal is dv / dt. R1 C2. Where R1 is the resistance of resistor R1, C2 is the capacitance of capacitor C2, and dv / dt is the rate of change of the gate-source voltage. Clearly, the voltage of the second filtered signal can indicate the rate of change of the gate-source voltage.

[0065] In one implementation, NMOS transistor N2 receives the supply voltage through resistor R2 and is grounded through its source. When the voltage of the second filter signal is greater than the turn-on voltage of NMOS transistor N2, NMOS transistor N2 turns on, thereby outputting a ground voltage, i.e., a low level, to Schmitt trigger U1. When the voltage of the second filter signal is less than or equal to the turn-on voltage of NMOS transistor N2, NMOS transistor N2 turns off, thereby outputting the voltage after the supply voltage is divided by resistor R2 to Schmitt trigger U1, i.e., a high level.

[0066] It is understandable that the resistance value of resistor R1 and the capacitance value of capacitor C2 can be determined based on the first threshold and the turn-on voltage of NMOS transistor N2. For example, the product of the resistance value of resistor R1 and the capacitance value of capacitor C2 needs to be greater than the quotient of the turn-on voltage and the first threshold, thereby ensuring that NMOS transistor N2 can be turned on when the rate of change of the gate-source voltage is greater than the first threshold, and that NMOS transistor N2 can be turned off when the rate of change of the gate-source voltage is less than or equal to the first threshold, thus improving the accuracy of the drive signal selection.

[0067] Furthermore, this embodiment utilizes filtering to detect rapid gate-source voltage changes, which are then used to control the driving strength of the drive signal. This allows for precise detection of the stage the power transistor is in, and by employing a detection-feedback approach, the vibration amplitude of the power transistor is reduced, thereby protecting the power transistor while improving its driving efficiency.

[0068] In some embodiments, the filter unit 1022 further includes a resistor R3 and a PMOS transistor M2. It is easy to see that the PMOS transistor M2 is used to feed the output of the Schmitt trigger U1 back to the input side to form positive feedback, thereby giving the Schmitt trigger U1 hysteresis characteristics and improving its noise immunity and input jitter immunity. The resistor R3 is used to limit the current in the feedback branch when the PMOS transistor M2 is turned on, avoiding a large current surge after the PMOS transistor M2 is turned on.

[0069] In one possible implementation, the second buffer module 102 is also used to obtain the gate level LG of another power transistor in the voltage converter, such as... Figure 1 In the NMOS transistor N1, during the dead time when the gate level LG is low (indicated by the reference drive signal to turn off the power transistor), the power transistor is in the turn-off process, and the filter starts working, enabling the second buffer module 102 to obtain the rate of change of the gate-source voltage. Outside of the dead time when the gate level LG is high (indicated by the reference drive signal to turn off the power transistor), or when the reference drive signal indicates that the power transistor is on, the filter stops working, and the first filter signal remains low.

[0070] In one implementation, such as Figure 7 As shown, the control unit 1023 includes a metal-oxide-semiconductor (MOS) transistor array and a first inverter. The filter unit, the MOS transistor array, and the first inverter are connected in sequence. The MOS transistor array is used to receive a drive inverting signal and a first filter signal, and outputs a first voltage to the first inverter. The drive inverting signal is inverted with a reference drive signal. The first inverter is used to receive the first voltage and output a control signal to the switch.

[0071] For example, the MOS transistor group includes PMOS transistor P2, PMOS transistor P3, NMOS transistor N3 and NMOS transistor N4, with PMOS transistor P2, PMOS transistor P3 and NMOS transistor N3 connected in series, and the drains of NMOS transistor N4, PMOS transistor P3 and NMOS transistor N3 interconnected.

[0072] In this circuit, PMOS transistor P2 receives the supply voltage through its source and the inverting drive signal through its gate; PMOS transistor P3 receives the first filtered signal through its gate; and NMOS transistor N4 receives the inverting drive signal through its gate. The node voltage connecting the drains of NMOS transistor N4, PMOS transistor P3, and NMOS transistor N3 is the first voltage output by the MOS transistor group to the first inverter. The first inverter inverts the first voltage and outputs a control signal to switch M1.

[0073] See Figure 8The first buffer module 101 provided in this application embodiment includes 6 inverters, each inverter including a PMOS transistor and an NMOS transistor connected in series. The 6 inverters are the second inverter to the seventh inverter, the PMOS transistors in the second inverter to the seventh inverter are P4 to P9 respectively, and the NMOS transistors in the second inverter to the seventh inverter are N5 to N10 respectively.

[0074] In this circuit, the second inverter receives a reference drive signal, inverts it, and outputs the inverted reference drive signal to the third and sixth inverters respectively. The third and fourth inverters work together to buffer the inverted reference drive signal, obtaining and outputting the inverted drive signal to the PMOS transistor P7 in the fifth inverter. The sixth and seventh inverters work together to buffer the inverted reference drive signal, obtaining and outputting the inverted drive signal to the NMOS transistor N8 in the fifth inverter. The fifth inverter then inverts the inverted drive signal, obtaining and outputting the first drive signal to the second buffer module 102.

[0075] Optionally, the inverters in the first buffer module 101 are connected by short wires, which reduces the parasitic capacitance between the inverters and reduces the signal propagation delay in the first buffer module 101. Therefore, when the reference drive signal changes, the first buffer module 101 can quickly complete the buffering operation of the reference drive signal, which helps to improve the loop dynamic response of the first buffer module 101.

[0076] The following is combined with Figure 1-8 For example, the working principle of the buffer circuit 100 is illustrated when the reference drive signal indicates that the power transistor is turned off and the rate of change of the gate-source voltage of the power transistor is greater than the first threshold.

[0077] The filter in the buffer circuit 100 receives the gate-source voltage and performs a high-pass filter on the gate-source voltage to obtain a second filtered signal. The voltage of the second filtered signal is greater than the turn-on voltage of the NMOS transistor N2, so the NMOS transistor N2 is turned on. The input level of the Schmitt trigger U1 is low, and the output level of the Schmitt trigger U1 is high. Obviously, the first filtered signal output by the AND gate U2 is also high. This high-level first filtered signal indicates that the gate-source voltage is greater than the first threshold.

[0078] In this case, the driving inverting signal is low, the NMOS transistor N4 in the MOS transistor group is turned off, the PMOS transistor P2 is turned on, and the supply voltage is output to the PMOS transistor P3. In addition, the PMOS transistor P3 is turned off by the high-level first filter signal, and the NMOS transistor N3 is turned on by the high-level first filter signal. As a result, the input terminal of the first inverter is low, the first inverter outputs a high-level control signal, the switch M1 is turned off, and the first drive signal is output to the power transistor to reduce the overvoltage risk of the power transistor.

[0079] It is understood that the working principle of the buffer circuit 100 can be referred to the foregoing description when the reference drive signal indicates that the power transistor is turned off and the rate of change of the gate-source voltage of the power transistor is less than or equal to the first threshold, and when the reference drive signal indicates that the power transistor is turned on, and will not be repeated here.

[0080] This application embodiment also provides a voltage converter, which includes a driver, a power transistor, and a buffer circuit 100 provided in any of the foregoing embodiments. The buffer circuit 100 is used to output a first driving signal or a second driving signal to the power transistor based on a reference driving signal output by the driver. The first driving signal or the second driving signal is used to drive the power transistor to convert the input voltage into an output voltage. The driving capabilities of the reference driving signal, the first driving signal, and the second driving signal increase sequentially.

[0081] This application also provides a vehicle that includes the voltage converter provided in any of the foregoing embodiments.

[0082] This application embodiment also provides a method for driving a power transistor, which can be executed by the buffer circuit 100 in any of the foregoing embodiments, such as... Figure 9 As shown, the driving method includes the following steps S91 and S92.

[0083] Step S91: Receive the reference drive signal output by the driver and output the first drive signal.

[0084] Step S91 can be executed by the first buffer module 101 in the buffer circuit 100. The execution principle can be found in the previous description of the first buffer module 101, which will not be repeated here.

[0085] Step S92: Receive the first drive signal and the reference drive signal, and output the first drive signal or the second drive signal to the power transistor based on the reference drive signal and the rate of change of the gate-source voltage.

[0086] Step S92 can be executed by the second buffer module 102 in the buffer circuit 100. The execution principle can be found in the previous description of the second buffer module 102, which will not be repeated here.

[0087] For example, step S92 includes: outputting a first drive signal to the power transistor when the reference drive signal indicates that the power transistor is turned off and the rate of change of the gate-source voltage is greater than a first threshold.

[0088] As another example, step S92 includes: outputting a first drive signal to the power transistor when the reference drive signal indicates that the power transistor is turned on.

[0089] As another example, step S92 includes: when the reference drive signal indicates that the power transistor is turned off and the rate of change of the gate-source voltage is less than or equal to a first threshold, buffering the first drive signal to obtain and output a second drive signal to the power transistor.

[0090] In one implementation, step S92 includes steps S93 and S94. Step S93: Receive a reference drive signal, and output a control signal based on the reference drive signal and the rate of change of the gate-source voltage. Step S94: Receive the supply current, the control signal, and the first drive signal; based on the control signal, output the first drive signal to the power transistor, or increase the current of the first drive signal based on the supply current to obtain and output a second drive signal to the power transistor.

[0091] Step S93 can be executed by the switch controller 1021, and step S94 can be executed by the switch M1.

[0092] In one implementation, step S93 includes steps S95 and S96. Step S95: Receive the gate-source voltage of the power transistor and a reference drive signal, and output a first filtered signal to the control unit, the first filtered signal indicating the rate of change of the gate-source voltage of the power transistor; Step S96: Receive the first filtered signal and output a control signal to the switch.

[0093] Step S95 can be executed by the filter unit 1022 in the switch controller 1021, and step S96 can be executed by the control unit 1023 in the switch controller 1021.

[0094] For example, step S95 includes steps S951 to S954. Step S951: Receive the gate-source voltage of the power transistor, filter the gate-source voltage to obtain a second filtered signal; Step S952: Receive the second filtered signal and output a level signal; Step S953: Invert the level signal and output an inverted signal; Step S954: Receive the inverted signal and a reference drive signal, perform an AND operation on the inverted signal and the reference drive signal, and output a first filtered signal.

[0095] Specifically, step S951 can be executed by the filter in the filter unit 1022, step S952 can be executed by the NMOS transistor N2 in the filter unit 1022, step S953 can be executed by the Schmitt trigger U1 in the filter unit 1022, and step S954 can be executed by the AND gate U2 in the filter unit 1022.

[0096] Optionally, step S96 includes steps S961 and S962. Step S961: Receive the driving inverting signal and the first filtered signal, and output the first voltage, wherein the driving inverting signal is inverted compared to the reference driving signal; Step S962: Receive the first voltage and output a control signal to the switch.

[0097] Step S961 can be executed by the MOS transistor group in the control unit 1023, and step S962 can be executed by the first inverter in the control unit 1023.

[0098] It is understood that the technical effects of each step of the driving method provided in this application embodiment are the same as those of the corresponding devices, units or modules mentioned above, and will not be repeated here.

[0099] The above content describes specific embodiments of this application, but the scope of protection of this application is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application.

Claims

1. A buffer circuit, characterized in that, The buffer circuit includes a first buffer module and a second buffer module. The first buffer module is connected to the driver of the power transistor and the second buffer module, and the second buffer module is connected to the power transistor and the driver. The first buffer module is used to receive the reference drive signal output by the driver and output a first drive signal to the second buffer module; The second buffer module is used to receive the first driving signal and the reference driving signal, and output the first driving signal or the second driving signal to the power transistor based on the reference driving signal and the rate of change of the gate-source voltage of the power transistor, wherein the driving capability of the reference driving signal, the first driving signal and the second driving signal increases sequentially.

2. The buffer circuit according to claim 1, characterized in that, The second buffer module is used to output the first drive signal to the power transistor when the reference drive signal indicates that the power transistor is turned off and the rate of change of the gate-source voltage is greater than a first threshold.

3. The buffer circuit according to claim 1, characterized in that, The second buffer module is used to output the first drive signal to the power transistor when the reference drive signal indicates that the power transistor is turned on.

4. The buffer circuit according to claim 1, characterized in that, The second buffer module is used to buffer the first drive signal when the reference drive signal indicates that the power transistor is turned off and the rate of change of the gate-source voltage is less than or equal to a first threshold, so as to obtain and output the second drive signal to the power transistor.

5. The buffer circuit according to any one of claims 1-4, characterized in that, The second buffer module includes a switch and a switch controller, wherein the switch controller, the switch, and the power transistor are connected in sequence; The switch controller is configured to receive the reference drive signal and output a control signal to the switch based on the reference drive signal and the rate of change of the gate-source voltage; The switch is used to receive the power supply current, the control signal, and the first drive signal, and output the first drive signal to the power transistor based on the control signal, or increase the current of the first drive signal based on the power supply current to obtain and output the second drive signal to the power transistor.

6. The buffer circuit according to claim 5, characterized in that, The switch controller includes a filtering unit and a control unit, wherein the filtering unit, the control unit, and the switch are connected in sequence; The filtering unit is used to receive the gate-source voltage of the power transistor and the reference drive signal, and output a first filtered signal to the control unit, wherein the first filtered signal indicates the rate of change of the gate-source voltage of the power transistor; The control unit is configured to receive the first filtered signal and output the control signal to the switch.

7. The buffer circuit according to claim 6, characterized in that, The filtering unit includes a filter, a negative channel metal-oxide-semiconductor (NMOS) transistor, a Schmitt trigger, and an AND gate, wherein the filter, the NMOS transistor, the Schmitt trigger, and the AND gate are connected in sequence. The filter is used to receive the gate-source voltage of the power transistor, filter the gate-source voltage, and obtain a second filtered signal. The NMOS transistor is used to receive the second filtered signal and output a level signal to the Schmitt trigger; The Schmitt trigger is used to invert the level signal to obtain and output an inverted signal to the AND gate; The AND gate is used to receive the inverted signal and the reference drive signal, perform an AND operation on the inverted signal and the reference drive signal, and output a first filtered signal to the control unit.

8. The buffer circuit according to claim 6 or 7, characterized in that, The control unit includes a metal-oxide-semiconductor (MOS) transistor group and a first inverter, and the filter unit, the MOS transistor group and the first inverter are connected in sequence; The MOS transistor group is used to receive the driving inverting signal and the first filtered signal, and output a first voltage to the first inverter, wherein the driving inverting signal is inverted with the reference driving signal; The first inverter is used to receive the first voltage and output the control signal to the switch.

9. A voltage converter, characterized in that, The voltage converter includes a driver, a power transistor, and a buffer circuit as described in any one of claims 1-8. The buffer circuit is used to output a first driving signal or a second driving signal to the power transistor based on a reference driving signal output by the driver. The first driving signal or the second driving signal is used to drive the power transistor to convert the input voltage into an output voltage. The driving capabilities of the reference driving signal, the first driving signal, and the second driving signal increase sequentially.

10. A vehicle, characterized in that, The vehicle includes the voltage converter as described in claim 9.

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