A totem column bridgeless boost PFC double closed loop PI parameter optimization method based on improved whale optimization algorithm

Abstract

The application discloses a totem pole bridgeless Boost PFC double-loop PI parameter optimization method based on an improved whale optimization algorithm, and relates to the technical field of power electronic converter control. The method is based on a totem pole bridgeless Boost PFC main circuit model, and a double-loop PI control model composed of a voltage outer loop and a current inner loop is constructed. Then, the current inner loop proportional coefficient, the current inner loop integral coefficient, the voltage outer loop proportional coefficient and the voltage outer loop integral coefficient are selected to form PI parameters to be optimized. Based on a constraint fitness function containing a direct-current bus voltage dynamic error evaluation, an input current total harmonic distortion rate evaluation, a direct-current bus voltage overshoot evaluation, an efficiency evaluation and a constraint penalty term, the improved whale optimization algorithm is used to iteratively optimize the PI parameters. The application can reduce the uncertainty of artificial setting of the PI parameters, improve the THD evaluation accuracy, improve the input current harmonic suppression effect while ensuring the stability of the direct-current bus voltage, and improve the comprehensive control performance of the totem pole bridgeless Boost PFC circuit.

Description

Technical Field

[0001] This invention relates to the field of power electronic converter control technology, and in particular to a totem pole bridgeless Boost PFC dual closed-loop PI parameter optimization method based on an improved whale optimization algorithm. Background Technology

[0002] With the development of new energy vehicles and high-power power electronic equipment, on-board chargers, as a crucial energy conversion interface connecting the AC power grid and power batteries, directly impact the power quality on the grid side and the stability of the charging system due to their power factor, current harmonics, and dynamic response performance. Compared to traditional bridged Boost PFC circuits, totem-pole bridgeless Boost PFC circuits reduce the number of conducting devices in the power transmission path, offering advantages such as low conduction loss, high efficiency, and high power density, making them suitable for on-board charger front-end power factor correction scenarios.

[0003] Currently, totem-pole bridgeless Boost PFC circuits typically employ a dual-closed-loop PI control structure consisting of an outer voltage loop and an inner current loop. The outer voltage loop maintains DC bus voltage stability, while the inner current loop ensures the input current follows the input voltage variation. However, traditional PI parameter tuning often relies on engineering experience or trial-and-error methods, resulting in cumbersome tuning processes and insufficient parameter adaptability. This makes it difficult to balance dynamic bus voltage response, steady-state accuracy, and total harmonic distortion of the input current under different operating conditions.

[0004] Existing intelligent optimization algorithms, if they only use a linear weighting method of indicators such as voltage error, overshoot, and total harmonic distortion (THD) to construct the fitness function, may lead to the optimization algorithm selecting excessively small voltage loop parameters in order to obtain a lower input current THD, making it impossible for the DC bus voltage to stabilize to the reference value. It may also lead to inaccurate THD evaluation results because the input current data is calculated at fixed intervals, mistaking transient processes for steady-state processes. Furthermore, when the adjustment time penalty term accounts for too large a proportion in the fitness function, the optimization algorithm may excessively pursue a fast bus voltage response, affecting the tracking performance of the inner current loop for the power frequency sinusoidal current, making it difficult to further reduce the total harmonic distortion of the input current. Summary of the Invention

[0005] The technical problem this invention aims to solve is as follows: In existing totem-pole bridgeless Boost PFC circuits, the PI parameters rely on manual experience for tuning, resulting in cumbersome tuning processes and insufficient parameter adaptability. Furthermore, existing intelligent optimization algorithms often suffer from poorly designed fitness functions, leading to difficulties in simultaneously addressing dynamic bus voltage response, steady-state error, and total harmonic distortion (THD) of the input current. This invention provides a totem-pole bridgeless Boost PFC dual-loop PI parameter optimization method based on an improved whale optimization algorithm. By setting a steady-state discrimination and unsteady-state penalty mechanism for bus voltage and employing a dynamic steady-state window identification method to determine the calculation range of the THD of the input current, a constrained fitness function suitable for tuning the dual-loop PI parameters of the totem-pole bridgeless Boost PFC is constructed. This enables joint optimization of the voltage outer loop and current inner loop PI parameters, improving the engineering effectiveness of the PI parameter optimization results and the overall system control performance. This method is applicable to control parameter tuning, bus voltage stabilization control, and input current harmonic suppression in on-board charger front-end power factor correction circuits.

[0006] The technical solution adopted by this invention to solve its technical problem is: a totem pole bridgeless Boost PFC dual closed-loop PI parameter optimization method based on an improved whale optimization algorithm, comprising the following steps: S1. Establish the bridgeless Boost PFC main circuit model of the totem pole; S2. Based on the totem pole bridgeless Boost PFC main circuit model, a dual closed-loop PI control model consisting of a voltage outer loop and a current inner loop is constructed. The voltage outer loop is used to generate an input current reference based on the error between the DC bus voltage and the DC bus reference voltage in the totem pole bridgeless Boost PFC main circuit model. The current inner loop is used to generate a duty cycle control quantity based on the error between the input current and the input current reference in the totem pole bridgeless Boost PFC main circuit model. S3. Select the current inner loop proportional coefficient, current inner loop integral coefficient, voltage outer loop proportional coefficient, and voltage outer loop integral coefficient in the dual closed-loop PI control model as variables to be optimized, and encode this set of variables to be optimized to form the whale individual position vector that constitutes the whale optimization algorithm; the four variables to be optimized together form a set of PI parameters. S4. Construct a constrained fitness function for evaluating the quality of the PI parameters. The constrained fitness function includes a DC bus voltage dynamic error evaluation term, an input current total harmonic distortion rate evaluation term, a DC bus voltage overshoot evaluation term, an efficiency evaluation term, and a constraint penalty term. S5. The improved whale optimization algorithm is used to iteratively optimize the PI parameters. The comprehensive fitness value of each whale individual is calculated according to the constrained fitness function. The whale population position in the improved whale optimization algorithm is updated according to the comprehensive fitness value to obtain the optimal PI parameters. S6. Write the optimal PI parameters into the dual closed-loop PI control model to achieve stable control of DC bus voltage and suppression of input current harmonics.

[0007] This solution employs an improved whale optimization algorithm combined with a constrained fitness function to jointly optimize dual-loop PI parameters, abandoning the traditional manual trial-and-error tuning method, resulting in higher tuning efficiency. It comprehensively considers DC bus voltage dynamic response, steady-state accuracy, power conversion efficiency, and input current harmonic performance, effectively improving the overall control performance of the totem-pole bridgeless Boost PFC circuit and adapting to the actual operating requirements of on-board chargers. The method is used in the front-end power factor correction circuit of the on-board charger, optimizing the voltage outer loop and current inner loop PI parameters to ensure the input current follows the input voltage changes and reducing the total harmonic distortion of the input current.

[0008] In some embodiments, in step S1, the totem pole bridgeless Boost PFC main circuit model includes: AC input power supply, configured to provide power frequency AC input voltage; A boost inductor, connected in series with the output terminal of the AC input power supply, is used to store energy and shape the input current to achieve power factor correction. The power conversion unit includes a high-frequency bridge arm and a power frequency bridge arm. The high-frequency bridge arm includes a first switch and a second switch, and the power frequency bridge arm includes a third switch and a fourth switch. Each switch is configured to be turned on / off according to a preset timing sequence to realize power conversion and freewheeling. A DC bus capacitor is connected in parallel to the output terminal of the power conversion unit to stabilize the output DC bus voltage. The load is connected in parallel across the DC bus capacitor and configured as a simulated on-board charger downstream load or an equivalent DC load.

[0009] The totem pole bridgeless Boost PFC main circuit model uses the publicly available totem pole bridgeless Boost PFC main circuit topology as the controlled object, which fits the actual engineering application requirements.

[0010] In some embodiments, in step S2, the dual closed-loop PI control model adopts the voltage outer loop and current inner loop control structure commonly used in totem pole bridgeless Boost PFC circuits, including a voltage outer loop PI controller, a current inner loop PI controller, an AC input voltage synchronization module, a sinusoidal current reference generation module, and a PWM drive module.

[0011] The totem pole bridgeless Boost PFC circuit includes the totem pole bridgeless Boost PFC main circuit (Totem pole bridgeless Boost PFC main circuit model) and a dual closed-loop PI control circuit consisting of a voltage outer loop and a current inner loop (dual closed-loop PI control model).

[0012] The outer voltage loop is used to acquire the DC bus voltage and compare it with the DC bus reference voltage to obtain the voltage error; the voltage error is adjusted by the outer voltage loop PI controller to generate a current amplitude command; the current amplitude command is combined with a sinusoidal synchronization signal in phase with the input voltage to generate an input current reference; The inner current loop acquires the input current and compares it with the input current reference to obtain the current error. The current error is adjusted by the inner current loop PI controller to generate a duty cycle control quantity, which is then output as a switching transistor drive signal by the PWM drive module in the dual closed-loop PI control model.

[0013] This scheme constructs a dual-closed-loop PI control model as a standard control platform for the controlled object, providing a stable and reproducible control carrier for subsequent improvement of the whale optimization algorithm's PI parameter optimization.

[0014] In some embodiments, in step S3, the position vector is represented as:

[0015] in, This is the proportionality coefficient for the inner current loop. The integral coefficient of the inner current loop. This is the voltage outer loop proportionality coefficient. This represents the voltage outer loop integral coefficient.

[0016] In some embodiments, in step S4, the constraint penalty includes a bus voltage unsteady-state penalty, an under-adjustment penalty, and an adjustment time exceeding a threshold penalty.

[0017] By setting three types of constraint penalties—unsteady bus voltage, under-adjustment, and adjustment time exceeding the threshold—multi-dimensional constraints are imposed on the optimization process to avoid the algorithm unilaterally optimizing a single index and to ensure the steady-state accuracy and dynamic response performance of the DC bus voltage.

[0018] The total harmonic distortion rate (THD) evaluation item for the input current uses dynamic steady-state window identification to determine the calculation range of the THD of the input current.

[0019] A dynamic steady-state window identification method is adopted to define the calculation range of total harmonic distortion of input current, distinguish between transient and steady-state operating conditions of the system (totem pole bridgeless Boost PFC circuit), improve the accuracy of the evaluation results of total harmonic distortion of input current, and ensure the true and reliable effect of PI parameter optimization.

[0020] In some embodiments, the constrained fitness function is expressed as:

[0021] in, This is the overall fitness value; This is an evaluation item for the dynamic error of DC bus voltage. This is an evaluation item for the total harmonic distortion rate of the input current. This is an evaluation item for DC bus voltage overshoot. For efficiency evaluation items, To constrain penalties, These are the weight coefficients for the corresponding evaluation items.

[0022] The constrained fitness function achieves multi-objective collaborative optimization of the PI parameter through a composite structure of weighted multiple evaluation terms and constraint penalty terms. This fundamentally solves the shortcomings of the traditional linear weighted fitness function, which tends to overlook some aspects, and at the same time improves the engineering effectiveness and robustness of the optimization results.

[0023] In one set of embodiments, the iterative optimization process of the improved whale optimization algorithm includes: Initialize the whale population size, maximum number of iterations, PI parameter search boundary and constrained fitness function weight coefficients, and add the preset baseline PI parameters to the initial population; The PI parameters corresponding to each individual whale in the population were simulated and calculated to obtain DC bus voltage, input current, input power and output power data; In the fitness evaluation process, the steady-state judgment of DC bus voltage is first performed. Individuals that do not meet the steady-state requirements (bus voltage is not steady-state) are penalized, and the calculation range of total harmonic distortion of input current is determined by identifying the dynamic steady-state window. The comprehensive fitness value is calculated by combining the evaluation items of DC bus voltage dynamic error, total harmonic distortion of input current, DC bus voltage overshoot, efficiency, and constraint penalty. The individual position is updated according to the position update mechanism and boundary constraint mechanism of the whale optimization algorithm. The iteration is repeated until the maximum number of iterations is met, and the PI parameter with the smallest comprehensive fitness value is output as the optimal PI parameter.

[0024] This scheme, based on the existing whale optimization algorithm, introduces preset benchmark PI parameters to initialize the population, reducing the number of algorithm iterations and accelerating convergence. It also avoids the local optimum problem caused by random initial populations, improving the reliability and stability of the optimization results. The constrained fitness function incorporates multiple penalty terms, forcing the algorithm to simultaneously consider DC bus voltage steady-state accuracy, dynamic response, input current harmonic suppression, and operating efficiency, overcoming the inherent contradiction in traditional linear weighted optimization: "sacrificing voltage stability to reduce THD and degrading current waveform to pursue response speed." The boundary constraint mechanism ensures that the optimized PI parameters always remain within a reasonable physical range, preventing system instability caused by parameter exceeding limits.

[0025] In some embodiments, in step S6, the optimal PI parameters are obtained through offline optimization. After the offline optimization is completed, the obtained current inner loop proportional coefficient, current inner loop integral coefficient, voltage outer loop proportional coefficient, and voltage outer loop integral coefficient are written into the voltage outer loop PI controller and the current inner loop PI controller for subsequent steady-state operation and input voltage disturbance operation.

[0026] The beneficial effects of this invention are: 1. This invention employs an improved whale optimization algorithm to jointly optimize the voltage outer loop and current inner loop PI parameters of the totem pole bridgeless Boost PFC circuit. The proportional coefficient of the current inner loop, the integral coefficient of the current inner loop, the proportional coefficient of the voltage outer loop, and the integral coefficient of the voltage outer loop are all used as variables to be optimized. This allows for the search of PI parameters with better overall fitness within the global search range, reducing the uncertainty caused by manually trial-and-error PI parameter selection and improving the tuning efficiency of the dual closed-loop control parameters.

[0027] 2. In the fitness evaluation process, this invention introduces a steady-state bus voltage discrimination and under-adjustment penalty mechanism, which can constrain the PI parameter when the DC bus voltage does not meet the steady-state requirements, avoid obtaining false low THD evaluation results when the bus voltage does not meet the reference voltage requirements, and improve the engineering effectiveness of the optimization results.

[0028] 3. This invention uses a dynamic steady-state window identification method to determine the calculation interval of the total harmonic distortion rate of the input current, which no longer relies on the current data interception at fixed time points. This can avoid the participation of transient current data in THD evaluation and improve the accuracy and stability of harmonic evaluation.

[0029] 4. In the evaluation of adjustment time, the present invention adopts low-weight soft constraints and generates an adjustment time over-threshold penalty term when the adjustment time exceeds the preset time. The adjustment time over-threshold penalty term is included in the constraint penalty term, so that the optimization algorithm can not only meet the dynamic response requirements of the bus voltage, but also take into account the total harmonic distortion rate of the input current, and avoid the adjustment time index from occupying too large a proportion in the comprehensive fitness evaluation, which would lead to the deviation of the optimization direction.

[0030] 5. This invention can improve the ability of input current to follow input voltage, reduce total harmonic distortion of input current, and improve the overall control performance of totem pole bridgeless Boost PFC circuit while ensuring DC bus voltage stability and dynamic response performance. Attached Figure Description

[0031] The present invention will be further described below with reference to the accompanying drawings and embodiments.

[0032] Figure 1 This is a topology diagram of the totem pole bridgeless Boost PFC main circuit in an embodiment of the present invention.

[0033] Figure 2 This is a block diagram of the dual-closed-loop PI control model consisting of the voltage outer loop and the current inner loop in the totem pole bridgeless Boost PFC circuit of this invention.

[0034] Figure 3 This is a flowchart of the PI parameter optimization method based on the improved whale optimization algorithm in an embodiment of the present invention.

[0035] Figure 4 This is a waveform diagram of the network-side voltage and current of the totem pole bridgeless Boost PFC circuit in an embodiment of the present invention.

[0036] Figure 5 This is a waveform diagram of the DC bus voltage in an embodiment of the present invention.

[0037] Figure 6 This is an input current waveform diagram in an embodiment of the present invention.

[0038] Figure 7 This is a diagram showing the total harmonic distortion rate of the input current in an embodiment of the present invention.

[0039] Figure 8 This is a waveform diagram of the system power factor in an embodiment of the present invention.

[0040] Figure 9 This is a waveform diagram of the DC bus output voltage response under grid-side voltage disturbance in an embodiment of the present invention.

[0041] Figure 10 This is a graph showing the overall fitness convergence curve of the improved whale optimization algorithm in this embodiment of the invention. Detailed Implementation

[0042] The present invention will now be described in further detail with reference to the accompanying drawings. These drawings are simplified schematic diagrams, illustrating only the basic structure of the invention, and therefore only show the components relevant to the invention.

[0043] like Figure 3As shown, a totem pole bridgeless Boost PFC dual-closed-loop PI parameter optimization method based on an improved whale optimization algorithm includes the following steps: S1. Establish the bridgeless Boost PFC main circuit model of the totem pole.

[0044] The specific implementation is as follows: (e.g.) Figure 1 As shown, the totem pole bridgeless Boost PFC main circuit model adopts the existing totem pole bridgeless Boost PFC main circuit topology (this invention does not use this existing structure as an improvement point). The totem pole bridgeless Boost PFC main circuit includes an AC input power supply ( ), boost inductor ( ), power switching devices and their freewheeling circuits, DC bus capacitors ( ) and load ( The AC input power supply provides the mains frequency AC input voltage; the boost inductor stores energy and shapes the input current; the power switching devices (including a high-frequency bridge arm and a mains frequency bridge arm, the high-frequency bridge arm including a first switch (S1 / g1) and a second switch (S2 / g2), the mains frequency bridge arm including a third switch (S3 / g3) and a fourth switch (S4 / g4), each switch being configured to turn on / off according to a preset timing sequence to achieve power conversion and freewheeling; in this embodiment, the mains frequency bridge arm is replaced by a MOSFET instead of a diode) and their freewheeling paths constitute a power conversion unit, used to realize energy conversion from the AC input side to the DC bus side; the DC bus capacitor is used to stabilize the output DC voltage; the load is used to simulate the DC / DC converter after the on-board charger or an equivalent DC load.

[0045] It should be noted that, in Figure 1 In this context, the DC bus refers to the high-voltage DC power supply path formed by the DC bus capacitor and the two ends of the load on the right side of the bridge arm (high-frequency bridge arm, power frequency bridge arm).

[0046] In one specific implementation, the AC input power supply voltage is set to 220V, and the DC bus reference voltage is set to 400V. This setting is used to simulate the typical operating conditions of the on-board charger's pre-stage power factor correction circuit.

[0047] S2. Based on the totem pole bridgeless Boost PFC main circuit model, a dual closed-loop PI control model consisting of a voltage outer loop and a current inner loop is constructed.

[0048] In this embodiment, as Figure 2As shown, the dual closed-loop PI control model adopts the voltage outer loop and current inner loop control structure commonly used in existing totem pole bridgeless Boost PFC circuits. The improvement of this invention does not lie in the control structure itself, but in optimizing the PI parameters composed of the current inner loop proportional coefficient, current inner loop integral coefficient, voltage outer loop proportional coefficient, and voltage outer loop integral coefficient in the control structure.

[0049] The dual closed-loop PI control model includes an outer voltage PI controller (outer voltage PI), an inner current PI controller (inner current PI), an AC input voltage synchronization module (PLL), a sinusoidal current reference generation module, and a PWM drive module (PWM generator).

[0050] The voltage outer loop PI controller is used to receive the voltage error between the DC bus reference voltage and the DC bus voltage, and outputs a current amplitude adjustment signal, i.e., a current amplitude command, according to the voltage error; the AC input voltage synchronization module is used to obtain the phase information of the AC input voltage (AC input power supply input voltage) and generate a sinusoidal synchronization signal in phase with the AC input voltage; the sinusoidal current reference generation module is used to combine the current amplitude command with the sinusoidal synchronization signal to generate an input current reference, so that the input current reference keeps the same frequency and phase as the AC input voltage. The inner current loop PI controller is used to receive the current error between the input current reference and the input current, and to perform proportional-integral adjustment on the current error, outputting a duty cycle control quantity to control the on / off state of the switching transistors (S1 / g1, S2 / g2, S3 / g3, S4 / g4) in the totem pole bridgeless Boost PFC circuit. The PWM drive module is used to generate a switching transistor drive signal based on the duty cycle control quantity, and apply the switching transistor drive signal to the power switching device in the totem pole bridgeless Boost PFC circuit to control the on and off states of the switching transistor; so that the input current changes according to the input current reference and keeps in phase and frequency with the AC input voltage.

[0051] The outer voltage loop is used to maintain DC bus voltage stability. Specifically, Figure 2 In the process, the DC bus voltage of the totem pole bridgeless Boost PFC circuit is collected. and compare it with the DC bus reference voltage. By comparison, the voltage error is obtained. :

[0052] The voltage error is input to the outer-loop PI controller, which adjusts the current amplitude command to achieve the desired result. The purpose of this adjustment is to generate the current amplitude command based on the DC bus voltage error, maintaining the DC bus voltage near the DC bus reference voltage. The outer-loop PI controller can be represented as:

[0053] in, This is the voltage outer loop proportionality coefficient; The voltage outer loop integral coefficient; s is the complex frequency domain variable in the Laplace transform.

[0054] The inner current loop is used to make the input current follow changes in the AC input voltage. Specifically, Figure 2 In the process, the current amplitude command output by the outer voltage loop is combined with the AC input voltage sinusoidal synchronization signal to obtain the input current reference. Collect actual input current. It is then compared with the input current reference to obtain the current error. :

[0055] The current error input current inner-loop PI controller, after adjustment, yields the duty cycle control value, which is then used by the PWM drive module to generate the switching drive signal for the power switching device. The purpose of the current inner-loop PI controller is to ensure the input current tracks the input current reference, and to adjust the duty cycle control value of the power switching device through the PWM drive module, thereby achieving input current shaping and power factor correction. The current inner-loop PI controller can be represented as:

[0056] in, This is the proportionality coefficient for the inner current loop; The integral coefficient of the inner current loop; s is the complex frequency domain variable in the Laplace transform.

[0057] The aforementioned dual-loop PI control model enables stable control of the DC bus voltage and ensures that the input current follows the input voltage changes, thereby improving the power factor and reducing input current harmonics. The basic control form of the aforementioned PI controllers (voltage outer-loop PI controller and current inner-loop PI controller) can adopt existing PI control methods. This invention improves the whale optimization algorithm to jointly optimize its proportional and integral coefficients.

[0058] S3. Select the PI parameters to be optimized and construct the PI parameter optimization model.

[0059] In this embodiment, the current inner loop proportional coefficient, the current inner loop integral coefficient, the voltage outer loop proportional coefficient, and the voltage outer loop integral coefficient are used as variables to be optimized, forming the position vector of the individual whale in the whale optimization algorithm. The above four variables to be optimized form a set of PI parameters, and the position vector is represented as follows:

[0060] in, This is the proportionality coefficient for the inner current loop. The integral coefficient of the inner current loop. This is the voltage outer loop proportionality coefficient. The voltage outer loop integral coefficient In one specific implementation, to ensure the feasibility of the PI parameter search process, upper and lower limits (i.e., search boundaries) are set for the PI parameters:

[0061]

[0062] in, This serves as the lower limit for the search. This represents the upper limit of the search. The whale optimization algorithm searches for the optimal PI parameter within the above search boundary.

[0063] It should be noted that traditional manual tuning does not involve setting the upper and lower limits of the algorithm before searching, but rather relies on manual trial and error; however, this invention uses an intelligent optimization algorithm, so it is necessary to transform human experience into the search boundaries of the algorithm.

[0064] In this embodiment, the lower and upper search limits are preset fixed boundary values, which can be determined based on the rated power of the totem-pole bridgeless Boost PFC circuit, the DC bus reference voltage, the sampling period, the stable operating range of the PI controller, and engineering experience. The improved Whale Optimization Algorithm (Improved WOA) searches for PI parameters within the preset search boundary, which remains unchanged during a single offline optimization process. When an individual position exceeds the search boundary, a boundary constraint mechanism is used to limit it to the corresponding upper or lower search limit value. This yields PI parameters that meet the requirements of DC bus voltage stability, input current harmonic suppression, and disturbance recovery.

[0065] S4. To avoid the whale optimization algorithm from having a non-physical optimal solution due to the ordinary linear weighted fitness function, a constrained fitness function is constructed.

[0066] In this embodiment, the constraint-type fitness function includes a DC bus voltage dynamic error evaluation term, an input current total harmonic distortion (THD) rate evaluation term, a DC bus voltage overshoot evaluation term, an efficiency evaluation term, and a constraint penalty term. The constraint penalty term includes a bus voltage unsteady-state penalty, an under-adjustment penalty, and a settling time exceeding a threshold penalty. The input current THD rate evaluation term uses a dynamic steady-state window to identify the calculation interval for the input current THD rate.

[0067] The constrained fitness function is executed as follows: 1. Steady-state determination of bus voltage: After each set of PI parameters completes the simulation calculation (the simulation calculation is completed by a dual closed-loop PI control model), the DC bus voltage data within the preset time window at the end of the simulation is extracted, and the average value and voltage fluctuation of the DC bus voltage within the preset time window are calculated.

[0068] Let the average DC bus voltage within the preset time window at the simulation end be... If the following conditions are met:

[0069] If the DC bus voltage fluctuation is less than a preset threshold, the system is determined to have entered a steady state. This represents the allowable steady-state voltage error threshold. If the above conditions are not met, the system corresponding to this set of PI parameters is determined to have not entered a steady state, and a penalty fitness value is applied to this set of PI parameters. This is then included in the constraint penalty term as a case of unsteady bus voltage penalty.

[0070] 2. Penalties for underperformance: When the average DC bus voltage within the preset time window at the end of the simulation is lower than the lower limit threshold of the DC bus reference voltage, the system is determined to be under-adjusted. This indicates that while the set of PI parameters may result in a better input current waveform, it cannot guarantee that the DC bus voltage will reach the DC bus reference voltage.

[0071] For PI parameters exhibiting under-adjustment, instead of performing a normal evaluation of the total harmonic distortion of the input current, an under-adjustment penalty is generated based on the deviation between the average DC bus voltage and the DC bus reference voltage.

[0072] in, For underpayment of penalties; This is the under-adjustment penalty coefficient. By imposing an under-adjustment penalty, the whale optimization algorithm can avoid selecting excessively small voltage outer loop PI parameters (voltage outer loop proportional coefficient and voltage outer loop integral coefficient) to reduce THD, which would prevent the DC bus voltage from reaching the DC bus reference voltage. The under-adjustment penalty coefficient is a positive number and is set according to the order of magnitude of each evaluation term in the constrained fitness function, ensuring that the fitness value corresponding to the under-adjustment state is higher than the fitness value of the PI parameters that satisfy the steady-state constraints. The under-adjustment penalty coefficient is not used as a variable to be optimized but is pre-set before offline optimization.

[0073] 3. Dynamic steady-state window identification: After the system meets the steady-state discrimination condition for the bus voltage, it determines whether the DC bus voltage has entered the allowable error of the DC bus reference voltage, and checks whether it remains within the allowable error of the DC bus reference voltage for a continuous preset time. The steady-state starting point is determined based on the time point when the DC bus voltage enters and remains within the allowable error of the DC bus reference voltage. Let the steady-state starting point be... Then select Instead of using fixed-time point intercepts, subsequent input current data is used for harmonic analysis. This reduces the likelihood of misinterpreting transient input current as steady-state input current when the system is still in a transient process, thereby improving the accuracy of THD calculation.

[0074] It should be noted that when the length of the input current data after the steady-state start point is less than the preset minimum selection time length for harmonic analysis data, the steady-state harmonic analysis data corresponding to that set of PI parameters is deemed insufficient. Therefore, a normal evaluation of the total harmonic distortion rate of the input current is not performed, and a penalty fitness value is applied to that set of PI parameters. The penalty fitness value corresponding to insufficient steady-state harmonic analysis data is also included in the constraint penalty item as a case of unsteady-state bus voltage penalty. 4. Evaluation of total harmonic distortion of input current: The input current data within the dynamic steady-state window is resampled at equal intervals, and input current data for an integer number of power frequency cycles is extracted. Then, a fast Fourier transform is performed on the input current data to obtain the fundamental current amplitude and the amplitudes of each harmonic current.

[0075] The total harmonic distortion of the input current is expressed as:

[0076] in, The amplitude of the fundamental current. For the first Second harmonic current amplitude The highest harmonic order used in the calculation is represented by this value. Calculating THD using a dynamic steady-state window can improve the accuracy and stability of harmonic assessment.

[0077] 5. Adjusting time soft constraints and over-threshold penalties: The adjustment time is determined based on the time it takes for the DC bus voltage to enter and remain within the allowable error range of the DC bus reference voltage. When the adjustment time is less than or equal to the preset time When the adjustment time is exceeded, a low-weight soft constraint is applied; when the adjustment time exceeds the preset time, an adjustment time over-threshold penalty is generated based on the degree of exceedance and included in the constraint penalty item. :

[0078] in, To adjust the penalty for exceeding the time threshold; This is to adjust the time penalty coefficient. This constraint prevents the whale optimization algorithm from excessively pursuing extremely short settling times, which could negatively impact the input current THD performance, making the optimization objective more aligned with actual engineering needs.

[0079] 6. Calculation of overall fitness value: The dynamic error evaluation term for DC bus voltage can be expressed as a time-weighted absolute error integral:

[0080] This evaluation item can simultaneously reflect the magnitude and duration of the deviation between the DC bus voltage and the DC bus reference voltage; the longer the deviation lasts, the larger the evaluation value. The DC bus voltage dynamic error evaluation item may include time-weighted absolute error integral and steady-state voltage deviation evaluation, used to comprehensively reflect the voltage dynamic process and steady-state deviation.

[0081] The evaluation item for total harmonic distortion of input current is:

[0082] The evaluation items for DC bus voltage overshoot are:

[0083] in, This represents the maximum DC bus voltage during the simulation. This evaluation term is used to suppress overshoot caused by excessively high DC bus voltage.

[0084] The efficiency evaluation items are:

[0085] in, For system efficiency; the higher the system efficiency, The smaller the value, the better the fitness evaluation of the corresponding PI parameter.

[0086] Based on the above evaluation criteria, the constraint-type fitness function in this embodiment is expressed as:

[0087] in, This represents the overall fitness value; a smaller overall fitness value indicates better overall performance of the corresponding PI parameter. This is a dynamic error evaluation item for DC bus voltage, used to evaluate the deviation of DC bus voltage during startup, regulation, and steady-state processes. This is the total harmonic distortion rate (THD) evaluation item for input current, used to evaluate the degree of harmonic distortion of the input current. This is a DC bus voltage overshoot evaluation item, used to suppress overshoot caused by excessively high DC bus voltage; This is an efficiency evaluation item used to evaluate the system's energy conversion efficiency; The constraint penalty terms include unsteady bus voltage penalty, under-adjustment penalty, and over-threshold adjustment time penalty, which are obtained by directly adding the three together; These are the weighting coefficients for the corresponding evaluation items. The weighting coefficients are preset non-negative coefficients, preferably positive values, used to balance the magnitude and optimization priority of different evaluation items. The weighting coefficients are not limited to normalized weights, and their sum does not have to be equal to 1.

[0088] In this embodiment, the reference voltage tolerance range, the preset threshold for voltage fluctuation, the lower limit threshold for DC bus reference voltage, the continuous preset time, the minimum selection time for harmonic analysis data, the adjustment time, the penalty coefficients (under-adjustment penalty coefficient, adjustment time penalty coefficient), and the weighting coefficients of the constraint-type fitness function are all preset parameters, which can be determined based on the DC bus reference voltage, power frequency period, simulation time, control accuracy requirements, and engineering experience. These parameters remain unchanged during a single offline optimization process.

[0089] S5. An improved whale optimization algorithm is used to optimize the PI parameter.

[0090] The improved whale optimization algorithm is an offline parameter optimization algorithm that, based on the position update framework of the whale optimization algorithm, introduces DC bus voltage steady-state discrimination, dynamic steady-state window identification, constraint-type fitness function evaluation, and a preset benchmark PI parameter initialization mechanism.

[0091] like Figure 3 As shown, this embodiment uses an improved whale optimization algorithm to optimize the PI parameter offline. The specific execution is as follows: First, initialize the whale population size. Maximum number of iterations Dimensions of variables to be optimized Search limit Search lower limit And the weight coefficients of the constrained fitness function. Each whale's position vector corresponds to a set of PI parameters: ,

[0092] in, This represents the number of PI parameters.

[0093] Then, an initial whale population is randomly generated, and a preset baseline PI parameter is included as an individual in the initial population to ensure that the initial population contains a workable baseline solution (i.e., the baseline PI parameter). The preset baseline PI parameter is a set of stable PI parameters obtained through traditional engineering tuning or simulation debugging. Adding it to the initial population does not change the position update mechanism of the whale optimization algorithm, but rather improves the feasibility of the initial population.

[0094] For each individual whale, its corresponding PI parameters are written into a dual-closed-loop PI control model, and simulation is run to obtain DC bus voltage, input current, input power, and output power data. Then, based on the constrained fitness function constructed in step S4, the individual whale is subjected to steady-state bus voltage determination, dynamic steady-state window identification, total harmonic distortion rate calculation of input current, and comprehensive fitness evaluation.

[0095] In each iteration, the individual with the smallest current overall fitness value is selected as the current best individual. Individual whales update their position based on a combination of prey-surrounding, spiraling, and random search mechanisms (i.e., position update mechanisms).

[0096] When the prey encirclement mechanism is executed, the individual's position is updated as follows:

[0097]

[0098] in, and For the coefficient vector, This is the distance vector, which represents the distance of the current individual whale. With the current best individual Between the coefficient vectors The adjusted distance; t represents the current iteration number of the whale optimization algorithm, and t+1 represents the next iteration.

[0099] When the spiral update mechanism is executed, the individual position is updated as follows:

[0100] in, ; It is a constant; It is a random number.

[0101] When the random search mechanism is executed, an individual is randomly selected from the population. And update the position according to the following formula:

[0102]

[0103] After the update, if an individual's location exceeds the search boundary, it will be restricted to the corresponding upper or lower search limit using the following formula:

[0104] The simulation calculation, comprehensive fitness evaluation, and population position update process are repeated until the maximum number of iterations is reached and convergence is shown by the iteration curve. Finally, the PI parameter with the minimum comprehensive fitness value is output as the optimal PI parameter.

[0105] In one specific implementation, the number of individuals in the whale optimization algorithm is set to 45, and the maximum number of iterations is set to 50. It should be noted that the population size and the maximum number of iterations can be adjusted according to simulation accuracy, computational resources, and control performance requirements.

[0106] It should be noted that the improved whale optimization algorithm is essentially a customized optimization adapted to PI parameter optimization and PFC control scenarios within the classic WOA framework.

[0107] S6. Write the optimal PI parameters into the dual closed-loop PI control model.

[0108] After optimizing the whale optimization algorithm, the optimal PI parameters were obtained:

[0109] in, and Write these into the inner loop PI controller of the current. and Write them into the outer loop PI controller of the voltage respectively.

[0110] After writing the optimal PI parameters into the PI controller, the totem-pole bridgeless Boost PFC circuit was simulated and verified. The simulation results are as follows: Figures 4 to 10 As shown, where, Figure 4 The grid-side voltage and current waveforms are shown. Figure 5 The DC bus voltage waveform is shown. Figure 6 The input current waveform was shown. Figure 7 The results of the total harmonic distortion analysis of the input current are presented. Figure 8 The system power factor waveform is shown. Figure 9 The DC bus output voltage response waveform under grid-side voltage disturbance is presented. Figure 10The overall fitness convergence curve of the improved whale optimization algorithm is presented.

[0111] In one specific implementation, after offline optimization using the improved whale optimization algorithm, the optimal PI parameter obtained is: the current inner loop proportional coefficient. The integral coefficient of the inner current loop is 1.273945. The voltage outer loop proportionality coefficient is 10.0000. The voltage outer loop integral coefficient is 0.779202. The value is 30.0000. After writing the above optimal PI parameters into the dual closed-loop PI control, the DC bus voltage can be stabilized at around 400V with a small steady-state error. The maximum DC bus voltage is about 414V, corresponding to a maximum DC bus voltage overshoot of about 3.5% and a settling time of about 0.25s, indicating that this method can achieve stable control of the DC bus voltage.

[0112] Depend on Figure 4 and Figure 6 It can be seen that the optimized input current can follow the grid-side input voltage changes well, and the voltage and current basically maintain the same frequency and phase, indicating that the system has a good power factor correction effect. Figure 7 It can be seen that the optimized total harmonic distortion (THD) of the input current is 3.33%, which meets the input current harmonic suppression requirements. From... Figure 8 It can be seen that the optimized system power factor PF is greater than 0.998, indicating that this method can effectively improve the grid-side current quality.

[0113] Depend on Figure 9 It can be seen that under disturbance conditions where the grid-side input voltage drops from 220V to 176V and rises from 220V to 264V, the DC bus voltage can recover to near the DC bus reference voltage after a brief fluctuation, with a maximum voltage deviation of approximately 8V and a recovery time of approximately 0.25s. This indicates that the method has good input voltage disturbance recovery capability. Figure 10 It can be seen that the overall fitness value of the improved whale optimization algorithm decreased from the initial 1.5221 to 1.485038 and remained stable in subsequent iterations, indicating that the improved whale optimization algorithm has good convergence.

[0114] In summary, simulation results show that the method of the present invention can improve the ability of input current to follow input voltage, reduce the total harmonic distortion rate of input current, improve the system power factor, and enhance the DC bus voltage recovery capability under grid-side input voltage disturbances, while ensuring the stability of DC bus voltage. This verifies the effectiveness of the totem pole bridgeless Boost PFC dual closed-loop PI parameter optimization method based on the improved whale optimization algorithm.

[0115] The improved whale optimization algorithm in this embodiment is an offline optimization algorithm. After offline optimization, the obtained optimal PI parameters are fixedly written into the PI controller for subsequent steady-state operation and operation under input voltage disturbance conditions. This method is applicable to the power factor correction circuit of the on-board charger, and can also be used in other power electronic conversion systems that adopt a totem-pole bridgeless Boost PFC structure.

[0116] Based on the above-described preferred embodiments of the present invention, and through the foregoing description, those skilled in the art can make various changes and modifications without departing from the inventive concept. The technical scope of this invention is not limited to the contents of the specification, but must be determined according to the scope of the claims.

Claims

1. A method for optimizing the parameters of a totem pole bridgeless Boost PFC dual-closed-loop PI system based on an improved whale optimization algorithm, characterized in that, Includes the following steps: Step 1: Establish the bridgeless Boost PFC main circuit model of the totem pole; Step 2: Based on the totem pole bridgeless Boost PFC main circuit model, construct a dual closed-loop PI control model consisting of a voltage outer loop and a current inner loop. The voltage outer loop is used to generate an input current reference based on the error between the DC bus voltage and the DC bus reference voltage in the totem pole bridgeless Boost PFC main circuit model. The current inner loop is used to generate a duty cycle control quantity based on the error between the input current and the input current reference. Step 3: Select the current inner loop proportional coefficient, current inner loop integral coefficient, voltage outer loop proportional coefficient, and voltage outer loop integral coefficient from the dual closed-loop PI control model as variables to be optimized, forming the position vector of an individual in the whale optimization algorithm; the four variables to be optimized together constitute the PI parameters. Step 4: Construct a constrained fitness function for evaluating the performance of PI parameters. The constrained fitness function includes a DC bus voltage dynamic error evaluation term, an input current total harmonic distortion rate evaluation term, a DC bus voltage overshoot evaluation term, an efficiency evaluation term, and a constraint penalty term. Step 5: Iteratively optimize the PI parameters using the improved whale optimization algorithm, calculate the comprehensive fitness value of each PI parameter according to the constrained fitness function, and update the whale population position according to the comprehensive fitness value to obtain the optimal PI parameters; Step 6: Write the optimal PI parameters into the dual closed-loop PI control model to achieve stable control of DC bus voltage and suppression of input current harmonics.

2. The totem pole bridgeless Boost PFC dual-closed-loop PI parameter optimization method based on the improved whale optimization algorithm according to claim 1, characterized in that, The dual closed-loop PI control model in step two includes a voltage outer loop PI controller, a current inner loop PI controller, an AC input voltage synchronization module, a sinusoidal current reference generation module, and a PWM drive module.

3. The totem pole bridgeless Boost PFC dual-closed-loop PI parameter optimization method based on the improved whale optimization algorithm according to claim 1, characterized in that, The position vector in step three is represented as follows: in, This is the proportionality coefficient for the inner current loop. The integral coefficient of the inner current loop. This is the voltage outer loop proportionality coefficient. This represents the voltage outer loop integral coefficient.

4. The totem pole bridgeless Boost PFC dual-closed-loop PI parameter optimization method based on the improved whale optimization algorithm according to claim 1, characterized in that, The constrained fitness function is expressed as follows: in, This is the overall fitness value; This is an evaluation item for the dynamic error of DC bus voltage. This is an evaluation item for the total harmonic distortion rate of the input current. This is an evaluation item for DC bus voltage overshoot. For efficiency evaluation items; To constrain penalty items; These are the weight coefficients for the corresponding evaluation items.

5. The totem pole bridgeless Boost PFC dual-closed-loop PI parameter optimization method based on the improved whale optimization algorithm according to claim 1, characterized in that, The constraint penalty items include bus voltage unsteady state penalty, under-adjustment penalty, and adjustment time exceeding the threshold penalty.

6. The totem pole bridgeless Boost PFC dual-closed-loop PI parameter optimization method based on the improved whale optimization algorithm according to claim 5, characterized in that, The unsteady-state penalty for the bus voltage is: After each set of PI parameters is simulated and calculated in the dual closed-loop PI control model, the DC bus voltage data within the preset time window at the end of the simulation is selected, and the average value and voltage fluctuation of the DC bus voltage within the preset time window are calculated. When the average DC bus voltage is within the allowable error of the DC bus reference voltage and the voltage fluctuation is less than the preset threshold, it is determined that the totem pole bridgeless Boost PFC circuit corresponding to the set of PI parameters has entered a steady state. When the average value of the DC bus voltage is not within the allowable error of the DC bus reference voltage, or the voltage fluctuation is equal to or greater than the preset threshold, it is determined that the totem pole bridgeless Boost PFC circuit corresponding to the set of PI parameters has not entered a steady state, and a penalty fitness value is applied to the set of PI parameters, and it is included in the constraint penalty item as a case of the bus voltage not being in a steady state penalty.

7. The totem pole bridgeless Boost PFC dual-closed-loop PI parameter optimization method based on the improved whale optimization algorithm according to claim 5, characterized in that, The penalty for under-reporting is as follows: After each set of PI parameters completes the simulation calculation, the DC bus voltage data within a preset time window at the end of the simulation is selected, and the average value of the DC bus voltage within the preset time window is calculated. When the average value of the DC bus voltage is lower than the lower limit threshold of the DC bus reference voltage, it is determined that the totem pole bridgeless Boost PFC circuit corresponding to that set of PI parameters is under-adjusted. For PI parameters with under-adjustment, the normal evaluation of the total harmonic distortion rate of the input current is not performed. Instead, the under-adjustment penalty is calculated based on the deviation between the average value of the DC bus voltage and the DC bus reference voltage, and is included in the constraint penalty term.

8. The totem pole bridgeless Boost PFC dual-closed-loop PI parameter optimization method based on the improved whale optimization algorithm according to claim 5, characterized in that, The penalty for exceeding the threshold during adjustment time is: The adjustment time is determined based on the time it takes for the DC bus voltage to enter and remain within the allowable error band of the DC bus reference voltage. When the adjustment time is less than or equal to a preset time, a low-weight soft constraint is applied to the adjustment time. When the adjustment time is greater than the preset time, an adjustment time over-threshold penalty is generated based on the degree to which the preset time is exceeded, and this penalty is included in the constraint penalty item.

9. The totem pole bridgeless Boost PFC dual-closed-loop PI parameter optimization method based on the improved whale optimization algorithm according to claim 1, characterized in that, In the evaluation item of total harmonic distortion of input current, a dynamic steady-state window is used to determine the calculation range of total harmonic distortion of input current. The dynamic steady-state window is: The dynamic steady-state window is determined based on the time it takes for the DC bus voltage to enter and remain continuously within the allowable error of the DC bus reference voltage. After the DC bus voltage meets the steady-state discrimination condition, the time point when the DC bus voltage first enters and remains continuously within the allowable error of the DC bus reference voltage is determined as the steady-state starting point. Input current data is extracted from the steady-state starting point and used as harmonic analysis data; The total harmonic distortion rate (THD) evaluation item for the input current is: The input current data within the dynamic steady-state window is resampled at equal intervals; the input current data for an integer number of power frequency cycles is extracted; and the input current data is subjected to a fast Fourier transform to obtain the fundamental current amplitude and the amplitudes of each harmonic current. The total harmonic distortion rate of the input current is calculated based on the fundamental current amplitude and the amplitudes of each harmonic current, and the total harmonic distortion rate of the input current is used as an evaluation term of the constrained fitness function.

10. The totem pole bridgeless Boost PFC dual-closed-loop PI parameter optimization method based on the improved whale optimization algorithm according to any one of claims 1-9, characterized in that, In step five, the improved whale optimization algorithm is based on the position update framework of the whale optimization algorithm, and introduces DC bus voltage steady-state discrimination, dynamic steady-state window identification, constraint fitness function evaluation, and offline parameter optimization algorithm with preset benchmark PI parameters. Specifically, it includes: Set the whale population size, maximum number of iterations, PI parameter search range and constrained fitness function weight coefficients, and use the PI parameter as an individual position vector; Simulate the PI parameters corresponding to each individual, and collect DC bus voltage, input current, input power and output power data; Calculate the overall fitness value using a constrained fitness function, and update the current best individual. The individual position is updated according to the position update mechanism and boundary constraint mechanism of the whale optimization algorithm; when the PI parameter exceeds the search range, it is restricted to the corresponding upper or lower search limit value; The iteration terminates, and the PI parameter with the minimum overall fitness value is output, which is the optimal PI parameter.

Images