A PWM signal reconstruction method, an interleaved PFC module and a controller

Abstract

The application discloses a PWM signal reconstruction method, an interleaved PFC module and a controller, and relates to the technical field of power electronic control. The method is applied to a logic unit in a configurable logic block in an interleaved PFC module controller, the logic unit acquires a to-be-reconstructed PWM signal output by a pulse modulation module without delay processing of a rising edge and performs edge detection, and when the rising edge is detected, a high-level signal is output after waiting for a preset dead-time delay. The application can independently construct a dead-time delay for upper and lower tubes, solve the problem of missing dead-time caused by phase shifting and limited resources in a DCM mode, and improve system operation safety.

Description

Technical Field

[0001] This application relates to the field of power electronics technology, specifically to a PWM signal reconstruction method, an interleaved PFC module, and a controller. Background Technology

[0002] High-power three-phase power factor correction (PFC) rectifiers are widely used in power conversion equipment such as charging piles and energy storage converters. To reduce input current ripple and increase the overall power density, these rectifiers generally adopt a multi-path interleaved parallel topology, which cancels input current ripple by staggering the conduction times of the switches in each branch.

[0003] Multi-channel interleaved power factor (PFC) relies on phase-shift control to achieve waveform phase misalignment. The pulse modulation module in the PFC controller uses the comparison matching point as a synchronization reference to achieve phase shifting. When multi-channel interleaved PFC operates in Discontinuous Conduction Mode (DCM), a single switching cycle of DCM has three timing intervals: upper transistor on, both transistors off simultaneously, and lower transistor on. The upper and lower transistors cannot be turned on simultaneously, as this would cause a short circuit between the positive and negative terminals of the power supply, damaging the power devices. Therefore, the PWM signal driving the power switching transistors must be configured with dead-time timing to reserve a safe shutdown window when the upper and lower transistor drive signal edges switch. However, the hardware resources of the pulse modulation module only support configuring rising edge delay or dead-time control for one output. In DCM control scenarios where the on-time and duty cycle dynamically change, it is impossible to simultaneously meet the dual requirements of stable operation with interleaved phase shifting and safe protection for upper and lower transistor drive. Summary of the Invention

[0004] In view of this, this application provides a PWM signal reconstruction method, an interleaved PFC module and a controller, which can independently construct configurable dead time for the upper and lower transistors, and solve the problem of dead time loss caused by phase shift and resource constraints in DCM mode.

[0005] To solve the above problems, the technical solution provided in this application is as follows:

[0006] In a first aspect of this application, a PWM signal reconstruction method is provided, applied to a logic unit in a configurable logic block of an interleaved PFC module controller, the interleaved PFC module controller further comprising a pulse modulation module, the method comprising:

[0007] The pulse modulation module outputs two PWM signals to the upper and lower transistors of the corresponding power branch, and obtains the PWM signal to be reconstructed from the two PWM signals, wherein the PWM signal to be reconstructed is a PWM signal without delay processing of the rising edge;

[0008] Edge detection is performed on the PWM signal to be reconstructed;

[0009] If a rising edge is detected, a high-level signal is output to the corresponding subsequent driver circuit after waiting for a preset dead time delay.

[0010] In one possible implementation, the step of outputting a high-level signal to the corresponding subsequent drive circuit after waiting for a preset dead-time delay includes:

[0011] Start the built-in counter of the logic unit;

[0012] After the counter reaches the count value corresponding to the preset dead time delay, a high-level signal is output to the corresponding subsequent drive circuit.

[0013] In one possible implementation, activating the counter built into the logic unit includes:

[0014] If a rising edge is detected, the finite state machine is controlled to switch from the waiting rising edge state to the delay counting state, triggering the execution of the step of starting the counter built into the logic unit;

[0015] The step of outputting a high-level signal to the corresponding subsequent drive circuit after the counter reaches the count value corresponding to the preset dead-time delay includes:

[0016] After the counter reaches the count value corresponding to the preset dead time delay, the finite state machine is controlled to switch from the delay counting state to the output high level state, triggering the execution of the step of outputting a high level signal to the corresponding subsequent drive circuit.

[0017] In one possible implementation, after edge detection of the PWM signal to be reconstructed, the method further includes:

[0018] If a falling edge or steady-state level is detected, the PWM signal to be reconstructed is directly output to the corresponding subsequent drive circuit.

[0019] In one possible implementation, the step of directly outputting the PWM signal to be reconstructed to the corresponding subsequent driving circuit if a falling edge or steady-state level is detected includes:

[0020] If a falling edge or steady-state level is detected, the finite state machine is controlled to switch from the output high level state to the waiting rising edge state, triggering the execution of the edge detection step for the PWM signal to be reconstructed.

[0021] In one possible implementation, edge detection of the PWM signal to be reconstructed includes:

[0022] The PWM signal to be reconstructed is compared with the stored level signal;

[0023] If the comparison result indicates that the level signal jumps from low level to high level, then it is determined that a rising edge has been detected, and the stored level signal is updated to high level.

[0024] If the comparison result indicates that the level signal has changed from high level to low level, then it is determined that a falling edge has been detected, and the stored level signal is updated to low level.

[0025] If the comparison result indicates that the level signal remains unchanged, then it is determined that a steady-state level has been detected, and the stored level signal remains unchanged.

[0026] In a second aspect of this application, an interleaved PFC module controller is provided, comprising: a pulse modulation module and a configurable logic block;

[0027] The configurable logic block includes multiple logic units;

[0028] Each power branch of the interleaved PFC module corresponds to one of the pulse modulation modules and one of the logic units;

[0029] The pulse modulation module is used to perform phase shifting with the comparison matching point as the synchronization reference, and output two PWM signals for the upper and lower transistors of the corresponding power branch. Among them, at least one of the two PWM signals is a PWM signal to be reconstructed without delay processing of the rising edge.

[0030] The logic unit acquires the PWM signal to be reconstructed output by the pulse modulation module, performs edge detection on the PWM signal to be reconstructed, and if a rising edge is detected, it outputs a high-level signal to the corresponding subsequent drive circuit after waiting for a preset dead time delay to drive the power switch of the corresponding power branch.

[0031] In one possible implementation, the logic unit includes at least one input lookup table, each of the input lookup tables corresponding to one of the PWM signals to be reconstructed;

[0032] The input lookup table compares the PWM signal to be reconstructed with the stored level signal. If the comparison result indicates that the level signal jumps from low to high, a rising edge is detected, and the stored level signal is updated to high. If the comparison result indicates that the level signal jumps from high to low, a falling edge is detected, and the stored level signal is updated to low. If the comparison result indicates that the level signal remains unchanged, a steady-state level is detected, and the stored level signal remains unchanged.

[0033] In one possible implementation, the logic unit further includes at least one counter and an output lookup table, with one counter and one output lookup table corresponding to one of the PWM signals to be reconstructed;

[0034] After the input lookup table detects a rising edge, it starts the corresponding counter. After the counter reaches the count value corresponding to the preset dead time delay, the corresponding output lookup table outputs the high-level signal, which is connected to the original output path of the pulse modulation module via the output cross switch, and then output to the subsequent drive circuit via the multiplexed controller pin.

[0035] In one possible implementation, the logic unit further includes at least one finite state machine, with one finite state machine corresponding to one of the PWM signals to be reconstructed;

[0036] After the input lookup table detects a rising edge, the corresponding finite state machine switches from the waiting rising edge state to the delay counting state, and the corresponding counter is started.

[0037] After the counter reaches the count value corresponding to the preset dead time delay, the finite state machine switches from the delay counting state to the output high level state, and the corresponding output lookup table converts the output high level state into the high level signal.

[0038] After the output lookup table converts the output high-level state to the high-level signal, the finite state machine switches from the output high-level state to the waiting-for-rising-edge state.

[0039] In one possible implementation, after the input lookup table detects a falling edge or a steady-state level, the logic unit outputs the PWM signal to be reconstructed, which is then connected to the original output path of the pulse modulation module via an output cross switch, and the controller pin is multiplexed to the subsequent drive circuit.

[0040] In a third aspect of this application, an interleaved PFC module is provided, comprising: three power branches and the aforementioned interleaved PFC module controller;

[0041] The interleaved PFC module controller is used to drive the upper and lower power switches of the three power branches.

[0042] This application provides a PWM signal reconstruction method that utilizes logic units in a configurable logic block to acquire the PWM signal to be reconstructed from the pulse modulation module without delay processing of the rising edge. Edge detection is performed on the PWM signal to be reconstructed. If a rising edge is detected, a high-level signal is output to the corresponding subsequent drive circuit after waiting for a preset dead-time delay. Simultaneously, the high-level duration of the reconstructed PWM signal is kept consistent with that of the PWM signal to be reconstructed. Rising edge delays can be independently introduced for the upper and lower transistors, achieving flexible construction of equivalent dead times. This process extends timing control capabilities from the internal resources of the pulse modulation module to the configurable logic block, decoupling the drive signal generation mechanism and enabling fine-grained independent reconstruction of the rising edges of the upper and lower transistor drive signals. This effectively solves the safety hazard of lacking effective dead-time protection in local time periods due to phase-shift strategy adjustments and limited hardware dead-time resources in intermittent conduction mode. This method does not require modification of the original phase-shift control logic of the pulse modulation module. High-precision, differentiated hardware dead-time protection can be achieved solely through the logic configuration within the controller. This decouples and enables the interleaved phase-shift control, DCM multi-interval timing switching, and dead-time timing adjustment to work together. Even under complex operating conditions, it can ensure the integrity of the drive signal timing, thereby improving the system's operational safety and control flexibility. Attached Figure Description

[0043] The above and other features, advantages, and aspects of the embodiments of this disclosure will become more apparent from the accompanying drawings and the following detailed description. Throughout the drawings, the same or similar reference numerals denote the same or similar elements. It should be understood that the drawings are schematic, and the originals and elements are not necessarily drawn to scale.

[0044] Figure 1 A schematic flowchart illustrating a PWM signal reconstruction method provided in an embodiment of this application;

[0045] Figure 2 This is a schematic diagram of PWM signal reconstruction timing provided in an embodiment of this application;

[0046] Figure 3 A flowchart illustrating another PWM signal reconstruction method provided in an embodiment of this application;

[0047] Figure 4 A partial structural diagram of the interleaved PFC module controller provided in an embodiment of this application;

[0048] Figure 5 This is a schematic diagram of the logic unit structure provided in an embodiment of this application. Detailed Implementation

[0049] The embodiments of this application are described below with reference to the accompanying drawings. The terminology used in the implementation section of this application is for explaining specific embodiments only and is not intended to limit the scope of this application.

[0050] The embodiments of this application will now be described with reference to the accompanying drawings. Those skilled in the art will recognize that, with technological advancements and the emergence of new scenarios, the technical solutions provided in the embodiments of this application are equally applicable to similar technical problems.

[0051] The terms "first," "second," etc., used in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such terms are interchangeable where appropriate; this is merely a way of distinguishing objects with the same attributes in the embodiments of this application. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion, so that a process, method, system, product, or apparatus that comprises a series of elements is not necessarily limited to those elements, but may include other elements not explicitly listed or inherent to those processes, methods, products, or apparatuses.

[0052] In engineering, PFC rectifiers are often operated in Discontinuous Conduction Mode (DCM). A single PFC circuit consists of two power switches, an upper and a lower one. A single switching cycle presents three timing sequences: the upper switch is on, both switches are off simultaneously, and the lower switch is on. The upper and lower switches cannot be turned on simultaneously, as this would cause a short circuit between the positive and negative terminals of the power supply, damaging the power devices. Therefore, the PWM signal driving the power switches must be configured with dead-time timing to reserve a safe shutdown window when the upper and lower switch drive signal edges switch.

[0053] To achieve multi-channel PFC interleaved phase shift control, one approach uses the end of the PWM cycle as a synchronization reference, uniformly refreshing the phase offset of the slave channel at the end of the cycle to achieve waveform staggering. This method directly jumps the slave channel counter value during synchronization. If the jumped counter value crosses the comparison point corresponding to the level flip of the current cycle, the counter will skip the pulse generation time, resulting in PWM signal loss and random phase deviation in multiple phases. Furthermore, in DCM mode, the duty cycle dynamically changes in real time with the load and input voltage, and the comparison point value is different every cycle, leading to frequent waveform loss and phase drift problems, causing input current distortion and uneven current stress on devices.

[0054] To address the timing defects caused by cycle boundary synchronization, an improved scheme adjusts the phase-shift synchronization trigger point to the CMPC comparison matching point in the middle of the PWM cycle. The phase shift offset and duty cycle parameters for the next cycle are loaded only when the counter reaches the preset CMPC value. Since all level-to-level transitions within the current cycle are completed before the CMPC event, the parameter update only affects the next switching cycle and does not alter the waveform currently being output. This fundamentally avoids the counter skipping the topping point, eliminating pulse loss and phase deviation issues. It has now become the mainstream phase-shift control scheme for DCM interleaved PFC.

[0055] However, after adopting CMPC comparison matching point triggering phase shift, the pulse modulation module hardware resources only support configuring rising edge delay or dead time control for one output. It cannot set independent turn-on delays for the upper and lower transistors respectively. At the end of the DCM full turn-off window and the moment when the switching transistor is turned on again, the driving edges of the upper and lower transistors are likely to coincide, causing a short circuit. In DCM control scenarios where the conduction time and duty cycle change dynamically, it is impossible to simultaneously meet the dual requirements of stable operation of staggered phase shift and safe protection of the upper and lower transistor drives.

[0056] This application provides a PWM signal reconstruction method, applied to a logic unit (Tile) in a Configurable Logic Block (CLB) of an interleaved PFC module controller operating in DCM mode. The controller also includes a pulse modulation module (ePWM). Each power branch of the interleaved PFC module corresponds to a pulse modulation module. The pulse modulation module implements phase shifting based on the comparison matching point as a synchronization reference and outputs two PWM signals for the upper and lower transistors of the corresponding power branch. Due to hardware resource limitations, the pulse modulation module only supports configuring rising edge delay for one PWM signal. The rising edge delay function of the pulse modulation module can also be disabled through configuration. If this function is disabled, neither of the two PWM signals output by the pulse modulation module has performed rising edge delay processing. Therefore, at least one of the two PWM signals output by the pulse modulation module is a PWM signal to be reconstructed without rising edge delay processing.

[0057] Reference Figure 1 , Figure 1 This is a flowchart illustrating a PWM signal reconstruction method provided in an embodiment of this application, as shown below. Figure 1 As shown in the figure, the PWM signal reconstruction method provided in this application embodiment may include steps 101 to 103, which are described in detail below.

[0058] 101: Receive the two PWM signals output by the pulse modulation module to the upper and lower transistors of the corresponding power branch, and obtain the PWM signal to be reconstructed from the two PWM signals.

[0059] The PWM signal to be reconstructed is a PWM signal for which the rising edge has not been delayed.

[0060] The configurable logic block includes multiple logic units (tiles), with each pulse modulation module corresponding to one logic unit. The configurable logic block receives the PWM signal to be reconstructed from the pulse modulation module through the input crossbar switch (CLBInput XBAR) and inputs it to the corresponding logic unit through the input routing.

[0061] The pulse modulation module uses the comparison matching point as a synchronization reference to achieve phase shifting and outputs two PWM signals corresponding to the upper and lower transistors of the corresponding power branch. Specifically, the pulse modulation module uses the CMPC comparison matching point in the middle of the PWM cycle as the phase shift synchronization trigger point. When the counter reaches the preset CMPC value, it loads the phase shift offset and duty cycle parameters for the next cycle. For example, taking the pulse modulation module corresponding to phase A, this module outputs two PWM signals for the upper and lower transistors of phase A's power branch. If the pulse modulation module enables the delay function, it can only delay the rising edge of one of the two PWM signals, but cannot delay the rising edge of the other PWM signal. The PWM signal whose rising edge is not delayed is the PWM signal to be reconstructed, and the logic unit obtains this PWM signal to be reconstructed. If the pulse modulation module disables the delay function, neither PWM signal has its rising edge delayed, and the logic unit obtains both PWM signals to be reconstructed.

[0062] The PWM signal to be reconstructed is characterized by the ideal switching timing calculated based on the staggered phase shift strategy. It includes high and low level signals that control the turn-on and turn-off of the corresponding power switch. A high level indicates turn-on and a low level indicates turn-off. The rising edge from low level to high level is not delayed.

[0063] 102: Perform edge detection on the PWM signal to be reconstructed.

[0064] Edge detection of the acquired PWM signal to be reconstructed is performed to identify the critical moment when the level signal changes, thereby determining the trigger point for inserting the dead-time delay.

[0065] Specifically, the logic unit includes at least one input lookup table (LUT) for edge detection of the PWM signal to be reconstructed. If there are two PWM signals to be reconstructed, two input lookup tables are needed to perform edge detection on each of the two PWM signals respectively. For example, for one PWM signal to be reconstructed, the PWM signal to be reconstructed is logically operated on with the level signal stored in the register. When the result of the logical operation indicates a transition from a low level to a high level, a rising edge pulse is generated.

[0066] 103: If a rising edge is detected, a high-level signal is output to the corresponding subsequent drive circuit after waiting for a preset dead time delay.

[0067] The preset dead time delay is a parameter that is set in advance based on the switching characteristics of the power switch, the response speed of the drive circuit, and the safety margin requirements of the system. Its specific value can be obtained by referring to the turn-off delay time in the device datasheet and calibrating it in conjunction with engineering experiments.

[0068] The preset dead-time delay can be implemented using a counter in the logic unit. The output signal remains low until the counter reaches the value corresponding to the preset dead-time delay. Once the counter reaches the value corresponding to the preset dead-time delay, the logic unit outputs a high-level signal to the subsequent driver circuit. The start time of the high-level output is shifted backward by the preset dead-time delay relative to the rising edge of the PWM signal to be reconstructed. In other words, the rising edge of the reconstructed PWM signal is delayed by the preset dead-time delay relative to the PWM signal to be reconstructed, and the duration of the high level in the reconstructed PWM signal is exactly the same as that in the PWM signal to be reconstructed. This processing method is equivalent to inserting a dead time before the switching transistor is turned on, effectively avoiding the shoot-through risk caused by the simultaneous conduction of the upper and lower switching transistors, and ensuring the safety and reliability of the interleaved PFC module operating in DCM mode.

[0069] This embodiment provides a PWM signal reconstruction method. The logic units in a configurable logic block utilize edge detection and delay reconstruction mechanisms to convert the PWM signal to be reconstructed into a PWM signal with independent dead-time protection. The upper and lower transistor PWM signals output to the subsequent drive circuit each have independent and adjustable rising edge delays, fundamentally solving the local dead-time problem that may occur during interleaved phase shifting and DCM three-phase switching. This process frees dead-time control from the hardware resource allocation of the pulse modulation module, enabling flexible adaptation to the dynamic changes in conduction time and duty cycle in DCM mode. It achieves refined timing management of dual-transistor drive without relying on fixed modulation rules.

[0070] In one possible implementation, after edge detection of the PWM signal to be reconstructed, if a falling edge or steady-state level is detected, the PWM signal to be reconstructed is directly output to the corresponding subsequent driver circuit. That is, the input lookup table in the logic unit monitors the edge characteristics of the input signal in real time, where the rising edge triggers the delayed reconstruction logic to insert the dead time, while the falling edge and steady-state level correspond to the time periods that do not require timing adjustment.

[0071] When a falling edge is detected, it indicates that the corresponding switch is about to enter the off state. When a steady-state level (including steady-state high level or steady-state low level) is detected, it indicates that the corresponding switch is in a continuous on or continuous off state. No switching state switching that may cause shoot-through risk has occurred. The timing of the current PWM signal is not changed and it is directly output to the subsequent driver circuit.

[0072] By maintaining the timing of the shutdown action and steady-state maintenance action consistent with the original control strategy, and performing targeted edge reconstruction only on rising edges with shoot-through risk, this differentiated processing mechanism introduces dead-time protection while preserving the time-domain characteristics of the original PWM signal to the maximum extent.

[0073] Please see Figure 2 The PWM signal reconstruction timing diagram shown is as follows: the pulse modulation module uses the comparison matching point as the synchronization reference to realize phase shift and outputs two PWM signals of the upper and lower transistors of the corresponding power branch. The logic unit obtains the PWM signal to be reconstructed from the two PWM signals and performs edge detection on the PWM signal to be reconstructed. If a rising edge is detected, a high-level signal is output to the corresponding subsequent drive circuit after waiting for a preset dead time delay. If no rising edge is detected, that is, a falling edge or steady-state level is detected, the PWM signal to be reconstructed is directly output to the corresponding subsequent drive circuit.

[0074] In one possible implementation, step 103 in the above embodiments includes: starting the counter built into the logic unit, and after the counter value reaches the count value corresponding to the preset dead time delay, outputting a high-level signal to the corresponding subsequent driving circuit.

[0075] Specifically, upon detecting a rising edge, a rising edge pulse is output to start the counter built into the logic unit. The counter performs a clearing operation and starts counting. After the counter value reaches the value corresponding to the preset dead time delay, the timing ends, extending the low level duration by the preset dead time delay. Subsequently, a high level is output, thus delaying the rising edge moment by the preset dead time delay.

[0076] This embodiment utilizes the accuracy of hardware counter counting to ensure that the dead time is strictly the preset dead time delay. Even under the condition of dynamic changes in conduction time and duty cycle in DCM mode, this mechanism can still maintain accurate and stable dead time protection, effectively avoiding the shoot-through risk caused by software delay uncertainty.

[0077] In one possible implementation, the state transitions of the logic unit are controlled using the finite state machine (FSM) built into the logic unit. (See [link to relevant documentation]). Figure 3 The schematic diagram of the PWM signal reconstruction method shown in this embodiment includes the following steps 301-307:

[0078] 301: Obtain the PWM signal to be reconstructed from the pulse modulation module.

[0079] 302: Perform edge detection on the PWM signal to be reconstructed.

[0080] 303: After detecting a rising edge, the control finite state machine switches from the waiting rising edge state to the delay counting state.

[0081] A finite state machine is a sequential logic circuit built into a logic unit. It coordinates the various execution steps of PWM signal reconstruction through preset state transition rules, ensuring the determinism and real-time performance of signal processing.

[0082] Initially, the finite state machine (FSM) is in a rising edge waiting state, during which the input lookup table continuously monitors changes in the PWM signal to be reconstructed. When a transition in the PWM signal to be reconstructed is detected and confirmed as a rising edge event, it indicates that the off state of the previous switching cycle has ended and the new switching cycle is about to begin the on state. At this point, to allow for a safe electrical isolation time between the switching of the upper and lower transistors, the FSM is configured to immediately switch from the rising edge waiting state to the delay counting state. This state transition is not only a change in logical state but also directly serves as a trigger signal for the hardware counter, triggering the execution of the start counter step, thereby beginning the precise measurement of the dead time.

[0083] 304: Starts the built-in counter of the configurable logic block.

[0084] 305: After the counter reaches the count value corresponding to the preset dead time delay, the finite state machine is controlled to switch from the delay counting state to the output high level state.

[0085] In delayed counting mode, the counter accumulates counts based on the system clock signal. The preset dead-time delay is a time parameter determined according to the turn-off characteristics of the power switches and the circuit safety margin, ensuring that one switch is completely turned off before the other begins to conduct. When the counter value reaches the value corresponding to the preset dead-time delay, it indicates that the required dead time has elapsed, and the timer ends. At this time, the finite state machine responds to the end of the counter count, and the control state switches from delayed counting mode to output high-level mode. This state switching operation simultaneously triggers the execution of the output action, outputting a high-level signal to the subsequent drive circuit. The rising edge of the reconstructed PWM signal is delayed by the preset dead-time delay compared to the rising edge of the PWM signal to be reconstructed, thus achieving edge reconstruction of the drive signal in terms of physical timing and effectively avoiding the risk of shoot-through.

[0086] 306: Outputs a high-level signal to the corresponding subsequent driver circuit.

[0087] 307: After detecting a falling edge or a steady-state level, the control finite state machine switches from the output high level state to the waiting rising edge state.

[0088] A high-level output indicates that a high-level signal has been successfully output and has turned on the corresponding power switch. To ensure that the logic unit can continuously respond to changes in the next switching cycle, the finite state machine needs to be reset to its initial state. This reset process is determined by the level characteristics of the input signal: when the input lookup table detects that the input PWM signal to be reconstructed maintains a steady-state level (low or high) or a falling edge occurs, the finite state machine control state switches from the high-level output state back to the waiting-for-rising-edge state, completing a complete control loop.

[0089] This embodiment decouples edge detection, delay counting, and signal output into three distinct execution stages using a finite state machine. This transforms the PWM reconstruction process, which originally required complex timing verification, into a simple state transition logic. Thus, without consuming CPU resources, hardware logic ensures the accuracy and reliability of drive signal switching. This state loop mechanism guarantees that regardless of changes in the frequency or duty cycle of the input signal, the finite state machine can trigger the counting delay and signal output in a predetermined logical order. Therefore, even in complex operating conditions like DCM mode where the on-time and duty cycle are not fixed, stable timing control capability is maintained.

[0090] In one possible implementation, a specific implementation of step 102 in the above embodiments includes the following steps 1021-1024:

[0091] 1021: Compare the PWM signal to be reconstructed with the stored level signal.

[0092] The stored level signal can refer to the latest updated level signal state latched by a register or flip-flop.

[0093] Specifically, an input lookup table is used to compare the current sampling point's PWM signal level with the stored level signals. The comparison result characterizes the signal's trend over time and is the basis for determining the signal transition type. This process transforms the continuous waveform in the time domain into a discrete state sequence, capturing signal edges by the differences between adjacent sampling points. This ensures that the corresponding edge event is triggered only when the signal level actually reverses, thus guaranteeing the accuracy and stability of the detection.

[0094] 1022: If the comparison result indicates that the level signal jumps from low level to high level, then it is determined that a rising edge has been detected, and the stored level signal is updated to high level.

[0095] In a register or flip-flop, 0 represents a low level and 1 represents a high level. If the PWM signal to be reconstructed at the current sampling point is a high level and the stored level signal is 0, then the comparison result represents the moment when logic 0 changes to logic 1, i.e., the rising edge.

[0096] Upon detecting a rising edge, the stored level signal is simultaneously updated to a high level. This update operation ensures the timeliness of the reference data for the next comparison, guaranteeing the correct identification of any subsequent falling edges or steady states.

[0097] 1023: If the comparison result indicates that the level signal has changed from high level to low level, then it is determined that a falling edge has been detected, and the stored level signal is updated to low level.

[0098] Under this condition, the moment when the signal changes from logic 1 to logic 0, i.e., the falling edge, is identified. After confirming that the falling edge has been detected, a storage update operation is also performed, setting the stored level signal to low.

[0099] 1024: If the comparison result indicates that the level signal remains unchanged, then it is determined that a steady-state level has been detected, and the stored level signal remains unchanged.

[0100] When the comparison result shows that the current sampling point level signal matches the stored level signal, a steady-state level is detected. At this point, it is neither a rising nor falling edge, and the signal level has not flipped. In this situation, no edge-related control actions, such as starting a dead-time counter, are needed, and the data in the memory cell remains unchanged. This processing logic avoids invalid operations and frequent writes to memory resources during signal stability.

[0101] The complete coverage of the above three scenarios enables accurate edge analysis and state management throughout the entire lifecycle of the PWM signal to be reconstructed. This mechanism of real-time judgment and updating constructs a closed-loop state tracking link, ensuring that the stored level signal remains synchronized with the actual state of the input signal, providing an accurate comparison benchmark for edge detection.

[0102] This application also provides an interleaved PFC module controller, including a pulse modulation module and a configurable logic block.

[0103] A configurable logic block comprises multiple logic units.

[0104] Each phase of the interleaved PFC module corresponds to a power branch, and each power branch corresponds to a pulse modulation module and a logic unit.

[0105] The pulse modulation module is used to perform phase shifting with the comparison matching point as the synchronization reference, and output two PWM signals for the upper and lower transistors of the corresponding power branch. Among them, at least one of the two PWM signals is a PWM signal to be reconstructed without delay processing of the rising edge.

[0106] The logic unit acquires the PWM signal to be reconstructed from the pulse modulation module, performs edge detection on the PWM signal to be reconstructed, and if a rising edge is detected, it outputs a high-level signal to the corresponding subsequent drive circuit after waiting for a preset dead time delay to drive the power switch of the corresponding power branch.

[0107] Due to hardware resource limitations, the pulse modulation module only supports configuring a rising edge delay for one PWM signal. This rising edge delay function can also be disabled through configuration. If disabled, neither of the two PWM signals output by the pulse modulation module will have its rising edge delayed, meaning both PWM signals are PWM signals to be reconstructed. If disabled, only one of the two PWM signals output by the pulse modulation module will not have its rising edge delayed, meaning only one PWM signal will exist to be reconstructed. Therefore, at least one of the two PWM signals output by the pulse modulation module will be a PWM signal to be reconstructed without rising edge delay. Please refer to [link to relevant documentation]. Figure 4 The schematic diagram of a partial structure of the interleaved PFC module controller, taking the pulse modulation module 1 with the delay function enabled as an example, shows that the pulse modulation module 1 uses the delay function to delay the rising edge of a PWM signal, which is directly output to the subsequent drive circuit through the controller pin A1 to drive the corresponding power switch. The PWM signal to be reconstructed without delaying the rising edge is routed to logic unit 1 through the input crossbar switch (CLBInput XBAR). After the logic unit 1 reconstructs the rising edge of the PWM signal to be reconstructed, it is connected to the original output path of the pulse modulation module 1 through the output crossbar switch (CLBOutput XBAR), and multiplexed to the subsequent drive circuit through the controller pin B1 to drive the corresponding power switch.

[0108] Please see Figure 5 The schematic diagram of the logic unit structure shown includes at least one input look-up table (LUT), at least one counter, at least one finite state machine (FSM), and at least one output look-up table (OUTLUT). Each PWM signal to be reconstructed corresponds to one input look-up table, one counter, one finite state machine, and one output look-up table.

[0109] The input lookup table can perform multi-input Boolean logic operations based on a preset truth table. In one possible implementation, by configuring the logic function of the input lookup table, the level state of the PWM signal to be reconstructed at the current sampling point can be compared with the level state stored at the previous sampling point, thereby identifying the trend of level signal changes and achieving edge detection. Specifically, the input lookup table compares the PWM signal to be reconstructed with the stored level signal; if the comparison result indicates that the level signal jumps from low to high, a rising edge is detected, and the stored level signal is updated to high; if the comparison result indicates that the level signal jumps from high to low, a falling edge is detected, and the stored level signal is updated to low; if the comparison result indicates that the level signal remains unchanged, a steady-state level is detected, and the stored level signal remains unchanged.

[0110] In one possible implementation, the counter receives a rising edge pulse signal from the input lookup table output, resets the counter to zero, and begins counting. After the counter value reaches the value corresponding to the preset dead-time delay, the corresponding output lookup table outputs a high-level signal, which is then connected to the original output path of the pulse modulation module via an output crossbar switch, and output to the subsequent driver circuit via the multiplexed controller pin.

[0111] When the current count value of the counter reaches the count value corresponding to the preset dead-time delay, the counter stops counting, indicating the end of the dead-time waiting phase and enabling the output drive level. Through this count-based delay implementation, the logic unit can provide an independent and precisely controllable rising edge delay for each phase and each transistor, effectively solving the problem of insufficient dead-time protection caused by limited hardware resources in the pulse modulation module.

[0112] The output crossbar switch flexibly routes high-level signals to the controller's existing physical pins. In this embodiment, one end of the output crossbar switch is connected to the output terminal of the output lookup table, and the other end is connected to the original output path of the pulse modulation module. By configuring the internal connection matrix of the output crossbar switch, the high-level signal generated by the logic unit can be seamlessly switched to the controller pin originally intended for outputting the PWM signal. This design achieves controller pin reuse, meaning that there is no need to allocate new physical pins for the reconstructed PWM signal; instead, the pin resources pre-allocated by the pulse modulation module are directly reused. No modification to the interleaved PFC module controller is required, and the subsequent drive circuit does not need to detect whether the signal originates from the pulse modulation module or is reconstructed by the logic unit; it only needs to obtain the drive signal from the original controller pin.

[0113] In one possible implementation, after a rising edge is detected in the input lookup table, the corresponding finite state machine switches from the waiting-for-rising-edge state to the delay-counting state, and starts the corresponding counter.

[0114] After the counter reaches the value corresponding to the preset dead-time delay, the finite state machine switches from the delay counting state to the output high-level state. The corresponding output lookup table converts the output high-level state into a high-level signal. Through precise monitoring of the counting process by the finite state machine, it is ensured that the output state is only allowed to flip after the preset safe dead time has elapsed, effectively preventing damage to the power switch due to shoot-through. Simultaneously, the output lookup table maps the logic state of the state machine to the actual drive level signal. The output lookup table performs signal generation and routing mapping functions within the logic unit. It contains a preset logic truth table or mapping relationship. When the finite state machine switches from the delay counting state to the output high-level state, the output lookup table converts the output high-level state into a high level according to the preset output strategy, thus generating a high-level signal. The rising edge of the reconstructed PWM signal lags behind the preset dead-time delay relative to the PWM signal to be reconstructed, but its high-level duration remains consistent with the high-level duration of the PWM signal to be reconstructed, ensuring that the original energy transfer control logic is not altered. The output lookup table has an extremely high response speed, capable of responding to state changes without delay, ensuring the real-time performance and accuracy of the drive signals.

[0115] After the output lookup table converts the output high-level state to a high-level signal, the finite state machine switches from the output high-level state to the waiting-for-rising-edge state. This state switching mechanism ensures that the logic unit can continuously and cyclically process the input PWM signal to be reconstructed, preparing for the detection and delay processing of the next rising edge, thus realizing real-time and dynamic reconstruction of continuous PWM waveforms.

[0116] This embodiment achieves precise scheduling of the PWM signal reconstruction process using a finite state machine in an interleaved PFC module controller, ensuring the logical rigor and timing accuracy between edge detection, dead-time delay counting, and signal output. Because the finite state machine can clearly define the three independent states—waiting for the rising edge, delay counting, and outputting a high level—and their transition conditions, it avoids logic races and false triggers. Thus, in the complex and variable switching timing of DCM mode, it constructs stable and reliable dead-time protection for the drive signals of the upper and lower transistors, significantly improving the system's operational safety and robustness.

[0117] In one possible implementation, after the input lookup table detects a falling edge or a steady-state level, it indicates that the current signal edge does not require dead-time reconstruction or is in a level-holding phase. The logic unit outputs the un-delayed PWM signal to be reconstructed, which is then connected to the original output path of the pulse modulation module via an output crossbar switch, and the multiplexed controller pin output is sent to the subsequent driver circuit. This embodiment implements intelligent routing selection for different signal edge types. During the rising edge phase, a dead time is inserted through the rising edge reconstruction logic of the PWM signal to ensure safety. During the falling edge or steady-state phase, the original signal timing is maintained, thereby ensuring the safety of the drive signal while maintaining the integrity of signal transmission and the system's response speed.

[0118] This application embodiment also provides an interleaved PFC module, including: three power branches and any of the interleaved PFC module controllers provided in this application embodiment;

[0119] The interleaved PFC module controller is used to drive the upper and lower power switches of the three power branches.

[0120] Each power branch corresponds to a pulse modulation module and a logic unit. A set of pulse modulation modules and logic units output two PWM signals for the same power branch. Both PWM signals have their rising edges delayed, enabling fine-grained independent reconstruction of the rising edges of the upper and lower transistor drive signals. This effectively solves the safety hazard of no effective dead-time protection in local periods due to phase shift strategy adjustment and limited hardware dead-time resources in intermittent conduction mode.

[0121] In the above embodiments, implementation can be achieved, in whole or in part, through software, hardware, firmware, or any combination thereof. When implemented in software, it can be implemented, in whole or in part, as a computer program product. A computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the flow or function according to the embodiments of this application is generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, fiber optic, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that integrates one or more available media. The available medium can be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape) or a semiconductor medium (e.g., solid-state disk (SSD)).

[0122] This application also provides a readable storage medium for storing the methods provided in the above embodiments. Examples include random access memory (RAM), flash memory, read-only memory (ROM), EPROM, non-volatile read-only memory (EPROM), registers, hard disks, removable disks, or any other form of storage medium in the art.

[0123] It should be noted that the various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. Regarding the methods disclosed in the embodiments, since they correspond to the product embodiments disclosed in the embodiments, the description is relatively simple; relevant parts can be referred to in the description of the product embodiments.

[0124] The above description of the disclosed embodiments enables those skilled in the art to make or use this application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of this application. Therefore, this application is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A PWM signal reconstruction method, characterized in that, A logic unit applied in a configurable logic block in an interleaved PFC module controller, the interleaved PFC module controller further comprising a pulse modulation module, the method comprising: The pulse modulation module outputs two PWM signals to the upper and lower transistors of the corresponding power branch, and obtains the PWM signal to be reconstructed from the two PWM signals, wherein the PWM signal to be reconstructed is a PWM signal without delay processing of the rising edge; Edge detection is performed on the PWM signal to be reconstructed; If a rising edge is detected, a high-level signal is output to the corresponding subsequent driver circuit after waiting for a preset dead time delay.

2. The PWM signal reconstruction method according to claim 1, characterized in that, The step of outputting a high-level signal to the corresponding subsequent drive circuit after waiting for a preset dead time delay includes: Start the built-in counter of the logic unit; After the counter reaches the count value corresponding to the preset dead time delay, a high-level signal is output to the corresponding subsequent drive circuit.

3. The PWM signal reconstruction method according to claim 2, characterized in that, The activation of the built-in counter in the logic unit includes: If a rising edge is detected, the finite state machine is controlled to switch from the waiting rising edge state to the delay counting state, triggering the execution of the step of starting the counter built into the logic unit; The step of outputting a high-level signal to the corresponding subsequent drive circuit after the counter reaches the count value corresponding to the preset dead-time delay includes: After the counter reaches the count value corresponding to the preset dead time delay, the finite state machine is controlled to switch from the delay counting state to the output high level state, triggering the execution of the step of outputting a high level signal to the corresponding subsequent drive circuit.

4. The PWM signal reconstruction method according to claim 1, characterized in that, After edge detection of the PWM signal to be reconstructed, the method further includes: If a falling edge or steady-state level is detected, the PWM signal to be reconstructed is directly output to the corresponding subsequent drive circuit.

5. The PWM signal reconstruction method according to claim 4, characterized in that, If a falling edge or steady-state level is detected, the PWM signal to be reconstructed is directly output to the corresponding subsequent driving circuit, including: If a falling edge or steady-state level is detected, the finite state machine is controlled to switch from the output high level state to the waiting rising edge state, triggering the execution of the edge detection step for the PWM signal to be reconstructed.

6. The PWM signal reconstruction method according to claim 1, characterized in that, The edge detection of the PWM signal to be reconstructed includes: The PWM signal to be reconstructed is compared with the stored level signal; If the comparison result indicates that the level signal jumps from low level to high level, then it is determined that a rising edge has been detected, and the stored level signal is updated to high level. If the comparison result indicates that the level signal has changed from high level to low level, then it is determined that a falling edge has been detected, and the stored level signal is updated to low level. If the comparison result indicates that the level signal remains unchanged, then it is determined that a steady-state level has been detected, and the stored level signal remains unchanged.

7. An interleaved PFC module controller, characterized in that, include: Pulse modulation module and configurable logic block; The configurable logic block includes multiple logic units; Each power branch of the interleaved PFC module corresponds to one of the pulse modulation modules and one of the logic units; The pulse modulation module is used to perform phase shifting with the comparison matching point as the synchronization reference, and output two PWM signals for the upper and lower transistors of the corresponding power branch. Among them, at least one of the two PWM signals is a PWM signal to be reconstructed without delay processing of the rising edge. The logic unit acquires the PWM signal to be reconstructed output by the pulse modulation module, performs edge detection on the PWM signal to be reconstructed, and if a rising edge is detected, it outputs a high-level signal to the corresponding subsequent drive circuit after waiting for a preset dead time delay to drive the power switch of the corresponding power branch.

8. The interleaved PFC module controller according to claim 7, characterized in that, The logic unit includes at least one input lookup table, which corresponds to one of the PWM signals to be reconstructed. The input lookup table compares the PWM signal to be reconstructed with the stored level signals; If the comparison result indicates that the level signal jumps from low to high, then a rising edge is detected, and the stored level signal is updated to high. If the comparison result indicates that the level signal jumps from high to low, then a falling edge is detected, and the stored level signal is updated to low. If the comparison result indicates that the level signal remains unchanged, then a steady-state level is detected, and the stored level signal remains unchanged.

9. The interleaved PFC module controller according to claim 8, characterized in that, The logic unit further includes at least one counter and an output lookup table, with each of the PWM signals to be reconstructed corresponding to a counter and an output lookup table; After the input lookup table detects a rising edge, it starts the corresponding counter. After the counter reaches the count value corresponding to the preset dead time delay, the corresponding output lookup table outputs the high-level signal, which is connected to the original output path of the pulse modulation module via the output cross switch, and then output to the subsequent drive circuit via the multiplexed controller pin.

10. The interleaved PFC module controller according to claim 9, characterized in that, The logic unit further includes at least one finite state machine, with one finite state machine corresponding to one of the PWM signals to be reconstructed. After the input lookup table detects a rising edge, the corresponding finite state machine switches from the waiting rising edge state to the delay counting state, and the corresponding counter is started. After the counter reaches the count value corresponding to the preset dead time delay, the finite state machine switches from the delay counting state to the output high level state, and the corresponding output lookup table converts the output high level state into the high level signal. After the output lookup table converts the output high-level state to the high-level signal, the finite state machine switches from the output high-level state to the waiting-for-rising-edge state.

11. The interleaved PFC module controller according to claim 9, characterized in that, After the input lookup table detects a falling edge or a steady-state level, the logic unit outputs the PWM signal to be reconstructed, which is then connected to the original output path of the pulse modulation module via an output cross switch, and the controller pin is multiplexed to the subsequent drive circuit.

12. An interleaved PFC module, characterized in that, include: Three power branches and an interleaved PFC module controller as described in any one of claims 7 to 11; The interleaved PFC module controller is used to drive the upper and lower power switches of the three power branches.

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