Power optimized charge pump circuit and passive radio frequency chip

Abstract

The application relates to the technical field of integrated circuits, and provides a power-optimized charge pump circuit and a passive radio frequency chip. The circuit comprises a charge pump module and a clocked limiting module comprising a capacitor voltage division sampling unit, a limiting switch comparator unit and an inverting clock generation unit. The charge pump module is used for generating an output voltage based on an input voltage under the control of a bleeder enable signal and an internal clock signal output by the inverting clock generation unit. The capacitor voltage division sampling unit is used for voltage division sampling of the output voltage to output a sampling voltage. The limiting switch comparator unit is used for outputting a clock enable signal based on a received reference voltage and the sampling voltage under the control of a limiting enable signal. The inverting clock generation unit is used for outputting the internal clock signal based on the clock enable signal under the control of a system clock signal. The application can effectively reduce power consumption and chip area and improve the stability of the output voltage.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, specifically to a power-optimized charge pump circuit and a passive radio frequency chip. Background Technology

[0002] Existing charge pump circuits typically operate under a fixed input voltage. However, in RF passive chip applications, the chip's spatial position may continuously change during dynamic read / write operations, causing significant fluctuations in the chip's input voltage. This wide range of input voltage fluctuations negatively impacts existing charge pumps operating under fixed input voltage conditions: insufficient output voltage will fail to generate enough tunneling current, leading to EEPROM memory erase operations failure; while excessively high output voltage will result in excessive tunneling current, creating defects in the thin dielectric oxide layer and impairing device lifespan and performance.

[0003] To ensure the reliability of memory cells in passive chips, the limiting circuit design at the charge pump output needs to balance voltage accuracy and power consumption. Current mainstream limiting and regulating solutions involve using diode clamping or an LDO to construct a high-voltage discharge path. While the diode solution offers the advantage of simple structure, it suffers from significant temperature drift and cannot precisely control the limiting voltage. The LDO solution offers fast response and high voltage regulation accuracy, but typically has a large quiescent current.

[0004] To address the aforementioned issues, a clock-modulated limiting scheme can be employed, controlling the charge pump's output voltage by adjusting the clock frequency, duty cycle, or start-stop timing. Its advantage lies in lower static power consumption during shutdown, but it requires addressing ripple degradation caused by clock jitter. Summary of the Invention

[0005] The purpose of this application is to provide a power-optimized charge pump circuit and a passive RF chip that can effectively reduce power consumption and chip area, and effectively control voltage output ripple.

[0006] To achieve the above objectives, this application provides a power-optimized charge pump circuit, comprising: a charge pump module and a clock-controlled limiting module. The clock-controlled limiting module includes a capacitor voltage divider sampling unit, a limiting switch comparator unit, and an inverting clock generation unit. The charge pump module is coupled to the inverting clock generation unit and is used to generate an output voltage based on the input voltage under the control of a bleed enable signal and an internal clock signal output by the inverting clock generation unit. The capacitor voltage divider sampling unit is coupled to the charge pump module and is used to perform voltage divider sampling on the output voltage to output a sampled voltage. The limiting switch comparator unit is coupled to the capacitor voltage divider sampling unit and is used to output a clock enable signal based on a received reference voltage and the sampled voltage under the control of a limiting enable signal. The inverting clock generation unit is coupled to the limiting switch comparator unit and is used to output an internal clock signal based on the clock enable signal under the control of a system clock signal.

[0007] To achieve the above objectives, this application also provides a passive radio frequency chip, which includes a power-optimized charge pump circuit as described in any embodiment of this application.

[0008] The above technical solution, by adding a clock control limiting module including a capacitor voltage divider sampling unit, a limiting switch comparator unit, and an inverting clock generation unit, can effectively reduce power consumption and chip area, effectively control voltage output ripple, avoid noise interference caused by clock jitter, and improve the stability of output voltage. Attached Figure Description

[0009] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the embodiments of this application will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0010] Figure 1 A schematic diagram of the architecture of a power-optimized charge pump circuit provided in an embodiment of this application; Figure 2 A circuit diagram of a capacitor voltage divider sampling unit provided in an embodiment of this application; Figure 3 A circuit diagram of a limiting switch comparator unit provided in an embodiment of this application; Figure 4 A circuit diagram of an inverting clock generation unit provided in an embodiment of this application; Figure 5 A circuit diagram of a charge pump module provided in an embodiment of this application; Figure 6A circuit diagram of a charge pump module provided in another embodiment of this application; Figure 7 Simulation results of the power-optimized charge pump circuit provided in the embodiments of this application are shown in the figure. Figure 8 This is a schematic diagram of a passive radio frequency chip according to an embodiment of this application. Detailed Implementation

[0011] The technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0012] Please see Figure 1 This is a schematic diagram of the architecture of a power-optimized charge pump circuit provided in an embodiment of this application. Figure 1 As shown, a power-optimized charge pump circuit 10 provided in one embodiment of this application may include a charge pump module 11 and a clock-controlled limiting module 12. The clock-controlled limiting module 12 may include a capacitor voltage divider sampling unit 121, a limiting switch comparator unit 122, and an inverting clock generation unit 123.

[0013] Specifically, the charge pump module 11 is coupled to the inverting clock generation unit 123 and is used to generate an output voltage VHH based on the input voltage VIN under the control of the bleed enable signal and the internal clock signal output by the inverting clock generation unit 123.

[0014] In this embodiment, the capacitive voltage divider sampling unit 121 is coupled to the charge pump module 11 and is used to perform voltage divider sampling on the output voltage VHH to output a sampled voltage Vc0. The capacitive voltage divider sampling unit 121 uses capacitive voltage divider, which not only significantly reduces the chip area but also greatly reduces static power consumption. Furthermore, the voltage divider capacitor can also serve as the output load capacitor of the charge pump, further improving the stability of the output voltage.

[0015] In this embodiment, the limiting switch comparator unit 122 is coupled to the capacitor voltage divider sampling unit 121 and, under the control of the limiting enable signal, outputs a clock enable signal CLK_EN based on the received reference voltage Vref and the sampled voltage Vc0. The limiting switch comparator unit 122 can be a low-voltage differential comparator with an enable function. Under the control of the limiting enable signal, it compares the reference voltage Vref with the sampled voltage Vc0 and outputs the clock enable signal CLK_EN to control the clock start / stop of the inverting clock generation unit 123. Through the limiting enable signal control, this unit circuit has zero static power consumption when turned off, adapting to the low-power design of the chip. The limiting enable signal may include a positive limiting enable signal Lit_EN and a negative limiting enable signal Lit_E.

[0016] In this embodiment, the inverting clock generation unit 123 is coupled to the limiting switch comparator unit 122 and is used to output an internal clock signal based on the clock enable signal CLK_EN under the control of the system clock signal CLK. The internal clock signal may include an internal clock positive signal CLK_CP and an internal clock negative signal CLKN_CP. Simultaneously, the internal clock signal of the inverting clock generation unit 123 can be forcibly shut down by controlling the clock enable signal CLK_EN, causing the charge pump module 11 to stop boosting voltage and achieving static shutdown protection.

[0017] Furthermore, the charge pump module 11 may include multiple charge pump units 111~11n connected in series. Each charge pump unit, under the control of the bleed current enable signal and the internal clock signal, boosts the received voltage and outputs it. Specifically, the first-stage charge pump unit 111 receives the input voltage VIN and outputs a boosted voltage Vcp1; each subsequent charge pump unit, excluding the first-stage charge pump unit 111, receives the boosted voltage from the previous stage charge pump unit; the last-stage charge pump unit 11n outputs the output voltage VHH. Specifically, the number of charge pump units can be an even number, such as 16 stages.

[0018] This embodiment, by adding a clock-controlled limiting module including a capacitor voltage divider sampling unit, a limiting switch comparator unit, and an inverting clock generation unit, can effectively reduce power consumption and chip area, and improve the stability of the output voltage. At the same time, under the control of the system clock signal, an internal clock signal is output based on the clock enable signal to supply the charge pump module. It can also force the internal clock signal supplied to the charge pump module to be turned off by the clock enable signal, so that the charge pump module stops boosting voltage and realizes static shutdown protection.

[0019] Please see Figure 2 This is a circuit diagram of a capacitor voltage divider sampling unit provided in an embodiment of this application. Figure 2As shown, in this embodiment, the capacitor voltage divider sampling unit 121 may include multi-stage voltage divider capacitors C0~C3.

[0020] Specifically, multi-stage voltage divider capacitors C0~C3 are connected in series between the output terminal of the charge pump module 11 and the ground terminal GND. Each voltage divider capacitor is used to divide and sample the output voltage VHH, and output the sampled voltage Vc0 through the coupling point of the two voltage divider capacitors closest to the ground terminal GND (in this embodiment, the voltage divider capacitor closest to the ground terminal GND is voltage divider capacitor C0, and the coupling point of the output sampled voltage Vc0 is the coupling point of voltage divider capacitor C0 and voltage divider capacitor C1).

[0021] In this embodiment, a four-stage voltage divider capacitor set C0~C3 is used to improve layout matching, and the capacitors have no DC power consumption, making them suitable for low-power charge pump modules. In some embodiments, the number of the voltage divider capacitors is adjustable; increasing or decreasing the number of the voltage divider capacitors can change the sampling voltage Vc0.

[0022] In this embodiment, the relationship between the sampling voltage Vc0 and the output voltage VHH is: Vc0 = VHH * (1 / C0) / (1 / C0 + 1 / C1 + 1 / C2 + 1 / C3).

[0023] In this embodiment, the voltage divider capacitors are proportional capacitors, specifically, C0:C1:C2:C3=6:1:1:1. In a practical layout, nine capacitors of the same size can be set, of which six are voltage divider capacitors C0.

[0024] Furthermore, the capacitor voltage divider sampling unit 121 may also include a plurality of bleed transistors MN1_lk~MN3_lk; the plurality of bleed transistors MN1_lk~MN3_lk are respectively coupled between the coupling point of two adjacent voltage divider capacitors and the ground terminal GND, and the control terminals of all the bleed transistors MN1_lk~MN3_lk are controlled by the bleed enable signal to discharge the output voltage VHH.

[0025] The discharge enable signal may include a positive discharge enable signal Discharge_EN and a negative discharge enable signal Discharge_E. In this embodiment, the positive discharge enable signal Discharge_EN is coupled to the charge pump module 11 and can be used to control the charge pump module 11, while the negative discharge enable signal Discharge_E is coupled to the discharge transistors MN1_lk~MN3_lk and can be used to control the discharge transistors MN1_lk~MN3_lk.

[0026] In this embodiment, all the current-discharging transistors MN1_lk~MN3_lk are N-type transistors. The source of each current-discharging transistor MN1_lk~MN3_lk is connected to the ground terminal GND, and the drain of each current-discharging transistor MN1_lk~MN3_lk is coupled to the coupling point of two adjacent voltage-dividing capacitors. The gate of each current-discharging transistor MN1_lk~MN3_lk is coupled to and controlled by the current-discharging enable inverse signal Discharge_E. When the current-discharging enable inverse signal Discharge_E is low, all current-discharging transistors MN1_lk~MN3_lk are turned off, and there is no discharge current; the output voltage VHH normally supplies the voltage-dividing capacitors of each stage. When the current-discharging enable inverse signal Discharge_E is high, all current-discharging transistors MN1_lk~MN3_lk are turned on, forming a discharge path from each coupling point to the ground terminal GND, avoiding excessive voltage division of a single transistor, which could lead to overvoltage breakdown. Controllable discharge is controlled by a single discharge enable signal Discharge_E, eliminating the need for multiple drives and simplifying the logic; each discharge transistor only conducts when discharge is required, and there is no leakage during normal operation.

[0027] Please see Figure 3 This is a circuit diagram of a limiting switch comparator unit provided in an embodiment of this application. Figure 3 As shown, in this embodiment, the limiting switch comparator unit 122 may include: a switch subunit 31, a comparator subunit 32, and an amplification and shaping subunit 33.

[0028] Specifically, the switching subunit 31 is coupled to the reference voltage Vref and the power supply voltage VDD, and is used to select the output of the reference voltage Vref or the power supply voltage VDD under the control of the limiting enable signal. The first comparison terminal of the comparator subunit 32 is coupled to the output terminal of the switching subunit 31, the second comparison terminal of the comparator subunit 32 receives the sampled voltage Vc0, and the output terminal of the comparator subunit 32 outputs the comparison result. The amplification and shaping subunit 33 is coupled to the output terminal of the comparator subunit 32, and is used to amplify and shape the comparison result to generate the clock enable signal CLK_EN and output it.

[0029] Further, the limiting enable signal may include a limiting enable positive signal Lit_EN and a limiting enable inverse signal Lit_E. The switching subunit 31 may include a first transmission gate T1 and a second transmission gate T2. The receiving terminal of the first transmission gate T1 receives the reference voltage Vref, and the control terminal of the first transmission gate T1 receives the limiting enable positive signal Lit_EN and the limiting enable inverse signal Lit_E, respectively. The receiving terminal of the second transmission gate T2 receives the power supply voltage VDD, and the control terminal of the second transmission gate T2 receives the limiting enable positive signal Lit_EN and the limiting enable inverse signal Lit_E, respectively. The output terminals of the first transmission gate T1 and the second transmission gate T2 are coupled to the output terminals of the switching subunit 31. The signals received by the in-phase control terminals of the first transmission gate T1 and the second transmission gate T2 are opposite.

[0030] The working logic of the switching subunit 31 is as follows: when the limiting enable positive signal Lit_EN is low, the first transmission gate T1 is turned on and the second transmission gate T2 is turned off, and the switching subunit 31 outputs the reference voltage Vref to the non-inverting input of the comparator subunit 32; when the limiting enable positive signal Lit_EN is high, the first transmission gate T1 is turned off and the second transmission gate T2 is turned on, and the switching subunit 31 outputs the power supply voltage VDD to the non-inverting input of the comparator subunit 32.

[0031] Furthermore, the comparator subunit 32 may include: a first transistor MN1_C, a second transistor MN2_C, a third transistor MP1_C, a fourth transistor MP2_C, and a first load transistor MN3_C.

[0032] In this embodiment, the first transistor MN1_C is coupled between the first node Q1 and the second node Q2, and the control terminal of the first transistor MN1_C is connected to the output terminal of the switching subunit 31. The second transistor MN2_C is coupled between the output terminal of the comparator subunit 32 and the second node Q2, and the control terminal of the second transistor MN2_C is controlled by the sampling voltage Vc0. The first transistor MN1_C and the second transistor MN2_C form an input differential pair.

[0033] In this embodiment, the third transistor MP1_C is coupled between the power supply voltage terminal VDD and the first node Q1, and the control terminal of the third transistor MP1_C is shorted to the first node Q1. The fourth transistor MP2_C is coupled between the power supply voltage terminal VDD and the output terminal of the comparator subunit 32, and the control terminal of the fourth transistor MP2_C is shorted to the first node Q1. The third transistor MP1_C and the fourth transistor MP2_C form a current mirror.

[0034] In this embodiment, the first load transistor MN3_C is coupled between the second node Q2 and the ground terminal GND, and the control terminal of the first load transistor MN3_C is controlled by the bias voltage Vbias. Using a transistor instead of a resistor as a load can improve gain, suppress power supply noise, improve common-mode rejection ratio, and generate a constant tail current.

[0035] Further, the amplification and shaping subunit 33 may include: an amplification transistor MP3_C, a second load transistor MN4_C, and a shaping inverter INV4. The amplification transistor MP3_C and the second load transistor MN4_C are connected in series between the power supply voltage terminal VDD and the ground terminal GND. The control terminal of the amplification transistor MP3_C is coupled to the output terminal of the comparator subunit 32, and the control terminal of the second load transistor MN4_C is controlled by the bias voltage Vbias. The input terminal of the shaping inverter INV4 is coupled to the common terminal between the amplification transistor MP3_C and the second load transistor MN4_C, and the output terminal of the shaping inverter INV4 outputs the clock enable signal CLK_EN.

[0036] In this embodiment, the first transistor MN1_C, the second transistor MN2_C, the first load transistor MN3_C, and the second load transistor MN4_C are all N-type transistors; the third transistor MP1_C, the fourth transistor MP2_C, and the amplifying transistor MP3_C are all P-type transistors.

[0037] Please see Figure 4 This is a circuit diagram of an inverting clock generation unit provided in an embodiment of this application. In this embodiment, the internal clock signal may include an internal clock positive signal CLK_CP and an internal clock inverse signal CLKN_CP; the inverting clock generation unit 123 may include: a NAND gate NAND1, an initial inverter INV0, an isolation transmission gate T0, a first NOR gate NOR1, a second NOR gate NOR2, a first inverter INV1, and a second inverter INV2.

[0038] Specifically, the first input of the NAND gate NAND1 receives the system clock signal CLK, and the second input of the NAND gate NAND1 receives the clock enable signal CLK_EN. The input of the initial inverter INV0 is coupled to the output of the NAND gate NAND1, and the output of the initial inverter INV0 is coupled to the second NOR gate NOR2. The input of the isolation transmission gate T0 is coupled to the output of the NAND gate NAND1, and the control terminal of the isolation transmission gate T0 is coupled to the power supply voltage terminal VDD and the ground terminal GND, respectively. The first input terminal of the first NOR gate NOR1 is coupled to the output terminal of the isolation transmission gate T0, and the second input terminal of the first NOR gate NOR1 is coupled to the output terminal of the second NOR gate NOR2; the first input terminal of the second NOR gate NOR2 is coupled to the output terminal of the first NOR gate NOR1, and the second input terminal of the second NOR gate NOR2 is coupled to the output terminal of the initial inverter INV0; that is, the first NOR gate NOR1 and the second NOR gate NOR2 form a symmetrical dual-channel interlocking structure, generating a pair of non-overlapping complementary clock signals (i.e., the internal clock positive signal CLK_CP and the internal clock inverse signal CLKN_CP), ensuring that CLK_CP and CLKN_CP will not be high at the same time, avoiding the simultaneous conduction of the charge pump's internal charging and discharging tubes, which could cause a power supply short circuit and high current breakdown. The input terminal of the first inverter INV1 is coupled to the output terminal of the first NOR gate NOR1, and the output terminal of the first inverter INV1 outputs the internal clock positive signal CLK_CP. The input of the second inverter INV2 is coupled to the output of the second NOR gate NOR2, and the output of the second inverter INV2 outputs the internal clock inversion signal CLKN_CP. The two-stage inverters INV1 and INV2 respectively shape and drive the outputs of the two NOR gates NOR1 and NOR2 to smooth the edges and improve the driving capability.

[0039] Please see Figure 5 This is a circuit diagram of a charge pump module provided in an embodiment of this application. Figure 5 As shown, in this embodiment, each charge pump unit may include a charge pump main unit 51, which may include a main charging transistor, a main boost transmission transistor, a main bleeder transistor, and a main capacitor.

[0040] Specifically, the main charging transistor is coupled between the main input node and the main node, and the control terminal of the main charging transistor is coupled to the first control node CN1. The main input node receives the input voltage VIN or the boost voltage output by the previous stage charge pump main unit. Specifically, the main input node of the first stage charge pump unit receives the input voltage VIN.

[0041] In this embodiment, the main boost transfer transistor is coupled between the main node and the main output node, and the control terminal of the main boost transfer transistor is coupled to the first control node CN1. The main output node outputs the boosted voltage. Specifically, the main output node of the last stage charge pump unit outputs the output voltage VHH.

[0042] In this embodiment, the main bleeder transistor is coupled between the main node and the power supply voltage terminal VDD, and the control terminal of the main bleeder transistor is controlled by the bleeder enable signal. The bleeder enable signal is the positive bleeder enable signal Discharge_EN.

[0043] In this embodiment, one end of the main capacitor is coupled to the main node, and the other end of the main capacitor is coupled to the second control node CN2.

[0044] The internal clock signal may include an internal clock positive signal CLK_CP and an internal clock negative signal CLKN_CP. The first control node CN1 receives one of the internal clock positive signal CLK_CP and the internal clock negative signal CLKN_CP, and the second control node CN2 receives the other of the internal clock positive signal CLK_CP and the internal clock negative signal CLKN_CP. The internal clock signals received by the same control node in adjacent charge pump units are different. For example, if the first control node CN1 receives the internal clock positive signal CLK_CP and the second control node CN2 receives the internal clock negative signal CLKN_CP in the current charge pump unit, then in the preceding and following charge pump units, the first control node CN1 receives the internal clock negative signal CLKN_CP and the second control node CN2 receives the internal clock positive signal CLK_CP.

[0045] In this embodiment, the main charging transistor is an N-type transistor; the main boost transmission transistor and the main bleeder transistor are both P-type transistors. The substrate of the main charging transistor is coupled to ground, and the substrates of the main boost transmission transistor and the main bleeder transistor are both coupled to the corresponding main output node.

[0046] In this embodiment, the charge pump unit has 16 stages.

[0047] In the first stage charge pump unit, the source of the main charging transistor MN1 receives the input voltage VIN, the drain of the main charging transistor MN1 is connected to the main node CP1, and the gate of the main charging transistor MN1 is connected to the first control node CN1 to receive the internal clock positive signal CLK_CP; the source of the main boost transfer transistor MP1 is connected to the main output node OUT1 to output the boost voltage Vcp1 generated by the charge pump unit of this stage, and the drain of the main boost transfer transistor MP1 is connected to the main node CP1. The gate of transistor MP1 is connected to the first control node CN1 to receive the internal clock positive signal CLK_CP; the source of the main bleeder transistor MP1_lk is connected to the power supply voltage terminal VDD, the drain of the main bleeder transistor MP1_lk is connected to the main node CP1, and the gate of the main bleeder transistor MP1_lk receives the bleed enable positive signal Discharge_EN; one end of the main capacitor Cf1 is coupled to the main node CP1, and the other end of the main capacitor Cf1 is coupled to the second control node CN2 to receive the internal clock inverse signal CLKN_CP.

[0048] In this embodiment, in the charge pump main unit of the last stage (16th stage) of the charge pump unit, the source of the main charging transistor MN16 receives the boost voltage Vcp15 output from the previous stage (15th stage) charge pump main unit, the drain of the main charging transistor MN16 is connected to the main node CP16, and the gate of the main charging transistor MN16 is connected to the first control node CN1 to receive the internal clock inversion signal CLKN_CP; the source of the main boost transfer transistor MP16 outputs the output voltage VHH, and the drain of the main boost transfer transistor MP16 is connected to the main node CP16. The gate of transistor MP16 is connected to the first control node CN1 to receive the internal clock inversion signal CLKN_CP; the source of the main bleeder transistor MP16_lk is connected to the power supply voltage terminal VDD, the drain of the main bleeder transistor MP16_lk is connected to the master node CP16, and the gate of the main bleeder transistor MP16_lk receives the bleeder enable positive signal Discharge_EN; one end of the main capacitor Cf16 is coupled to the master node CP16, and the other end of the main capacitor Cf16 is coupled to the second control node CN2 to receive the internal clock positive signal CLK_CP.

[0049] Please see Figure 6 This is a circuit diagram of a charge pump module provided in another embodiment of this application. Figure 6As shown, in this embodiment, each charge pump unit may further include a charge pump auxiliary unit 61 cross-coupled with the charge pump main unit 51. The components and connection method of the charge pump auxiliary unit 61 are basically the same as those of the charge pump main unit 51. The charge pump auxiliary unit 61 may include: an auxiliary charging transistor, an auxiliary boost transmission transistor, an auxiliary bleeder transistor, and an auxiliary capacitor.

[0050] Specifically, the auxiliary charging transistor is coupled between the auxiliary input node and the auxiliary node, and the control terminal of the auxiliary charging transistor is coupled to the second control node CN2. The auxiliary input node receives the input voltage VIN or the boost voltage output by the previous stage charge pump auxiliary unit. Specifically, the auxiliary input node of the first stage charge pump unit receives the input voltage VIN.

[0051] In this embodiment, the auxiliary boost transfer transistor is coupled between the auxiliary node and the auxiliary output node, and the control terminal of the auxiliary boost transfer transistor is coupled to the second control node CN2. The auxiliary output node outputs the boosted voltage. Specifically, the auxiliary output node of the last stage charge pump unit outputs the output voltage VHH.

[0052] In this embodiment, the auxiliary bleeder transistor is coupled between the auxiliary node and the power supply voltage terminal VDD, and the control terminal of the auxiliary bleeder transistor is controlled by the bleeder enable signal. The bleeder enable signal is a positive bleeder enable signal Discharge_EN.

[0053] In this embodiment, one end of the auxiliary capacitor is coupled to the auxiliary node, and the other end of the auxiliary capacitor is coupled to the first control node CN1.

[0054] In this embodiment, the auxiliary charging transistor is an N-type transistor; the auxiliary boost transmission transistor and the auxiliary bleeder transistor are both P-type transistors.

[0055] In this embodiment, the charge pump unit has 16 stages.

[0056] In the first stage of the charge pump unit, the auxiliary charging transistor MN1' receives the input voltage VIN at its source, its drain is connected to the auxiliary node CP1', and its gate is connected to the second control node CN2 to receive the internal clock inversion signal CLKN_CP. The auxiliary boost transfer transistor MP1' has its source connected to the auxiliary output node OUT1' to output the boost voltage Vcp1' generated by this stage's auxiliary charge pump unit. Its drain is connected to the auxiliary node CP1'. The gate of the body transistor MP1' is connected to the second control node CN2 to receive the internal clock inversion signal CLKN_CP; the source of the auxiliary bleeder transistor MP1_lk' is connected to the power supply voltage terminal VDD, the drain of the auxiliary bleeder transistor MP1_lk' is connected to the auxiliary node CP1', and the gate of the auxiliary bleeder transistor MP1_lk' receives the bleeder enable positive signal Discharge_EN; one end of the auxiliary capacitor Cf1' is coupled to the auxiliary node CP1', and the other end of the auxiliary capacitor Cf1' is coupled to the first control node CN1 to receive the internal clock positive signal CLK_CP.

[0057] In this embodiment, in the charge pump auxiliary unit of the last stage (16th stage) of the charge pump unit, the source of the auxiliary charging transistor MN16' receives the boost voltage Vcp15' output from the previous stage (15th stage) of the charge pump auxiliary unit, the drain of the auxiliary charging transistor MN16' is connected to the auxiliary node CP16', and the gate of the auxiliary charging transistor MN16' is connected to the second control node CN2 to receive the internal clock positive signal CLK_CP; the source of the auxiliary boost transmission transistor MP16' outputs the output voltage VHH, and the drain of the auxiliary boost transmission transistor MP16' is connected to the auxiliary node CP16', the auxiliary boost transmission... The gate of transistor MP16' is connected to the second control node CN2 to receive the internal clock positive signal CLK_CP; the source of auxiliary bleed transistor MP16_lk' is connected to the power supply voltage terminal VDD, the drain of auxiliary bleed transistor MP16_lk' is connected to the auxiliary node CP16', and the gate of auxiliary bleed transistor MP16_lk' receives the bleed enable positive signal Discharge_EN; one end of auxiliary capacitor Cf16' is coupled to the auxiliary node CP16', and the other end of auxiliary capacitor Cf16' is coupled to the first control node CN1 to receive the internal clock inverse signal CLKN_CP.

[0058] In this embodiment, the circuit signal flow of the power-optimized charge pump circuit 10 is as follows: When the positive discharge enable signal Discharge_EN=0 and the negative discharge enable signal Discharge_E=1, the charge pump module operates normally, and the discharge tubes MP1_lk~MP16_lk, MP1_lk'~MP16_lk', and MN1_lk~MN3_lk are turned off. Conversely, when the discharge tubes are turned off, the discharge tubes are turned on, and the output voltage VHH of the charge pump module is quickly discharged to the power supply voltage. When the positive limit enable signal Lit_EN=0 and the negative limit enable signal Lit_E=1, the reference voltage Vref is input to the non-inverting input of the comparator subunit through transmission gate T1. When the sampled voltage Vc0 is greater than the reference voltage Vref, the clock enable signal CLK_EN=0, and the clock-controlled limiter module performs the limiting function. Conversely, when the power supply voltage is much greater than the sampled voltage Vc0, the clock enable signal CLK_EN=1, and the clock-controlled limiter module does not perform the limiting function.

[0059] In the boost mode of the charge pump module, Discharge_EN=0, Discharge_E=1, Lit_EN=0, Lit_E=1, and the input voltage VIN enters the circuit. Initially, without clock signal switching, the output voltage VHH of the charge pump module is approximately equal to the input voltage VIN. At this time, the sampled voltage Vc0 is less than the reference voltage Vref, the clock enable signal CLK_EN=1, the inverting clock generation unit is enabled, and a pair of non-overlapping internal clock positive signals CLK_CP and internal clock inverse signals CLKN_CP are generated and output to the charge pump module, at which point the charge pump module begins to operate.

[0060] Taking the first-stage charge pump unit as an example, for the charge pump master unit: in the first half of the clock cycle, CLK_CP is high, CLKN_CP is low, MN1 is on, MP1 is off, and one end of Cf1 connected to the master node CP1 is charged to VIN. The other end of Cf1 connected to CLKN_CP has the same voltage level as CLKN_CP. In the second half of the clock cycle, CLK_CP is low, CLKN_CP is high, MN1 is off, MP1 is on, one end of Cf1 connected to the master node CP1 remains at VIN, and the other end of Cf1 connected to CLKN_CP is charged to 2VIN and transmitted to the next stage charge pump master unit, thus increasing the voltage step by step. At the same time, the Cf1' of the cross-coupled charge pump auxiliary unit has the opposite charging and discharging cycle to Cf1, and the clock jitter phase is opposite. Finally, the outputs of the charge pump master unit and the charge pump auxiliary unit are connected in parallel in the 16th stage to cancel out the overall voltage ripple.

[0061] Please see Figure 7 The figure shown is a simulation result diagram of the power-optimized charge pump circuit provided in the embodiments of this application. To verify the effectiveness of this application, the power-optimized charge pump circuit provided in this application was simulated. Figure 7 Part (a) shows the change in output voltage of the charge pump with input voltage, and part (b) shows the change in power consumption of the charge pump with input voltage. Under typical and extreme process corners, the output of the charge pump can be maintained at around 15.5V. Within the range of VIN = 1.1V to 1.8V, the output voltage range of the charge pump at the tt process corner is 14.77V to 17.49V, with current consumption during voltage rise ranging from 0.4741μA to 0.5454μA. Compared to existing charge pump circuits where power consumption is generally above 2μA, the power consumption of the power-optimized charge pump circuit provided in this application is effectively reduced. Simultaneously, the area of ​​the voltage divider capacitor in the power-optimized charge pump circuit provided in this application is only about half the area of ​​the voltage divider resistor in existing charge pump circuits, effectively reducing the chip area of ​​the power-optimized charge pump circuit provided in this application. Furthermore, through a cross-coupling and parallel output charge pump improvement scheme, the voltage output ripple can be controlled within 2%.

[0062] Based on the same inventive concept, this application also provides a passive radio frequency chip, which may include the power-optimized charge pump circuit described in any of the above embodiments, effectively reducing power consumption and chip area, effectively controlling voltage output ripple, avoiding noise interference caused by clock jitter, and improving the stability of output voltage.

[0063] Please see Figure 8 This is a schematic diagram of the passive radio frequency chip in this embodiment. Figure 8 As shown, the passive RF chip 1 provided in this embodiment may include the power-optimized charge pump circuit 10 described in any of the above embodiments. The passive RF chip 1 can be various types of integrated circuit chips or electronic products, such as passive RF chips with integrated EEPROM storage. In these passive RF chips 1, the power-optimized charge pump circuit 10, as part of a boost circuit, can multiply the input voltage through a multi-stage charge pump to generate the EEPROM erase / write high voltage VHH. Since the power-optimized charge pump circuit 10 of this application can effectively reduce power consumption and chip area, effectively control voltage output ripple, avoid noise interference caused by clock jitter, and improve the stability of the output voltage, the passive RF chip 1 using this power-optimized charge pump circuit 10 has higher integration and better voltage stability.

[0064] It should be noted that in the above embodiments, each embodiment focuses on the differences from other embodiments, and the same / similar parts between the embodiments can be referred to each other.

[0065] The terms "comprising" and "having," and variations thereof, used in this application are intended to cover non-exclusive inclusion. The terms "first," "second," etc., are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence, unless explicitly indicated by the context; such use of terms should be understood to be interchangeable where appropriate. The term "one or more," at least in part depending on the context, can be used to describe features, structures, or characteristics in a singular sense, or in a plural sense, to describe combinations of features, structures, or characteristics. The term "based on" can be understood as not necessarily intended to express an exclusive set of factors, but can instead, also at least in part depending on the context, allow for the presence of other factors that are not necessarily explicitly described. Furthermore, embodiments and features in embodiments of this application can be combined with each other without conflict. In addition, descriptions of well-known components and technologies have been omitted in the above description to avoid unnecessarily obscuring the concepts of this application.

[0066] The above description is merely a preferred embodiment of this application and is not intended to limit the scope of protection of this application. It should be noted that those skilled in the art can make various improvements and modifications without departing from the principles of this application, and these improvements and modifications should also be considered within the scope of protection of this application.

Claims

1. A power-optimized charge pump circuit, characterized in that, include: The charge pump module and the clock-controlled limiting module, wherein the clock-controlled limiting module includes a capacitor voltage divider sampling unit, a limiting switch comparator unit, and an inverting clock generation unit; The charge pump module is coupled to the inverting clock generation unit and is used to generate an output voltage based on the input voltage under the control of the bleed enable signal and the internal clock signal output by the inverting clock generation unit. The capacitor voltage divider sampling unit is coupled to the charge pump module and is used to perform voltage divider sampling on the output voltage to output a sampled voltage; The limiting switch comparator unit is coupled to the capacitor voltage divider sampling unit and is used to output a clock enable signal based on the received reference voltage and the sampling voltage under the control of the limiting enable signal. The inverting clock generation unit is coupled to the limiting switch comparator unit and is used to output an internal clock signal based on the clock enable signal under the control of the system clock signal.

2. The power-optimized charge pump circuit as described in claim 1, characterized in that, The capacitive voltage divider sampling unit includes a multi-stage voltage divider capacitor connected in series between the output terminal and the ground terminal of the charge pump module. Each of the voltage-dividing capacitors is used to divide and sample the output voltage, and the sampled voltage is output through the coupling point of the two voltage-dividing capacitors near the ground terminal.

3. The power-optimized charge pump circuit as described in claim 2, characterized in that, The capacitor voltage divider sampling unit also includes a bleed transistor coupled between the coupling point of two adjacent voltage divider capacitors and the ground terminal, and the control terminals of all the bleed transistors are controlled by the bleed enable signal to discharge the output voltage.

4. The power-optimized charge pump circuit as described in claim 1, characterized in that, The limiting switch comparator unit includes: A switching subunit, coupled to a reference voltage and a power supply voltage terminal, is used to select the output of the reference voltage or the power supply voltage of the power supply voltage terminal under the control of the limiting enable signal. A comparator subunit, wherein the first comparison terminal of the comparator subunit is coupled to the output terminal of the switch subunit, the second comparison terminal of the comparator subunit receives the sampled voltage, and the output terminal of the comparator subunit outputs the comparison result; An amplification and shaping subunit, coupled to the output of the comparator subunit, is used to amplify and shape the comparison result to generate a clock enable signal and output it.

5. The power-optimized charge pump circuit as described in claim 4, characterized in that, The limiting enable signal includes a limiting enable positive signal and a limiting enable negative signal; The switching subunit includes: a first transmission gate and a second transmission gate; The receiving end of the first transmission gate receives the reference voltage, and the control end of the first transmission gate receives the limiting enable positive signal and the limiting enable inverse signal respectively. The receiving end of the second transmission gate receives the power supply voltage of the power supply voltage terminal, and the control end of the second transmission gate receives the limiting enable positive signal and the limiting enable inverse signal respectively. The output ends of the first transmission gate and the second transmission gate are coupled to the output end of the switching subunit. The comparator subunit includes: a first transistor, a second transistor, a third transistor, a fourth transistor, and a first load transistor; The first transistor is coupled between the first node and the second node, and the control terminal of the first transistor is connected to the output terminal of the switching subunit. The second transistor is coupled between the output of the comparator subunit and the second node, and the control terminal of the second transistor is controlled by the sampling voltage. The first transistor and the second transistor form an input differential pair. The third transistor is coupled between the power supply voltage terminal and the first node, and the control terminal of the third transistor is shorted to the first node; The fourth transistor is coupled between the power supply voltage terminal and the output terminal of the comparator subunit, and the control terminal of the fourth transistor is shorted to the first node. The third transistor and the fourth transistor form a current mirror. The first load transistor is coupled between the second node and the ground terminal, and the control terminal of the first load transistor is controlled by a bias voltage; The amplification and shaping subunit includes: an amplification transistor, a second load transistor, and a shaping inverter; The amplifying transistor and the second load transistor are connected in series between the power supply voltage terminal and the ground terminal, and the control terminal of the amplifying transistor is coupled to the output terminal of the comparator subunit, and the control terminal of the second load transistor is controlled by the bias voltage. The input terminal of the shaping inverter is coupled to the common terminal between the amplifying transistor and the second load transistor, and the output terminal of the shaping inverter outputs the clock enable signal.

6. The power-optimized charge pump circuit as described in claim 1, characterized in that, The internal clock signal includes an internal clock positive signal and an internal clock negative signal; The inverted clock generation unit includes: A NAND gate, wherein the first input terminal of the NAND gate receives the system clock signal, and the second input terminal of the NAND gate receives the clock enable signal; An initial inverter, the input of which is coupled to the output of the NAND gate; An isolation transmission gate, wherein the input terminal of the isolation transmission gate is coupled to the output terminal of the NAND gate, and the control terminal of the isolation transmission gate is coupled to the power supply voltage terminal and the ground terminal respectively; The first NOR gate and the second NOR gate form a symmetrical dual-channel interlocking structure. The first input terminal of the first NOR gate is coupled to the output terminal of the isolation transmission gate, the second input terminal of the first NOR gate is coupled to the output terminal of the second NOR gate, the first input terminal of the second NOR gate is coupled to the output terminal of the first NOR gate, and the second input terminal of the second NOR gate is coupled to the output terminal of the initial inverter. A first inverter, the input of which is coupled to the output of the first NOR gate, and the output of which outputs the internal clock positive signal; The second inverter has its input coupled to the output of the second NOR gate, and its output outputs the internal clock inversion signal.

7. The power-optimized charge pump circuit as described in claim 1, characterized in that, The charge pump module includes a series of multi-stage charge pump units. Each stage of the charge pump unit, under the control of the bleed enable signal and the internal clock signal, boosts the received voltage and outputs it.

8. The power-optimized charge pump circuit as described in claim 7, characterized in that, Each of the charge pump units includes a charge pump main unit, and the charge pump main unit includes: A main charging transistor is coupled between the main input node and the main node, and the control terminal of the main charging transistor is coupled to the first control node. The main input node receives the input voltage or the boost voltage output by the previous stage charge pump main unit. A main boost transmission transistor is coupled between the main node and the main output node, and the control terminal of the main boost transmission transistor is coupled to the first control node. The main output node outputs the boosted voltage. A main bleed transistor is coupled between the main node and the power supply voltage terminal, and the control terminal of the main bleed transistor is controlled by the bleed enable signal; A main capacitor, one end of which is coupled to the main node, and the other end of which is coupled to the second control node; The internal clock signal includes an internal clock positive signal and an internal clock negative signal. The first control node receives one of the internal clock positive signal and the internal clock negative signal, and the second control node receives the other of the internal clock positive signal and the internal clock negative signal. The internal clock signals received by the same control node in two adjacent charge pump units are different.

9. The power-optimized charge pump circuit as described in claim 8, characterized in that, Each of the charge pump units further includes a charge pump auxiliary unit cross-coupled with the charge pump main unit, the charge pump auxiliary unit comprising: An auxiliary charging transistor is coupled between an auxiliary input node and an auxiliary node, and the control terminal of the auxiliary charging transistor is coupled to the second control node. The auxiliary input node receives the input voltage or the boost voltage output by the previous stage charge pump auxiliary unit. An auxiliary boost transmission transistor is coupled between the auxiliary node and the auxiliary output node, and the control terminal of the auxiliary boost transmission transistor is coupled to the second control node. The auxiliary output node outputs the boosted voltage. An auxiliary bleed transistor is coupled between the auxiliary node and the power supply voltage terminal, and the control terminal of the auxiliary bleed transistor is controlled by the bleed enable signal; An auxiliary capacitor, one end of which is coupled to the auxiliary node, and the other end of which is coupled to the first control node.

10. A passive radio frequency chip, characterized in that, Includes the power-optimized charge pump circuit as described in any one of claims 1 to 9.

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