Switching mode power supply and method

Abstract

This description relates to a switch mode power supply and method. In each operating cycle, a circuit controls: a first period in a high side switch on state, which is constant or proportional to 1 / (Vsup-Vout), where Vsup is a supply potential and Vout is a regulated voltage provided by the switch mode power supply; and a second period in a low side switch on state at the end of the first period, which is proportional to the inverse of a first current. A correction circuit compares a second current proportional to Vsup-Vout and a constant current, and supplies a first current equal to a third current plus a fourth current, the fourth current being zero if the second current is greater than the constant current, otherwise proportional to the constant current minus the second current.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to French patent application No. FR2504467, filed on April 28, 2025, entitled “Device and method for limiting a current”, which is incorporated herein by reference to the fullest extent permitted by law. Technical Field

[0003] This disclosure relates generally to electronic circuits and methods, and more particularly to switch-mode power supplies (SMPS) (preferably buck type) and methods. Background Technology

[0004] Known switch-mode power supplies consist of a high-side switch and a low-side switch connected in series between a supply potential and a reference potential. An intermediate node between the two switches (e.g., the node connecting the two switches to each other) is coupled to the load to be powered via an inductor (or inductive element). Energy is stored in the inductor by controlling the on and off states of the high-side and low-side switches, respectively, and then released to the load by controlling the off and on states of the high-side and low-side switches, respectively. Each alternation between the energy storage phase in the inductor and the energy release phase to the load forms an operating cycle.

[0005] Among these known switch-mode power supplies, those operating in pulse frequency modulation (PFM) and discontinuous conduction mode (DCM) can be distinguished. In such switch-mode power supplies, two successive operating cycles can be separated by an idle phase during which both switches are off. In such switch-mode power supplies, the duration of the energy storage phase in the inductor during each operating cycle is typically defined as ending when the current in the inductor reaches its maximum target value. Furthermore, in such switch-mode power supplies, the duration of the energy release phase during each operating cycle is typically defined as ending after the current in the inductor reaches zero, after which a new operating cycle can begin.

[0006] However, these known switch-mode power supplies have many drawbacks. Summary of the Invention

[0007] There is a need to overcome all or some of the drawbacks of the above-mentioned types of switch-mode power supplies.

[0008] One embodiment overcomes all or some of the disadvantages of the above-described type of switch-mode power supply.

[0009] One embodiment provides a switch-mode power supply, including:

[0010] A high-side switch is connected between a first node configured to receive a power supply potential and a second node configured to be coupled via an inductor to a node for supplying a regulated voltage.

[0011] A low-side switch is connected between the second node and a third node configured to receive a reference potential;

[0012] The circuitry used to control the high-side and low-side switches is configured to:

[0013] - A first time period during which the high-side switch is in the on-state is controlled, which is constant or proportional to 1 / (Vsup-Vout), where Vsup is the power supply potential and Vout is the regulated voltage.

[0014] - At the end of the first time period, a second time period is controlled in the on-state of the low-side switch, the second time period being proportional to the reciprocal of the first current; and

[0015] The correction circuit is configured as follows:

[0016] - Compare the second current and the constant current that are proportional to Vsup-Vout;

[0017] The supply equals the first current equal to the third current plus the fourth current. When the second current is greater than the constant current, the fourth current is zero. When the second current is less than the constant current, the fourth current is proportional to the constant current minus the second current.

[0018] According to an embodiment, the control circuit is configured to control the high-side switch and the low-side switch in pulse frequency modulation and intermittent conduction mode.

[0019] According to an embodiment, the correction circuit includes:

[0020] The circuit used to generate the fourth current is configured to supply the fourth current to the current summing node;

[0021] A first current source is configured to supply a second current to a fourth current generation circuit; and

[0022] A second current source is configured to supply a constant current to a circuit used to generate a fourth current; and

[0023] The third current source is configured to supply a third current to the current summing node, where the first current is available.

[0024] According to an embodiment, the circuit for generating the fourth current includes:

[0025] The first MOS transistor has its gate and drain connected to a current comparator node configured to receive a second current and a constant current, such that:

[0026] - The first transistor turns off when the second current is greater than the constant current, and

[0027] - When the second current is less than the constant current, the first transistor is turned on, and a current equal to the constant current minus the second current flows through the first transistor; and

[0028] The second transistor is assembled with the first transistor as a current mirror and configured to supply a fourth current.

[0029] According to an embodiment, the first current source includes:

[0030] A MOS transistor and a resistor are connected in series between the first node and the third node;

[0031] An operational amplifier having a first input terminal connected to a node connecting a transistor and a resistor, a second input terminal configured to receive a regulated voltage, and an output terminal connected to the gate of the transistor; and

[0032] At least one current mirror is configured to supply a second current based on the current flowing through the transistor.

[0033] According to an embodiment, the third current source includes at least one current mirror configured to supply a third current based on the current flowing through the transistor of the first current source.

[0034] According to an embodiment, the third current source includes at least one current mirror with the first current source, configured to supply a third current based on a second current flowing through the first current source.

[0035] According to the embodiment, the third current is constant or proportional to 1 / (Vsup-Vout). According to the example:

[0036] The switch-mode power supply includes a generator for a first voltage ramp, the first voltage ramp having a slope proportional to a first current; and

[0037] The control circuit is configured to: in each second time period:

[0038] - Control the start of the first ramp at the beginning of the second time period.

[0039] - Compare the first ramp with the first threshold, and

[0040] - The second time period terminates when the first slope crosses the first threshold.

[0041] According to the example:

[0042] The switch-mode power supply includes a generator for a second voltage ramp, which has a slope proportional to the constant current or a slope proportional to Vsup-Vout; and

[0043] The control circuit is configured to:

[0044] - Control the start of the second ramp at the beginning of the first time period.

[0045] - Compare the second ramp with the second threshold, and

[0046] - The first time period terminates when the second slope crosses the second threshold.

[0047] According to the example:

[0048] The switch-mode power supply includes a generator for a first voltage ramp, the first voltage ramp having a slope proportional to a first current; and

[0049] The control circuit is configured to operate in each second time period as follows:

[0050] - Control the start of the first ramp at the beginning of the second time period.

[0051] - Compare the first ramp with the first threshold, and

[0052] - The second time period terminates when the first ramp crosses the first threshold;

[0053] The switch-mode power supply includes a generator for a second voltage ramp, which has a slope proportional to a fifth current, which is proportional to Vsup-Vout.

[0054] The control circuit is configured to:

[0055] - Control the start of the second ramp at the beginning of the first time period.

[0056] - Compare the second ramp with the second threshold, and

[0057] - The first time period terminates when the second ramp crosses the second threshold;

[0058] The switch-mode power supply includes a fourth current source configured to supply a fifth current; and

[0059] The fourth current source includes at least one current mirror of the first current source, the at least one current mirror being configured to supply a fifth current based on a second current flowing through the first current source.

[0060] According to an embodiment, the switch-mode power supply is configured to reduce the second time period when the difference Vsup-Vout decreases and the fourth current is not zero. Attached Figure Description

[0061] The foregoing features and advantages, as well as other features and advantages, will be described in detail in the remainder of the disclosure of specific embodiments given by way of illustration and not limitation, with reference to the accompanying drawings, wherein:

[0062] Figure 1 An example of a switch-mode power supply is shown;

[0063] Figure 2 The timing diagram illustrates this. Figure 1 Operation of the switch-mode power supply;

[0064] Figure 3 The timing diagram illustrates this. Figure 1 There are problems with the operation of the switch-mode power supply;

[0065] Figure 4 The solution is shown in the form of a block diagram. Figure 3 An example of an embodiment of the circuit illustrating the operational problem;

[0066] Figure 5 It is illustrated with a curve. Figure 4 The operation of the circuit;

[0067] Figure 6 The timing diagram illustrates the following: Figure 4 The circuit Figure 1 Operation of the switch-mode power supply;

[0068] Figure 7 It shows Figure 4 A more detailed example of the circuit implementation;

[0069] Figure 8 It shows Figure 4 and Figure 7 A more detailed example of the implementation of the current source in the circuit;

[0070] Figure 9 It shows including Figure 4 The circuit Figure 1 A more detailed example of the implementation of a switch-mode power supply circuit; and

[0071] Figure 10 It shows including Figure 4 The circuit Figure 1 A more detailed example of the implementation of a switch-mode power supply circuit. Detailed Implementation

[0073] In the various figures, the same features are indicated by the same reference numerals. In particular, common structural and / or functional features between different embodiments may have the same reference numerals, and may have the same structure, dimensions, and material properties.

[0074] For clarity, only those operations and elements useful for understanding the embodiments described herein are shown and described in detail. In particular, various known electronic systems and applications (where switch-mode power supplies can be used to supply regulated voltages to a load to be powered) are not described, and the described embodiments and variations are compatible with these known systems and applications.

[0075] Unless otherwise stated, when referring to two elements being connected to each other, it means that there is no direct connection between them except for a conductor, and when referring to two elements being coupled to each other, it means that the two elements can be connected or can be coupled via one or more other elements.

[0076] Unless otherwise stated, when indicating that the first quantity A is proportional to the second quantity B, it means that A equals D multiplied by B, with constant multiplication coefficients.

[0077] In the following description, unless otherwise specified, when referring to absolute positional qualifiers such as the terms “front,” “back,” “top,” “bottom,” “left,” “right,” etc., or relative positional qualifiers such as the terms “top,” “bottom,” “higher,” “lower,” etc., or orientational qualifiers such as “horizontal,” “vertical,” etc., the orientation of the figure is being referred to.

[0078] Unless otherwise specified, the expressions “about,” “approximately,” “substantially,” and “approximately” indicate plus or minus 10% or 10°, and preferably plus or minus 5% or 5°.

[0079] Figure 1 An example of a switch-mode power supply 1 is shown.

[0080] Switch-mode power supply 1 (also known as a DC-DC converter) is configured to supply a voltage Vout based on the power supply voltage Vsup, which is regulated to a setpoint value Vtarget determined by a reference voltage Vref. Voltages Vout and Vsup are DC voltages. Figure 1 In the example, converter 1 is a buck converter, meaning that the voltage Vout is regulated to a setpoint value Vtarget that is lower than the supply voltage Vsup. For example, the setpoint value Vtarget of voltage Vout is the value of voltage Vref.

[0081] Converter 1 includes a high-side switch HS connected between node (or conductor rail) 100 and node 102, configured to receive a power supply potential Vsup. Switch HS is controlled by a control signal ctrlHS. For example, switch HS is implemented by one or more metal-oxide-semiconductor (MOS) transistors, such as P-channel MOS transistors (or PMOS), with its source coupled (e.g., connected) to node 100, its drain coupled (e.g., connected) to node 102, and its gate receiving the signal ctrlHS.

[0082] Converter 1 includes a low-side switch LS connected between node 102 and a node (or conductor rail) 104 configured to receive a reference potential GND (e.g., ground). The potential Vsup is the reference potential GND, and... Figure 1 In the example, it is positive. Switch LS is controlled by the control signal ctrlLS. For example, switch LS is implemented by one or more MOS transistors, such as N-channel MOS transistors (or NMOS), whose source is coupled (e.g., connected) to node 104, whose drain is coupled (e.g., connected) to node 102, and whose gate receives the signal ctrlLS.

[0083] Node 102 is coupled via inductor L to node 106, which supplies the regulated voltage Vout. The load to be powered (not in...) Figure 1 (As shown in the diagram) A smoothing capacitor may be connected between nodes 106 and 104 in parallel with the load. As an example, an inductor L has a first terminal coupled (e.g., connected) to node 102 and a second terminal coupled (e.g., connected) to node 106.

[0084] Converter 1 includes a control circuit CTRL configured to supply signals ctrlHS and ctrlLS to switches LS and HS. The circuit CTRL is configured to control switches LS and HS such that converter 1 operates in pulse frequency modulation (PFM) and discontinuous conduction mode (DCM).

[0085] The circuit CTRL is configured to control the on state of the high-side switch HS for a period of time TON during each operating cycle of the switch-mode power supply, during which the switch LS is controlled to be in the off state.

[0086] The time period TON is, for example, constant, and is configured such that the maximum or peak value of the current IL flowing through the inductor L is the same for each operating cycle.

[0087] As an alternative example, the time period TON is proportional to 1 / (Vsup-Vout) and is configured, for example, such that the maximum or peak value of the current IL flowing through the inductor L is the same in each operating cycle and does not change when the voltage Vsup varies (e.g., because the voltage Vsup is supplied by a discharging battery). As examples, French patent FR1911933 B1, US patent US11750095 B2, and Chinese patent application CN112713773 A describe converters in which the time period TON is proportional to 1 / (Vsup-Vout).

[0088] The circuit CTRL is configured to control the low-side switch LS for a time period TOFF for each operating cycle of the switch-mode power supply, starting at the end of the operating cycle's time period TON. During each time period TOFF, the switch HS is controlled to be in the off state.

[0089] exist Figure 1 In the example, it is assumed that the voltage Vout is regulated to its constant setpoint value Vtarget, and the time period TOFF is constant and determined such that the current IL in the inductor is zero at the end of the time period TOFF in each operating cycle.

[0090] As an example, after each operating cycle, if the value of voltage Vout is less than its setpoint value Vtarget determined by voltage Vref (e.g., equal to the value of voltage Vref), then a new operating cycle and therefore the time period TON of that cycle begins.

[0091] As an example, in each operating cycle, the time period TON is proportional to the reciprocal of the current IbP, that is, proportional to 1 / IbP, which is constant when the time period TON is constant, or proportional to Vsup-Vout when the time period TON is proportional to 1 / (Vsup-Vout).

[0092] For example, the current IbP determines the slope of the voltage slope VP supplied by the slope generator RP. For example, the slope of the slope VP is proportional to IbP. In each operating cycle, the time period TON of that cycle is then determined, for example, by comparing the voltage slope VP with a threshold voltage determined by the setpoint value Vtarget of the voltage Vout (e.g., by comparing the slope VP with the voltage Vref). For example, for each time period TON, the slope VP begins with that time period TON and ends when the slope VP crosses the threshold voltage.

[0093] As an example, in each operating cycle, the time period TOFF is proportional to the reciprocal of the current IbN, which is constant, or proportional to Vsup-Vout.

[0094] For example, the current IbN determines the slope of the voltage ramp VN supplied by the ramp generator RN. For example, the slope of ramp VN is proportional to IbN. In each operating cycle, the time period TOFF of that cycle is then determined, for example, by comparing the voltage ramp VN with a threshold voltage determined by the setpoint value Vtarget of the voltage Vout (e.g., by comparing the voltage ramp VN with the voltage Vref). For example, for each time period TOFF, ramp VN begins with that time period TOFF and ends when ramp VN crosses the threshold voltage.

[0095] As an example, the circuit CTRL receives a setpoint voltage Vref and a voltage Vout, for example, to determine when the value of the voltage Vout becomes lower than the setpoint value Vtarget determined by the voltage Vref, in order to control the start of a new operating cycle.

[0096] As an example, the circuit CTRL receives voltages VP and VN to compare them with corresponding thresholds determined by the setpoint value Vtarget of voltage Vout in order to determine the time periods TON and TOFF for each cycle, and supplies signals ctrlHS and ctrlLS accordingly.

[0097] As an example, the start of each ramp VP is controlled by the signal ctrlRP supplied by the circuit CTRL to the ramp generator RP.

[0098] As an example, the start of each ramp VN is controlled by the signal ctrlRN supplied by the circuit CTRL to the ramp generator RN.

[0099] As an example, the generator RP receives a current IpP at input 108.

[0100] As an example, the generator RN receives a current IbN at input 110.

[0101] Figure 2 The timing diagram illustrates this. Figure 1 The operation of the switch-mode power supply 1. More specifically, Figure 2 The diagram shows the change of current IL in inductor L of converter 1 with time t during the operating cycle.

[0102] At time t0, the current IL is zero. Switches HS and LS are in the off state. Switch-mode power supply 1 is in the switching mode between two operating cycles.

[0103] At time t1 after time t0, although this is not in Figure 2 As shown, however, the voltage Vout becomes less than its setpoint voltage Vtarget, and the circuit CTRL controls the start of the time period TON.

[0104] During the time period TON, the current IL in the inductor increases. It is generally assumed that the current IL increases with a slope A1 proportional to Vsup - Vout. In other words, the current IL is considered to increase linearly in the inductor L.

[0105] At time t2, which is after time t1 and corresponds to the end of time period TON, the current IL reaches its maximum value or peak value Ip for this operating cycle. The value Ip equals... An approximation is adopted where the current IL increases linearly in the inductor L. The dimensions of converter 1 are set such that the value Ip equals the target value Itarget, that is, A1.TON = Itarget.

[0106] The end time t2 of the time period TON, within the dead time that avoids cross-conduction, also corresponds to the beginning of the time period TOFF of the operating cycle. During the time period TOFF, the current IL decreases. It is generally assumed that the current IL decreases with a constant slope A2. For example, the slope A2 is proportional to Vout, and when the voltage Vout is adjusted to its setpoint value Vtarget, the slope A2 is constant, for example, constant relative to Vsup.

[0107] The time period TOFF ends at time t3, following time t2. As previously stated, the time period TOFF is determined at least in part based on the target peak value Itarget, such that the current IL is zero at time t3, the end of the time period TOFF.

[0108] The above text is about Figure 2 The described operation is only observed in practice when the difference Vsup-Vout is sufficiently large (e.g., greater than the threshold Th). In reality, when the difference Vsup-Vout decreases and, for example, becomes less than the threshold Th, parasitic phenomena that are ignored when considering the current IL increasing at a slope A1 during each time period TON and decreasing at a slope A2 during each time period TOFF become more significant. Consequently, the observed operation is no longer as... Figure 2 As shown, it is as expected, but rather as Figure 3 As shown.

[0109] Figure 3 The timing diagram illustrates this. Figure 1 There is a problem with the operation of the switch-mode power supply 1. More specifically, Figure 2 The figure illustrates the change of current IL in inductor L of converter 1 with time t during the operating cycle.

[0110] In this example, the voltage difference Vsup-Vout is low enough that the approximation of a linear increase in current IL during each time period TON no longer holds true.

[0111] In practice, the control signals ctrlHS and ctrlLS have a high level corresponding to the voltage Vsup and a low level corresponding to zero voltage.

[0112] Therefore, when the difference Vsup-Vout decreases due to the decrease in voltage Vsup, and the switch HS is controlled to be on by the low level of the signal ctrlHS, the difference between the low level of the signal ctrlHS and the voltage Vsup is less than expected, and the resistance of the switch HS is greater than expected. This further results in the potential difference across inductor L during each time period TON being lower than expected, and, for example, lower than a certain value, below which the inductive effect in inductor L decreases and the weight of this inductive effect relative to the weight of the resistive effect in the inductor decreases.

[0113] As another result, when the difference Vsup-Vout decreases due to the decrease in voltage Vsup, and the switch LS is controlled to be in the on state by the high level of the signal ctrlLS, the high level of the signal ctrlLS is lower than expected, and the resistance of the switch LS is larger than expected.

[0114] Therefore, in Figure 3 In, with Figure 2 Compared to the description, during the time period TON between times t1 and t2, the current IL increases less rapidly than expected. As a result, at time t3, the current IL reaches a peak value Ip, which is lower than the value Itarget used to determine the time period TON.

[0115] In addition, Figure 3 In, with Figure 2 Compared to the description in the previous section, during the time interval TOFF between times t2 and t3, the current IL not only decreases from a value Ip that is lower than the expected value Itarget, but also decreases faster than expected because the resistance of the switch LS is larger than expected. As a result, the current IL reaches zero at time t3b, earlier than the expected time t3, and continues to decrease until time t3.

[0116] After time t3, Figure 3 In the example, the time period TOFF is followed by a phase during which both switches HS and LS are off, and the current IL increases until it becomes zero again at time t4 after time t3.

[0117] The fact that the current IL is negative between times t3b and t4 reduces the energy efficiency of converter 1.

[0118] It can be considered that when the voltage difference Vsup-Vbat drops below the threshold Th, it will cause... Figure 3During the observed operation, the time period TON was increased so that even under these conditions, the current IL reached the value Ip equal to Itarget.

[0119] However, this will increase the amplitude of oscillations ("ripple") on the output voltage Vout.

[0120] Furthermore, this also risks increasing the value of voltage Vout, which would lead to a decrease in the difference Vsup-Vout, thus causing issues related to... Figure 3 The described operation leads to an increase in unwanted parasitic phenomena.

[0121] It is proposed that when the difference Vsup-Vout becomes lower than the threshold Th, the time period TOFF decreases as the difference Vsup-Vout decreases, instead of increasing the time period TON when the difference Vsup-Vout decreases and is lower than the threshold Th.

[0122] To this end, it is proposed that in a switch-mode power supply 1 where the time period TOFF is proportional to the reciprocal of the constant current IbN or proportional to Vsup-Vout, the time period TOFF is inversely proportional to the current IbNcorr, which is equal to the current IbN plus a correction current Icorr. The current Icorr is zero when the current Iprop, which is proportional to Vsup-Vout, is greater than the constant current Icst, and is proportional to the difference Icst-Iprop when the current Iprop is less than the current Icst. In particular, a correction circuit is provided, configured to supply the current IbNcorr instead of the current IbN, and to make the time period TOFF proportional to the reciprocal of the current IbNcorr, rather than as per the previous description. Figure 1 The current is described as being proportional to the reciprocal of the current IbN. Specifically, the correction circuit is configured to compare the current Iprop with the current Icst in order to determine whether the current Icorr is zero or proportional to the difference Icst - Iprop.

[0123] According to an embodiment, when the correction circuit is implemented in a switch-mode power supply such that the time period TOFF is proportional to the reciprocal of the current IbNcorr, the switch-mode power supply is configured to reduce the time period TOFF when the difference Vsup-Vout decreases and the current Icorr is non-zero.

[0124] According to an embodiment, a correction circuit is added Figure 1 The switching mode power supply 1, and the current IbN supplied to the ramp generator RN is replaced by the current IbNcorr supplied by the current correction circuit.

[0125] Figure 4 The block diagram illustrates the configuration for supplying current IbNcorr and thus solving... Figure 3The diagram illustrates an example of an embodiment of this correction circuit 400 for operational problems.

[0126] Circuit 400 includes a circuit CORR for generating a current Icorr. The circuit CORR is configured to supply the current Icorr to the current summing node 402. For example, when the current Icorr flows from the circuit CORR to the node 402, the current Icorr is positive.

[0127] Circuit 400 includes a current source 404 configured to supply current Iprop to circuit CORR. For example, current Iprop is positive when it flows from current source 404 to circuit CORR. For example, current source 404 is connected between node 100 and circuit CORR.

[0128] Circuit 400 includes a current source 406 configured to supply a constant current Icst to circuit CORR. For example, the current Icst is positive when it flows from circuit CORR to current source 406. For example, current source 406 is connected between node 104 and circuit CORR.

[0129] Circuit 400 includes a current source 408 configured to supply current IbN to node 402. Therefore, current IbNcorr is available at node 402 (e.g., can be drawn from node 402) and is equal to IbN + Icorr. For example, current IbN is positive when it flows from current source 408 to node 402. For example, current source 408 is connected between node 100 and node 402. For example, node 402 is connected to... Figure 1 The input terminal 110 of the ramp generator RN of power supply 1.

[0130] Figure 5 The curve diagram illustrates this. Figure 4 The operation of circuit 400.

[0131] More specifically, Figure 5 Curve 500 shows an example in which the current IbN is proportional to the difference Vsup-Vout, and curve 500 also shows the change of the corresponding current IbNcorr supplied by circuit 400.

[0132] For voltage differences Vsup-Vout greater than the threshold Th, i.e., as long as the current Iprop is greater than the current Icst, then the current Icorr is zero and the current IbNcorr (curve 502) is equal to the current IbN (curve 500). As a result, the duration TOFF is as follows: Figure 1 The description is confirmed.

[0133] On the other hand, for voltage differences Vsup-Vout less than the threshold Th, i.e., as long as the current Iprop is lower than the current Icst, the current IbNcorr increases as the difference Vsup-Vout decreases, so that it becomes substantially constant and equal to the value IbNcst determined by the current Icst. In fact, as the difference Vsup-Vout decreases, the current Iprop decreases, and thus the current Icorr, which is equal to Icst-Iprop, increases from zero when the current Iprop equals the current Icst (i.e., when the difference Vsup-Vout equals the threshold Th).

[0134] Since the time interval TOFF is proportional to the reciprocal of the current IbNcorr, it can be concluded that for a value Vsup-Vout less than the threshold Th, when the value Vsup-Vout decreases and the current IbNcorr increases, the time interval TOFF decreases compared to the case where the time interval TOFF is proportional to the reciprocal of the current IbN.

[0135] Figure 6 The timing diagram illustrates the following: Figure 4 The circuit Figure 1 The operation of the switch-mode power supply is such that the time period TOFF is proportional to the reciprocal of the current IbNcorr, rather than the reciprocal of the current IbN. More specifically, Figure 6 The diagram shows the variation of the current IL in the inductor L of converter 1 with time t during the operating cycle when the voltage difference Vsup-Vout is less than the threshold Th.

[0136] The change and combination of current IL between time t0 and t3b Figure 3 The descriptions are the same.

[0137] However, in Figure 6 In the example, since the voltage Vsup-Vout is lower than the threshold Th, the current IbNcorr is greater than the current IbN, therefore... Figure 6 The time period TOFF ratio Figure 3 Short in the middle. Especially, such as Figure 6 As shown, by appropriately selecting the value of the current Icst and the scaling factor between the current Iprop and the difference Vsup-Vout, the time period TOFF ends at time t3b.

[0138] Therefore, when the current IL becomes zero, the time period TOFF ends, and the current IL then remains zero.

[0139] As a result, the energy efficiency of the switch-mode power supply 1, including circuit 400, is relative to... Figure 1 The situation shown (where the switch-mode power supply does not include circuit 400) is improved.

[0140] Figure 7 It shows Figure 4 A more detailed example of the implementation of circuit 400. More specifically, Figure 7 A more detailed example of the implementation of the CORR circuit is shown.

[0141] exist Figure 7 In an example of the embodiment, the CORR circuit includes a MOS transistor T1. Transistor T1 has its gate and drain connected to node 700. Node 700 is a comparison node capable of comparing current Iprop and current Icst (i.e., comparing the difference Vsup-Vout with a threshold Vth). More specifically, node 700 is configured to receive current Iprop and a constant current Icst such that transistor T1 is turned off when current Iprop is greater than the constant current Icst, and turned on when current Iprop is less than the constant current Icst. Furthermore, when transistor T1 is on, a current Idiff equal to Icst-Iprop flows through transistor T1.

[0142] As an example, transistor T1 has a P-channel and its source is coupled (preferably connected) to node 100 at the receiving potential Vsup.

[0143] Figure 7 The example circuit 700 also includes a MOS transistor T2 assembled with transistor T1 as a current mirror and configured to supply current Icorr to node 402. Due to the fact that transistors T1 and T2 are assembled as a current mirror, the current Icorr flowing through transistor T2 is proportional to, for example, equal to, the current Idiff flowing through transistor T1.

[0144] Since the current Idiff is zero when the current Iprop is greater than the current Icst, and the current Idiff is equal to Icst-Iprop when the current Iprop is less than the current Icst, the current Icorr is zero when the current Iprop is greater than the current Icst (Vsup-Vout is greater than Th), and the current Icorr is proportional to Icst-Iprop when the current Iprop is less than the current Icst (Vsup-Vout is less than Th).

[0145] As an example, transistor T2 has a P-channel and its gate is coupled (preferably connected) to the gate of transistor T1, its source is coupled (preferably connected) to node 100, and its drain is coupled (preferably connected) to node 402.

[0146] As an example, such as Figure 7As shown, current source 404 includes, for example, a MOS transistor T3 having a P-channel. For example, transistor T3 has its source coupled (preferably connected) to node 100 and its drain coupled (preferably connected) to node 700. The gate of transistor T3 receives a potential Vprop, which is configured such that the current Iprop flowing through transistor T3 is proportional to the difference Vsup-Vout.

[0147] As an example, such as Figure 7 As shown, current source 406 includes, for example, a MOS transistor T4 having an N-channel. For example, transistor T4 has its source coupled (preferably connected) to node 100 and its drain coupled (preferably connected) to node 700. The gate of transistor T4 receives a constant potential Vcst that determines the value of the constant current Icst flowing through transistor T4.

[0148] As an example, such as Figure 7 As shown, current source 408 includes, for example, a MOS transistor T5 having a P-channel. For example, transistor T5 has its source coupled (preferably connected) to node 100 and its drain coupled (preferably connected) to node 402. The gate of transistor T5 is configured such that the current Iprop flowing through transistor T3 is a potential proportional to the current IbN.

[0149] For example, the potential applied to the gate of transistor T5 is configured such that the current IbN is proportional to the difference Vsup-Vout. According to an embodiment, current source 408 then includes a current mirror with current source 404, such that the current IbN is proportional to or equal to the current Iprop. For example, the potential applied to the gate of transistor T5 is potential Vprop, and transistor T5 and transistor T3 are assembled as a current mirror.

[0150] As another example, the potential applied to the gate of transistor T5 is configured such that the current IbN is constant.

[0151] According to an embodiment, circuit 400 is also configured to supply a current IpP of a value for a defined time period TON. In this case, circuit 400 includes components configured to (e.g., to supply) Figure 1 The ramp generator VP of the switch-mode power supply 1 (input 108) supplies a current source 702 for the current IbP. For example, the current source 702 is connected between node 100 and input 108. For example, the current source 702 includes a MOS transistor T6 configured to supply the current IbP. For example, the MOS transistor T6 has a P-channel and its source is coupled (preferably connected) to node 100, and its gate receives a potential that determines the value of the current IbP flowing through the transistor T6.

[0152] Specifically, when the current IbP is proportional to the difference Vsup-Vout, the current source 702 may include a current mirror with the current source 404, such that the current IbP is equal to or proportional to the current Iprop. For example, transistor T6 and transistor T3 are assembled as a current mirror and receive a potential Vprop on their gates.

[0153] Figure 8 It shows Figure 4 and Figure 7 A more detailed example of the implementation of the current source 402 in circuit 400.

[0154] Current source 404 includes a MOS transistor T7 and a resistor R connected in series between nodes 100 and 104. Current source 404 also includes an operational amplifier AOP. Amplifier AOP is configured to control transistor T7 such that the voltage across resistor R is equal to Vsup-Vout, and the current I1 flowing through resistor R is then equal to (Vsup-Vout) / R, and therefore proportional to Vsup-Vout.

[0155] For example, the first input terminal of amplifier AOP (e.g., the non-inverting (+) input terminal) is coupled (preferably connected) to node 800 connecting transistor T7 and resistor R, the second input terminal of amplifier AOP (e.g., the inverting input terminal (-)) is configured to receive a regulated voltage Vout, and the output terminal of amplifier is connected to the gate of transistor T7.

[0156] The current source 404 also includes at least one current mirror configured to supply current Iprop according to the current I1 flowing through transistor T7.

[0157] For example, transistor T7 has an N-channel and its source is coupled (preferably connected) to node 104, and its drain is coupled (preferably connected) to node 800.

[0158] For example, current source 404 includes two current mirrors to supply current Iprop from current I1. For example, the first current mirror includes a MOS transistor T8 assembled with transistor T7 as a current mirror. For example, transistor T8 has a P-channel and its source is coupled (preferably connected) to node 104, and its gate is coupled (preferably connected) to the gate of transistor T7. For example, the second current mirror includes a transistor T9 connected in series with transistor T8 and a transistor T3 assembled with transistor T9 as a current mirror. For example, transistor T9 has an N-channel and its source is coupled (preferably connected) to node 100, its drain is connected to the gate of transistor T9 and the drain of transistor T8, and its gate is connected to the gate of transistor T3. Potential Vprop is then available at the gate of transistor T9.

[0159] Figure 9This illustrates the case where current IbNcorr is received at input terminal 110 of generator RN. Figure 1 A more detailed example of the implementation of the ramp generator RN for switch-mode power supply 1. In this example, the ramp VN is a ramp that decreases from the potential Vsup.

[0160] The ramp generator RN includes a capacitor C1 and a switch IT1 connected in parallel. The parallel combination of the capacitor and the switch is configured to receive a charging (increasing the VN ramp) or discharging (decreasing the VN ramp) current from the capacitor C1, which is proportional to the current IbNcorr.

[0161] In this example, the generator RN includes a current mirror comprising an N-channel MOS transistor T10 connected between input 110 and node 104, and an N-channel MOS transistor T11 assembled mirror-with transistor T10.

[0162] For example, transistor T10 couples its source (preferably connected) to node 104, its drain (preferably connected) to input terminal 110 and the gate of transistor T10, and its gate is connected to the gate of transistor T11, whose source is coupled (preferably connected) to node 104. Therefore, the current I2 in transistor T11 is proportional to, for example, equal to, the current IbNcorr.

[0163] exist Figure 9 In the example, the parallel combination of capacitor C1 and switch IT1 receives current I2. For example, the parallel combination of capacitor C1 and switch IT1 is connected between transistor T11 (e.g., the drain of transistor T11) and node 100. A voltage ramp VN is obtained at the terminal of the parallel combination of capacitor C1 and switch IT1 connected to transistor T11. Switch IT1 is controlled by the signal crtlRN, such that... Figure 9 In the example shown, switch IT1 switches from the on state to the off state at the start of ramp VN and switches from the off state to the on state at the end of each ramp VN, for example as a response to detecting that ramp VN has crossed a threshold voltage determined by voltage Vref.

[0164] Figure 10 It shows Figure 1 A more detailed example of the implementation of the ramp generator RP of the switch-mode power supply 1, wherein the input 108 of the generator RP receives the current IbP. In this example, the ramp VP is a ramp that increases from zero.

[0165] The ramp generator RP includes a capacitor C2 and a switch IT2 connected in parallel. The parallel combination of capacitor C2 and switch IT2 is configured to receive charging (increased VP ramp) or discharging (decreased VP ramp) current from capacitor C2, which is proportional to the current IbP.

[0166] In this example, the generator RP does not include a current mirror configured to supply charging or discharging current from current IbP to capacitor C2, although this could be the case in other examples.

[0167] exist Figure 10 In the example, the parallel combination of capacitor C2 and switch IT2 receives the charging current IbP directly from capacitor C2. For example, the parallel combination of capacitor C2 and switch IT2 is connected between input terminal 108 and node 104. Switch IT2 is controlled by the signal crtlRP, such that... Figure 10 In the example, switch IT2 switches from the on state to the off state at the start of ramp VP and switches from the off state to the on state at the end of each ramp VP, for example as a response to detecting that ramp VP has crossed a threshold voltage determined by voltage Vref.

[0168] Various embodiments and variations have been described. Those skilled in the art will understand that certain features of these different embodiments and variations can be combined, and other variations will occur to them. In particular, the implementation of the circuit CORR, current source 404, other current sources, and ramp generators RP and RN is not limited to the examples described above. For example, it can be... Figure 7 In circuit 400, the potentials Vsup and GND received by the corresponding nodes 100 and 104 of the circuit are reversed by replacing each N-channel transistor with a P-channel transistor and vice versa. Similar modifications can be made in... Figure 8 In the circuit, Figure 9 In the circuit and / or Figure 10 It is carried out in the circuit.

[0169] Finally, based on the functional indications given above, the actual implementation of the described embodiments and variations is within the capabilities of those skilled in the art. In particular, those skilled in the art can determine the value of the threshold Th (e.g., from computer-aided simulation) to determine the value of the difference Vsup-Vout, below which, in the absence of circuit 400, an event occurs related to… Figure 3The described operation, i.e., if circuit 400 is not used, results in a negative current IL at the end of the time period TOFF due to the lower of the difference Vsup-Vout values. Furthermore, those skilled in the art can determine the value of the current Icst, as well as the scaling factors between the current Iprop and the difference Vsup-Vout, the scaling factors between the current Idiff and the current Icorr, and the scaling factors between the current IbN and the difference Vsup-Vout, such that the current IL is zero at the end of each time period TOFF.

Claims

1. A switch-mode power supply, comprising: A high-side switch is connected between a first node configured to receive a power supply potential Vsup and a second node configured to be coupled to a supply node via an inductor, the supply node being configured to supply a regulated voltage Vout. A low-side switch is connected between the second node and a third node configured to receive a reference potential; The control circuit for controlling the high-side switch and the low-side switch is configured to, in each operating cycle: The first time period during which the high-side switch is in the on state is controlled is constant or proportional to 1 / (Vsup-Vout); and At the end of the first time period, a second time period is controlled in the on state of the low-side switch, the second time period being proportional to the reciprocal of the first current; as well as The correction circuit is configured as follows: A second current, which is proportional to Vsup-Vout, is compared with a constant current. and The supply is equal to the first current, which is equal to the third current plus the fourth current. When the second current is greater than the constant current, the fourth current is zero. When the second current is less than the constant current, the fourth current is proportional to the constant current minus the second current.

2. The switch-mode power supply according to claim 1, wherein, The control circuit is configured to control the high-side switch and the low-side switch in pulse frequency modulation and intermittent conduction mode.

3. The switch-mode power supply according to claim 1, wherein, The correction circuit includes: A first circuit for generating the fourth current is configured to supply the fourth current to a current summing node; A first current source is configured to supply the second current to the first circuit used to generate the fourth current; A second current source is configured to supply the constant current to the first circuit used to generate the fourth current; and A third current source is configured to supply the third current to the current summing node, wherein the first current is available at the current summing node.

4. The switch-mode power supply according to claim 3, wherein, The first circuit for generating the fourth current includes: A first metal-oxide-semiconductor (MOS) transistor, the gate of which and the drain of which are connected to a current comparison node configured to receive the second current and the constant current, such that: When the second current is greater than the constant current, the first MOS transistor is turned off; and When the second current is less than the constant current, the first MOS transistor is turned on, and a current equal to the constant current minus the second current flows through the first MOS transistor; and The second MOS transistor, assembled with the first MOS transistor as a current mirror, is configured to supply the fourth current.

5. The switch-mode power supply according to claim 3, wherein, The first current source includes: A MOS transistor and a resistor are connected in series between the first node and the third node; An operational amplifier having a first input terminal connected to a fourth node, a second input terminal configured to receive the regulated voltage, and an output terminal connected to the gate of the MOS transistor, the fourth node connecting the MOS transistor to the resistor; and At least one current mirror is configured to supply the second current based on the current flowing through the MOS transistor.

6. The switch-mode power supply according to claim 5, wherein, The third current source includes at least one second current mirror, which is configured to supply the third current based on the current flowing through the MOS transistor of the first current source.

7. The switch-mode power supply according to claim 3, wherein, The third current source includes at least one current mirror to the first current source, the current mirror being configured to supply the third current based on a second current flowing through the first current source.

8. The switch-mode power supply according to claim 1, wherein, The third current is constant or proportional to 1 / (Vsup-Vout).

9. The switch-mode power supply according to claim 1, wherein: The switch-mode power supply includes a generator having a first voltage ramp with a first slope proportional to the first current; and The control circuit is configured to, in each second time period: At the start of the second time period, control the start of the first slope; Compare the first ramp with the first threshold; and The second time period terminates when the first slope crosses the first threshold.

10. The switch-mode power supply according to claim 9, wherein: The switch-mode power supply includes a generator with a second voltage ramp having a second slope proportional to the constant current or proportional to Vsup-Vout; and The control circuit is configured to, in each first time period: At the start of the first time period, control the start of the second ramp; Compare the second ramp with the second threshold; and The first time period ends when the second slope crosses the second threshold.

11. The switch-mode power supply according to claim 3, wherein: The switch-mode power supply includes a generator having a first voltage ramp with a first slope proportional to the first current; and The control circuit is configured to, in each second time period: At the start of the second time period, control the start of the first slope; Compare the first ramp with the first threshold; and The second time period terminates when the first slope crosses the first threshold. The switch-mode power supply includes a generator having a second voltage ramp with a second slope proportional to a fifth current, said fifth current being proportional to Vsup-Vout; The control circuit is configured to: At the start of the first time period, control the start of the second ramp; Compare the second ramp with the second threshold; and The first time period ends when the second slope crosses the second threshold. The switch-mode power supply includes a fourth current source configured to supply the fifth current; as well as The fourth current source includes at least one current mirror to the first current source, the at least one current mirror being configured to supply the fifth current according to a second current flowing through the first current source.

12. The switch-mode power supply of claim 1, wherein the switch-mode power supply is configured to reduce the second time period when the difference Vsup-Vout decreases and the fourth current is not zero.

13. A method for controlling a switch-mode power supply, the switch-mode power supply comprising a high-side switch connected between a first node and a second node, and a low-side switch connected between the second node and a third node, the method comprising: The power supply potential Vsup is received by the first node; A regulated voltage Vout is supplied by a supply node coupled to the second node via an inductor; The reference potential is received by the third node; as well as In each operating cycle, the control circuit: The first time period during the conduction state of the high-side switch is constant or proportional to 1 / (Vsup-Vout); as well as At the end of the first time period, a second time period is controlled in the on state of the low-side switch, and the second time period is proportional to the reciprocal of the first current. The correction circuit compares a second current, which is proportional to Vsup-Vout, with a constant current. as well as The first current, which is equal to the third current plus the fourth current, is supplied by the correction circuit. The fourth current is zero in response to the second current being greater than the constant current, and is proportional to the constant current minus the second current in response to the second current being less than the constant current.

14. The method of claim 13, further comprising controlling the high-side switch and the low-side switch by a control circuit in a pulse frequency modulation and intermittent conduction mode.

15. The method of claim 13, further comprising: The first circuit of the correction circuit generates a fourth current and supplies the fourth current to the current summing node; The first current source of the correction circuit supplies the second current to the first circuit used to generate the fourth current. The constant current is supplied to the first circuit for generating the fourth current by the second current source of the correction circuit; as well as The third current is supplied to the current summing node by the third current source of the correction circuit, and the first current is available at the current summing node.

16. The method of claim 15, wherein the first circuit comprises a first metal-oxide-semiconductor (MOS) transistor having its gate and drain connected to a current comparison node, and the method comprises: The second current and the constant current are received by the current comparison node; In response to the second current being greater than the constant current, the first MOS transistor is disconnected; In response to the second current being less than the constant current, the first MOS transistor is turned on, and a current equal to the constant current minus the second current flows through the first MOS transistor; as well as The fourth current is supplied by the second MOS transistor of the first circuit, which forms a current mirror with the first MOS transistor.

17. The method of claim 13, wherein the third current is constant or proportional to 1 / (Vsup-Vout).

18. The method of claim 13, further comprising: A first voltage ramp with a first slope proportional to the first current is generated by a first generator; as well as At each second time period: At the start of the second time period, the control circuit controls the initiation of the first ramp; The control circuit compares the first ramp with the first threshold; and When the first ramp crosses the first threshold, the second time period is terminated by the control circuit.

19. The method of claim 18, further comprising: A second voltage ramp with a second slope proportional to the constant current or proportional to Vsup-Vout is generated by a second generator; At each first time period: At the beginning of the first time period, the control circuit controls the start of the second ramp; The control circuit compares the second ramp with the second threshold; and When the second ramp crosses the second threshold, the first time period is terminated by the control circuit.

20. The method of claim 13, further comprising reducing the second time period in response to a decrease in the difference Vsup-Vout and a non-zero fourth current.

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