Phase management method for multi-phase interleaved FSBB converter based on quasi-peak current control strategy

Abstract

The application provides a phase management method of a multi-phase interleaved FSBB converter based on a quasi-peak current control strategy, and belongs to the technical field of quasi-peak current control. The application comprises the following steps: each phase FSBB converter follows a quasi-peak current control strategy under multi-phase interleaved control, and a logic conditioning circuit of a converter control circuit shares an output signal of a compensator; three management modes are constructed, including a parallel phase management mode, an I-type serial phase management mode and a II-type serial phase management mode; the phase management mode is replaced by changing an input signal of a phase management mode circuit in the logic conditioning circuit; inductance current regulation, dynamic phase adjustment and error correction. In the application, the FSBB converter keeps real-time dynamic interleaving under quadrilateral current modulation; has a phase error correction mechanism; adjusts the phase shift only at an interval of one period; has no maximum interleaving phase number limit; and each switching device can keep zero voltage turn-on in a transient process.

Description

Technical Field

[0001] This invention relates to a phase management method for a multiphase interleaved parallel FSBB converter based on a quasi-peak current control strategy, belonging to the field of quasi-peak current control technology. Background Technology

[0002] The Four Switch Buck-Boost (FSBB) converter, as a power conversion topology with both boost and buck capabilities, can be cascaded with an LLC DCX to achieve high-voltage, high-current power conversion from 48V to 1.8V required by AI computing chips such as GPUs and CPUs. The FSBB, as a pre-regulator module, is primarily responsible for handling a wide range of input voltages and stabilizing the 1.8V power supply voltage to the terminal chip.

[0003] Patent application number 202211603927.5 discloses a quasi-peak current control method for a four-switch Buck-Boost converter. It reveals a quadrilateral current regulation strategy and its implementation method for a single-phase FSBB converter. This method obtains the desired switching timing by accurately sampling the current signal on the inductor L in the FSBB converter and inputting it to a logic conditioning circuit. The control strategy is a variable frequency, variable duty cycle control strategy, which does not require input voltage detection and can achieve zero-voltage turn-on of all switching devices across the entire load range and the entire input voltage range. Through corresponding optimization design methods, the effective value of the inductor current can be reduced, achieving high frequency, miniaturization, and high efficiency of the converter. Furthermore, the quasi-peak current control strategy can achieve automatic and smooth transitions between boost and buck converters, as well as between continuous heavy-load current and discontinuous light-load current, without changing the control logic. Finally, the control strategy does not require complex calculations, can be implemented using a mixed-signal circuit, and has good real-time performance.

[0004] However, with the exponential increase in power consumption of AI computing chips, single-phase FSBBs often cannot meet the power requirements of the chips, necessitating multi-phase interleaved parallel connection to achieve: 1) expand power capacity; 2) reduce bus voltage ripple; and 3) improve dynamic response capability. However, the quadrilateral current modulation control of FSBBs has many degrees of freedom and complex coupling relationships between them. Furthermore, the quasi-peak current control strategy is a variable frequency, variable duty cycle control strategy, which presents significant challenges in dynamic phase management for multi-phase interleaved parallel FSBBs. This invention addresses the aforementioned application scenario requirements and the phase management challenges faced by multi-phase interleaved parallel FSBBs by proposing a phase management method for multi-phase interleaved parallel FSBB converters based on the quasi-peak current control strategy of single-phase FSBB converters. Summary of the Invention

[0005] The purpose of this invention is to solve the problems existing in the prior art and to meet the increasing power and dynamic response requirements in the power supply scenarios of AI computing chips. Specifically, for the front-stage FSBB converter in the FSBB+LLC two-stage chip power supply architecture, a phase management method for a multi-phase interleaved parallel FSBB converter based on a single-phase quasi-peak current control strategy is provided.

[0006] The objective of this invention is achieved through the following technical solution:

[0007] A phase management method for a multiphase interleaved parallel FSBB converter based on a quasi-peak current control strategy includes the following steps:

[0008] Step 1: In the multi-phase interleaved parallel FSBB converter, each phase of the FSBB converter follows a quasi-peak current control strategy under multi-phase interleaved parallel regulation. The control circuit of each phase FSBB converter includes a current sampling circuit and a set of logic conditioning circuits. The logic conditioning circuits of each phase share a compensator output signal. The current sampling circuit samples the inductor current signals of each phase. The output is sent to the logic conditioning circuit to form the switching timing of each phase and input to the drive circuit to obtain the final switching drive signal;

[0009] Step 2: Based on Step 1, construct three multi-phase interleaved parallel dynamic phase management modes, including: parallel phase management mode, Type I serial phase management mode, and Type II serial phase management mode; change the phase management mode by changing the input signal of the phase management paradigm circuit in the logic conditioning circuit.

[0010] Step 3: Inductor current adjustment, dynamic phase adjustment, and error correction; each phase outputs a signal from the compensator. Under the action of the switch, the current of each inductor is adjusted in real time; by determining the turn-on / turn-off time of the corresponding phase FSBB converter switch Q1, the current sampling signal of each phase inductor is used. Clamping phase in Phase adjustment and error correction can be achieved by flexibly adjusting the phase current period.

[0011] Preferably, the quasi-peak current control strategy described in step one is as follows:

[0012] The inductor current of each phase in step one It consists of four stages, namely the input stage. Input-output stage descent phase and clamping phase To enable the switching device to achieve zero-voltage turn-on, the absolute value of the inductor current must be greater than or equal to the minimum zero-voltage turn-on current at the switching points of the four stages. It is determined by equation (1), and the formula is as follows:

[0013] (1)

[0014] in, For the drain-source parasitic capacitance of the switching device, Dead time, Input voltage, Output voltage; Input stage With input-output stage The switching point is point A, and the input-output stage With the decline phase The switching point is point B, during the descent phase. With clamping phase The switching point is point C, during the clamping phase. With the next cycle input phase The switching point is point D;

[0015] The compensator output signal Used to adjust the amplitude of point A in the inductor current waveform ,Right now Simultaneous input phase and input-output stage The sum of time is made up of and proportionality coefficient The decision is made jointly, as given by equation (2), and the formula is as follows:

[0016] (2)

[0017] in, Inductor for FSBB converter The sensitivity value;

[0018] Therefore, the current amplitude at point B can be obtained. and the decline phase The duration is given by formulas (3) and (4), as follows:

[0019] (3)

[0020] (4)

[0021] During the clamping phase Used to fill time gaps, limiting the minimum work cycle to The inductor current is discontinuous; During the clamping phase Discarded, the inductor current is continuous, therefore the inductor current real-time duty cycle Given by (5), and mainly related to the input voltage and load current Related to, affected The regulation formula is as follows:

[0022] (5).

[0023] Preferably, the logic conditioning circuit in step one includes: a Q1 turn-on / Q2 turn-off logic circuit, a Q2 turn-on / Q1 turn-off logic circuit, a Q3 turn-on / Q4 turn-off logic circuit, and a Q3 turn-on / Q4 turn-off logic circuit.

[0024] The Q1 turn-on / Q2 turn-off logic circuit includes: a first OR gate OR1, a first AND gate AND1, a first comparator CP1, a first timer, a second timer, and a phase management paradigm circuit;

[0025] The output of the phase management paradigm circuit, the output of the first comparator CP1, and the output of the second timer are respectively connected to the input of the first AND gate AND1, and the output of the first AND gate AND1 and the output of the first timer are respectively connected to the input of the first OR gate OR1.

[0026] The phase management paradigm circuit includes: a second comparator CP2, a third timer, a fourth timer, a gain G1, and a latch; the output of the third timer is connected to the non-inverting input of the second comparator CP2, the output of the fourth timer is connected to the input of the gain G1, the output of the gain G1 is connected to the input of the latch, and the output of the latch is connected to the inverting input of the second comparator CP2.

[0027] Q2 turn-on / Q1 turn-off logic circuit: second OR gate OR2, second AND gate AND2, third comparator CP3, fourth comparator CP4, fifth timer and gain G2;

[0028] The output of the third comparator CP3 is connected to the input of the second AND gate AND2, the output of the fifth timer is connected to the non-inverting input of the fourth comparator CP4, the output of the gain G2 is connected to the inverting input of the fourth comparator CP4, and the outputs of the second AND gate AND2 and the fourth comparator CP4 are respectively connected to the input of the second OR gate OR2.

[0029] The Q3 turn-on / Q4 turn-off logic circuit includes: a third AND gate AND3, a fifth comparator CP5, and a sixth comparator CP6; the outputs of the fifth comparator CP5 and the sixth comparator CP6 are respectively connected to the input of the third AND gate AND3.

[0030] The logic circuit for Q4 turn-on / Q3 turn-off is the seventh comparator CP7.

[0031] Preferably, the specific process of the parallel phase management mode in step two is as follows:

[0032] Point D is the starting point of the inductor current for each cycle. At this point, the FSBB converter's switch Q1 is turned on, triggering the main phase 1 switch Q1 to turn on with the signal P. Q1(1) Based on this, a fourth timer is used to record the two P phases of the main phase in real time. Q1(1) Trigger interval That is, the current The inductor current operates for one cycle, and the trigger interval for the next cycle from phase 2 is obtained based on the number of parallel phases n. The interval time is latched from phase 2 latch, P Q1(1) When the timer arrives, it starts counting from the third timer in phase 2 and compares it with the value in the latch. If they are equal, it controls the switch Q1 in phase 2 to turn on; similarly, it controls the switch Q1 in phase 2 to turn on. Q1(1) Based on this, the phase shift interval time of the next cycle is latched from phase 3 latch. P Q1(1) When the timer arrives, it is compared with the third timer of phase 3. If they are equal, the switch Q1 of phase 3 is turned on. This process is repeated for phase n. Q1(1) Based on this, the phase shift interval time of the next cycle is latched from the phase n latch. And compare it with the third timer of phase n; if they are equal, control the switch Q1 of phase n to turn on; the above phase shift interval time is adjusted in each latch. Updated periodically; furthermore, the trigger pulses for switches Q2, Q3, and Q4 are independently generated by the logic conditioning circuits of each of the n phases according to a quasi-peak current control strategy; when the load changes abruptly or the input voltage fluctuates, both the master phase and each slave phase are capable of being affected. The system has the ability to adjust the inductor current in real time, and each slave phase can adjust the phase shift interval in real time according to the current cycle of the master phase 1, with a lag of only one cycle. After stabilization, the current cycle of the master phase 1 becomes constant, and each phase naturally recovers. Evenly interlaced.

[0033] Preferably, the specific process of the Type I serial phase management mode in step two is as follows:

[0034] Point D is the starting point of the inductor current for each cycle. At this time, switch Q1 is turned on, triggering the switch Q1 of main phase 1 to turn on with the signal P. Q1(1) Based on this, a fourth timer is used to record the two P phases of the main phase in real time. Q1(1) Trigger interval That is, the current The inductor current operates for one cycle, and the trigger interval is obtained based on the number of parallel phases n. Latched into each of the latches from phase 2 to n; from phase 2, P Q1(1) Based on, PQ1(1) When the timer arrives, it starts counting from the third timer of phase 2 and compares it with the value in the latch. If they are equal, P is generated. Q1(2) The control is activated by switching transistor Q1 in phase 2; the control is activated by switching transistor Q1 in phase 3 triggered by the switch P in phase 2. Q1(2) Based on, P Q1(2) When the timer arrives, it starts counting from the third timer in phase 3 and compares it with the value in the latch. If they are equal, P is generated. Q1(3) The control signal P turns on the switch Q1 of phase 3; similarly, the control signal P turns on the switch Q1 of phase n-1. Q1(n-1) Based on, P Q1(n-1) When it arrives, start counting from the third timer of phase n and compare it with the value in the latch. If they are equal, generate P. Q1(n) The control starts from the turn-on of phase n switch Q1; the aforementioned phase shift interval time is adjusted in each latch. Updated periodically; in addition, the trigger pulses P of switches Q2, Q3 and Q4 Q2(1～n) P Q3(1～n) and P Q4(1～n) The current is generated independently by the logic conditioning circuits of each of the n phases according to a quasi-peak current strategy; when the load changes abruptly or the input voltage fluctuates, both the master phase and each slave phase are capable of withstanding the change. The system has the ability to adjust the inductor current in real time, and each slave phase can adjust the phase shift interval in real time according to the current cycle of the master phase 1, with a lag of only one cycle. After stabilization, the current cycle of the master phase 1 becomes constant, and each phase naturally recovers. Evenly interlaced.

[0035] Preferably, the specific process of the Type II serial phase management mode in step two is as follows:

[0036] Point D is the starting point of the inductor current for each cycle. At this time, switch Q1 is turned on, and the trigger signal P is generated by turning on switch Q1 in main phase 1 from phase 2. Q1(1) Based on this, a fourth timer is used to record the two P phases of the main phase in real time. Q1(1) Trigger interval That is, the current The operating cycle of the inductor current in the lower main phase 1 is determined, and the trigger interval is obtained based on the number of parallel phases n. P is latched into phase 2 latch. Q1(1) When the timer arrives, it starts counting from the third timer of phase 2 and compares it with the value in the latch. If they are equal, P is generated. Q1(2) The switch Q1 in phase 2 is turned on; the switch Q1 in phase 3 is turned on by the trigger signal P. Q1(2) Based on this, a fourth timer was used to record P twice in real time. Q1(2) Trigger interval That is, the current The operating cycle of the inductor current in phase 2 is calculated, and the trigger interval is obtained based on the number of parallel phases n. P is latched into phase 3 latch. Q1(2) When the timer arrives, it starts counting from the third timer in phase 3 and compares it with the value in the latch. If they are equal, P is generated. Q1(3) The control signal P turns on the switch Q1 of phase 3; similarly, the control signal P turns on the switch Q1 of phase n-1. Q1(n-1) Based on this, a fourth timer was used to record P twice in real time. Q1(n-1) Trigger interval That is, the current The operating cycle of the inductor current from phase n-1 is calculated, and the trigger interval is obtained based on the number of parallel phases n. P is latched into the n-phase latch. Q1(n-1) When the timer arrives, it starts counting from the third timer of phase n and compares it with the value in the latch. If they are equal, P is generated. Q1(n) The control starts by turning on the phase n switch Q1; the phase shift interval in each phase latch is updated periodically; in addition, the trigger pulses P of switches Q2, Q3, and Q4... Q2(1～n) P Q3(1～n) and P Q4(1～n) The current is generated independently by the logic conditioning circuits of each of the n phases according to a quasi-peak current strategy; when the load changes abruptly or the input voltage fluctuates, both the master phase and each slave phase are capable of withstanding the change. The inductor current can be adjusted in real time. The phase shift interval of the nth phase can be adjusted in real time according to the current cycle of the (n-1)th phase, with a lag of only one cycle. After stabilization, the current cycles of each phase are constant and naturally recover. Evenly interlaced.

[0037] Preferably, the step two method of changing the phase management mode by altering the input signal of the phase management paradigm circuit in the logic conditioning circuit is as follows:

[0038] 1) The input signals for the third and fourth timers are P and P, respectively. Q1(1) and P Q1(1) At this time, it is in parallel phase management mode;

[0039] 2) The input signals for the third and fourth timers are P and P, respectively. Q1(n-1) and P Q1(1) At this time, it is in Type I serial phase management mode;

[0040] 3) The input signals for the third and fourth timers are P and P, respectively. Q1(n-1) and P Q1(n-1) At this time, it is in Type II serial phase management mode.

[0041] Preferably, the specific method for determining the turn-on / turn-off times of the corresponding phase FSBB converter's switching transistors Q1 and Q2 in step three is as follows:

[0042] Phase-shift management signal output by the phase management paradigm circuit and The minimum duty cycle of the FSBB inductor current controlled by the comparison signal and timer 2. The first AND gate AND1 jointly determines the turn-on / turn-off times of the corresponding phase FSBB converter's switching transistors Q1 and Q2, thus realizing the use of the clamping stage. The phase current cycle can be flexibly adjusted to complete phase adjustment and error correction, preventing conflicts between phase shifting commands, soft switching conditions and quasi-peak current control logic in phase management mode.

[0043] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0044] 1) In this invention, the FSBB converter maintains real-time dynamic interleaved parallel connection under quadrilateral current modulation;

[0045] 2) This invention has an automatic phase error correction mechanism to dynamically prevent phase misalignment;

[0046] 3) This invention adjusts the phase shift interval by only one cycle, and the adjustment can be completed from the first phase.

[0047] 4) This invention has no maximum limit on the number of interleaved phases;

[0048] 5) During the transient process of this invention, each switching device can still maintain zero voltage turn-on;

[0049] 6) The phase management method of the present invention includes three modes: parallel phase management mode, type I serial phase management mode, and type II serial phase management mode. Attached Figure Description

[0050] Figure 1 This is a schematic diagram of the control architecture of the multiphase interleaved parallel FSBB converter of the present invention.

[0051] Figure 2 This is a schematic diagram of the inductor current adjustment of each phase FSBB under the quasi-peak current control strategy of the present invention.

[0052] Figure 3 This is a schematic diagram of the dynamic phase management process of the present invention.

[0053] Figure 4 This is a circuit diagram of the multiphase interleaved parallel FSBB quasi-peak current logic conditioning circuit of the present invention; wherein:

[0054] Figure 4 (a) is a circuit diagram of the parallel phase management mode;

[0055] Figure 4 (b) is a circuit diagram of the Type I serial phase management mode;

[0056] Figure 4 (c) is a circuit diagram of the Type II serial phase management mode;

[0057] Figure 5 This is a schematic diagram illustrating the transient performance of a three-phase interleaved FSBB cascaded LLC DCX in parallel phase management mode; where:

[0058] Figure 5 (a) is a schematic diagram of the transient process of loading from 25A to 550A;

[0059] Figure 5 (b) is a schematic diagram of the transient process of load reduction for 550A-25A.

[0060] Figure 6 This is a schematic diagram of the transient performance of a single-phase FSBB cascaded LLC DCX; where:

[0061] Figure 6 (a) is a schematic diagram of the transient process of loading from 25A to 550A;

[0062] Figure 6 (b) is a schematic diagram of the transient process of load reduction for 550A-25A. Detailed Implementation

[0063] The present invention will be further described in detail below with reference to the accompanying drawings: This embodiment is implemented under the premise of the technical solution of the present invention, and detailed implementation methods are given, but the protection scope of the present invention is not limited to the following embodiments.

[0064] like Figure 1 The diagram shown illustrates the control architecture of the multiphase interleaved FSBB converter proposed in this invention. The multiphase interleaved FSBB converter consists of Phases 1 to n, with each phase equipped with a current sampling circuit and a set of logic conditioning circuits. The logic conditioning circuits of each phase can share a single compensator output signal. Simultaneously, combined with the sampling signals of the inductor current of each phase The switching timing sequence of FSBB Phase 1 to n is formed and input to the drive circuit to obtain the final switching drive signal.

[0065] like Figure 2 As shown, this illustrates the basic principle of phase management for a multiphase interleaved parallel FSBB converter based on a quasi-peak current control strategy. Each phase of the FSBB converter follows this basic principle under multiphase interleaved parallel control, with the inductor current... It consists of four stages, namely the input stage. Input-output stage descent phase and clamping phase To ensure that the switching device can achieve zero-voltage turn-on, the absolute value of the inductor current must be greater than or equal to the minimum zero-voltage turn-on current at the four switching points A to D. It is determined by equation (1), as follows:

[0066] (1)

[0067] in, For the drain-source parasitic capacitance of the switching device, Dead time, Input voltage, This is the output voltage.

[0068] In the proposed quasi-peak current control strategy, the compensator output Used to adjust the amplitude of point A in the inductor current waveform ,Right now Simultaneous input phase and input-output stage The sum of time is made up of and proportionality coefficient The value is jointly determined and given by equation (2). Therefore, the current amplitude at point B can be obtained. and the decline phase Duration (3) and (4). During the clamping phase Used to fill time gaps, limiting the minimum work cycle to The inductor current is intermittent. During the clamping phase Discarded, the inductor current is continuous, therefore the inductor current real-time duty cycle Given by (5), and mainly related to the input voltage and load current Related to, affected Regulation. Other regulation details are the same as those in the prior art, namely the invention patent with patent application number 202211603927.5, which discloses the quasi-peak current control method of the four-switch Buck-Boost converter, and will not be repeated here.

[0069] (2) (3)

[0070] (4)

[0071] (5)

[0072] in, Inductor for FSBB converter The sensitivity value;

[0073] Based on the aforementioned fundamental principles, it is known that under the quasi-peak current control strategy, the operating cycle of the FSBB inductor current in each phase is affected in real time by the input voltage and load current. Therefore, in multi-phase interleaved parallel control, it is impossible to simply achieve phase shifting at fixed time intervals. An additional phase management method is needed to achieve dynamic phase shifting while maintaining the aforementioned control principle. Based on the quasi-peak current control strategy, this invention constructs the following multi-phase interleaved parallel dynamic phase management mode.

[0074] Mode 1: Based on Figure 2 As shown, point D is the starting point of the inductor current for each cycle. At this time, switch Q1 is turned on, triggered by the switch Q1 of main phase 1 being turned on by the signal P. Q1(1) Based on this, a fourth timer is used to record the two P phases of the main phase in real time. Q1(1) Trigger interval That is, the current The inductor current operates for one cycle, and the trigger interval for the next cycle from phase 2 is obtained based on the number of parallel phases n. The interval time is latched from phase 2 latch, P Q1(1) When the timer arrives, it starts counting from the third timer in phase 2 and compares it with the value in the latch. If they are equal, it controls the switch Q1 in phase 2 to turn on; similarly, it controls the switch Q1 in phase 2 to turn on. Q1(1) Based on this, the phase shift interval time of the next cycle is latched from phase 3 latch. P Q1(1) When the timer arrives, it is compared with the third timer of phase 3. If they are equal, the switch Q1 of phase 3 is turned on. This process is repeated for phase n. Q1 Based on this, the phase shift interval time of the next cycle is latched from the phase n latch. The time is compared with the third timer of phase n; if they are equal, the switch Q1 of phase n is turned on. The phase shift interval is adjusted in each latch. Updated cycle by cycle. Furthermore, the trigger pulses for switches Q2, Q3, and Q4 are independently generated by the logic conditioning circuits of each of the n phases according to a quasi-peak current strategy. When the load changes abruptly or the input voltage fluctuates, both the master phase and each slave phase are capable of withstanding... The system has the ability to adjust the inductor current in real time, and each slave phase can adjust the phase shift interval in real time according to the current cycle of the master phase 1, with a lag of only one cycle. After stabilization, the current cycle of the master phase 1 becomes constant, and each phase naturally recovers. Uniformly staggered. In mode one, each slave phase is triggered by the turn-on of the master phase 1 switch Q1 using the signal P. Q1(1) Based on this, it is called the parallel phase management mode.

[0075] Mode 2: Based on Figure 2As shown, point D is the starting point of the inductor current for each cycle. At this time, switch Q1 is turned on, triggered by the switch Q1 of main phase 1 being turned on by the signal P. Q1(1) Based on this, a fourth timer is used to record the two P phases of the main phase in real time. Q1(1) Trigger interval That is, the current The inductor current operates for one cycle, and the trigger interval is obtained based on the number of parallel phases n. The data is latched into the latches of each of phases 2 to n. Phase 2 is latched using P... Q1(1) Based on, P Q1(1) When the timer arrives, it starts counting from the third timer of phase 2 and compares it with the value in the latch. If they are equal, P is generated. Q1(2) The control switches Q1 and Q1 in phase 2 are turned on; the control switches Q1 and Q1 in phase 3 are turned on by the trigger signal P. Q1(2) Based on, P Q1(2) When the timer arrives, it starts counting from the third timer in phase 3 and compares it with the value in the latch. If they are equal, P is generated. Q1(3) The control starts by turning on switch Q1 in phase 3; similarly, the control starts by turning on switch Q1 in phase n-1, triggered by the signal P. Q1(n-1) Based on, P Q1(n-1) When it arrives, start counting from the third timer of phase n and compare it with the value in the latch. If they are equal, generate P. Q1(n) The control starts by turning on the phase n switch Q1. The aforementioned phase shift interval time varies in each latch. Updated cycle by cycle. In addition, the trigger pulses P for switches Q2, Q3, and Q4... Q2(1～n) P Q3(1～n) and P Q4(1～n) The phase management of each of the n phases is independently generated by the logic conditioning circuits of the multiphase interleaved parallel FSBB converter based on a quasi-peak current control strategy. When the load changes abruptly or the input voltage fluctuates, both the main phase and each slave phase are capable of withstanding [various changes]. The system has the ability to adjust the inductor current in real time, and each slave phase can adjust the phase shift interval in real time according to the current cycle of the master phase 1, with a lag of only one cycle. After stabilization, the current cycle of the master phase 1 becomes constant, and each phase naturally recovers. Uniformly staggered. In mode two, each slave phase is phase-shifted based on the turn-on trigger signal of the previous phase's switch Q1, hence it is called type I serial phase management mode.

[0076] Mode 3: Based on Mode 2, the following dynamic phase management modes can be further derived. For example... Figure 2 As shown, point D is the starting point of the inductor current for each cycle. At this time, switch Q1 is turned on, triggering the switch Q1 of main phase 1 to turn on from phase 2 with the signal P. Q1(1) Based on this, a fourth timer is used to record the two P phases of the main phase in real time. Q1(1) Trigger interval That is, the current The operating cycle of the inductor current in the lower main phase 1 is determined, and the trigger interval is obtained based on the number of parallel phases n. P is latched into phase 2 latch. Q1(1) When the timer arrives, it starts counting from the third timer of phase 2 and compares it with the value in the latch. If they are equal, P is generated. Q1(2) The switch Q1 in phase 2 is turned on; the switch Q1 in phase 3 is turned on by the trigger signal P. Q1(2) Based on this, a fourth timer was used to record P twice in real time. Q1(2) Trigger interval That is, the current The operating cycle of the inductor current in phase 2 is calculated, and the trigger interval is obtained based on the number of parallel phases n. P is latched into phase 3 latch. Q1(2) When the timer arrives, it starts counting from the third timer in phase 3 and compares it with the value in the latch. If they are equal, P is generated. Q1(3) The control signal P turns on the switch Q1 of phase 3; similarly, the control signal P turns on the switch Q1 of phase n-1. Q1(n-1) Based on this, a fourth timer was used to record P twice in real time. Q1(n-1) Trigger interval That is, the current The operating cycle of the inductor current from phase n-1 is calculated, and the trigger interval is obtained based on the number of parallel phases n. P is latched into the n-phase latch. Q1(n-1) When the timer arrives, it starts counting from the third timer of phase n and compares it with the value in the latch. If they are equal, P is generated. Q1(n) The control starts by turning on the phase n switch Q1. The phase shift interval in each phase latch is updated periodically. In addition, the trigger pulses P of switches Q2, Q3, and Q4 are also updated. Q2(1～n) P Q3(1～n) and P Q4(1～n) The current is generated independently by the logic conditioning circuits of each of the n phases according to a quasi-peak current strategy. When the load changes abruptly or the input voltage fluctuates, both the master phase and each slave phase are capable of withstanding the load changes. The inductor current can be adjusted in real time. The phase shift interval of the nth phase can be adjusted in real time according to the current cycle of the (n-1)th phase, with a lag of only one cycle. After stabilization, the current cycles of each phase are constant and naturally recover. Uniformly interleaved. In Mode 3, the reference signals and reference phase shift periods of each phase are all in series, hence it is called Type II serial phase management mode.

[0077] like Figure 3 As shown, taking a three-phase interleaved FSBB as an example, the process of inductor current regulation, dynamic phase adjustment, and error correction is illustrated. This represents the phase-shift management signal. First, in Before that time, the inductor current of each phase was operating at a high frequency and a small amplitude. At a certain moment, the load current experiences a step change, and the output voltage... A fall occurred. The inductor current increases under the action of the compensator, and the inductor current of each phase begins to be controlled under the quasi-peak current control strategy. Adjustment. In During the time period, both principal phase 1 and secondary phases 2 and 3 can be in Under the action of the clamping phase, the inductor currents of each phase are adjusted in real time, which helps to improve the system response speed. In the proposed phase management method for multiphase interleaved parallel FSBB converters based on a quasi-peak current control strategy, the clamping phase is utilized. The phase current period can be flexibly adjusted to prevent conflicts between phase shift commands and soft-switching conditions and control logic under the aforementioned phase management methods, thus achieving phase error correction. For example: 1) In At that moment, the inductor current of phase 3 had dropped back to The zero-voltage turn-on condition of its switching transistor Q1 is met, but the phase-shifting signal has not yet arrived at this time, and the clamping phase begins. This is introduced, causing a delay in the turn-on of switch Q1. Compared to Inside, the inductor current from phase 2 operates in a continuous state, while the inductor current from phase 3 is currently in a continuous state. The internal manifestation is a discontinuous state. At that moment, the current waveform from phase 2 is similar; 2) at At a certain moment, a phase-shift signal arrives from phase 3, but the current does not meet the zero-voltage turn-on condition for switch Q1 in the next cycle. Therefore, the phase-shift signal is invalidated, and the inductor current continues to operate according to the quasi-peak current control logic. Time arrives To prevent phase misalignment, switch Q1 is turned on with a delayed start-up during the clamping phase. Introduced, lasting until When the next phase shift command arrives, the zero-voltage turn-on condition of switch Q1 has been met, and the phase shift command can be successfully executed and real-time phase correction can be completed.

[0078] Combining the phase management method for multiphase interleaved parallel FSBB converters based on the aforementioned quasi-peak current control strategy, the following improvements can be made to the single-phase FSBB quasi-peak current control logic conditioning circuit. For example... Figure 4As shown in (a) to (c), a phase management paradigm circuit is constructed, comprising: a second comparator CP2, a third timer, a fourth timer, a gain G1, and a latch. The output of the third timer is connected to the non-inverting input of the second comparator CP2, the output of the fourth timer is connected to the input of the gain G1, the output of the gain G1 is connected to the input of the latch, and the output of the latch is connected to the inverting input of the second comparator CP2. This phase management paradigm circuit is integrated into the switching transistor Q1 turn-on / Q2 turn-off logic circuit, and the phase-shifting management signal... and The minimum duty cycle of the FSBB inductor current controlled by the comparison signal and timer 2. The AND gate AND1 jointly determines the turn-on time of switch Q1 and the turn-off time of switch Q2, realizing the clamping phase. The phase current cycle can be flexibly adjusted to complete phase adjustment and error correction, preventing conflicts between phase shifting commands, soft switching conditions and quasi-peak current control logic in the above phase management mode.

[0079] The first timer controls the maximum operating cycle of the FSBB inductor current. It mainly functions during the startup process, and under normal circumstances, the maximum stable operating period of the FSBB is less than [a certain value]. When the FSBB cycle time is greater than At that time, the timer 2 control signal is set first, followed by the phase management signal. When it arrives, if the inductor current of that phase... Less than or equal to This indicates that the ZVS condition for switch Q1 has been met, and CP1 outputs a high level. At this time, the phase management signal is valid and can be used together with the second timer and CP1 to set AND1 high, thus obtaining the turn-on signal P for switch Q1. Q1(n) ,accomplish Figure 3 middle Phase adjustment as shown at the time. If the inductor current of this phase... Greater than This indicates that the ZVS condition for switch Q1 is not met, CP1 outputs a low level, the phase management signal is invalid, AND1 output cannot be set high, and switch Q1 is delayed in turning on until the next cycle, thus achieving... Figure 3 middle Phase correction as shown at the time. When the FSBB is operating in discontinuous mode, as... Figure 2 As shown, A phase is added, inductor current First fall back to This causes CP1 to output a high level first. If the second timer goes high before the switching transistor Q1 can be turned on in advance, it must wait for the second timer to go high to ensure that the maximum operating frequency of FSBB is limited. Later than when the second timer goes high, the switch Q1 is turned on with a delay, thus achieving... Figure 3 middle Phase adjustment indicated by the time.

[0080] In addition, such as Figure 4 As shown, the constructed phase management paradigm circuit can change its phase management mode by altering its input signal:

[0081] 1) The input signal is P Q1(1) +P Q1(1) At this time, it is in parallel phase management mode;

[0082] 2) The input signal is P Q1(n-1) +P Q1(1) At this time, it is in Type I serial phase management mode;

[0083] 3) The input signal is P Q1(n-1) +P Q1(n-1) At this time, it is in Type II serial phase management mode. Specific Implementation Method 1

[0085] like Figure 5 The figure shows the simulation results of a three-phase interleaved FSBB cascaded LLC DCX in parallel phase management mode. Simulation conditions: input voltage Output voltage The load switching range is 25A ←→ 550A, and the load switching slope is di / dt = 5000A / µs. Main phase 1 inductor current, and These represent the inductor currents of slave phase 2 and slave phase 3, respectively. The figure details the implementation of steady-state multiphase interleaving and transient phase management, with the shaded area highlighting the phase error correction function of slave phase 2 and slave phase 3. During the transient loading process, The drop duration decreased to 7.8 µs, with a maximum drop of 70 mV. During the load shearing transient, The overshoot duration is 9µs, and the maximum overshoot is 60mV.

[0086] like Figure 6 As shown, for comparison, the single-phase FSBB cascaded LLC DCX is demonstrated with varying input voltage. Output voltage Simulation results are given with a load transition range of 25A to 550A, a load transition slope of di / dt = 5000A / µs, and all other conditions remaining constant. The output voltage during the transient loading process is... The drop duration was 13.5 µs, and the maximum drop was 190 mV. During the load shearing transient, The overshoot duration is 19.1 µs, and the maximum overshoot is 198 mV.

[0087] In summary, through verification and comparison, under the proposed multiphase interleaved FSBB quasi-peak current control strategy and its phase management method, the multiphase FSBB can achieve stable interleaving in steady state, dynamic phase management and phase error correction in transient state, and can significantly improve the transient response speed of FSBB cascaded LLC DCX. Compared with single phase, the output voltage drop / overshoot duration can be shortened by about 50%, and the drop / overshoot amplitude can be reduced by about 65%.

[0088] The above description is merely a preferred embodiment of the present invention. These specific embodiments are different implementations based on the overall concept of the present invention, and the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A phase management method for a multiphase interleaved parallel FSBB converter based on a quasi-peak current control strategy, characterized in that, Includes the following steps: Step 1: In the multi-phase interleaved parallel FSBB converter, each phase of the FSBB converter follows a quasi-peak current control strategy under multi-phase interleaved parallel regulation. The control circuit of each phase FSBB converter includes a current sampling circuit and a set of logic conditioning circuits. The logic conditioning circuits of each phase share a compensator output signal. ; The current sampling circuit samples the current signals of each phase inductor. The output is sent to the logic conditioning circuit to form the switching timing of each phase and input to the drive circuit to obtain the final switching drive signal; Step 2: Based on Step 1, construct three multi-phase interleaved parallel dynamic phase management modes, including: parallel phase management mode, Type I serial phase management mode, and Type II serial phase management mode; change the phase management mode by changing the input signal of the phase management paradigm circuit in the logic conditioning circuit. Step 3: Inductor current adjustment, dynamic phase adjustment, and error correction; each phase outputs a signal from the compensator. Under the action of the switch, the current of each inductor is adjusted in real time; by determining the turn-on / turn-off time of the corresponding phase FSBB converter switch Q1, the current sampling signal of each phase inductor is used. Clamping phase in Phase adjustment and error correction can be achieved by flexibly adjusting the phase current period.

2. The phase management method for a multiphase interleaved parallel FSBB converter based on a quasi-peak current control strategy according to claim 1, characterized in that, The quasi-peak current control strategy described in step one is as follows: The inductor current of each phase in step one It consists of four stages, namely the input stage. Input-output stage descent phase and clamping phase To enable the switching device to achieve zero-voltage turn-on, the absolute value of the inductor current must be greater than or equal to the minimum zero-voltage turn-on current at the switching points of the four stages. It is determined by equation (1), and the formula is as follows: (1) in, For the drain-source parasitic capacitance of the switching device, Dead time, Input voltage, Output voltage; Input stage With input-output stage The switching point is point A, and the input-output stage With the decline phase The switching point is point B, during the descent phase. With clamping phase The switching point is point C, during the clamping phase. With the next cycle input phase The switching point is point D; The compensator output signal Used to adjust the amplitude of point A in the inductor current waveform ,Right now Simultaneous input phase and input-output stage The sum of time is made up of and proportionality coefficient The decision is made jointly, as given by equation (2), and the formula is as follows: (2) in, Inductor for FSBB converter The sensitivity value; Therefore, the current amplitude at point B can be obtained. and the decline phase The duration is given by formulas (3) and (4), as follows: (3) (4) During the clamping phase Used to fill time gaps, limiting the minimum work cycle to The inductor current is discontinuous; During the clamping phase Discarded, the inductor current is continuous, therefore the inductor current real-time duty cycle Given by (5), and mainly related to the input voltage and load current Related to, affected The regulation formula is as follows: (5)。 3. The phase management method for a multiphase interleaved parallel FSBB converter based on a quasi-peak current control strategy according to claim 2, characterized in that, The logic conditioning circuit described in step one includes: a Q1 turn-on / Q2 turn-off logic circuit, a Q2 turn-on / Q1 turn-off logic circuit, a Q3 turn-on / Q4 turn-off logic circuit, and a Q3 turn-on / Q4 turn-off logic circuit. The Q1 turn-on / Q2 turn-off logic circuit includes: a first OR gate OR1, a first AND gate AND1, a first comparator CP1, a first timer, a second timer, and a phase management paradigm circuit; The output of the phase management paradigm circuit, the output of the first comparator CP1, and the output of the second timer are respectively connected to the input of the first AND gate AND1, and the output of the first AND gate AND1 and the output of the first timer are respectively connected to the input of the first OR gate OR1. The phase management paradigm circuit includes: a second comparator CP2, a third timer, a fourth timer, a gain G1, and a latch; the output of the third timer is connected to the non-inverting input of the second comparator CP2, the output of the fourth timer is connected to the input of the gain G1, the output of the gain G1 is connected to the input of the latch, and the output of the latch is connected to the inverting input of the second comparator CP2. Q2 turn-on / Q1 turn-off logic circuit: second OR gate OR2, second AND gate AND2, third comparator CP3, fourth comparator CP4, fifth timer and gain G2; The output of the third comparator CP3 is connected to the input of the second AND gate AND2, the output of the fifth timer is connected to the non-inverting input of the fourth comparator CP4, the output of the gain G2 is connected to the inverting input of the fourth comparator CP4, and the outputs of the second AND gate AND2 and the fourth comparator CP4 are respectively connected to the input of the second OR gate OR2. The Q3 turn-on / Q4 turn-off logic circuit includes: a third AND gate AND3, a fifth comparator CP5, and a sixth comparator CP6; the outputs of the fifth comparator CP5 and the sixth comparator CP6 are respectively connected to the input of the third AND gate AND3. The logic circuit for Q4 turn-on / Q3 turn-off is the seventh comparator CP7.

4. The phase management method for a multiphase interleaved parallel FSBB converter based on a quasi-peak current control strategy according to claim 3, characterized in that, The specific process of the parallel phase management mode described in step two is as follows: Point D is the starting point of the inductor current for each cycle. At this point, the FSBB converter's switch Q1 is turned on, triggering the main phase 1 switch Q1 to turn on with the signal P. Q1(1) Based on this, a fourth timer is used to record the two P phases of the main phase in real time. Q1(1) Trigger interval That is, the current The inductor current operates for one cycle, and the trigger interval for the next cycle from phase 2 is obtained based on the number of parallel phases n. The interval time is latched from phase 2 latch, P Q1(1) When the timer arrives, it starts counting from the third timer of phase 2 and compares it with the value in the latch. If they are equal, it controls the switch Q1 of phase 2 to turn on. From phase 3, also with P Q1(1) Based on this, the phase shift interval time of the next cycle is latched from phase 3 latch. P Q1(1) When the timer arrives, it is compared with the third timer of phase 3. If they are equal, the switch Q1 of phase 3 is turned on. This process is repeated for phase n. Q1(1) Based on this, the phase shift interval time of the next cycle is latched from the phase n latch. And compare it with the third timer of phase n; if they are equal, control the switch Q1 of phase n to turn on; the above phase shift interval time is adjusted in each latch. Updated periodically; furthermore, the trigger pulses for switches Q2, Q3, and Q4 are independently generated by the logic conditioning circuits of each of the n phases according to a quasi-peak current control strategy; when the load changes abruptly or the input voltage fluctuates, both the master phase and each slave phase are capable of being affected. The system has the ability to adjust the inductor current in real time, and each slave phase can adjust the phase shift interval in real time according to the current cycle of the master phase 1, with a lag of only one cycle. After stabilization, the current cycle of the master phase 1 becomes constant, and each phase naturally recovers. Evenly interlaced.

5. The phase management method for a multiphase interleaved parallel FSBB converter based on a quasi-peak current control strategy according to claim 4, characterized in that, The specific process of the Type I serial phase management mode described in step two is as follows: Point D is the starting point of the inductor current for each cycle. At this time, switch Q1 is turned on, triggering the switch Q1 of main phase 1 to turn on with the signal P. Q1(1) Based on this, a fourth timer is used to record the two P phases of the main phase in real time. Q1(1) Trigger interval That is, the current The inductor current operates for one cycle, and the trigger interval is obtained based on the number of parallel phases n. Latched into each of the latches from phase 2 to n; from phase 2, P Q1(1) Based on, P Q1(1) When the timer arrives, it starts counting from the third timer of phase 2 and compares it with the value in the latch. If they are equal, P is generated. Q1(2) The control switches Q1 and Q1 in phase 2 are turned on; the control switches Q1 and Q1 in phase 3 are turned on by the trigger signal P. Q1(2) Based on, P Q1(2) When the timer arrives, it starts counting from the third timer in phase 3 and compares it with the value in the latch. If they are equal, P is generated. Q1(3) The control starts by turning on the switch Q1 in phase 3; similarly, the control starts by turning on the switch Q1 in phase n-1, triggered by the signal P. Q1(n-1) Based on, P Q1(n-1) When it arrives, start counting from the third timer of phase n and compare it with the value in the latch. If they are equal, generate P. Q1(n) The control starts from the turn-on of phase n switch Q1; the aforementioned phase shift interval time is adjusted in each latch. Updated periodically; in addition, the trigger pulses P of switches Q2, Q3 and Q4 Q2(1～n) P Q3(1～n) and P Q4(1～n) The current is generated independently by the logic conditioning circuits of each of the n phases according to a quasi-peak current strategy; when the load changes abruptly or the input voltage fluctuates, both the master phase and each slave phase are capable of withstanding the change. The system has the ability to adjust the inductor current in real time, and each slave phase can adjust the phase shift interval in real time according to the current cycle of the master phase 1, with a lag of only one cycle. After stabilization, the current cycle of the master phase 1 becomes constant, and each phase naturally recovers. Evenly interlaced.

6. The phase management method for a multiphase interleaved parallel FSBB converter based on a quasi-peak current control strategy according to claim 5, characterized in that, The specific process of the Type II serial phase management mode described in step two is as follows: Point D is the starting point of the inductor current for each cycle. At this time, switch Q1 is turned on, and the trigger signal P is generated by turning on switch Q1 in main phase 1 from phase 2. Q1(1) Based on this, a fourth timer is used to record the two P phases of the main phase in real time. Q1(1) Trigger interval That is, the current The operating cycle of the inductor current in the lower main phase 1 is determined, and the trigger interval is obtained based on the number of parallel phases n. P is latched into phase 2 latch. Q1(1) When the timer arrives, it starts counting from the third timer of phase 2 and compares it with the value in the latch. If they are equal, P is generated. Q1(2) The switch Q1 in phase 2 is turned on; the switch Q1 in phase 3 is turned on by the trigger signal P. Q1(2) Based on this, a fourth timer was used to record P twice in real time. Q1(2) Trigger interval That is, the current The operating cycle of the inductor current in phase 2 is calculated, and the trigger interval is obtained based on the number of parallel phases n. P is latched into phase 3 latch. Q1(2) When the timer arrives, it starts counting from the third timer in phase 3 and compares it with the value in the latch. If they are equal, P is generated. Q1(3) The control signal P turns on the switch Q1 of phase 3; similarly, the control signal P turns on the switch Q1 of phase n-1. Q1(n-1) Based on this, a fourth timer was used to record P twice in real time. Q1(n-1) Trigger interval That is, the current The operating cycle of the inductor current from phase n-1 is calculated, and the trigger interval is obtained based on the number of parallel phases n. P is latched into the n-phase latch. Q1(n-1) When the timer arrives, it starts counting from the third timer of phase n and compares it with the value in the latch. If they are equal, P is generated. Q1(n) The control starts by turning on the phase n switch Q1; the phase shift interval in each phase latch is updated periodically; in addition, the trigger pulses P of switches Q2, Q3, and Q4... Q2(1～n) P Q3(1～n) and P Q4(1～n) The current is generated independently by the logic conditioning circuits of each of the n phases according to a quasi-peak current strategy; when the load changes abruptly or the input voltage fluctuates, both the master phase and each slave phase are capable of withstanding the change. The inductor current can be adjusted in real time. The phase shift interval of the nth phase can be adjusted in real time according to the current cycle of the (n-1)th phase, with a lag of only one cycle. After stabilization, the current cycles of each phase are constant and naturally recover. Evenly interlaced.

7. The phase management method for a multiphase interleaved parallel FSBB converter based on a quasi-peak current control strategy according to claim 6, characterized in that, The step two, which involves changing the input signal of the phase management paradigm circuit in the logic conditioning circuit to switch the phase management mode, is as follows: 1) The input signals for the third and fourth timers are P and P, respectively. Q1(1) and P Q1(1) At this time, it is in parallel phase management mode; 2) The input signals for the third and fourth timers are P and P, respectively. Q1(n-1) and P Q1(1) At this time, it is in Type I serial phase management mode; 3) The input signals for the third and fourth timers are P and P, respectively. Q1(n-1) and P Q1(n-1) At this time, it is in Type II serial phase management mode.

8. The phase management method for a multiphase interleaved parallel FSBB converter based on a quasi-peak current control strategy according to claim 7, characterized in that, The specific method for determining the turn-on / turn-off times of the corresponding phase FSBB converter's switching transistors Q1 and Q2 in step three is as follows: Phase-shift management signal output by the phase management paradigm circuit and The minimum duty cycle of the FSBB inductor current controlled by the comparison signal and timer 2. The first AND gate AND1 jointly determines the turn-on / turn-off times of the corresponding phase FSBB converter's switching transistors Q1 and Q2, thus realizing the use of the clamping stage. The phase current cycle can be flexibly adjusted to complete phase adjustment and error correction, preventing conflicts between phase shifting commands, soft switching conditions and quasi-peak current control logic in phase management mode.

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