Circuit for driving an isolated DC-DC resonant converter with isolated voltage sensing and ZVS / ZCS SR drive.

Abstract

Embodiments of the present disclosure relate to a circuit for driving an isolated DC-DC resonant converter with ZVS / ZCS SR driven with isolated voltage sensing. An isolated CLLC DC-DC converter includes transistors arranged in a full-bridge configuration on both primary and secondary sides, and a resonant assembly and transformer providing isolation between the two sides. A drive circuit arrangement monitors the switching node voltage to determine zero voltage and zero current conditions, improving switching efficiency. The converter adjusts its control strategy based on the relationship between the switching frequency and the resonant frequency. When the switching frequency exceeds the resonant frequency, the synchronous rectification transistors turn off based on a time delay signal. When the switching frequency is below the resonant frequency, the synchronous rectification transistors turn off based on a comparator signal at the zero current detection point. The converter is bidirectional, enabling the same hardware to operate in both charging and discharging modes by switching the primary drive and synchronous rectification function usage modes between the two sides. A threshold generation circuit arrangement produces a voltage reference that determines the precise switching timing in all operating conditions.

Description

Technical Field

[0001] This disclosure relates to DC-DC converter circuits, and more particularly to an isolated bidirectional CLLC resonant DC-DC converter having adaptive drive logic for optimizing conversion efficiency. Background Technology

[0002] Bidirectional isolated resonant DC-DC converters are widely used in electric vehicle chargers, energy storage systems, and renewable energy interfaces. Resonant DC-DC converters use a resonant tank circuit of reactive components to create a resonant waveform, thus providing soft switching, in which power transistors turn on or off when the voltage or current is zero. This contrasts with hard switching, where power transistors switch while simultaneously experiencing high voltage and high current, resulting in significant power losses compared to soft switching. Hard switching can cause 2% to 5% power loss per conversion, accounting for more than 30% of the converter's total loss budget in many applications. LLC converters (using an inductor-inductor-capacitor resonant tank circuit) and CLLC converters (adding another capacitor for bidirectional operation) are isolated resonant DC-DC converter topologies widely used due to their high efficiency (peak efficiency exceeding 98% in optimized implementations).

[0003] These converters operate through precise switching events to achieve zero-voltage switching (ZVS) during turn-on and zero-current switching (ZCS) during turn-off, thereby reducing or eliminating switching losses. The primary side typically uses a PWM signal with a 50% duty cycle and an adjustable dead time, while the secondary side (rectifier stage) uses diodes or semiconductor switches. Synchronous rectification (SR) stages are created using switches such as transistors.

[0004] In bidirectional converters used in battery chargers, the primary side and the SR stage interchange roles based on the direction of energy flow. This requires sensing circuitry in both stages to detect ZCS and ZVS conditions, increasing complexity and cost. Various sensing methods can be used for ZVS and ZCS detection, each facing different isolation challenges. Voltage sensing typically relies on optocouplers or digital isolators for high-voltage isolation, which introduce propagation delays in the 100ns to 500ns range and parasitic capacitances of 5pF to 20pF, distorting the timing of switching signals. Current sensing achieves isolation more directly through current transformers, but these components add 0.1% to 0.3% insertion loss, introduce a 2-degree to 5-degree phase shift due to transformer characteristics, and may present DC bias issues requiring compensation.

[0005] Furthermore, the increasing complexity of power systems in data centers, aerospace, and industrial automation demands more sophisticated power conversion solutions. The need for higher efficiency, smaller size, and greater reliability is driving the demand for novel DC-DC converter designs. This growing demand further increases the complexity of converter development by requiring multi-stage architectures that demand large amounts of precisely timed PWM signals and fast control responses to adapt the switching frequency to varying input and output conditions. Existing commercial solutions lack isolation capabilities, primarily because they are designed for single-stage converters with a common reference. Implementing isolation in these integrated circuits increases chip complexity, cost, and size, while potentially compromising the precise timing required for effective operation. Therefore, system designers must add external isolation components, further complicating circuit design and introducing an additional signal delay of 200ns to 500ns, which can reduce efficiency in high-frequency applications by 0.5% to 1.5%.

[0006] Given the continued growth in power demand, particularly in applications such as vehicle-to-grid systems and renewable energy interfaces, where efficient bidirectional power flow is critical and multi-stage converters are being used more widely, there is a need for further development. Summary of the Invention

[0007] This disclosure discloses an isolated DC-DC converter comprising: a primary-side circuit having a first full-bridge arrangement of transistors; a secondary-side circuit having a second full-bridge arrangement of transistors; a transformer coupling the primary-side circuit to the secondary-side circuit; and a drive circuit arrangement. The drive circuit arrangement monitors the switching node voltages on both the primary-side and secondary-side circuits; selectively operates in a charging mode or a discharging mode, wherein in the charging mode, the first full-bridge arrangement of transistors functions as a primary drive transistor, and the second full-bridge arrangement of transistors functions as a synchronous rectifier transistor; in the discharging mode, the second full-bridge arrangement of transistors functions as a primary drive transistor, and the first full-bridge arrangement of transistors functions as a synchronous rectifier transistor; detects a zero-current crossing point in a resonant current waveform; and adaptively controls the turn-off timing of the transistors used as synchronous rectifier transistors based on a relationship between the switching frequency and the resonant frequency of the converter, wherein the drive circuit arrangement turns off the transistors used as synchronous rectifier transistors based on a time-delay signal when the switching frequency exceeds the resonant frequency, and turns off the transistors used as synchronous rectifier transistors based on a comparator signal at the zero-current crossing point when the switching frequency is below the resonant frequency.

[0008] This isolated DC-DC converter is suitable for a wide range of applications, including but not limited to electric vehicles, renewable energy systems, data centers, aerospace, telecommunications, and industrial automation. The converter's design allows for integration with smart grid technologies, providing enhanced control and monitoring capabilities.

[0009] The driving circuit device may include: a first voltage sensing circuit device configured to monitor the switching node voltage of the primary side circuit; and a second voltage sensing circuit device configured to monitor the switching node voltage of the secondary side circuit.

[0010] The first voltage sensing circuit device may include a first pair of diodes coupled to a switching node of the primary side circuit, and the second voltage sensing circuit device may include a second pair of diodes coupled to a switching node of the secondary side circuit.

[0011] The driving circuit device may further include: a first comparator configured to compare a rectified voltage from a first voltage sensing circuit device with a first threshold voltage; and a second comparator configured to compare a rectified voltage from a second voltage sensing circuit device with a second threshold voltage.

[0012] The driving circuit device may further include a driving logic unit configured to generate a sawtooth waveform synchronized with the switching frequency and compare the sawtooth waveform with a plurality of threshold voltages to generate timing signals for controlling a first full-bridge arrangement of transistors and a second full-bridge arrangement of transistors.

[0013] The isolated DC-DC converter may include a threshold generation circuit configured to generate a plurality of threshold voltages, including: a turn-on threshold voltage indicating suitable conditions for turning on transistors in a first full-bridge arrangement and a second full-bridge arrangement while achieving zero-voltage switching; and a turn-off threshold voltage indicating suitable conditions for turning off transistors in the first full-bridge arrangement and the second full-bridge arrangement while achieving zero-current switching.

[0014] The threshold generation circuitry can also generate a blocking threshold voltage configured to prevent premature turn-off of transistors used as synchronous rectifier transistors in the first and second full-bridge arrangements.

[0015] The drive circuitry can be configured to enable and disable synchronous rectification during light-load conditions.

[0016] The primary-side circuit can be coupled to a bus voltage source, and the secondary-side circuit can be coupled to a battery voltage source.

[0017] In charging mode, power can flow from the primary side circuit to the secondary side circuit; and in discharging mode, power can flow from the secondary side circuit to the primary side circuit.

[0018] The driving circuitry may include: a mode selection input configured to select between a charging mode and a discharging mode; and a switching circuitry configured to route appropriate drive signals to a first full-bridge arrangement and a second full-bridge arrangement of transistors based on the selected mode, wherein the drive signals implement adaptive control of the turn-off timing based on the relationship between the switching frequency and the resonant frequency, such that the switching circuitry routes a time-delay signal or a comparator signal for turn-off control of either full-bridge arrangement used as a synchronous rectifier transistor in the selected mode, and wherein the comparator signal is also used to enable safe turn-on of the synchronous rectifier transistor when an appropriate zero-voltage switching condition is indicated.

[0019] A drive circuit arrangement for an isolated DC-DC converter having a primary side and a secondary side, each having a full-bridge transistor arrangement, the drive circuit arrangement may include: a first voltage sensing circuit arrangement, a second voltage sensing circuit arrangement, a first comparator, a second comparator, and a drive logic unit. The first voltage sensing circuit arrangement may include: a first diode, the cathode of which is coupled to a first switching node on the primary side; a second diode, the cathode of which is coupled to a second switching node on the primary side, wherein the anodes of the first and second diodes are connected to a first common node; a first resistor, coupled between a power supply voltage and the first common node; a first capacitor, connected between the first common node and a first ground reference; and a first isolation transformer, the primary side of which is connected between the first common node and the first ground reference. The second voltage sensing circuit may include: a third diode, the cathode of which is coupled to a first switching node on the secondary side; a fourth diode, the cathode of which is coupled to a second switching node on the secondary side, wherein the anodes of the third and fourth diodes are connected to a second common node; a second resistor, coupled between a power supply voltage and the second common node; a second capacitor, connected between the second common node and a second ground reference; and a second isolation transformer, the primary side of which is connected between the second common node and the second ground reference. A first comparator may couple its non-inverting input to the secondary side of the first isolation transformer, connect its inverting input to receive a first threshold voltage, and configure its output to provide a first comparator output signal. A second comparator may couple its non-inverting input to the secondary side of the second isolation transformer, connect its inverting input to receive a second threshold voltage, and configure its output to provide a second comparator output signal. A drive logic unit may be configured to generate gate drive signals for a full-bridge transistor arrangement based on the first and second comparator output signals.

[0020] The driving logic unit may include: a clock signal input; a voltage-controlled oscillator coupled to the clock signal input via an optional digital-to-analog converter (DAC); a sawtooth wave generator coupled to the output of the VCO; a first comparator, the non-inverting input of which is coupled to receive a sawtooth waveform from the sawtooth wave generator, and the inverting input of which is coupled to receive a first turn-on threshold voltage; a second comparator, the non-inverting input of which is coupled to receive the sawtooth waveform, and the inverting input of which is coupled to receive a first turn-off threshold voltage; a third comparator, the non-inverting input of which is coupled to receive the sawtooth waveform, and the inverting input of which is coupled to receive a second turn-on threshold voltage; and a fourth comparator, the non-inverting input of which is coupled to receive the sawtooth waveform, and the inverting input of which is coupled to receive a second turn-off threshold voltage.

[0021] The driving logic unit may further include: a first SR flip-flop having a set input coupled to the output of a first comparator, a reset input coupled to a clock signal input, and an output configured to provide a first primary drive signal; a second SR flip-flop having a set input coupled to the output of a third comparator, a reset input coupled to the output of the second comparator, and an output configured to provide a second primary drive signal; a first switch having a first input coupled to receive a first comparator output signal from the first comparator, a second input coupled to receive a second comparator output signal, and a control input coupled to receive a mode selection signal; and a second switch. The second switch has a first input coupled to receive a second comparator output signal from a second comparator, a second input coupled to receive a first comparator output signal, and a control input coupled to receive a mode selection signal; a first inverter has an input coupled to the output of the first switch; a fifth comparator has its non-inverting input coupled to receive a sawtooth waveform and its inverting input coupled to receive a first synchronous rectification turn-on threshold voltage; a first AND gate has a first input coupled to the output of the fifth comparator and a second input coupled to the output of the first inverter; and a third SR flip-flop has a first input coupled to the output of the first comparator and a second input coupled to the output of the first inverter. The output of an AND gate is set at its input; a sixth comparator, the non-inverting input of which is coupled to receive a sawtooth waveform, and the inverting input of which is coupled to receive a first synchronous rectification turn-off threshold voltage; a first OR gate, having a first input coupled to the output of the sixth comparator and a second input coupled to the output of a first switch and a second switch; a seventh comparator, the non-inverting input of which is coupled to receive a sawtooth waveform, and the inverting input of which is coupled to receive a first blocking threshold voltage; a second AND gate, having a first input coupled to the output of the first OR gate and a second input coupled to the output of the seventh comparator; the... The third SR flip-flop has a reset input coupled to the output of a second AND gate and an output configured to provide a first synchronous rectification drive signal; a second inverter has an input coupled to the output of a second switch and an input coupled to the output of a first switch; an eighth comparator has its non-inverting input coupled to receive a sawtooth waveform and its inverting input coupled to receive a second synchronous rectification turn-on threshold voltage; a third AND gate has a first input coupled to the output of the eighth comparator and a second input coupled to the output of the second inverter; and a fourth SR flip-flop has a set input coupled to the output of the third AND gate.A ninth comparator, the non-inverting input of which is coupled to receive a sawtooth waveform, and the inverting input of which is coupled to receive a second synchronous rectification turn-off threshold voltage; a second OR gate, having a first input coupled to the output of the ninth comparator and a second input coupled to the output of a second switch and also coupled to the output of a first switch; a tenth comparator, the non-inverting input of which is coupled to receive a sawtooth waveform, and the inverting input of which is coupled to receive a second blocking threshold voltage; a fourth AND gate, having a first input coupled to the output of the second OR gate and a second input coupled to the output of the tenth comparator; a fourth SR flip-flop, having a reset input coupled to the output of the fourth AND gate and an output configured to provide a second synchronous rectification drive signal.

[0022] The driving circuit device may further include a first fifth AND gate having a first input coupled to the output of a third SR flip-flop, a second input coupled to receive a synchronization enable signal, and an output configured to provide a first synchronous rectification drive signal; and a second sixth AND gate having a first input coupled to the output of a fourth SR flip-flop, a second input coupled to receive a synchronization enable signal, and an output configured to provide a second synchronous rectification drive signal.

[0023] The driving circuit device may further include an output switching circuit device having: a first set of switches configured to selectively route a first primary driving signal and a second primary driving signal or a first synchronous rectified driving signal and a second synchronous rectified driving signal to a driving input terminal of a full-bridge transistor arrangement on the primary side based on a mode selection signal; and a second set of switches configured to selectively route the first synchronous rectified driving signal and the second synchronous rectified driving signal or the first primary driving signal and the second primary driving signal to a driving input terminal of a full-bridge transistor arrangement on the secondary side based on a mode selection signal.

[0024] The driving logic unit may include a delay generator configured to receive a signal proportional to a clock signal and generate a plurality of delay signals, including: a first primary turn-on delay signal, a second primary turn-on delay signal, a second primary turn-off delay signal, a first synchronous rectification turn-on delay signal, a first synchronous rectification turn-off delay signal, a first blocking delay signal, a second synchronous rectification turn-on delay signal, a second synchronous rectification turn-off delay signal, and a second blocking delay signal.

[0025] The driving circuit device may further include: a first SR flip-flop having a set input coupled to receive a first primary turn-on delay signal, a reset input coupled to receive a clock signal, and an output configured to provide a first primary drive signal; a second SR flip-flop having a set input coupled to receive a second primary turn-on delay signal, a reset input coupled to receive a second primary turn-off delay signal, and an output configured to provide a second primary drive signal; a first inverter having an input coupled to a first comparator output signal or a second comparator output signal of a first sensing circuit device or a second sensing circuit device via a switching circuit device; a first AND gate having an input coupled to receive the output of the first inverter and a first synchronous rectification turn-on delay signal; a first OR gate having an input coupled to receive the first synchronous rectification turn-off delay signal and the first comparator output signal or the second comparator output signal of the first sensing circuit device or the second sensing circuit device via a switching circuit device; and a second AND gate having an input coupled to receive the first synchronous rectification turn-off delay signal and an input coupled to receive the first synchronous rectification turn-off delay signal and an input of the first comparator output signal or the second comparator output signal of the first sensing circuit device or the second sensing circuit device; and a second AND gate having an input coupled to receive the first primary drive signal. The system comprises: an OR gate output and an input to a first blocking delay signal; a third SR flip-flop having a set input coupled to the output of a first AND gate, a reset input coupled to the output of a second AND gate, and an output providing a first synchronous rectified signal; a second inverter having an input coupled to a first comparator output signal or a second comparator output signal of a first detection circuit or a second detection circuit via a switching circuit device; a third AND gate having an input coupled to receive the output of the second inverter and a second synchronous rectified turn-on delay signal; a second OR gate having an input coupled to receive a second synchronous rectified turn-off delay signal and a first comparator output signal or a second comparator output signal of a first sensing circuit or a second sensing circuit device via a switching circuit device; a fourth AND gate having an input coupled to receive the output of the second OR gate and a second blocking delay signal; and a fourth SR flip-flop having a set input coupled to the output of the third AND gate, a reset input coupled to the output of the fourth AND gate, and an output providing a second synchronous rectified signal.

[0026] The first ground reference can be connected to the control system ground associated with the drive logic unit, and the second ground reference can be electrically isolated from the first ground reference through a first isolation transformer and a second isolation transformer.

[0027] The first ground reference may be connected to the control system ground associated with the primary side of the isolated DC-DC converter, and the second ground reference may be electrically isolated from the first ground reference via at least one of the first and second isolation transformers and via the main isolation transformer of the DC-DC converter, wherein the ground reference of the isolation transformer and the connection configuration of the isolation transformer may be adjusted based on a desired grounding arrangement connected to the secondary side of the isolated DC-DC converter and connected to the control system ground associated with the drive logic unit. Attached Figure Description

[0028] Figure 1 This is a schematic diagram of an isolated CLLC DC-DC converter according to one embodiment.

[0029] Figure 2 It is used for control Figure 1 A schematic diagram of the drive circuit device for the converter.

[0030] Figure 3 A to Figure 3 F is a graph showing the converter operation when the switching frequency is greater than the resonant frequency.

[0031] Figure 4 A to Figure 4 F is a graph showing the converter operation when the switching frequency is less than the resonant frequency.

[0032] Figure 5 This is a schematic diagram of an alternative embodiment of an isolated CLLC DC-DC converter with reverse grounding connection.

[0033] Figure 6 It is used for control Figure 5 A schematic diagram of the drive circuit device for the converter.

[0034] Figure 7 This is a schematic diagram of a threshold generation circuit device used to generate various threshold voltages for use by the drive logic.

[0035] Figures 8A to 8B This is a schematic diagram of the first embodiment of the driving logic unit.

[0036] Figure 9 This is a schematic diagram of a second embodiment of the driving logic unit. Detailed Implementation

[0037] The following disclosure enables those skilled in the art to make and use the subject matter described herein. The general principles outlined in this disclosure can be applied to embodiments and applications other than those detailed above, without departing from the spirit and scope of this disclosure. This disclosure is not intended to be limited to the embodiments shown, but is to be given the widest scope consistent with the principles and features disclosed or suggested herein.

[0038] For reference Figure 1 An isolated CLLC DC-DC converter 10 is described.

[0039] On the primary side: the drain of n-channel transistor T1 is connected to VBUS, its source is connected to node N1, and its gate is coupled to receive the gate drive signal S1; the drain of n-channel transistor T2 is connected to node N1, its source is connected to GND_ctl, and its gate is coupled to receive the gate drive signal S2; the drain of n-channel transistor T3 is connected to VBUS, its source is connected to node N2, and its gate is coupled to receive the gate drive signal S3; the drain of n-channel transistor T4 is connected to node N2, its source is connected to GND_ctl, and its gate is coupled to receive the gate drive signal S4. A resonant capacitor CR1, representing the primary-side resonant capacitance, and a resonant inductor LR1, representing the primary-side resonant inductance, are connected in series between node N1 and the first terminal of the primary-side transformer LP, where the second terminal of the primary-side transformer is connected to node N2. A magnetizing inductor LM1, representing the primary magnetizing inductance of the transformer, is connected in parallel with the primary-side transformer LP.

[0040] On the secondary side: the drain of n-channel transistor T5 is connected to the battery voltage VBATT (the battery voltage source, whose positive terminal is connected to the drains of T5 and T7, and whose negative terminal is connected to GND_iso), its source is connected to node N4, and its gate is coupled to receive the gate drive signal S5; the drain of n-channel transistor T6 is connected to node N4, its source is connected to GND_iso, and its gate is coupled to receive the gate drive signal S6; the drain of n-channel transistor T7 is connected to the battery voltage VBATT, its source is connected to N3, and its gate is coupled to receive the gate drive signal S7; and the drain of n-channel transistor T8 is connected to node N3, its source is connected to GND_iso, and its gate is coupled to receive the gate drive signal S8. A resonant inductor LR2, representing the secondary-side resonant inductance, and a resonant capacitor CR2, representing the secondary-side resonant capacitance, are connected in series between the first terminal of the secondary-side transformer LS and node N3, wherein the second terminal of the secondary-side transformer is connected to node N4.

[0041] For reference Figure 2Describes a drive circuit arrangement 20 for controlling converter 10. The drive circuit arrangement 20 includes: a diode DA, the cathode of which is coupled to receive voltage VA from node N1, and the anode of which is connected to node ND1; a diode DB, the cathode of which is coupled to receive voltage VB from node N2, and the anode of which is connected to node ND1; a resistor Rr1 coupled between VDD and node ND1; a capacitor CP1 connected between node ND1 and GND_ctrl; and a primary side LP1 of a transformer connected between node ND1 and GND_CTRL. The drive circuit arrangement 20 also includes: a secondary side LS1 of the transformer connected between the non-inverting input of comparator 22 and GND_ctrl, the inverting input of comparator 22 being connected to receive voltage Vth_1 from drive logic unit 21, and the output of comparator 22 being connected to provide CMP1_OUT to the input of drive logic unit 21.

[0042] The drive circuit assembly 20 further includes: a diode DC, the cathode of which is coupled to receive voltage VC from node N3, and the anode of which is connected to node ND2; a diode DD, the cathode of which is coupled to receive voltage VD from node N4, and the anode of which is connected to node ND2; a resistor R2 coupled between VDD and node ND2; a capacitor CP2 connected between node ND2 and GND_iso; and the primary side LP2 of a transformer connected between node ND2 and GND_iso. Each diode DA, DB, DC, and DD can be a single diode or multiple diodes connected in series.

[0043] The drive circuit device 20 further includes: a secondary side LS2 of a transformer, which is connected between the non-inverting input of comparator 23 and GND_ctl, the inverting input of comparator 23 is connected to receive voltage Vth_2 from drive logic unit 21, and the output of comparator 23 is connected to provide CMP2_OUT to the input of drive logic unit 21.

[0044] The driving circuit device 20 uses various threshold voltage signals to determine the switching time of the transistors. The comparator threshold voltages Vth_1 and Vth_2 are reference voltages provided by the driving logic unit 21 to comparators 22 and 23, respectively. These threshold voltages are set to approximately 0.7V, equal to... Figure 2The forward voltage VF of diodes DA, DB, DC, and DD is used to detect the ZCD point in the resonant current waveform. These threshold voltages VF can be varied depending on the application and hardware specifics. It should also be noted that if diodes DA, DB, DC, and DD are multiple diodes connected in series, the threshold voltage VF will be multiplied by the number of diodes connected in series.

[0045] The gate drive threshold voltages include turn-on thresholds Vth_ON_1,4, Vth_ON_2,3, Vth_ON_5,8, and Vth_ON_6,7. When these thresholds are exceeded, they indicate the appropriate conditions for turning on the corresponding transistor pairs T1 / T4, T2 / T3, T5 / T8, and T6 / T7 while achieving ZVS. Turn-off thresholds Vth_OFF_1,4, Vth_OFF_2,3, Vth_OFF_5,8, and Vth_OFF_6,7 indicate the appropriate conditions for turning off the corresponding transistor pairs while achieving ZCS. Furthermore, the blocking threshold voltages Vth_OFF_BLK_5,8 and Vth_OFF_BLK_6,7 prevent premature transistor turn-off under certain operating conditions, particularly when the switching frequency differs from the resonant frequency.

[0046] Control unit 24 provides signals Synch_EN, TSW, and Mode_SEL to drive logic unit 21. The Synch_EN signal is a logic enable signal for synchronous drive, which can be disabled under light load conditions to improve efficiency. The TSW signal represents the switching cycle value, which can be provided digitally (e.g., from a microcontroller) or as an analog signal (e.g., from an integrated circuit). The Mode_SEL signal is a logic selector used to determine whether the converter is operating in charging or discharging mode, thereby effectively controlling the switching of primary drive and SR drive functions between the two sides of the converter. Drive logic unit 21 generates gate drive signals S1 to S8 based on these control signals and the comparator output.

[0047] Now for reference Figure 1 , Figure 2 and Figure 3 A to Figure 3 F describes the operation of the isolated CLLC DC-DC converter 10 and its drive circuitry 20. For example... Figure 2 As shown, converter 10 operates in two different modes: charging mode and discharging mode. In charging mode, transistors T1 to T4 on the primary side operate as the primary drive stage with a duty cycle of 50%, while transistors T5 to T8 on the secondary side act as the synchronous rectification (SR) stage. Conversely, in discharging mode, the roles are reversed, with T5 to T8 acting as the primary drive stage and T1 to T4 acting as the SR stage.

[0048] The driving logic for these two stages is different. The primary drive signal is based on a time delay, where complementary transistors operate with dead time on T1 / T2, T3 / T4, T5 / T6, and T7 / T8 to prevent shoot-through. However, the SR drive relies on both a time delay and comparator flip-flops CMP1_OUT or CMP2_OUT to implement ZVS and ZCS.

[0049] For SR drives, the turn-on condition occurs when a predetermined delay time has elapsed and the corresponding comparator output is low (indicating a zero-voltage state suitable for turn-on). The turn-off condition occurs when a predetermined delay time Tdelay_OFF has elapsed or the comparator output experiences RISING_EDGE (indicating a zero-current condition suitable for turn-off).

[0050] The drive circuit device 20 implements a voltage sensing method to detect these switching conditions. On the primary side, diodes DA and DB rectify the switching node voltages VA and VB to generate a voltage signal Vds_AB at node ND1. Similarly, on the secondary side, diodes DC and DD rectify voltages VC and VD to generate a voltage signal Vds_CD at node ND2. These voltage signals are isolated by transformers LP1 / LS1 and LP2 / LS2, and comparators 22 and 23 compare these voltage signals with threshold voltages Vth_1 and Vth_2.

[0051] The isolated CLLC DC-DC converter 10 adapts its control strategy based on the relationship between the switching frequency (fsw) and the resonant frequency (fres) to maintain optimal switching conditions. Two turn-off mechanisms are always enabled, but the "winning" turn-off mechanism naturally depends on the switching frequency relationship determined by the operation of the resonant converter. When fsw exceeds fres, the secondary resonant current Ires2 does not reach zero within its half-switching cycle, thus requiring the synchronous rectifier (SR) transistors T5 to T8 to be turned off based on predetermined time delay signals Tdelay_OFF_6,7 and Tdelay_OFF_5,8. Conversely, when fsw is less than fres, the secondary resonant current Ires2 drops to zero within its half-switching cycle, allowing the system to turn off SR transistors T5 to T8 at the zero-current-sense (ZCD) point in response to the comparator output signal CMP2_OUT. This adaptive control mechanism provides ZCS where possible, thereby reducing switching losses and improving efficiency under various operating conditions. Dual-mode operation allows converter 10 to maintain robust performance regardless of input / output voltage conditions, load changes, or the selected operating frequency determined by the TSW signal from control unit 24.

[0052] More in detail, Figure 3 A to Figure 3F illustrates the operation of the converter when the switching frequency fsw is greater than the resonant frequency fres. Figure 3 A shows the voltages VC, VD, Vds_CD, and Vth_2. Figure 3 B shows the resonant currents Ires1 and Ires2. Figure 3 C to Figure 3 F shows the gate drive signals S1 to S8, various timing delays, threshold voltages, and comparator output CMP2_OUT.

[0053] The drive logic for the primary and secondary sides is fundamentally different. For the primary side (T1 to T4 or T5 to T8, depending on the mode), both turn-on and turn-off operations are based solely on time delay. For the secondary side (T5 to T8 or T1 to T4, depending on the mode), the logic is more complex: turn-on occurs when the delay time has elapsed and CMP2_OUT is low; while turn-off occurs when the delay time has elapsed or comparator 23 detects a rising edge. This OR logic for turn-off provides appropriate switching under various operating conditions. The threshold voltage Vth_2 is set equal to VF (the forward voltage of the diode), which should be approximately 0.7V or higher to provide robust turn-off triggering for the zero-current switch (ZCS).

[0054] observe Figure 3 A to Figure 3 The timing relationships in F implement several delays to provide an appropriate switching sequence. Tdelay_ON_2,3 represents the delay between the turn-off of transistors T1 and T4 (the start of switching cycle Tsw) and the turn-on of transistors T2 and T3. Similarly, Tdelay_ON_1,4 represents the delay between the turn-off of T1 and T4 and the turn-on of T1 and T4. On the secondary side, Tdelay_ON_6,7 represents the delay between the turn-off of primary-side transistors T1 and T4 and the turn-on of secondary-side transistors T6 and T7. Likewise, Tdelay_ON_5,8 represents the delay between the turn-off of primary-side transistors T1 and T4 and the turn-on of secondary-side transistors T5 and T8. All these turn-on delays are timed to provide the ZVS turn-on condition.

[0055] These inter-switch delays provide appropriate operation. For example, the delay (Tdelay_ON_6,7) between turning off the primary-side transistors T1 and T4 and turning on the secondary-side transistors T6 and T7 (especially when Tdelay_ON_6,7 has a larger value than Tdelay_ON_2,3) allows the body diodes of T6 and T7 to begin conducting, thus creating conditions for zero-voltage switching (ZVS) when the MOSFETs finally turn on.

[0056] Under these operating conditions (fsw>fres), the secondary resonant current will not reach zero within its half-switching cycle. Therefore, the safe turn-off trigger of the SR transistor is provided by the turn-off time delay signals Tdelay_OFF_6,7 and Tdelay_OFF_5,8 of the secondary-side SR. For the reverse / discharge mode, the correct converter control behavior is obtained by swapping the roles of the switches and comparators and their corresponding drive signals: T1 is swapped with T5, T2 with T6, etc., and CMP2 is swapped with CMP1, VC, VD with VA, VB, etc., as shown below. Figure 8A and Figure 8B As shown in the figure, the turn-off delay signals are timed to provide an appropriate switching sequence, where Tdelay_OFF_2,3 is equal to half the switching period Tsw / 2, and Tdelay_OFF_1,4 is equal to the full switching period Tsw. Furthermore, blocking delays Tdelay_OFF_BLK_6,7 and Tdelay_OFF_BLK_5,8 prevent the secondary-side transistors from turning off prematurely under certain operating conditions.

[0057] Secondary-side MOSFETs T5 through T8 must be turned off before their corresponding primary-side MOSFETs T1 through T4 change state to prevent reverse current flow. This timing is maintained by carefully coordinating these delayed signals. The same coordination is used between T6 and T7 and their corresponding MOSFETs T2 and T3.

[0058] The comparator threshold Vth_2, which is equal to Vds_CD at the zero-cross detection (ZCD) point, is set to approximately 0.7V to provide turn-off triggering for ZCS and also to prevent reverse flow of the secondary resonant current within the same half-switching cycle.

[0059] The drive logic unit 21 processes these signals to generate appropriate gate drive signals S1 to S8, adapting to varying input / output conditions and operating modes. The Mode_SEL signal from the control unit 24 determines whether the converter operates in charging mode (bus to battery) or discharging mode (battery to bus), effectively switching the roles of primary drive and SR drive between the two sides of the converter. The TSW signal sets the basic switching frequency, while the Synch_EN signal enables or disables synchronous rectification, typically disabling it during light-load conditions to improve efficiency.

[0060] Figure 4 A to Figure 4 F illustrates the operation of the converter when the switching frequency fsw is less than the resonant frequency fres. Figure 4 A shows the voltages VC, VD, Vds_CD, and Vth_2. Figure 4 B shows the resonant currents Ires1 and Ires2, with the zero-current detection (ZCD) point clearly marked. Figure 4 C to Figure 4 F illustrate the gate drive signals S1-S8, various timing delays, threshold voltages, and comparator output CMP2_OUT.

[0061] Under this operating condition (fsw<fres), the secondary resonant current drops to zero within its half switching period, as indicated by the ZCD point. Although the drive logic is identical to that described in Figure 3 A to Figure 3 F, its behavior is different. For the secondary drive, the turn-on condition still follows a logical AND operation that the time delay has elapsed and CMP2_OUT is low, but the turn-off operation follows a logical OR condition that the time delay has elapsed or comparator 23 detects a rising edge. This is because the CMP2_OUT signal experiences a rising edge at the ZCD point before the time delay signal is triggered. Therefore, the safe turn-off trigger for the SR transistor is provided by the comparator signal CMP2_OUT instead of the time delay signal. The comparator output experiences a rising edge at the ZCD point, thus providing an optimal turn-off trigger for ZCS. As shown in Figure 4 A to Figure 4 F, the turn-off delay signals Tdelay_OFF_6,7 and Tdelay_OFF_5,8 for the secondary-side SR still exist, but the actual turn-off is triggered by the CMP2_OUT signal. The timing of the turn-on delays Tdelay_ON_2,3, Tdelay_ON_1,4, Tdelay_ON_6,7 and Tdelay_ON_5,8 is designed to provide ZVS turn-on conditions, similar to the case where fsw>fres.

[0062] The threshold voltage Vth_2, which is set equal to VF (approximately 0.7V), provides a robust turn-off trigger at the ZCD point, thereby enabling proper ZCS operation. This demonstrates how the drive logic adapts to the relationship between the switching frequency and the resonant frequency to maintain proper operation under various operating conditions.

[0063] Figures 5 to 6 respectively show alternative embodiments of the isolated CLLC DC-DC converter 10' and its drive circuit arrangement 20'. This embodiment differs from the embodiment shown in Figures 1 to 2 in the reversal of the ground connection. In Figures 5 to 6 , GND_iso is connected to the primary side (bus side) of converter 10', while GND_ctrl is connected to the secondary side (battery side). This is in contrast to Figures 1 to 2In this configuration, GND_ctrl is located on the bus side, while GND_iso is located on the battery side, creating a contrast. This grounding arrangement has implications for system integration. GND_ctrl represents the control system ground, which is connected to the drive logic unit 21 and control unit 24 that generate gate drive signals and control functions. GND_iso represents an isolated ground reference, which is electrically isolated from GND_ctrl via an isolation barrier formed by a transformer. Figures 1 to 2 The configuration in this case may be preferred in systems where the drive circuitry shares a ground with the bus, and Figures 5 to 6 The configuration in this configuration can be advantageous in applications where it is desirable to isolate the drive circuitry from the bus.

[0064] It should be noted that the grounding connection configuration of the detection circuit provides additional flexibility in system design. Figures 1 to 2 In this configuration, the ground pin of the first sensing transformer (LP1) is connected together to GND_ctrl, effectively "short-circuiting" GND_ctrl and negating its isolation function, while the ground pin of the second sensing transformer (LP2) is used to separate GND_iso from GND_ctrl. Conversely, in Figures 5 to 6 In this configuration, the ground pin of the second sensing transformer (LP2) is "short-circuited," while the ground pin of the first transformer (LP1) is used to separate GND_iso from GND_ctrl. This adaptive approach allows the sensing circuitry to be integrated with external pins for grounding connections, which can be configured according to the required grounding arrangement, thus providing flexibility to adapt to various system integration requirements without redesigning the sensing circuitry.

[0065] Now for reference Figure 7A threshold generation circuit arrangement 30 (integrated into the drive logic unit 21, or a separate circuit connected to the drive logic unit 21) is described for generating Vth_1, Vth_2, Vth_OFF_5,8, Vth_OFF_BLK_5,8, Vth_ON_5,8, Vth_ON_1,4, Vth_OFF_2,3, Vth_OFF_6,7, Vth_OFF_BLK_6,7, Vth_ON_6,7, and Vth_ON_2,3. The threshold generation circuit arrangement 30 includes: an amplifier 31, the non-inverting input of which is connected to a tap between resistors R1 and R2 connected in series between VDD and ground, wherein Vth_1 is generated at the output of amplifier 31; and an amplifier 32, the non-inverting input of which is connected to a tap between resistors R3 and R4 connected in series between VDD and ground, wherein Vth_2 is generated at the output of amplifier 32. It also includes resistors R5 through R14 connected in series between VDD and ground. The non-inverting input of amplifier 33 is connected to a tap between resistors R5 and R6, generating Vth_OFF_5,8 at its output. The non-inverting input of amplifier 34 is connected to a tap between resistors R6 and R7, generating Vth_OFF_BLK_5,8 at its output. The non-inverting input of amplifier 35 is connected to a tap between resistors R7 and R8, generating Vth_ON_5,8 at its output. The non-inverting input of amplifier 36 is connected to a tap between resistors R8 and R9, generating Vth_ON_1,4 at its output. The non-inverting input of amplifier 37 is connected to a tap between resistors R9 and R10, generating Vth_OFF_2,3 at its output. Amplifier 38's non-inverting input is connected to the tap between resistors R10 and R11, generating Vth_OFF_6,7 at its output. Amplifier 39's non-inverting input is connected to the tap between resistors R11 and R12, generating Vth_OFF_BLK_6,7 at its output. Amplifier 40's non-inverting input is connected to the tap between resistors R12 and R13, generating Vth_ON_6,7 at its output. Amplifier 41's non-inverting input is connected to the tap between resistors R13 and R14, generating Vth_ON_2,3 at its output.

[0066] For reference Figures 8A to 8BSpecific details of a first embodiment of the drive logic unit 21 are described below. As shown, the drive logic unit 21 includes a DAC 51 that receives CLK_Fsw as input. The output of the DAC 51 is fed to a VCO 52, and the output of the VCO 52 is Fclk (proportional to the switching frequency fsw). Fclk is passed to a sawtooth wave generator 53 to generate SAWTOOTH_Fsw. The SAWTOOTH_Fsw waveform ranges from 0V to VDD, thus providing a full-scale reference against which various threshold voltages are compared, such as... Figures 3 to 4 As shown.

[0067] It should be noted that, as an alternative, DAC 51 may be absent, and VCO 52 may receive the appropriate analog input signal used to set Tsw.

[0068] Comparator 54 has a non-inverting input connected to receive SAWTOOTH_Fsw, and its inverting input connected to receive Vth_ON_1,4. Its output is provided to the set input of SR flip-flop 55. SAWTOOTH_Fsw is provided to the reset input of SR flip-flop 55, and the output of SR flip-flop 55 provides S1_drv and S4_drv. Comparator 56 has a non-inverting input connected to receive SAWTOOTH_Fsw, and its inverting input connected to receive Vth_ON_2,3. Its output is provided to the set input of SR flip-flop 57. Comparator 58 has a non-inverting input connected to receive SAWTOOTH_Fsw, and its inverting input connected to receive Vth_OFF_2,3. Its output is provided to the reset input of SR flip-flop 57. The output of SR flip-flop 57 provides S3_drv and S2_drv.

[0069] Switch SW1 selectively provides CMP1_OUT to the inputs of NOT gates 61 and 69, and OR gates 65 and 73. Switch SW2 selectively provides CMP2_OUT to the inputs of NOT gates 61 and 69, and OR gates 65 and 73. Switches SW1 and SW2 are controlled by the mode selection signal MODE_SEL and operate in opposite phases.

[0070] The non-inverting input of comparator 59 is connected to receive SAWOTH_Fsw, and its inverting input is connected to receive Vth_ON_5,8. The input of AND gate 60 is connected to the output of comparator 59 and to the output of inverter 61. The output of AND gate 60 is connected to the set input of SR flip-flop 62.

[0071] The non-inverting input of comparator 63 is connected to receive SAWTOOTH_Fsw, and its inverting input is connected to receive Vth_OFF_5,8. The input of OR gate 65 is connected to the output of comparator 63 and to switches SW1 and SW2.

[0072] The non-inverting input of comparator 66 is connected to receive SAWTOOTH_Fsw, and its inverting input is connected to receive Vth_OFF_BLK_5,8. The output of comparator 66 is connected to one input of AND gate 64, and the output of OR gate 65 is connected to the other input of AND gate 64. The output of AND gate 64 is connected to the reset input of SR flip-flop 62.

[0073] The non-inverting input of comparator 67 is connected to receive SAWTOOTH_Fsw, and its inverting input is connected to receive Vth_ON_6,7. The output of comparator 67 is connected to one input of AND gate 68, and the other input of AND gate 68 is connected to the output of inverter 69.

[0074] The non-inverting input of comparator 71 is connected to receive SAWTOOTH_Fsw, and its inverting input is connected to receive Vth_OFF_6,7. The output of comparator 71 is connected to one input of OR gate 73, and the other input of OR gate 73 is connected to switches SW1 and SW2.

[0075] The non-inverting input of comparator 74 is connected to receive SAWOTH_Fsw, and its inverting input is connected to receive Vth_OFF_BLK_6,7. The output of OR gate 73 is connected to one input of AND gate 72, and the output of comparator 74 is connected to the other input of AND gate 72. The output of AND gate 68 is connected to the set input of SR flip-flop 70, and the output of AND gate 72 is connected to the reset input of SR flip-flop 70.

[0076] The input of AND gate 76 is connected to the output of SR flip-flop 62 and to the SYNCH_EN signal. Signals S5_drv and S8_drv are provided at the output of AND gate 76. The input of AND gate 75 is connected to the output of SR flip-flop 70 and to the SYNCH_EN signal. Signals S6_drv and S7_drv are provided at the output of AND gate 75.

[0077] The drive logic unit 21 generates gate drive signals S1 to S8. A sawtooth waveform SAWTOOTH_Fsw, generated by the chain of DAC 51, VCO 52, and sawtooth waveform generator 53, provides a timing reference. This sawtooth waveform is compared with various threshold voltages.

[0078] For the primary drive side, complementary drive signal pairs S1_drv / S4_drv and S2_drv / S3_drv are generated via SR flip-flops 55 and 57. These flip-flops 55 and 57 are triggered by comparing the sawtooth waveform SAWTOOTH_Fsw with threshold voltages Vth_ON_1,4, Vth_ON_2,3, and Vth_OFF_2,3 using comparators 54, 56, and 58. This provides appropriate timing and a suitable dead time interval to prevent shoot-through conditions.

[0079] For the synchronous rectification (SR) side, the control scheme uses SR flip-flops 62 and 70, which generate S5_drv / S8_drv and S6_drv / S7_drv signal pairs. The set and reset conditions of these flip-flops combine time-based triggering (by comparing SAWTOOTH_Fsw with threshold voltages Vth_ON_5,8, Vth_OFF_5,8, Vth_ON_6,7, and Vth_OFF_6,7) and current / voltage feedback signals (CMP1_OUT and CMP2_OUT). Additional blocking thresholds Vth_OFF_BLK_5,8 and Vth_OFF_BLK_6,7 prevent premature switching. The MODE_SEL signal controls switches SW1 and SW2, which select the appropriate signal CMP1_OUT or CMP2_OUT based on whether the converter is operating in discharge or charge mode, effectively swapping the primary and SR functions between the two sides of the converter. For example, during light load conditions, the SYNCH_EN signal can be disabled via AND gates 75 and 76 to improve efficiency.

[0080] Under the control of the mode selection signal MODE_SEL, switches SW1A and SW1B selectively provide either S1_drv or S5_drv as the gate drive signal S1. Switches SW2A and SW2B selectively provide either S2_drv or S6_drv as the gate drive signal S2. Switches SW3A and SW3B selectively provide either S3_drv or S7_drv as the gate drive signal S3. Switches SW4A and SW4B selectively provide either S4_drv or S8_drv as the gate drive signal S4. Switches SW5A and SW5B selectively provide either S5_drv or S1_drv as the gate drive signal S5. Switches SW6A and SW6B, under the control of the mode selection signal MODE_SEL, selectively provide either S6_drv or S2_drv as the gate drive signal S6. Switches SW7A and SW7B, under the control of the mode selection signal MODE_SEL, selectively provide either S7_drv or S3_drv as the gate drive signal S7. Switches SW8A and SW8B, under the control of the mode selection signal MODE_SEL, selectively provide either S8_drv or S4_drv as the gate drive signal S8.

[0081] When MODE_SEL selects the charging mode, drive signals S1_drv to S4_drv are routed to gate drive signals S1 to S4 (primary side), while S5_drv to S8_drv are routed to gate drive signals S5 to S8 (secondary side). Conversely, when MODE_SEL selects the discharging mode, the routing is reversed: S5_drv to S8_drv control the primary-side transistors, while S1_drv to S4_drv control the secondary-side transistors. This switchable routing architecture enables bidirectional power flow without requiring redesigning the control logic for each direction.

[0082] refer to Figure 9Specific details of a second embodiment of the drive logic unit 21' are described below. As shown, the drive logic unit 21' includes a DAC 81 that receives CLK_Fsw as input. The output of DAC 81 is fed to VCO 82, and the output of VCO 82 generates Fclk (proportional to the switching frequency fsw), which is passed to delay generator 83. Note that, alternatively, DAC 81 may be absent, and VCO 82 may receive an appropriate analog input signal for setting Tsw. Of particular note is that delay generator 83 generates signals Tdelay_OFF_5,8, Tdelay_OFF_BLK_5,8, Tdelay_ON_5,8, Tdelay_ON_1,4, Tdelay_OFF_2,3, Tdelay_OFF_6,7, Tdelay_OFF_BLK_6,7, Tdelay_ON_6,7, and Tdelay_ON_2,3.

[0083] Tdelay_ON_1,4 is provided to the set input of SR flip-flop 84, and CLK_Fsw is provided to the reset input of SR flip-flop 84. The output of SR flip-flop 84 generates S1_drv and S4_drv. Tdelay_ON_2,3 is provided to the set input of SR flip-flop 85, and Tdelay_OFF_2,3 is provided to the reset input of SR flip-flop 85. The output of SR flip-flop 85 generates S2_drv and S3_drv.

[0084] Switches SW1 and SW2 selectively provide CMP1_OUT and CMP2_OUT to the inputs of inverters 86 and 92, and also to the inputs of OR gates 89 and 94. OR gate 89 also receives Tdelay_OFF_5,8 as input, and OR gate 94 also receives Tdelay_OFF_6,7 as input. AND gate 87 has an input connected to receive the output of inverter 86 and Tdelay_ON_5,8. AND gate 90 has an input connected to receive the output of OR gate 89 and Tdelay_off_blk_5,8. The set input of SR flip-flop 88 is connected to receive the output of AND gate 87, and its reset input is connected to receive the output of AND gate 90. AND gate 93 receives the output of inverter 92 and Tdelay_ON_6,7 as input. AND gate 95 receives the output of OR gate 94 and Tdelay_OFF_BLK_6,7 as input. The set input of SR flip-flop 96 is connected to receive the output of AND gate 93, and its reset input is connected to receive the output of AND gate 95. The input of AND gate 91 is connected to receive the output of SR flip-flop 88 and SYNCH_EN, and provides S5_drv and S8_drv at its output. The input of AND gate 97 is connected to receive the output of SR flip-flop 96 and SYNCH_EN, and provides S6_drv and S7_drv at its output.

[0085] Here, with Figure 8B Similarly, when MODE_SEL selects the charging mode, drive signals S1_drv to S4_drv are routed to gate drive signals S1 to S4 (primary side), while S5_drv to S8_drv are routed to gate drive signals S5 to S8 (secondary side). Conversely, when MODE_SEL selects the discharging mode, the routing is reversed: S5_drv to S8_drv control the primary-side transistors, while S1_drv to S4_drv control the secondary-side transistors. This switchable routing architecture enables bidirectional power flow without requiring redesigning the control logic for each direction.

[0086] The isolated CLLC DC-DC converter and drive circuitry described herein offer several advantages. An adaptive control strategy, adjusted based on the relationship between the switching frequency and the resonant frequency, ensures efficient switching conditions across a wide range of operating scenarios. By implementing ZVS turn-on and ZCS turn-off where possible, the converter achieves high efficiency while minimizing switching losses. The bidirectional capability enabled by the mode selection function allows the same hardware to operate in both charging and discharging modes without the need for additional components. Selectively enabled synchronous rectification improves efficiency during light load conditions. Furthermore, flexible grounding configuration options provide system designers with specific implementation choices tailored to particular isolation and noise immunity requirements.

[0087] Furthermore, this drive circuitry has the capability to generate all eight gate drive signals (S1-S8) from a single input PWM signal (CLK_Fsw). This architecture significantly reduces the number of control signals required from a microcontroller or other control source, enabling a single controller to efficiently manage multiple converters simultaneously. In large-scale applications such as server power supplies or data centers, the reduction from eight PWM signals per converter to a single PWM signal achieves significant scaling, allowing a single microcontroller to drive twelve or more converters with minimal control overhead.

[0088] This converter is particularly suitable for power applications in data centers and servers, where high efficiency and power density are desirable. In such applications, the ability to manage multiple converters in parallel is becoming increasingly important to meet the growing power demands of modern computing infrastructure. The aforementioned driver logic implementation reduces the number of resources required to drive multiple bridge circuits while maintaining optimal switching conditions, making it effective for high-power server applications where a single control unit must manage multiple power conversion stages.

[0089] Finally, it will be apparent that modifications and variations can be made to the content described and shown herein without departing from the scope of this disclosure. For example, in alternative embodiments, the drive circuitry utilizes GaN transistors instead of conventional silicon-based transistors, thereby providing higher efficiency and faster switching speeds. The control logic can be implemented using a digital signal processor (DSP) or a field-programmable gate array (FPGA) to provide more precise control and adaptability.

[0090] Although this disclosure has been described in conjunction with a limited number of embodiments, those skilled in the art, upon benefiting from this disclosure, will envision other embodiments without departing from the scope of the disclosure. Furthermore, those skilled in the art will envision various combinations of embodiments that combine the embodiments disclosed herein in various ways.

Claims

1. An isolated DC-DC converter, comprising: The primary-side circuitry includes a first full-bridge arrangement of transistors; The secondary-side circuitry includes a second full-bridge arrangement of transistors; A transformer couples the primary circuit to the secondary circuit; and The drive circuit device is configured as follows: Monitor the switching node voltages on both the primary side circuit and the secondary side circuit; The transistor can be selectively operated in either a charging mode or a discharging mode, wherein in the charging mode, the first full-bridge arrangement of the transistor is used as a primary driving transistor and the second full-bridge arrangement of the transistor is used as a synchronous rectifier transistor; and in the discharging mode, the second full-bridge arrangement of the transistor is used as a primary driving transistor and the first full-bridge arrangement of the transistor is used as a synchronous rectifier transistor. Detect the zero-current crossing point in the resonant current waveform; as well as The turn-off timing of the transistor used as a synchronous rectifier transistor is adaptively controlled based on the relationship between the switching frequency and the resonant frequency of the converter, wherein the driving circuit device turns off the transistor used as a synchronous rectifier transistor based on a time delay signal when the switching frequency exceeds the resonant frequency, and turns off the transistor used as a synchronous rectifier transistor based on a comparator signal at the zero current crossing point when the switching frequency is below the resonant frequency.

2. The isolated DC-DC converter according to claim 1, wherein the drive circuit device comprises: A first voltage sensing circuit is configured to monitor the switching node voltage of the primary-side circuit; and The second voltage sensing circuit is configured to monitor the switching node voltage of the secondary side circuit.

3. The isolated DC-DC converter according to claim 2, wherein: The first voltage sensing circuit includes a first pair of diodes coupled to a switching node of the primary side circuit; and the second voltage sensing circuit includes a second pair of diodes coupled to a switching node of the secondary side circuit.

4. The isolated DC-DC converter according to claim 2, wherein the drive circuit device further comprises: A first comparator is configured to compare a rectified voltage from the first voltage sensing circuit with a first threshold voltage. The second comparator is configured to compare the rectified voltage from the second voltage sensing circuit with a second threshold voltage.

5. The isolated DC-DC converter according to claim 1, wherein the drive circuit device further comprises a drive logic unit, the drive logic unit being configured to: Generate a sawtooth waveform synchronized with the switching frequency; and The sawtooth waveform is compared with multiple threshold voltages to generate timing signals for controlling a first full-bridge arrangement and a second full-bridge arrangement of the transistors.

6. The isolated DC-DC converter of claim 5, further comprising a threshold generation circuit configured to generate a plurality of threshold voltages, the plurality of threshold voltages comprising: Turn-on threshold voltage, which indicates the appropriate conditions for turning on the transistors of the first full-bridge arrangement and the second full-bridge arrangement while achieving zero-voltage switching; as well as A turn-off threshold voltage, which indicates the appropriate conditions for turning off the transistors of the first full-bridge arrangement and the second full-bridge arrangement while achieving zero-current switching.

7. The isolated DC-DC converter of claim 6, wherein the threshold generation circuitry further generates a blocking threshold voltage configured to prevent premature turn-off of transistors in the first full-bridge arrangement and the second full-bridge arrangement, which are used as synchronous rectifier transistors.

8. The isolated DC-DC converter of claim 1, wherein the drive circuitry is configured to enable and disable synchronous rectification under light load conditions.

9. The isolated DC-DC converter of claim 1, wherein the primary-side circuit is coupled to a bus voltage source and the secondary-side circuit is coupled to a battery voltage source.

10. The isolated DC-DC converter according to claim 1, wherein: In the charging mode, power flows from the primary side circuit to the secondary side circuit; and In the discharge mode, power flows from the secondary side circuit to the primary side circuit.

11. The isolated DC-DC converter according to claim 1, wherein the drive circuit device comprises: The mode selection input is configured to select between the charging mode and the discharging mode; and A switching circuit device is configured to route appropriate drive signals to a first full-bridge arrangement and a second full-bridge arrangement of the transistors based on a selected mode, wherein the drive signals implement adaptive control of the turn-off timing based on the relationship between the switching frequency and the resonant frequency, such that the switching circuit device routes a time-delay signal or a comparator signal for turn-off control of either full-bridge arrangement used as a synchronous rectifier transistor in the selected mode, and wherein the comparator signal is also used to enable safe turn-on of the synchronous rectifier transistor when an appropriate zero-voltage switching condition is indicated.

12. A drive circuit arrangement for an isolated DC-DC converter, the isolated DC-DC converter having a primary side and a secondary side, each of the primary side and the secondary side having a full-bridge transistor arrangement, the drive circuit arrangement comprising: The first voltage sensing circuit includes: A first diode, the cathode of which is coupled to a first switching node on the primary side; A second diode, the cathode of which is coupled to a second switching node on the primary side; The anodes of the first diode and the second diode are connected to the first common node; A first resistor is coupled between the power supply voltage and the first common node; A first capacitor is connected between the first common node and the first ground reference; and A first isolation transformer, wherein the primary side of the first isolation transformer is connected between the first common node and the first ground reference; The second voltage sensing circuit includes: A third diode, the cathode of which is coupled to the first switching node on the secondary side; A fourth diode, the cathode of which is coupled to a second switching node on the secondary side; The anodes of the third diode and the fourth diode are connected to the second common node; A second resistor is coupled between the power supply voltage and the second common node; A second capacitor is connected between the second common node and the second ground reference; and The second isolation transformer has its primary side connected between the second common node and the second ground reference. A first comparator, wherein the non-inverting input of the first comparator is coupled to the secondary side of the first isolation transformer, the inverting input of the first comparator is connected to receive a first threshold voltage, and the output of the first comparator is configured to provide a first comparator output signal; A second comparator, wherein the non-inverting input of the second comparator is coupled to the secondary side of the second isolation transformer, the inverting input of the second comparator is connected to receive a second threshold voltage, and the output of the second comparator is configured to provide a second comparator output signal; and The drive logic unit is configured to generate a gate drive signal for the full-bridge transistor arrangement based on the first comparator output signal and the second comparator output signal.

13. The driving circuit device according to claim 12, wherein the driving logic unit comprises: Clock signal input; A voltage-controlled oscillator (VCO) is coupled to the clock signal input via an optional digital-to-analog converter (DAC). A sawtooth wave generator is coupled to the output of the VCO; A first comparator, wherein the non-inverting input of the first comparator is coupled to receive a sawtooth waveform from the sawtooth wave generator, and the inverting input of the first comparator is coupled to receive a first turn-on threshold voltage; A second comparator, wherein the non-inverting input of the second comparator is coupled to receive a sawtooth waveform, and the inverting input of the second comparator is coupled to receive a first turn-off threshold voltage; A third comparator, wherein the non-inverting input of the third comparator is coupled to receive a sawtooth waveform, and the inverting input of the third comparator is coupled to receive a second turn-on threshold voltage.

14. The driving circuit device according to claim 13, wherein the driving logic unit further comprises: The first SR flip-flop has: a set input terminal coupled to the output terminal of the first comparator; The reset input terminal is coupled to the clock signal input terminal; And the output terminal is configured to provide a first primary drive signal; The second SR flip-flop has a set input terminal coupled to the output terminal of the third comparator; The reset input is coupled to the output of the second comparator. And the output terminal is configured to provide a second primary drive signal; A first switch has: a first input terminal coupled to receive a first comparator output signal from the first comparator; And the control input is coupled to receive the mode selection signal; The second switch has: a first input terminal coupled to receive the second comparator output signal from the second comparator; And a control input terminal, coupled to receive the mode selection signal; The first inverter has an input terminal coupled to the output terminal of the first switch; A fourth comparator, wherein the non-inverting input of the fourth comparator is coupled to receive the sawtooth waveform, and the inverting input of the fourth comparator is coupled to receive the first synchronous rectification turn-on threshold voltage; The first AND gate has: a first input terminal coupled to the output terminal of the fourth comparator; The second input terminal is coupled to the output terminal of the first inverter; The third SR flip-flop has a set input coupled to the output of the first AND gate; A fifth comparator, wherein the non-inverting input of the fifth comparator is coupled to receive the sawtooth waveform, and the inverting input of the fifth comparator is coupled to receive the first synchronous rectification turn-off threshold voltage; The first OR gate has: a first input terminal coupled to the output terminal of the fifth comparator; The second input terminal is coupled to the output terminal of the first switch and also coupled to the output terminal of the second switch; A sixth comparator, wherein the non-inverting input of the sixth comparator is coupled to receive the sawtooth waveform, and the inverting input of the sixth comparator is coupled to receive a first blocking threshold voltage; The second AND gate has: a first input terminal coupled to the output terminal of the first OR gate; The second input terminal is coupled to the output terminal of the sixth comparator; The third SR flip-flop has: a reset input terminal coupled to the output terminal of the second AND gate; The output terminal is configured to provide a first synchronous rectification drive signal; A second inverter has an input terminal coupled to the output terminal of the second switch and the output terminal of the first switch; A seventh comparator, wherein the non-inverting input of the seventh comparator is coupled to receive the sawtooth waveform, and the inverting input of the seventh comparator is coupled to receive the second synchronous rectification turn-on threshold voltage; The third AND gate has: a first input terminal coupled to the output terminal of the seventh comparator; and a second input terminal coupled to the output terminal of the second inverter; The fourth SR flip-flop has a set input terminal, which is coupled to the output terminal of the third AND gate; An eighth comparator, wherein the non-inverting input of the eighth comparator is coupled to receive the sawtooth waveform, and the inverting input of the eighth comparator is coupled to receive the second synchronous rectification turn-off threshold voltage; The second OR gate has: a first input terminal coupled to the output terminal of the eighth comparator; And a second input terminal, coupled to the output terminal of the second switch and coupled to the output terminal of the first switch; A ninth comparator, wherein the non-inverting input of the ninth comparator is coupled to receive the sawtooth waveform, and the inverting input of the ninth comparator is coupled to receive a second blocking threshold voltage; The fourth AND gate has: a first input terminal coupled to the output terminal of the second OR gate; and a second input terminal coupled to the output terminal of the ninth comparator; The fourth SR flip-flop has: a reset input terminal coupled to the output terminal of the fourth AND gate; The output terminal is configured to provide a second synchronous rectification drive signal.

15. The driving circuit device according to claim 14, further comprising: The fifth AND gate has: a first input terminal coupled to the output terminal of the third SR flip-flop; The second input terminal is coupled to receive the synchronization enable signal; And the output terminal is configured to provide the first synchronous rectification drive signal; and The sixth AND gate has: a first input terminal coupled to the output terminal of the fourth SR flip-flop; The second input terminal is coupled to receive a synchronization enable signal; and the output terminal is configured to provide the second synchronization rectification drive signal.

16. The driving circuit device according to claim 14, further comprising: The output switching circuit device includes: The first set of switches is configured to selectively route the first primary drive signal and the second primary drive signal, or the first synchronous rectification drive signal and the second synchronous rectification drive signal, to the drive input terminals of the full-bridge transistor arrangement on the primary side based on the mode selection signal; and The second set of switches is configured to selectively route the first synchronous rectified drive signal and the second synchronous rectified drive signal or the first primary drive signal and the second primary drive signal to the drive input terminal of the full-bridge transistor arrangement on the secondary side based on the mode selection signal.

17. The driving circuit device according to claim 12, wherein the driving logic unit comprises: A delay generator is configured to receive a signal proportional to the clock signal and generate a plurality of delayed signals, the delayed signals including: First primary conduction delay signal; Second primary conduction delay signal; Second primary turn-off delay signal; First synchronous rectification conduction delay signal; First synchronous rectification turn-off delay signal; First blocking delay signal; Second synchronous rectification turn-on delay signal; The second synchronous rectification turn-off delay signal; and Second blocking delay signal.

18. The driving circuit device according to claim 12, further comprising: The first SR flip-flop has: a set input terminal coupled to receive the first primary conduction delay signal; The reset input is coupled to receive the clock signal; And the output terminal is configured to provide a first primary drive signal; The second SR flip-flop has: a set input terminal, which is coupled to receive the second primary conduction delay signal; The reset input is coupled to receive the second primary turn-off delay signal; And the output terminal is configured to provide a second primary drive signal; A first inverter has an input terminal, which is coupled to the first comparator output signal or the second comparator output signal of the first sensing circuit or the second sensing circuit via a switching circuit device. A first AND gate has an input terminal coupled to receive the output terminal of the first inverter and the first synchronous rectification turn-on delay signal; A first OR gate has an input terminal coupled to receive, via a switching circuit device, a first synchronous rectified turn-off delay signal and a first comparator output signal or a second comparator output signal of the first sensing circuit or the second sensing circuit. The second AND gate has an input terminal coupled to receive the output terminal of the first OR gate and the first blocking delay signal; The third SR flip-flop has: a set input terminal coupled to the output terminal of the first AND gate; The reset input is coupled to the output of the second AND gate; And at the output end, a first synchronous rectified signal is provided; The second inverter has an input terminal, which is coupled to the first comparator output signal or the second comparator output signal of the first sensing circuit or the second sensing circuit via a switching circuit device. A third AND gate has an input terminal coupled to receive the output terminal of the second inverter and the second synchronous rectification turn-on delay signal; The second OR gate has an input terminal coupled to receive the second synchronous rectified turn-off delay signal and the first comparator output signal or the second comparator output signal of the first sensing circuit or the second sensing circuit via a switching circuit device. The fourth AND gate has an input terminal coupled to receive the output terminal of the second OR gate and the second blocking delay signal; and The fourth SR flip-flop has: a set input terminal coupled to the output terminal of the third AND gate; The reset input is coupled to the output of the fourth AND gate; And at the output end, a second synchronous rectified signal is provided.

19. The drive circuit device according to claim 12, wherein: The first ground reference is connected to the control system ground associated with the drive logic unit; and The second ground reference is electrically isolated from the first ground reference through the second isolation transformer.

20. The driving circuit device according to claim 12, wherein: The first ground reference is connected to the control system ground associated with the drive logic unit; and The second ground reference is electrically isolated from the first ground reference via at least one of the first isolation transformer and the second isolation transformer, and via the main isolation transformer of the DC-DC converter, wherein the connection configuration of the ground reference of the isolation transformer is adaptive.

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