A digital control processing system and method for a three-phase interleaved LLC resonant converter

Abstract

The application discloses a kind of digital control processing systems for three-phase interleaved LLC resonant converter, the system is single-chip integrated structure, including: deployment in CPU three-phase staggered hybrid modulation module, hardware acceleration processing module independent of CPU, and pulse width modulation and atomic update module deployed in peripheral area;Hardware acceleration processing module integrates hardware IIR filter and PID accelerator, independent of CPU operation, for filtering and floating-point calculation to voltage current sampling signal;Hybrid modulation module is used to perform multi-phase staggered hybrid modulation calculation under single control quantity to generate PWM driving parameter;Pulse width modulation and atomic update module temporarily shield periodic interruption when updating parameter, by bottom bus using back-to-back continuous writing mode Parameter is synchronously loaded to hardware comparison register.The application greatly releases CPU computing power, shortens loop delay, improves response speed and PWM update synchronization reliability.

Description

Technical Field

[0001] This invention relates to the field of power electronic DC-DC conversion control technology, and in particular to a digital control processing system for a three-phase interleaved LLC resonant converter. Background Technology

[0002] LLC resonant converters have become the mainstream topology for medium- and high-power DC-DC conversion due to their ability to achieve zero-voltage turn-on (ZVS) of the primary-side switches and zero-current turn-off (ZCS) of the secondary-side rectifiers across the entire load range. With the increasing power density demands of data centers, 5G communication base stations, and electric vehicle charging stations, multiphase interleaved LLC converters, by operating multiple LLC converter units in parallel with a fixed phase difference, can effectively reduce output current ripple, increase power ratings, and reduce the size of filter components. Two-phase interleaved LLC converters are connected in parallel with a 90-degree phase difference, while three-phase converters further extend the phase difference to 120 degrees, resulting in even more significant ripple suppression.

[0003] The existing digital control systems for LLC resonant converters mainly suffer from the following technical bottlenecks: First, in traditional pure software PID control schemes, floating-point PID calculations consume a large number of CPU cycles. In a 100kHz high-frequency interrupt service routine (ISR), a single software PID calculation typically takes 8 to 15 microseconds, severely limiting the complexity of the control algorithm and the system's response speed. Second, existing modulation methods (pure PFM, pure PWM, or two-phase hybrid) lack a multi-phase coordinated single PI loop control architecture. Each phase usually requires an independent PI controller, increasing the complexity of control parameter tuning and the CPU's computational load. Third, during multi-phase PWM register updates, the conventional phase-by-phase writing method leads to inconsistent PWM parameter activation times for each phase, resulting in phase jitter and increased output ripple, which is particularly prominent in high-speed control scenarios (100kHz). Fourth, when switching between PFM and PWM modes, traditional gain scheduling strategies require offline pre-setting of multiple sets of PID parameters and table lookup loading during switching. The sudden parameter changes during switching pose a risk of discontinuous control output.

[0004] Therefore, there is an urgent need for a digital control processing system for three-phase interleaved LLC resonant converters that can compress the total ISR time while ensuring control accuracy, and achieve precise coordination and smooth mode switching between the three phases. Summary of the Invention

[0005] In view of this, the present invention provides a digital control processing system for a three-phase interleaved LLC resonant converter, which solves the technical problems of long control loop delay, slow dynamic response, and asynchronous loading of multi-channel PWM drive parameters caused by heavy CPU computing load in the existing digital control system of the three-phase interleaved LLC resonant converter.

[0006] To achieve the above-mentioned technical objectives, the present invention adopts the following technical solution:

[0007] In a first aspect, the present invention provides a digital control processing system for a three-phase interleaved LLC resonant converter, which is deployed in a control device containing a three-phase interleaved parallel LLC resonant converter unit. The digital control system is a single-chip integrated structure, including a three-phase phase-shifted hybrid modulation module deployed in the single-chip central processing unit, a hardware acceleration processing module independent of the central processing unit, and a pulse width modulation and atomic update module deployed in the peripheral area of ​​the single chip.

[0008] The hardware acceleration processing module operates independently of the central processing unit and includes a hardware IIR filter and a hardware PID accelerator. It is used to perform hardware filtering and floating-point proportional-integral-differential calculations on the voltage and current acquisition signals of the three-phase out-of-phase LLC resonant converter within several peripheral clock cycles.

[0009] The three-phase phase-shift hybrid modulation module is used to call the calculation results output by the hardware acceleration processing module to perform multi-phase phase-shift hybrid modulation calculation under a single control quantity, so as to generate multi-channel PWM drive parameters.

[0010] The pulse width modulation and atomic update module is used to temporarily disable periodic interrupts when updating the multi-channel PWM drive parameters, and synchronously load the multi-channel parameters into the hardware comparison register through a back-to-back continuous writing method via the underlying bus.

[0011] Secondly, the present invention provides a digital control processing method for a three-phase interleaved LLC resonant converter, implemented using the system described above, comprising:

[0012] The hardware acceleration processing module performs hardware filtering and floating-point proportional-integral-derivative calculations on the output voltage and output current acquisition signals of the three-phase misaligned LLC resonant converter within a preset number of peripheral clock cycles to generate a unified control quantity.

[0013] The three-phase phase-shift hybrid modulation module calls the output of the hardware acceleration processing module to perform multi-phase phase-shift hybrid modulation calculation under a single control quantity, and generates multi-path pulse width modulation drive parameters.

[0014] When updating the multi-channel pulse width modulation drive parameters, the temporary periodic interrupt is masked. After parameter verification and phase crossover safety detection are completed in the software shadow register, the multi-channel parameters are synchronously loaded into the hardware comparison register through the underlying bus using a back-to-back continuous writing method.

[0015] Compared with existing technologies, the digital control processing system for a three-phase interleaved LLC resonant converter proposed in this invention has the following advantages:

[0016] (1) By setting up a dedicated on-chip hardware acceleration area (integrating hardware IIR filters and hardware PID accelerators) that runs independently of the CPU, the computationally intensive signal filtering and floating-point PID calculations are completely offloaded to the hardware kernel, and the control quantity calculation can be completed in just a few peripheral clock cycles. This not only compresses the calculation delay of the control loop to the microsecond / submicrosecond level, greatly improving the dynamic response speed of the converter, but also frees the CPU from the heavy real-time loop calculation, significantly reducing interrupt usage and improving CPU availability.

[0017] (2) Based on the three-phase phase-shifting hybrid modulation module, the unified control quantity generated by the hardware acceleration module is used to directly perform multi-phase phase-shifting hybrid modulation calculation, avoiding the problems of cumbersome parameter tuning and difficult phase decoupling in traditional multi-loop control. This mechanism greatly simplifies the configuration of control parameters while ensuring smooth parameter transition and strict balance of three-phase phases during the switching process of the three-phase interleaved LLC converter in different operating modes (such as PFM / PWM).

[0018] (3) By utilizing the pulse width modulation and atomic update module to temporarily shield periodic interrupts during parameter updates and performing back-to-back continuous writing through the underlying bus, the synchronous latching and one-time loading of multiple PWM drive parameters to the hardware comparison register are realized. This atomic update mechanism completely avoids waveform tearing and phase jitter caused by multi-cycle step-by-step writing on the bus, ensuring accurate synchronization of multiple drive pulses and significantly improving phase-to-phase uneven current and output ripple.

[0019] (4) This solution adopts a single-chip integrated structure, which deeply integrates the CPU, hardware acceleration area and peripheral PWM atomic update module into the same chip, eliminating the communication delay and anti-interference risks between multiple chips on the board. While significantly reducing system hardware overhead and PCB board area, it achieves the comprehensive technical effects of reducing control delay, suppressing output ripple and improving operating efficiency. Attached Figure Description

[0020] Figure 1 A schematic diagram of the digital control processing system for a three-phase interleaved LLC resonant converter provided by the present invention;

[0021] Figure 2 A schematic diagram of the structure of the three-phase staggered LLC resonant converter provided by the present invention;

[0022] Figure 3a The efficiency comparison curves of the system provided by this invention and the traditional pure PFM two-phase solution across the entire load range;

[0023] Figure 3bA schematic diagram comparing the output ripple waveform of the system provided by this invention with that of a conventional system under full load;

[0024] Figure 3c A comparison chart of five key indicators between the system provided by this invention and traditional systems: full-load efficiency, light-load efficiency, output ripple, control delay, and three-phase current unevenness. Detailed Implementation

[0025] Preferred embodiments of the present invention will now be described in detail with reference to the accompanying drawings, which form part of this application and are used together with the embodiments of the present invention to illustrate the principles of the present invention, but are not intended to limit the scope of the present invention.

[0026] Example 1

[0027] This embodiment provides a digital control processing system for a three-phase interleaved LLC resonant converter, deployed in a control device containing a three-phase interleaved parallel LLC resonant converter unit. The digital control system is a single-chip integrated structure. Figure 1 As shown, it includes a three-phase phase-shift hybrid modulation module deployed in the single-chip central processing unit, a hardware acceleration processing module independent of the central processing unit, and a pulse width modulation and atomic update module deployed in the peripheral area of ​​the single chip.

[0028] The hardware acceleration processing module operates independently of the central processing unit and includes a hardware IIR filter and a hardware PID accelerator. It is used to perform hardware filtering and floating-point proportional-integral-differential calculations on the voltage and current acquisition signals of the three-phase out-of-phase LLC resonant converter within several peripheral clock cycles.

[0029] The three-phase phase-shift hybrid modulation module is used to call the calculation results output by the hardware acceleration processing module to perform multi-phase phase-shift hybrid modulation calculation under a single control quantity, so as to generate multi-channel PWM drive parameters.

[0030] The pulse width modulation and atomic update module is used to temporarily disable periodic interrupts when updating the multi-channel PWM drive parameters, and synchronously load the multi-channel parameters into the hardware comparison register through a back-to-back continuous writing method via the underlying bus.

[0031] The digital control processing system for a three-phase interleaved LLC resonant converter provided in this embodiment adopts a single-chip integrated CPU + on-chip dedicated hardware acceleration architecture. By using hardware IIR and PID modules independent of the CPU, it performs ultra-fast calculations on the three-phase LLC sampling signals within several clock cycles. Combined with a hybrid modulation algorithm under a single control quantity and an atomic update mechanism for PWM registers that "masks interrupts + back-to-back bus writing", it frees up CPU computing resources, shortens the processing latency of the control loop, and completely eliminates the risk of asynchronous tearing and phase jitter that may occur when updating multi-channel PWM drive parameters across cycles. This improves the dynamic response speed, multi-phase current balance, and overall stability and reliability of the three-phase interleaved LLC resonant converter during high-frequency operation.

[0032] As a specific implementation, the system is deployed in a digital controller, employing a Cortex-M4 core (200MHz clock speed, 5nm PCLK cycle). It integrates on-chip hardware PID accelerators (4 channels PID0 to PID3), hardware IIR accelerators (4 channels IIR0 to IIR3), a CPU, and a high-resolution PWM module (HRPWM, supporting 6 complementary outputs). The system control architecture uses a fixed 100kHz interrupt service routine (ISR) with a control cycle of 10 microseconds.

[0033] like Figure 2 As shown, the three-phase staggered LLC resonant converter includes: Phase 1 full-bridge (switches Q1 to Q4), Phase 1 resonant cavity (Lr1 and Cr1), and Phase 1 transformer T1; Phase 2 full-bridge (switches Q5 to Q8), Phase 2 resonant cavity (Lr2 and Cr2), and Phase 2 transformer T2; Phase 3 full-bridge (switches Q9 to Q12), Phase 3 resonant cavity (Lr3 and Cr3), and Phase 3 transformer T3; the three phases are synchronously rectified on the secondary side and then connected in parallel to the output filter capacitor Co and the load (rated output 53.5V / 168A, i.e., 56A per phase equivalent).

[0034] As a specific embodiment, the system operates as follows: In each control cycle, the ADC sampling module samples the output voltage Vout and output current Iout of the three-phase staggered LLC resonant converter using an independent time base, and transfers them to memory via DMA; the hardware IIR accelerator (IIR2 filters Vout, IIR3 filters Iout) completes the filtering operation within 1 to 2 PCLK cycles, and the result is directly sent to the hardware PID accelerator; the voltage loop PID0 calculates the control quantity llc_result based on the Vout reference value and the filtered Vout feedback value, and the current loop PID1 calculates the current sharing correction quantity llc_result based on the Iout reference value and the filtered Iout feedback value; the three-phase staggered hybrid modulation module determines the PFM or PWM mode based on the llc_result value and calculates the PWM parameters for each of the three phases; under interrupt shielding protection, the atomic update module writes the multi-channel PWM parameters into the hardware register at once.

[0035] The following analysis examines the hardware-accelerated integrated control cycle delay of this system. The hardware accelerators (PID0 / PID1, IIR2 / IIR3) handle all floating-point PID / IIR calculations. The calculation delay for each accelerator channel is 1-2 PCLK cycles (approximately 5-10 nanoseconds). The CPU only reads the result register and performs three-phase phase shift calculations and PWM register updates after the hardware calculations are completed. This hardware-software division of labor completely frees the CPU from traditional software PID calculations (approximately 8-15 microseconds), allowing the CPU to allocate the freed-up computing resources to three-phase offset calculations (approximately 1.0 microsecond) and atomic register updates (approximately 0.2 microseconds). The hardware PID / IIR calculations themselves only occupy 0.3 + 0.2 microseconds. The total control delay is 2.2 microseconds, only 22% of the 100kHz control cycle (10 microseconds), far lower than traditional pure software solutions (greater than 80%), providing ample timing margin for real-time three-phase phase shift control.

[0036] Specifically, the timing budget for the control cycle is shown in Table 1:

[0037] Table 1

[0038] Control phase Execution Entity Timing occupancy (μs) percentage ADC sampling ADC IP core (DMA) 0.5 5% Hardware IIR Filtering IIR2 / IIR3, Hardware Accelerators 0.2 2% Hardware PID Calculation PID0 / PID1, hardware accelerator 0.3 3% Three-phase modulation calculation CPU (Software Algorithm) 1.0 (including phase shift) 10% Atomic PWM Update CPU + Interrupt Disabling 0.2 2% Total control delay - 2.2 22%

[0039] Furthermore, the comparison results with the traditional solution are shown in Table 2:

[0040] Table 2

[0041] Comparison items Traditional software solutions Pure hardware solution This plan Software PID delay 8-15μs 3-5μs (ASIC) 0.3μs Three-phase update method Phase-by-phase update (3 times) Partial parallel 6-channel atomic update Total ISR delay 15-25μs 8-12μs 2.2μs ISR duty cycle @ 100Hz 15-25% 8-12% 2.2%

[0042] It should be noted that the results in Table 2 are based on Cortex-M4 200MHz operation, PCLK=200MHz, single PCLK cycle=5ns, hardware PID1-2PCLK=10ns, and the actual measured 0.3us includes register configuration overhead.

[0043] As can be seen from the comparison results in Table 2, this solution significantly reduces the PID calculation latency to 0.3 μs (including register configuration overhead, which is tens of times better than the traditional software solution) by using an on-chip hardware accelerator. Furthermore, thanks to the 6-channel atomic update mechanism, it completely eliminates the risk of asynchronous waveforms between phases caused by traditional phase-by-phase updates or partial parallel methods. Ultimately, it reduces the total ISR interrupt latency from 15~25 μs in the traditional solution to 2.2 μs, significantly reducing interrupt overhead. While greatly improving the real-time control and synchronous reliability of the three-phase LLC converter, it also leaves a margin for CPU computing power in the system.

[0044] Example 2

[0045] In a preferred embodiment, the hardware PID accelerator includes at least four independent second-order filter channels;

[0046] Specifically, the outer voltage loop is mapped to the first PID channel, the inner current loop is mapped to the second PID channel, the output voltage sampling signal is mapped to the third IIR channel, and the output current sampling signal is mapped to the fourth IIR channel.

[0047] In a preferred embodiment, the hardware IIR filter includes multiple independent hardware filtering channels, each of which is configured as a second-order IIR direct type I structure on the underlying circuit.

[0048] The second-order IIR direct type I structure integrates a dedicated coefficient register, a delay state register array, and a hardware multiply-accumulate unit in hardware, which is used to perform parallel multiply-accumulate calculations independent of the central processing unit.

[0049] The hardware filtering channels allocated to the output voltage and output current are each configured with a corresponding low-pass cutoff frequency parameter register.

[0050] In some embodiments, the hardware PID accelerator provides four independent channels (PID0 to PID3), each supporting 32-bit (FP32) floating-point proportional-integral-differential operations, with a hardware computation latency of 1 to 2 PCLK cycles (approximately 5 to 10 nanoseconds). The hardware IIR accelerator also provides four independent channels (IIR0 to IIR3), each supporting a second-order IIR direct I-type structure, with a hardware computation latency of 1 to 2 PCLK cycles.

[0051] In some embodiments, the hardware PID accelerator supports online updating of proportional, integral, and derivative coefficients during runtime, and the hardware IIR accelerator supports online updating of filter coefficients during runtime. The coefficient update operation is performed synchronously at the moment of PFM / PWM mode switching, and the control quantity remains continuous without abrupt changes before and after the switching.

[0052] As a specific embodiment, the hardware acceleration processing module also includes a software abstraction layer program module, which encapsulates the register operations of the hardware PID accelerator and the hardware IIR accelerator through the HW_PID_Context structure and the HW_IIR_Context structure, providing a unified interface for initialization, coefficient writing, calculation triggering and result reading.

[0053] Specifically, at the supporting software implementation level, the software abstraction layer encapsulates hardware register operations through the defined structures HW_PID_Context and HW_IIR_Context, providing initialization functions (hw_pid_init and hw_iir_init), coefficient writing functions (hw_pid_set_coeffs and hw_iir_set_coeffs), calculation trigger functions (hw_pid_trigger and hw_iir_trigger), and result reading functions (hw_pid_get_result and hw_iir_get_result). The context structure contains the channel number, coefficient register address mapping, input / output data register address mapping, and status flags.

[0054] By abstracting away the complex details of low-level hardware registers through a software abstraction layer and standardized APIs, the coupling between software and hardware is greatly reduced, improving the maintainability and cross-platform portability of the control software. Utilizing context structures to independently encapsulate the register mappings and states of each channel enables efficient and unified management and secure scheduling of multi-channel hardware acceleration resources, simplifying the driver call process in real-time control.

[0055] It should also be noted that runtime coefficient updates are a key mechanism for achieving smooth switching between PFM and PWM modes. When switching between PFM and PWM modulation modes, the parameter requirements of the voltage loop PID0 differ. Specifically: in PFM mode, the resonant cavity gain characteristics are more sensitive to frequency changes, requiring a larger proportional gain and a moderate integral time constant; in PWM mode, the resonant cavity operates at a non-resonant fixed frequency point, the system gain decreases, and a smaller proportional gain and a larger integral time constant are required.

[0056] Traditional solutions require looking up and loading new parameters from a preset parameter table during mode switching. This lookup and loading process introduces a delay of approximately 2 to 5 microseconds, and the control input may change abruptly during loading. In contrast, this invention utilizes the runtime coefficient update capability of a hardware PID accelerator. Within the same control cycle after mode determination, the new coefficients are directly written to the hardware register via the `hw_pid_set_coeffs` function. This operation is a single AHB bus write operation (approximately 20 nanoseconds), introducing no additional delay. Furthermore, the new coefficients take effect immediately in the hardware calculation of the next PCLK cycle, achieving truly zero-latency, seamless parameter switching.

[0057] Example 3

[0058] In some embodiments, the three-phase phase-shift hybrid modulation module is configured with a mode-switching hysteresis comparator;

[0059] The hysteresis comparator integrates a hysteresis interval threshold register with a preset width, which provides hard threshold protection when switching between pulse frequency modulation mode and pulse width modulation mode.

[0060] In a preferred embodiment, the three-phase phase-out hybrid modulation module is configured with phase out-of-bounds detection hardware logic and a flag register;

[0061] The phase boundary detection hardware logic is used to compare the calculated phase offset comparison value with the real-time value of the current comparison register, and to set the flag register when the phase crosses the current cycle boundary.

[0062] As a specific embodiment, the three-phase phase-shifting hybrid modulation module is also configured with a sudden shutdown protection comparison circuit;

[0063] The comparison circuit is used to compare the calculated duty cycle on-time with the hard-set value in the dead time preset multiple register in pulse width modulation mode, and to trigger the forced pull-down logic of the PWM output control gate according to the comparison result.

[0064] It should be noted that the core innovation of the three-phase phase-shifting hybrid modulation module lies in using the output of a single voltage loop PI (PID0 hardware accelerator) as the unified control quantity for all three phases (for specific implementation methods, please refer to the detailed description in Example 5). The three phases are only distinguished by a fixed time offset (Phase 2 offset 240 degrees, Phase 3 offset 120 degrees), which avoids the parameter tuning complexity and inter-phase coupling problems caused by independent PI controllers for each phase in conventional schemes.

[0065] Example 4

[0066] In a preferred embodiment, the pulse width modulation and atomic update module includes a periodic interrupt mask register, a software shadow register array, and a six-channel hardware comparison register array;

[0067] The periodic interrupt mask register is configured to be set when the start instruction of the back-to-back continuous write operation is received, so as to temporarily block the periodic overload interrupt signal of the pulse width modulation and atomic update module.

[0068] The software shadow register array is connected via the on-chip low-level bus and is used to receive and temporarily store the six-channel pulse width modulation drive parameters calculated by the three-phase phase-shift hybrid modulation module back-to-back.

[0069] The six-channel hardware comparator register array is connected to the software shadow register array and the switching transistor drive circuits of the three-phase interleaved parallel LLC resonant converter, respectively.

[0070] Specifically, after the back-to-back continuous write operation is completed and the periodic interrupt mask register is reset, the six-channel hardware comparator array synchronously loads the six-channel pulse width modulation drive parameters in the software shadow register array into their respective hardware comparators at the next pulse width modulation cycle counting node.

[0071] The core objective of this module is to ensure that the parameters of the six PWM channels (CH1 to CH6 correspond to the upper and lower transistors of Phase 1 to Phase 3, respectively) take effect simultaneously at the same PWM cycle boundary, eliminating phase inconsistencies that may be caused by phase-by-phase writing.

[0072] Based on the calculated switching cycle, three-phase phase offset, and preset dead time, the on-time comparison value and off-time comparison value of the six complementary pulse width modulation drive signals corresponding to the six power switches of the three-phase bridge arm in the three-phase interleaved parallel LLC resonant converter unit are calculated in parallel. During the dynamic change of the switching cycle, the dead time of each drive signal is kept independently locked or scaled proportionally with the switching cycle to avoid shoot-through between the upper and lower bridge arms of the same phase.

[0073] As a specific embodiment, the pulse width modulation and atomic update module mainly implements four main functions: security verification logic, interrupt mask control, bus transmission mechanism, and hardware synchronization triggering. Specifically:

[0074] (1) Interruptions to the temporary shielding cycle include:

[0075] Before performing the back-to-back continuous write operation, the hardware-level periodic overload interrupt masking flag is set by writing a mask instruction to the periodic interrupt masking register.

[0076] After writing the last pulse width modulation drive parameter to the software shadow register via the underlying bus, the periodic overload interrupt mask flag is immediately cleared, and the periodic interrupt response is restored.

[0077] (2) Perform parameter verification and phase crossover security detection in the software shadow register, including:

[0078] The calculated switching period and duty cycle are limited and verified to ensure that they are within the preset safe operating range of the resonant converter;

[0079] Calculate the phase offset change between the current control cycle and the previous control cycle, determine whether the phase offset change exceeds the preset step size safety threshold, and whether the phase order of the three-phase drive signals remains consistent.

[0080] If the step size safety threshold is exceeded or the phase sequence is abnormal, the phase offset of the current cycle will be limited to within the step size safety threshold to prevent the drive waveform from overlapping or phase crossing.

[0081] (3) Back-to-back continuous writing via the underlying bus includes:

[0082] The continuous base addresses of the software shadow register array are mapped using the multi-register continuous write instruction or direct memory access controller of the central processing unit.

[0083] During the continuous clock cycles without bus arbitration waiting, the multi-channel pulse width modulation drive parameters are continuously written into the corresponding channel address at once.

[0084] (4) Synchronous loading into the hardware compare register includes:

[0085] After the back-to-back continuous writing is completed and the cycle interrupt response is restored, the hardware pulse width modulation counter runs to the next cycle zero point or cycle matching node.

[0086] At the zero point of the cycle or the matching node of the cycle, the hardware comparator register array responds to the hardware synchronization latch pulse and updates the multi-path pulse width modulation drive parameters in the software shadow register to the hardware comparator in parallel within a single clock cycle.

[0087] In some embodiments, the system further includes a dedicated hardware debug pin and a state flip control circuit, the state flip control circuit being connected to the pulse width modulation and atomic update module and configured to automatically drive the debug pin to flip the output level at the start and end points of the back-to-back continuous write operation.

[0088] In practice, the GPIO debug pin toggles the GPIO pin level at the start and end of the atomic update, outputting a timing pulse with a width of approximately 0.2 to 0.3 microseconds for external oscilloscope measurement.

[0089] Example 5

[0090] This embodiment provides a digital control processing method for a three-phase interleaved LLC resonant converter, implemented using the system described in the above technical solution, including:

[0091] Step S101: Using the hardware acceleration processing module, the output voltage and output current acquisition signals of the three-phase misaligned LLC resonant converter are subjected to hardware filtering and floating-point proportional-integral-derivative calculation within a preset number of peripheral clock cycles to generate a unified control quantity.

[0092] Step S102: By calling the output result of the hardware acceleration processing module through the three-phase phase-shifting hybrid modulation module, multi-phase phase-shifting hybrid modulation calculation under a single control quantity is performed to generate multi-path pulse width modulation drive parameters;

[0093] Step S103: When updating the multi-channel pulse width modulation drive parameters, the periodic interrupt is temporarily masked. After completing parameter verification and phase crossover security detection in the software shadow register, the multi-channel parameters are synchronously loaded into the hardware comparison register through the underlying bus using a back-to-back continuous writing method.

[0094] As a specific embodiment, in step S101, the channel mapping scheme of the hardware IIR filter and the hardware PID accelerator is as follows: PID0 is assigned to the voltage outer loop (Vloop), with input Vref minus Vout_filt and output llc_result control quantity; PID1 is assigned to the current inner loop (Iloop), with input Iref minus Iout_filt and output current sharing correction quantity; IIR2 is assigned to the output voltage filtering channel, performing low-pass filtering on Vout_raw sampled by the ADC, with the cutoff frequency set to 1kHz to suppress switching ripple; IIR3 is assigned to the output current filtering channel, performing low-pass filtering on Iout_raw, with the cutoff frequency set to 2kHz.

[0095] In step S102, the implementation process of the three-phase staggered PFM / PWM hybrid modulation algorithm in the three-phase staggered hybrid modulation module includes: performing the following steps in each control cycle:

[0096] Step S21: Read the lllc_result value (FP32 floating-point number, typically ranging from -1.0 to +1.0) from hardware PID0.

[0097] Step S22: Determine the modulation mode: If llc_result is greater than the preset switching threshold = 50 / 200 = 0.25, proceed to the PFM mode described in step S23; if llc_result is not greater than the threshold, proceed to the PWM mode described in step S24.

[0098] Step S23: When switching to PFM mode, the switching period is calculated based on the value of llc_result using a frequency mapping function. The mapping relationship is period = llc_result × LLC_SW_PERIOD_MAX (corresponding to 20000ns~5000ns, i.e. 50kHz~200kHz); the duty cycle is fixed at 50%; the comparison values ​​of the rising and falling edges of CH1 / CH2 in Phase 1 are calculated. The comparison values ​​of Phase 2 are offset by 4 times the period / 6 (i.e., 240-degree equivalent delay) based on Phase 1, and the comparison values ​​of Phase 3 are offset by 2 times the period / 6 (i.e., 120-degree equivalent delay).

[0099] Step S24: When switching to PWM mode, the switching frequency is fixed at 200kHz (period 5000 nanoseconds), and the duty cycle is determined by the llc_result value through linear mapping: the minimum duty cycle is dead time × 4 (to ensure that burst is not triggered), and the maximum duty cycle is the conduction time corresponding to 50% duty cycle of PFM at 200kHz; the three-phase offset calculation is the same as in PFM mode; in PWM mode, phase crossover detection is additionally performed - when the conduction time corresponding to the calculated duty cycle is less than 4 times the dead time, the burst automatic shutdown flag is triggered, and the PWM output of the corresponding phase is forcibly pulled low to protect the power devices.

[0100] By using the above method, the output llc_result of a single voltage loop PI (PID0 hardware accelerator) is used as the unified control quantity for all three phases. The three phases are only distinguished by a fixed time offset (Phase 2 offset 240 degrees, Phase 3 offset 120 degrees), which avoids the parameter tuning complexity and inter-phase coupling problems caused by independent PI controllers for each phase in conventional schemes.

[0101] Furthermore, the precise calculation method for the three-phase offset is as follows: Let the switching period determined by the current control cycle be T (nanoseconds), and the reference zero point of Phase 1 be the start time of the PWM module's cycle. The offset of Phase 2 relative to Phase 1 is floor(T × 240 / 360) = floor(T × 2 / 3) nanoseconds, and the offset of Phase 3 relative to Phase 1 is floor(T × 120 / 360) = floor(T × 1 / 3) nanoseconds. In PFM mode, T varies with the load, so the three-phase offset is recalculated for each control cycle; in PWM mode, T is fixed at 5000 nanoseconds, and the three-phase offset is correspondingly fixed.

[0102] In some embodiments, the three-phase phase-shifting hybrid modulation module is configured with a phase crossover detection mechanism, which is used to automatically trigger a sudden shutdown when the duty cycle is less than a preset multiple of the dead time in pulse width modulation mode, so as to prevent reverse power flow under extremely light load conditions.

[0103] Specifically, in PWM mode, when load changes cause a large change in the duty cycle, the fixed offsets phase_2_value and phase_3_value may cross the boundary of the current PWM cycle (i.e., the phase offset value is greater than the current CMPDR register value), causing the comparator to fail to trigger in the current cycle, resulting in phase misalignment.

[0104] To address the aforementioned issue, two detection flags, `llc2_cmp_over` and `llc3_cmp_over`, are used to identify this situation: After each control cycle calculation, the new phase offset value is compared with the current CMPDR value. If `phase_2_value` is greater than `pwm.compd` and the current CMPDR is still greater than `phase_2_value`, it is determined that Phase 2 is about to go out of bounds, `llc2_cmp_over` is set, and phase alignment of this phase is prioritized in the next control cycle. Similarly, `llc3_cmp_over` detects the risk of Phase 3 going out of bounds. This mechanism ensures that the three phases always maintain a strict 120-degree phase misalignment relationship across the entire load range, avoiding sudden increases in output current ripple caused by phase out of bounds.

[0105] The control delay in the three-phase modulation calculation stage is analyzed below:

[0106] The software performs the following operations in the CPU: reads the `llc_result` output by PID0 → determines the PFM / PWM mode → calculates the switching period T and duty cycle D based on the mode → calculates the shadow values ​​of the comparison registers for each PWM channel (CH1 to CH6) of Phase 1 / Phase 2 / Phase 3 respectively → performs phase crossover detection → stores the calculation results in the shadow register array. The total time for this calculation stage is approximately 1.0 microsecond (including 0.15 microseconds for mode determination, 0.45 microseconds for each of the three phases, 0.30 microseconds for crossover checking and burst determination, and 0.10 microseconds for boundary processing). That is: PFM / PWM mode determination: 0.15us; Phase duty cycle / period: 0.15us; Phase2 (240° offset): 0.1u5s; Phase3 (120° offset): 0.15s; Phase crossover detection: 0.10us; 3-phase crossover check and burst determination: 0.30us; The total CPU time for three-phase modulation calculation is 1.0us.

[0107] As a specific embodiment, in step S103, the core objective of the atomic update mechanism is to ensure that the parameters of the six PWM channels (CH1 to CH6 correspond to the upper and lower transistors of Phase 1 to Phase 3, respectively) take effect simultaneously at the same PWM cycle boundary, eliminating phase inconsistencies that may be caused by phase-by-phase writing. The execution flow is as follows:

[0108] Step S31: When the ISR enters the PWM parameter update stage, the timer period interrupt is temporarily masked through hardware register operations to prevent nested interrupts from causing repeated modifications to the PWM register during the update process. The delay of the interrupt masking operation is only a single register write instruction (approximately 10 nanoseconds).

[0109] Step S32: In the CPU software, the shadow register array (containing all comparison register values ​​of the 6 PWM channels) calculated in the three-phase modulation calculation stage is checked item by item to confirm that all values ​​are within the legal range (the comparison value is not greater than the period value, and the dead time is not less than the minimum dead time limit).

[0110] Step S33, perform phase crossover safety detection: read the real-time value of the current PWM counter to confirm that there is still enough time margin before the end of the current PWM cycle (at least twice the shadow register write time) to prevent writing abnormal pulses near the boundary of the PWM cycle that would cause abnormal pulses in the current cycle.

[0111] In step S34, within the atomic update critical region, the values ​​of the six compare registers are moved to the hardware PWM register in a back-to-back sequential write manner according to the order of CH1_CR, CH2_CR, CH3_CR, CH4_CR, CH5_CR, and CH6_CR. After all six write operations are completed, the cycle interrupt is re-enabled. This atomic transfer stage takes approximately 0.2 microseconds.

[0112] As a preferred embodiment, the interrupt masking time is quantified by engineering: the interrupt masking operation in step S31 is completed by a single AHB bus write instruction, the execution time of which is about 10~20 nanoseconds (the AHB write operation of 200MHz Cortex-M4 is 1~2 HCLK cycles), which is much smaller than the minimum protection time margin of PWM (100 nanosecond level).

[0113] The total duration of the entire interrupt masking window (steps S31, S32, S33, and S34) is approximately 0.2 to 0.3 microseconds. During this period, the CMP values ​​of all three phases and six channels of PWM have been atomically written. This time window is only 2% to 3% of the 100kHz control cycle (10 microseconds) and has no impact on the system's real-time performance.

[0114] Compared with the conventional approach (writing PWM registers directly in the ISR without interrupt protection), this approach eliminates the nanosecond-level time difference between writing to each phase register through atomic updates, ensuring that all 6 PWM channels are strictly synchronized.

[0115] In some embodiments, the method further includes: outputting a low level (or high level) via a GPIO debug pin before the atomic update begins, and toggling the level after the atomic update is completed, forming a timing pulse with a width of approximately 0.2 to 0.3 microseconds, which can be directly observed with an oscilloscope to verify the actual time consumed by the atomic update.

[0116] As a preferred embodiment, the interrupt masking protection timing design is as follows: A periodic interrupt is triggered at the end of each PWM cycle. If the atomic update operation in the ISR competes with the next periodic interrupt, the new parameters may take effect at the wrong time. By masking the interrupt in advance, the total masking time of the critical section (end of steps S31 to S34) is controlled to within 0.5 microseconds, far less than the 10 microsecond control cycle. Even in the worst case (the interrupt is suspended just during the masking period), the interrupt will be serviced immediately after re-enabling, without losing the interrupt event. Measurement data shows that this mechanism reduces the maximum deviation of the PWM update time between the three phases from approximately 300 nanoseconds (3 writes × approximately 100 nanoseconds / AHB bus delay) in the traditional phase-by-phase scheme to less than 5 nanoseconds (total register effective delay difference of 6 back-to-back writes), improving phase jitter by approximately 60 times.

[0117] The synergistic effect of three-phase modulation calculation, hardware accelerator, and atomic update management is analyzed below. Specifically, the hardware accelerator (hereinafter referred to as B) releases CPU computing power, providing the execution basis for three-phase modulation calculation (hereinafter referred to as A) and atomic update management (hereinafter referred to as C); at the same time, A generates 6 channels of consistent control quantities, so that the batch transfer of C has a unified data source; and the timing protection of C ensures the reliable effectiveness of the calculation results of A. The absence of any one of the three will result in a significant degradation in system performance.

[0118] The synergistic effect is quantitatively analyzed as follows:

[0119] Synergistic effect one (B→A): Hardware PID0 compresses voltage loop calculation from about 8 to 15 microseconds in the traditional software solution to 0.3 microseconds (including register configuration overhead). The freed CPU time is directly used for three-phase phase-shifting modulation calculation (1.0 microsecond). Without hardware acceleration, the CPU cannot complete PID calculation and three-phase modulation calculation simultaneously in a 100kHz ISR (total control cycle limit of 10 microseconds).

[0120] Synergistic effect two (A→C): The unified llc_result generated by the single PI loop ensures that the PWM parameters of each of the three phases have a deterministic phase relationship (240 degrees and 120 degrees offset). The simultaneous activation of the 6 atomically updated channels ensures that this deterministic phase relationship is accurately reflected in the physical PWM output, without the exposure of intermediate states phase by phase.

[0121] Synergistic effect three (B→A mode switching): The runtime coefficient update capability of the hardware PID (< 20 nanoseconds) ensures that parameter adjustments during PFM / PWM mode switching will not introduce any observable delay or abrupt change in the control quantity calculation path, and the PID output remains continuous before and after the switching point.

[0122] As analyzed in Example 1, the overall timing measurement data (100kHz ISR, 200MHz Cortex-M4) is as follows: ADC sampling and DMA transfer stage: 0.5 microseconds; hardware IIR filtering stage: 0.2 microseconds (IIR2 and IIR3 in parallel); hardware PID calculation stage: 0.3 microseconds (PID0 and PID1 in parallel); three-phase phase misalignment modulation calculation stage: 1.0 microseconds (CPU software); atomic PWM update stage: 0.2 microseconds (interrupt masking + batch writing); total control delay: approximately 2.2 microseconds, accounting for 22.0% of the 10 microsecond control cycle. The GPIO debug pin output pulse width is approximately 0.25 microseconds, consistent with the design value. The measured phase deviation of the three-phase PWM output is less than 5 nanoseconds, and the three-phase output current non-uniformity is less than 3.5%.

[0123] To further verify the performance of the system provided by this invention under different operating conditions, this application designed a comparative experiment with a traditional pure PFM two-phase scheme. The test conditions were: DC input voltage 400V, output target 53.5V / 168A (equivalent to 56A for each of the three phases), control cycle 10 microseconds (100kHz ISR), and digital controller main frequency 200MHz. The comparison results are as follows:

[0124] Case 1: Full load condition (168A / 56A each for three phases): The system operates in PFM mode with a switching frequency of approximately 60kHz. Three-phase ZVS is achieved across the entire bridge, achieving a full load efficiency of 96.5%, a 2.3 percentage point improvement compared to the traditional two-phase solution's 94.2%. Output ripple is 45mVpp, a 72% reduction compared to the traditional solution's 160mVpp. Three-phase current unevenness is 3.5%, a 71% reduction compared to the traditional solution's 12%. Control delay is 2.2 microseconds, an 85% reduction compared to the traditional solution's 15 microseconds.

[0125] Scenario 2: Half-load condition (84A / 28A each for three phases): The system operates in PFM mode, with a switching frequency of approximately 110kHz, an efficiency of 95.1%, and an output ripple of 38mVpp; the three-phase current unevenness is 2.8%. Mode switching point condition (approximately 45A / 15A each for three phases): The system is at the PFM / PWM switching boundary, with a switching frequency of 200kHz and an efficiency of 93.5%. Seamless switching is achieved by updating the coefficients during hardware PID operation, and the output voltage fluctuation before and after switching is less than 0.5%.

[0126] Scenario 3: Light load condition (30A / 10A each for three phases): The system operates in PWM mode with a fixed switching frequency of 200kHz. The duty cycle is adaptively adjusted according to `llc_result`, achieving an efficiency of 91.8%, a 5.3 percentage point improvement compared to the traditional pure PFM solution's 86.5% under the same load. Phase crossover detection and automatic burst shutdown functions function normally in PWM mode. Under extremely light load conditions (duty cycle less than 4 times the dead time), the system automatically enters burst mode, effectively protecting the power devices. No-load condition (1.5A): The system operates in PWM with an extremely low duty cycle. The auxiliary power supply maintains the control circuit operation without abnormal oscillation or overvoltage.

[0127] Figure 3a The efficiency comparison curves of the integrated system of this invention and the traditional pure PFM two-phase solution are shown across the entire load range (0A to 56A). Figure 3b A schematic diagram showing the comparison of the output ripple waveform of this system and a traditional system under full load is presented; Figure 3c The chart shows a comparison between this system and a traditional system in five key indicators: full-load efficiency, light-load efficiency, output ripple, control delay, and three-phase current unevenness.

[0128] In addition, this application also conducted load transient response tests. In PFM mode, when the load jumped from 84A to 168A, the output voltage drop was less than 1.5%, and the recovery time was less than 150 microseconds. When switching from PWM to PFM mode, when the load jumped from 30A to 90A, the hardware PID coefficients were updated synchronously during operation, the switching process was smooth and shock-free, and the output voltage overshoot was less than 0.8%.

[0129] Based on the above analysis and experimental results, the advantages of this system are as follows:

[0130] First, the hardware-accelerated PID / IIR dual-unloading mechanism compresses the core control calculation from 15 microseconds to 0.5 microseconds. The freed-up CPU bandwidth supports three-phase phase-shifting modulation calculation (approximately 1.0 microsecond) and 6-channel atomic update management (approximately 0.3 microsecond), keeping the total time for 100kHz high-frequency ISR within 2.0 microseconds. The CPU utilization rate is only about 20%, far lower than the 80% to 150% of traditional solutions (exceeding the single control cycle). This provides ample computing power margin for integrating more advanced functions (such as efficiency optimization algorithms, fault prediction, and digital communication protocol stacks). Furthermore, the hardware accelerator's runtime coefficient update capability allows PID parameters and IIR filter coefficients to be synchronously adjusted without delay within the same control cycle during PFM / PWM mode switching. This eliminates the control variable abrupt changes and system oscillation risks introduced by parameter table switching in traditional gain scheduling schemes, resulting in a smooth and shock-free mode switching process.

[0131] Secondly, the single-PI-loop three-phase phase-shifting modulation architecture eliminates the coupling and parameter tuning complexity between phase controllers in the traditional multi-PI-loop scheme, reducing the number of control parameters by about two-thirds; the 120-degree equal-interval phase shift between the three phases increases the output current ripple frequency to six times the switching frequency, and reduces the ripple amplitude by about 60% to 72% under the same output filter capacitor conditions; the phase crossover detection and automatic burst shutdown mechanism in PWM mode effectively prevent reverse power flow and efficiency degradation under extremely light load conditions.

[0132] Third, the interrupt masking + shadow register atomic update mechanism ensures that the parameters of the 6 PWM channels take effect simultaneously on the same clock edge, eliminating the nanosecond to microsecond level phase jitter introduced by phase-by-phase updates; the GPIO debug pin output mechanism allows the update timing to be directly measured with an oscilloscope during system operation, which is convenient for debugging and performance verification.

[0133] Fourth, the hardware-accelerated PID / IIR dual unloading mechanism, the single PI-loop three-phase phase-shifted modulation architecture, and the interrupt masking + shadow register atomic update mechanism produce a synergistic effect, enabling the system to achieve a three-phase current sharing ZVS efficiency of over 96.5% under full load conditions. Under light load conditions, the efficiency is improved by 5 to 8 percentage points compared to the pure PFM solution, and the output ripple is reduced from 160mVpp in the traditional solution to 45mVpp. The control bandwidth can reach the equivalent 600kHz three-phase comprehensive update rate corresponding to the 100kHz ISR.

[0134] The above description is only a preferred embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in the present invention should be included within the scope of protection of the present invention.

Claims

1. A digital control processing system for a three-phase interleaved LLC resonant converter, deployed in a control device comprising three-phase interleaved parallel LLC resonant converter units, characterized in that, The digital control system is a single-chip integrated structure, including a three-phase phase-shift hybrid modulation module deployed in the single-chip central processing unit, a hardware acceleration processing module independent of the central processing unit, and a pulse width modulation and atomic update module deployed in the peripheral area of ​​the single chip. The hardware acceleration processing module operates independently of the central processing unit and includes a hardware IIR filter and a hardware PID accelerator. It is used to perform hardware filtering and floating-point proportional-integral-differential calculations on the voltage and current acquisition signals of the three-phase out-of-phase LLC resonant converter within several peripheral clock cycles. The three-phase phase-shift hybrid modulation module is used to call the calculation results output by the hardware acceleration processing module to perform multi-phase phase-shift hybrid modulation calculation under a single control quantity, so as to generate multi-channel PWM drive parameters. The pulse width modulation and atomic update module is used to temporarily disable periodic interrupts when updating the multi-channel PWM drive parameters, and synchronously load the multi-channel parameters into the hardware comparison register through a back-to-back continuous writing method via the underlying bus.

2. The system according to claim 1, characterized in that, The hardware acceleration processing module includes multiple shared hardware channels, each of which is configured to switch between proportional-integral-derivative (PID) operation mode and infinite impulse response (IIR) filter operation mode, so that the PID operation and the IIR filter share on-chip hardware computing resources. The plurality of shared hardware channels include at least a first shared hardware channel, a second shared hardware channel, a third shared hardware channel, and a fourth shared hardware channel. The first shared hardware channel is configured as a PID0 channel and is used to perform PID calculations for the outer voltage loop. The second shared hardware channel is configured as a PID1 channel and is used to perform PID calculations for the inner current loop. The third shared hardware channel is configured as an IIR2 channel and is used to perform IIR filtering on the output voltage sampling signal. The fourth shared hardware channel is configured as an IIR3 channel and is used to perform IIR filtering on the output current sampling signal.

3. The system according to claim 1, characterized in that, The hardware IIR filter includes multiple independent hardware filtering channels, each of which is configured as a second-order IIR direct type I structure on the underlying circuit. The second-order IIR direct type I structure integrates a dedicated coefficient register, a delay state register array, and a hardware multiply-accumulate unit in hardware, which is used to perform parallel multiply-accumulate calculations independent of the central processing unit. The hardware filtering channels allocated to the output voltage and output current are each configured with a corresponding low-pass cutoff frequency parameter register.

4. The system according to claim 1, characterized in that, The three-phase phase-out hybrid modulation module is equipped with a phase out-of-bounds detection unit and a flag register; The phase boundary crossing detection unit is used to compare the calculated phase offset comparison value with the real-time value of the current comparison register, and to set the flag register when the phase crosses the current cycle boundary.

5. The system according to claim 1, characterized in that, The pulse width modulation and atomic update module includes a periodic interrupt mask register, a software shadow register array, and a six-channel hardware comparison register array. The periodic interrupt mask register is configured to be set when the start instruction of the back-to-back continuous write operation is received, so as to temporarily block the periodic overload interrupt signal of the pulse width modulation and atomic update module. The software shadow register array is connected via the on-chip low-level bus and is used to receive and temporarily store the six-channel pulse width modulation drive parameters calculated by the three-phase phase-shift hybrid modulation module back-to-back. The six-channel hardware comparator register array is connected to the software shadow register array and the switching transistor drive circuits of the three-phase interleaved parallel LLC resonant converter, respectively. Specifically, after the back-to-back continuous write operation is completed and the periodic interrupt mask register is reset, the six-channel hardware comparator array synchronously loads the six-channel pulse width modulation drive parameters in the software shadow register array into their respective hardware comparators at the next pulse width modulation cycle counting node.

6. The system according to claim 5, characterized in that, It also includes dedicated hardware debugging pins located in the pin area of ​​the single chip, as well as a state toggle control circuit; The state flip control circuit is connected between the pulse width modulation and atomic update module and the dedicated hardware debugging pin. It is configured to drive the dedicated hardware debugging pin to flip to a first level at the start of the back-to-back continuous write operation and to drive the dedicated hardware debugging pin to flip to a second level at the end of the back-to-back continuous write operation, so as to output a test pulse signal indicating the duration of the back-to-back continuous write operation through the dedicated hardware debugging pin.

7. A digital control processing method for a three-phase interleaved LLC resonant converter, implemented using the system described in any one of claims 1-6, characterized in that, include: The hardware acceleration processing module performs hardware filtering and floating-point proportional-integral-derivative calculations on the output voltage and output current acquisition signals of the three-phase misaligned LLC resonant converter within a preset number of peripheral clock cycles to generate a unified control quantity. The three-phase phase-shift hybrid modulation module calls the output of the hardware acceleration processing module to perform multi-phase phase-shift hybrid modulation calculation under a single control quantity, and generates multi-path pulse width modulation drive parameters. When updating the multi-channel pulse width modulation drive parameters, the temporary periodic interrupt is masked. After parameter verification and phase crossover safety detection are completed in the software shadow register, the multi-channel parameters are synchronously loaded into the hardware comparison register through the underlying bus using a back-to-back continuous writing method.

8. The method according to claim 7, characterized in that, The calculation of multiphase phase-shift hybrid modulation under a single control quantity generates multi-path pulse width modulation drive parameters, including: The switching cycle of the current control cycle is determined based on the unified control quantity. The three-phase phase offset is recalculated based on the switching cycle. The phase offset of the second phase relative to the first phase is calculated as follows: the clock cycle count value corresponding to one-third of the switching cycle is used as the time delay; the phase offset of the third phase relative to the first phase is calculated as follows: the clock cycle count value corresponding to two-thirds of the switching cycle is used as the time delay.

9. The method according to claim 8, characterized in that, The generated multi-path pulse width modulation driving parameters include: Based on the calculated switching period, three-phase phase offset, and preset dead time, the multi-path pulse width modulation drive parameters of the three-phase interleaved parallel LLC resonant converter are calculated in parallel. During the dynamic change of the switching cycle, the dead time of each drive signal remains independently locked or scales proportionally with the switching cycle.

10. The method according to claim 7, characterized in that, Parameter verification and phase crossover security detection are performed in the software shadow register, including: The calculated switching period and duty cycle are limited and verified to ensure that they are within the preset safe operating range of the resonant converter; Calculate the phase offset change between the current control cycle and the previous control cycle, determine whether the phase offset change exceeds the preset step size safety threshold, and whether the phase order of the three-phase drive signals remains consistent. If the step size safety threshold is exceeded or the phase sequence is abnormal, the phase offset of the current cycle will be limited to within the step size safety threshold to prevent the drive waveform from overlapping or phase crossing.

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