Hardware synchronous rectification control method and system based on clb and storage medium

Abstract

The application relates to the technical field of power electronic converter control, in particular to a hardware synchronous rectification control method and system based on a CLB and a storage medium, the method being used for an LLC resonant converter with a configurable logic block, comprising the following steps: detecting a secondary side current and generating a current comparison signal, inputting the current comparison signal and a primary side driving signal into the configurable logic block; using a state machine to identify a rising edge of the primary side driving signal, combining a obtained rising edge flag, the current comparison signal and current driving states of each synchronous rectification switch of a same secondary side bridge arm to generate a state machine output signal; performing priority processing on the state machine output signal according to a current state of the primary side driving signal, retaining one path and turning off the other path when a simultaneous conduction conflict occurs, obtaining and outputting a secondary side driving signal to control the conduction or turn-off of a corresponding secondary side synchronous rectification switch. The application can reduce the occupation of control resources and improve the reliability of the secondary side driving signal, thereby ensuring the stable synchronous rectification process.

Description

Technical Field

[0001] This application relates to the field of power electronic converter control technology, and in particular to a hardware synchronous rectification control method, system and storage medium based on CLB. Background Technology

[0002] In the process of DC-DC power conversion, DC-DC converters are used to convert input DC power into output DC power that meets the load requirements. LLC resonant converters, as a commonly used DC-DC conversion topology, convert input DC power into high-frequency AC power through the alternating conduction of primary-side switches. This AC power is then transmitted to the secondary side via a transformer, where it is rectified by a secondary-side rectifier circuit and converted back into DC output power. In low-voltage, high-current applications, using diodes for secondary-side rectification results in significant conduction losses. Therefore, existing LLC resonant converters typically use switches with lower on-resistance to replace rectifier diodes, and control the switching on or off of the switches based on the secondary-side current to achieve synchronous rectification.

[0003] Existing synchronous rectification control methods mainly include software real-time calculation, turn-on timing lookup table method, and hardware synchronous rectification method. The software real-time calculation method establishes a time-domain model of the LLC resonant converter, derives the relationship between the secondary current and the phase shift angle, and calculates the turn-on timing of the secondary synchronous rectifier switch in real time. The turn-on timing lookup table method uses simulation or testing to pre-determine the turn-on timing of each synchronous rectifier switch under different input voltages, output loads, and switching frequencies, and forms a turn-on timing table. During operation, the corresponding turn-on timing is looked up according to the current operating conditions. The hardware synchronous rectification method uses hardware circuitry to detect the drain-source voltage or secondary current of the synchronous rectifier switch, compares the detection results with preset conditions, and directly generates the drive signal for the synchronous rectifier switch based on the comparison result.

[0004] However, all three synchronous rectification control methods mentioned above have certain limitations in practical applications. For the software real-time calculation method, the turn-on time of the synchronous rectifier switch needs to be determined in real time within each switching cycle based on a pre-established relationship between the secondary current and the phase shift angle. Continuously performing this calculation consumes significant processor resources, and when the LLC resonant converter's switching frequency is high, the processor may struggle to complete the calculations in a timely manner. For the turn-on time lookup table method, extensive testing or simulation is required beforehand for different input voltages, output loads, and switching frequencies. The turn-on times corresponding to each condition are recorded in a table and stored in the processor. This not only consumes significant storage resources, but also means that the original turn-on time table may no longer be applicable after adjustments to hardware parameters such as the switch, transformer, or resonant parameters, requiring retesting or simulation. For hardware synchronous rectification, dedicated synchronous rectification control chips or LLC main control chips with integrated synchronous rectification control functions are typically used. Corresponding detection circuits are used to detect the drain-source voltage or secondary current of the synchronous rectification switch, increasing the number of detection circuits and control chips. Furthermore, some hardware synchronous rectification methods control the synchronous rectification switch only based on whether the detection result meets preset conduction conditions. Fluctuations or anomalies in the detection signal may cause the corresponding drive signal to be erroneously triggered. Therefore, while existing synchronous rectification control methods reduce control resource consumption, they struggle to ensure the reliability of synchronous rectification control, potentially affecting the stability of the synchronous rectification process. Summary of the Invention

[0005] This application provides a hardware synchronous rectification control method, system, and storage medium based on a CLB, which can reduce the control resource consumption of synchronous rectification control while improving the reliability of secondary-side drive signal generation and output, thereby ensuring the stable operation of the synchronous rectification process. This application provides the following technical solution: In a first aspect, this application provides a hardware synchronous rectification control method based on CLB, applied to an LLC resonant converter equipped with configurable logic blocks, the control method comprising: The primary-side drive signal of the LLC resonant converter is acquired, and the secondary-side current of the LLC resonant converter is detected; a current comparison signal is generated based on the detected secondary-side current, and the primary-side drive signal and the current comparison signal are input to the configurable logic block. The rising edge of each primary-side drive signal is identified by the state machine in the configurable logic block to obtain the corresponding rising edge flag; the corresponding state machine output signal is generated based on the rising edge flag, the current comparison signal, and the current drive state of each secondary-side synchronous rectifier switch in the same secondary-side bridge arm. Based on the current state of each primary side driving signal, the output priority processing is performed on the state machine output signal corresponding to the same secondary side bridge arm. When a simultaneous conduction conflict occurs, one path is kept in the conduction state and the conflicting path is turned off to obtain the secondary side driving signal. The secondary-side drive signal is output through the configurable logic block to control the corresponding secondary-side synchronous rectifier switch to be turned on or off.

[0006] In one specific implementation scheme, generating a corresponding state machine output signal based on the rising edge flag, the current comparison signal, and the current drive state of each secondary synchronous rectifier switch in the same secondary bridge arm includes: For each of the primary-side driving signals, determine the first secondary-side conduction condition and the second secondary-side conduction condition; The first secondary side conduction condition is: the rising edge flag of the primary side drive signal is in an active state, the current comparison signal indicates that the detected secondary side current is greater than the first preset current threshold, and the current drive state of the other secondary side synchronous rectifier switch in the same secondary side bridge arm is in an off state. The second secondary side conduction condition is as follows: the current comparison signal indicates that the detected secondary side current is greater than the second preset current threshold, the current driving state of the secondary side synchronous rectifier switch corresponding to the primary side drive signal in the same secondary side bridge arm is the on state, and the current driving state of the other secondary side synchronous rectifier switch in the same secondary side bridge arm is the off state. When the first secondary side conduction condition is met, the state machine output signal for the primary side drive signal is set to conduction state; when the second secondary side conduction condition is met, the state machine output signal for the primary side drive signal remains in conduction state; when neither the first secondary side conduction condition nor the second secondary side conduction condition is met, the state machine output signal for the primary side drive signal is set to de-conduction state.

[0007] In one specific implementation, the step of generating a corresponding state machine output signal based on the rising edge flag, the current comparison signal, and the current driving state of each secondary synchronous rectifier switch in the same secondary bridge arm further includes: For each of the primary-side drive signals, a corresponding state machine is configured; each of the primary-side drive signals is input into the corresponding state machine, and the current comparison signal is input into each of the state machines; Each state machine identifies the rising edge of the corresponding primary-side drive signal, obtains the corresponding rising edge flag, and generates a state machine output signal corresponding to the primary-side drive signal.

[0008] In one specific implementation, the step of identifying the rising edge of each primary-side driving signal through the state machine in the configurable logic block to obtain the corresponding rising edge flag includes: For each of the primary-side driving signals, the rising edge detection condition of the primary-side driving signal is that the primary-side driving signal is at a high level and its rising edge flag is not currently set. When the rising edge detection condition is met, a rising edge flag in a valid state is generated; when the rising edge detection condition is not met, a rising edge flag in an invalid state is generated.

[0009] In a specific implementation scheme, based on the current state of each primary-side driving signal, the output priority processing of the state machine output signal corresponding to the same secondary-side bridge arm is performed. When a simultaneous conduction conflict occurs, one path is kept in the conducting state and the conflicting path is turned off, thus obtaining the secondary-side driving signal, including: When any of the primary-side driving signals is low and the state machine output signal corresponding to the primary-side driving signal is in the on state, the state machine output signal is kept in the on state. If the output signal of the other state machine corresponding to the same secondary side bridge arm is simultaneously in the on state, then the output signal of the other state machine is adjusted to the off state to obtain the secondary side drive signal.

[0010] In one specific implementation scheme, the step of prioritizing the output signals of the state machine corresponding to the same secondary bridge arm based on the current state of each primary-side driving signal, and retaining one path as the on state and turning off the conflicting path when a simultaneous conduction conflict occurs, to obtain the secondary-side driving signal, further includes: For each secondary synchronous rectifier switch in the same secondary bridge arm, a corresponding lookup table is configured. The primary side drive signal used for the output priority processing and the output signals of each state machine corresponding to the same secondary side bridge arm are respectively input into each of the lookup tables; By using the lookup tables, the output signals of each state machine are logically combined according to the current state of the primary-side drive signal to generate a secondary-side drive signal corresponding to each secondary-side synchronous rectifier switch.

[0011] In one specific implementation, the step of outputting the secondary-side drive signal through the configurable logic block to control the corresponding secondary-side synchronous rectifier switch to be turned on or off includes: Configure a corresponding pulse width modulation output channel for each of the secondary-side synchronous rectifier switches; transmit the secondary-side drive signal output by the configurable logic block to the corresponding pulse width modulation output channel; When the secondary-side drive signal is in the ON state, a high level is output through the corresponding pulse width modulation output channel to control the secondary-side synchronous rectifier switch to be turned on; when the secondary-side drive signal is in the OFF state, a low level is output through the corresponding pulse width modulation output channel to control the secondary-side synchronous rectifier switch to be turned off.

[0012] Secondly, this application provides a hardware synchronous rectification control system based on CLB, which adopts the following technical solution: A CLB-based hardware synchronous rectification control system is provided for executing the CLB-based hardware synchronous rectification control method as described in the first aspect. The system includes an LLC resonant converter, a configurable logic block, and a pulse width modulation output channel. The LLC resonant converter is provided with a primary-side switching circuit and a secondary-side synchronous rectification switch. The output terminal of the primary-side switching circuit is connected to the input terminal of the configurable logic block, the output terminal of the configurable logic block is connected to the input terminal of each pulse width modulation output channel, and the output terminal of each pulse width modulation output channel is connected to the driving terminal of the corresponding secondary-side synchronous rectifier switch.

[0013] Thirdly, this application provides an electronic device, the device including a processor and a memory; the memory stores a program, the program being loaded and executed by the processor to implement a CLB-based hardware synchronous rectification control method as described in the first aspect.

[0014] Fourthly, this application provides a computer-readable storage medium storing a program that, when executed by a processor, is used to implement a CLB-based hardware synchronous rectification control method as described in the first aspect.

[0015] A current comparison signal is generated by detecting the secondary current of the LLC resonant converter, and this signal, along with the primary-side drive signal, is input to a configurable logic block. The state machine within the configurable logic block identifies the rising edge of each primary-side drive signal. Based on the obtained rising edge flag, the current comparison signal, and the current drive state of each secondary-side synchronous rectifier switch in the same secondary-side bridge arm, a state machine output signal is generated. The rising edge flag determines the timing of the state judgment, the current comparison signal provides the detection result of the secondary-side current, and the current drive state of each secondary-side synchronous rectifier switch reflects the current conduction status of the same secondary-side bridge arm, ensuring that the state machine output signal is simultaneously constrained by the drive timing, secondary-side current, and bridge arm state. Subsequently, based on the current state of each primary-side drive signal, the state machine output signal corresponding to the same secondary-side bridge arm is prioritized. In the event of a simultaneous conduction conflict, one output signal is kept in the conduction state while the conflicting signal is turned off, preventing conflicting state machine output signals from directly forming the secondary-side drive signal. Finally, the secondary-side drive signal is output through the configurable logic block to control the corresponding secondary-side synchronous rectifier switch to turn on or off. Therefore, the state judgment and conflict handling in the synchronous rectification process are implemented in a configurable logic block, and the reasonable output of the secondary drive signal is ensured through multiple state constraints and conflict handling. This can reduce the control resource occupation of synchronous rectification control, improve the reliability of synchronous rectification control, and ensure the stable operation of the synchronous rectification process.

[0016] The above description is only an overview of the technical solution of this application. In order to better understand the technical means of this application and to implement it in accordance with the contents of the specification, the preferred embodiments of this application are described in detail below with reference to the accompanying drawings. Attached Figure Description

[0017] Figure 1 This is a schematic diagram of the topology of the LLC resonant converter in the embodiments of this application.

[0018] Figure 2 This is a flowchart illustrating the hardware synchronous rectification control method based on CLB in the embodiments of this application.

[0019] Figure 3 This is a schematic diagram of the internal logic unit processing of the configurable logic block in the embodiments of this application.

[0020] Figure 4 This is a schematic diagram of the state machine output logic relationship in the embodiments of this application.

[0021] Figure 5 This is a waveform diagram of the secondary side drive being turned off in advance in an embodiment of this application.

[0022] Figure 6 This is a schematic diagram of the lookup table output logic in the embodiments of this application.

[0023] Figure 7 This is a waveform diagram of synchronous rectification control in an embodiment of this application.

[0024] Figure 8 This is a schematic diagram of the overall process of the hardware synchronous rectification control method based on CLB in the embodiments of this application.

[0025] Figure 9 This is a block diagram of an electronic device based on CLB hardware synchronous rectification control in an embodiment of this application. Detailed Implementation

[0026] The specific embodiments of this application will be described in further detail below with reference to the accompanying drawings and examples. The following examples are used to illustrate this application, but are not intended to limit the scope of this application.

[0027] Optionally, this application uses the CLB-based hardware synchronous rectification control method provided in various embodiments as an example for description in electronic devices. The electronic device is a terminal or a server. The terminal can be a computer, tablet computer, etc. This embodiment does not limit the type of electronic device.

[0028] To facilitate understanding of the technical solutions of the embodiments of this application, the abbreviations and related technical terms involved in this application will be explained before introducing the specific control process.

[0029] ①SR (Synchronous Rectification): refers to the process of controlling the secondary-side synchronous rectifier switch to conduct within the corresponding secondary-side current conduction range, thereby replacing the ordinary rectifier diode to complete the rectification and reducing the conduction loss during the secondary-side rectification process.

[0030] ②CLB (Configurable Logic Block): This is a configurable logic unit internal to the C2000 series digital signal processor, such as the configurable logic block inside the F280039 chip. It integrates lookup tables, flip-flops, counters, finite state machines, and on-chip peripheral interconnect resources. After logic configuration, each logic unit can form a custom digital logic according to the pre-configured connection relationship. Signal processing is completed in parallel by hardware without real-time CPU intervention, and it can be directly connected to on-chip peripherals such as ePWM, eCAP, and GPIO. Configurable logic blocks are suitable for implementing nanosecond-level fault latching, pulse shaping, phase synchronization, and fast protection logic. They can reduce the real-time computing pressure on the CPU and replace external logic chips used to implement simple digital logic, thereby improving the high-frequency control reliability of the power converter. In the embodiments of this application, the configurable logic block is used to perform logic processing on the primary-side drive signal and the current comparison signal to generate a secondary-side drive signal for controlling the secondary-side synchronous rectifier switch.

[0031] ③ EPWM (Enhanced Pulse Width Modulation) and AQ (ActionQualifier): EPWM is an on-chip peripheral used to output switch drive signals, and AQ is an action-qualifying submodule within EPWM used to control the output level. By configuring the registers corresponding to AQ, EPWMxA and EPWMxB can be set high, set low, toggle, or remain unchanged based on counter events. In this embodiment, the secondary-side drive signal generated by the configurable logic block can be output through the corresponding EPWM output channel to control the secondary-side synchronous rectifier switch to turn on or off.

[0032] ④ZVS (Zero Voltage Switching) and ZCS (Zero Current Switching): ZVS refers to controlling the switching device to conduct when the voltage across the switching device is close to zero, i.e., zero voltage turn-on; ZCS refers to controlling the switching device to turn off when the current flowing through the switching device is close to zero, i.e., zero current turn-off.

[0033] This application provides a CLB-based hardware synchronous rectification control method applied to an LLC resonant converter equipped with a configurable logic block. The configurable logic block refers to a control chip containing this block on the control side of the LLC resonant converter. The configurable logic block receives signals related to the operating state of the LLC resonant converter and generates secondary-side drive signals to control the secondary-side synchronous rectifier switch through internal hardware logic. The configurable logic block does not participate in energy transfer in the main power circuit of the LLC resonant converter; instead, it serves as the control part of the LLC resonant converter, processing the primary-side drive signal, the current comparison signal obtained based on the secondary-side current detection signal, and the current drive state of the secondary-side synchronous rectifier switch.

[0034] Reference Figure 1This is a topology diagram of an LLC resonant converter provided in one embodiment of this application. The LLC resonant converter includes a primary-side switching circuit, a resonant network, a transformer, and a secondary-side rectifier circuit. The primary-side switching circuit includes multiple primary-side switching devices, each of which is turned on or off under the control of a corresponding primary-side drive signal to convert the input DC current into high-frequency AC current and input it to the resonant network. The resonant network is connected to the primary winding of the transformer, coupling the primary-side energy to the secondary side through the transformer. The secondary-side rectifier circuit includes multiple secondary-side synchronous rectifier switches, each of which is turned on or off according to a corresponding secondary-side drive signal to synchronously rectify the current output from the secondary side of the transformer. A secondary-side current detection point is provided on the output side of the secondary-side rectifier circuit. The secondary-side current of the LLC resonant converter is detected through the secondary-side current detection point to obtain a secondary-side current detection signal, and a current comparison signal for the input configurable logic block is obtained based on the secondary-side current detection signal.

[0035] Figure 1 In the diagram, g1, g2, g3, and g4 represent primary-side drive signals, used to control four primary-side switching devices in the primary-side switching circuit. Specifically, primary-side drive signals g1 and g2 control two primary-side switching devices in the same primary-side bridge arm, and primary-side drive signals g4 and g3 control two primary-side switching devices in the other primary-side bridge arm. g5, g6, g7, and g8 represent secondary-side drive signals, used to control four secondary-side synchronous rectifier switches in the secondary-side rectifier circuit. Specifically, secondary-side drive signals g5 and g6 control two secondary-side synchronous rectifier switches in the same secondary-side bridge arm, and secondary-side drive signals g8 and g7 control two secondary-side synchronous rectifier switches in the other secondary-side bridge arm. In terms of control correspondence, the primary side drive signal g1 corresponds to the secondary side drive signal g5, the primary side drive signal g2 corresponds to the secondary side drive signal g6, the primary side drive signal g4 corresponds to the secondary side drive signal g8, and the primary side drive signal g3 corresponds to the secondary side drive signal g7.

[0036] To facilitate the explanation of the control process of this application, the following description only uses primary-side drive signals g1 and g2 and secondary-side drive signals g5 and g6 as examples. The processing methods for other primary-side drive signals and their corresponding secondary-side drive signals are the same. Therefore, for primary-side drive signal g1, the secondary-side synchronous rectifier switch corresponding to primary-side drive signal g1 is controlled by secondary-side drive signal g5, and the other secondary-side synchronous rectifier switch in the same secondary-side bridge arm is controlled by secondary-side drive signal g6; for primary-side drive signal g2, the secondary-side synchronous rectifier switch corresponding to primary-side drive signal g2 is controlled by secondary-side drive signal g6, and the other secondary-side synchronous rectifier switch in the same secondary-side bridge arm is controlled by secondary-side drive signal g5.

[0037] In this example, the configurable logic block receives primary-side drive signals g1 and g2, as well as a current comparison signal obtained based on the secondary-side current detection signal. Based on the primary-side drive signals g1 and g2, the current comparison signal, and the current drive states of the two secondary-side synchronous rectifier switches in the same secondary-side bridge arm, it generates corresponding state machine output signals and performs output priority processing on the state machine output signals to obtain secondary-side drive signals g5 and g6. Therefore, the following hardware synchronous rectification control method can be executed in the aforementioned LLC resonant converter.

[0038] Reference Figure 2 This is a flowchart illustrating a CLB-based hardware synchronous rectification control method according to an embodiment of this application. The method includes at least the following steps: Step S100: Obtain the primary-side drive signal of the LLC resonant converter and detect the secondary-side current of the LLC resonant converter; generate a current comparison signal based on the detected secondary-side current, and input the primary-side drive signal and the current comparison signal to the configurable logic block.

[0039] In step S100, an input signal relationship is first established for the configurable logic block, enabling the configurable logic block to simultaneously receive multiple primary-side drive signals and one current comparison signal. The primary-side drive signal indicates the drive state of the corresponding primary-side switching device, and the current comparison signal indicates the comparison result of the secondary-side current.

[0040] Specifically, the primary-side drive signal is a signal used to control the primary-side switching device to turn on or off. Figure 1 The primary-side drive signals include g1, g2, g3, and g4, and the level state of each primary-side drive signal reflects the current drive state of the corresponding primary-side switching device. Taking primary-side drive signals g1 and g2 as examples, the primary-side drive signals g1 and g2 are configured as input signals of configurable logic blocks by controlling the signal transmission path inside the control chip.

[0041] Meanwhile, for the detection of secondary current, in Figure 1 The secondary current detection position is marked to detect the secondary current of the LLC resonant converter and obtain the secondary current detection signal. In one specific embodiment, a high-frequency sampling chip is used to sample the secondary current to obtain an analog signal corresponding to the change in secondary current, and this analog signal is transmitted to the CMPSS (Comparator Subsystem) as the secondary current detection signal.

[0042] After obtaining the secondary current detection signal, an analog input channel is configured in CMPSS to receive the secondary current detection signal, and the secondary current detection signal is compared with a preset threshold to obtain a current comparison signal. The current comparison signal is used to characterize whether the secondary current meets the corresponding current comparison condition.

[0043] Furthermore, a filtering window is configured in CMPSS to filter the continuously generated comparison results, causing CMPSS to output a current comparison signal based on the filtered comparison results. After outputting the current comparison signal, CMPSS transmits the signal to the configurable logic block via CLB-XBar. CLB-XBar (Configurable Logic Block Crossbar) is a signal routing unit located inside the control chip, used to select the signal to be input to the configurable logic block and establish the connection between the signal and the input terminal of the configurable logic block. In this embodiment, the current comparison signal output by CMPSS is selected via CLB-XBar and transmitted to the configurable logic block.

[0044] After completing the above signal configuration, taking the primary-side drive signals g1 and g2 and the secondary-side drive signals g5 and g6 as examples, the three input signals of the configurable logic block are the current comparison signal, the primary-side drive signal g1, and the primary-side drive signal g2, respectively. Therefore, the configurable logic block can simultaneously receive the primary-side drive signal g1, the primary-side drive signal g2, and the current comparison signal obtained based on the secondary-side current detection signal. The same input configuration method can be used for the primary-side drive signals g4 and g3 and the secondary-side drive signals g8 and g7.

[0045] Step S200: Identify the rising edge of each primary-side drive signal through the state machine in the configurable logic block to obtain the corresponding rising edge flag; generate the corresponding state machine output signal based on the rising edge flag, the current comparison signal, and the current drive state of each secondary-side synchronous rectifier switch in the same secondary-side bridge arm.

[0046] In step S200, a corresponding state machine is set up for different primary-side drive signals, so that each state machine processes the corresponding primary-side drive signal, current comparison signal, and the current drive state of each secondary-side synchronous rectifier switch in the same secondary-side bridge arm. The state machine records the rising edge flag of the primary-side drive signal and the current drive state of the corresponding secondary-side synchronous rectifier switch through internal state bits, and generates a state machine output signal of conduction state or de-conduction state according to the combination result of each input signal and internal state bits.

[0047] In implementation, if the real-time level of the primary-side drive signal is directly used to determine the secondary-side conduction, the conduction state of the secondary-side synchronous rectifier switch is mainly affected by the secondary-side current state while the primary-side drive signal is continuously high. When the secondary-side current oscillates, the current comparison result may change repeatedly, causing the secondary-side synchronous rectifier switch to repeatedly turn on and off. If only the instantaneous pulse generated by the rising edge of the primary-side drive signal is used for judgment, the effective time corresponding to the rising edge is short. When the zero-crossing moment of the secondary-side current changing from negative to positive lags behind the rising edge of the primary-side drive signal, the effective time corresponding to the rising edge may not coincide with the time when the secondary-side current condition is met, making it difficult to complete the corresponding conduction judgment of the secondary-side synchronous rectifier switch.

[0048] Therefore, in this embodiment, the rising edge of the primary-side drive signal is identified by the state machine in the configurable logic block, and the identified rising edge flag is combined with the current comparison signal and the current drive state of the secondary-side synchronous rectifier switch, so that the timing of the change of the primary-side drive signal can participate in the conduction judgment of the secondary-side synchronous rectifier switch, while the internal state of the state machine is used to maintain the already formed conduction state.

[0049] Specifically, for each primary-side drive signal, a corresponding state machine is configured; each primary-side drive signal is input into the corresponding state machine, and a current comparison signal is input into each state machine; the rising edge of the corresponding primary-side drive signal is identified by each state machine, the corresponding rising edge flag is obtained, and a state machine output signal corresponding to the primary-side drive signal is generated.

[0050] Taking primary-side drive signals g1 and g2 and secondary-side drive signals g5 and g6 as examples, a first state machine FSM0 and a second state machine FSM1 are configured in the configurable logic block. The first state machine FSM0 generates a state machine output signal controlling the secondary-side drive signal g5 based on the primary-side drive signal g1. The external input signal EXT_IN1 of the first state machine FSM0 receives the primary-side drive signal g1, and the external input signal EXT_IN0 receives a current comparison signal. The second state machine FSM1 generates a state machine output signal controlling the secondary-side drive signal g6 based on the primary-side drive signal g2. The external input signal EXT_IN1 of the second state machine FSM1 also receives the primary-side drive signal g2, and the external input signal EXT_IN0 also receives a current comparison signal.

[0051] In addition, each state machine includes a first state bit S1 and a second state bit S0. The first state bit S1 stores the rising edge flag of the corresponding primary-side drive signal, and the second state bit S0 characterizes the current drive state of the secondary-side synchronous rectifier switch corresponding to the primary-side drive signal. The state machine's output terminal Out outputs the current state machine output signal, which is determined by the second state bit S0 and used to control the corresponding secondary-side synchronous rectifier switch. Each state machine also includes a next first state bit Next S1 and a next second state bit Next S0. The next first state bit Next S1 represents the value of the first state bit S1 in the next cycle, and the next second state bit Next S0 represents the value of the second state bit S0 in the next cycle. At the arrival of the clock edge, S1 and S0 are updated using Next S1 and Next S0, respectively. The state transition condition is determined based on the primary-side drive signal, the current comparison signal, and the drive state of the other secondary-side synchronous rectifier switch in the same secondary-side bridge arm.

[0052] Reference Figure 3 This is a schematic diagram of the internal logic unit processing of a configurable logic block provided in one embodiment of this application. Figure 3 The diagram illustrates the first state machine FSM0, the second state machine FSM1, and the connections between each state machine and its input signals, state bits, and output signals. Current comparison signals are input to both state machines FSM0 and FSM1. Primary-side drive signal g1 is input to FSM0, and primary-side drive signal g2 is input to FSM1. The next first state bit Next S1 and the next second state bit Next S0 generated by each state machine are fed back to their corresponding first state bit S1 and second state bit S0, enabling the state machine to update its internal state based on the current input signal and the current state bit, and generate the corresponding state machine output signal. Thus, the same current comparison signal can be combined with primary-side drive signals g1 and g2, respectively, so that state machines FSM0 and FSM1 form state judgment results corresponding to secondary-side drive signals g5 and g6, respectively. Figure 3 The connection between the output terminals of each state machine and the output logic unit is also shown, and the state machine output signals generated by each state machine are transmitted to the output logic unit respectively.

[0053] The following method is used to identify the rising edge of the primary-side drive signal: For each primary-side drive signal, the rising edge detection condition is that the primary-side drive signal is at a high level and the corresponding rising edge flag is not currently set; when the rising edge detection condition is met, a rising edge flag in a valid state is generated; when the rising edge detection condition is not met, a rising edge flag in an invalid state is generated.

[0054] Specifically, when the primary-side drive signal is high and the first state bit S1 is currently 0, the next first state bit Next S1 outputs 1, making the rising edge flag valid. When the primary-side drive signal is not high, or the first state bit S1 is already 1, the next first state bit Next S1 outputs 0, making the rising edge flag invalid. By combining the current level of the primary-side drive signal with the current state of the first state bit S1, the state of the primary-side drive signal remaining high can be distinguished from the newly occurring rising edge change, making the rising edge flag correspond to the timing of the primary-side drive signal changing from low to high.

[0055] After obtaining the rising edge flag, the corresponding state machine output signal is generated based on the rising edge flag, the current comparison signal, and the current driving state of each secondary synchronous rectifier switch in the same secondary bridge arm. Specifically, it includes: determining the first secondary conduction condition and the second secondary conduction condition for each primary drive signal.

[0056] The first secondary side conduction condition is: the rising edge of the primary side drive signal is in an active state, the current comparison signal indicates that the detected secondary side current is greater than the first preset current threshold, and the current drive state of the other secondary side synchronous rectifier switch in the same secondary side bridge arm is in an off state.

[0057] When the first secondary-side conduction condition is met, the state machine output signal for the current primary-side drive signal is set to the conduction state. The first secondary-side conduction condition is used to determine whether the corresponding secondary-side synchronous rectifier switch transitions from the off state to the conduction state. By simultaneously combining the rising edge of the primary-side drive signal, the comparison result of the secondary-side current, and the current drive state of another secondary-side synchronous rectifier switch in the same secondary-side bridge arm, the start of conduction of the corresponding state machine output signal is constrained by the primary-side drive timing, the secondary-side current state, and the current drive state of the bridge arm, avoiding the formation of conduction judgment solely based on the instantaneous change of the secondary-side current.

[0058] The second secondary side conduction condition is as follows: the current comparison signal indicates that the detected secondary side current is greater than the second preset current threshold, the current driving state of the secondary side synchronous rectifier switch corresponding to the primary side drive signal in the same secondary side bridge arm is the on state, and the current driving state of the other secondary side synchronous rectifier switch in the same secondary side bridge arm is the off state.

[0059] When the second secondary-side conduction condition is met, the state machine output signal for the current primary-side drive signal remains in the conduction state. The second secondary-side conduction condition is used to determine whether to continue conducting after the corresponding secondary-side synchronous rectifier switch has already been turned on. At this time, even if the rising edge flag of the primary-side drive signal is no longer valid, as long as the secondary-side current still meets the corresponding current condition, and the other secondary-side synchronous rectifier switch in the same secondary-side bridge arm remains off, the state machine output signal remains in the conduction state. Therefore, the continuous conduction of the corresponding secondary-side synchronous rectifier switch no longer depends on the rising edge flag remaining valid, but can be maintained based on the secondary-side current state and the current drive state.

[0060] When neither the first nor the second secondary-side conduction condition is met, the state machine output signal for the current primary-side drive signal is set to the off state. Thus, the first secondary-side conduction condition is used to determine when the corresponding secondary-side synchronous rectifier switch begins to conduct, the second secondary-side conduction condition is used to maintain the established conduction state, and the state machine output signal is restored to the off state when the corresponding conduction condition is no longer met. This forms the process of the state machine output signal changing from the off state to the on state, maintaining the on state, and returning to the off state.

[0061] It should be noted that in both the first and second secondary-side conduction conditions, the other secondary-side synchronous rectifier switch in the same secondary-side bridge arm must remain in the off state. By using the current drive state of the other secondary-side synchronous rectifier switch in the same secondary-side bridge arm as the conduction constraint, the conduction judgment of the current secondary-side synchronous rectifier switch is simultaneously limited by the current state of the other secondary-side synchronous rectifier switch, thus avoiding the independent conduction judgments of the two secondary-side synchronous rectifier switches.

[0062] Taking the primary-side drive signal g1 as an example, the secondary-side synchronous rectifier switch controlled by the secondary-side drive signal g5 is the same as the secondary-side synchronous rectifier switch controlled by the primary-side drive signal g1, and the secondary-side synchronous rectifier switch controlled by the secondary-side drive signal g6 is another secondary-side synchronous rectifier switch in the same secondary-side bridge arm. Therefore, the first state machine FSM0 generates the state machine output signal corresponding to the primary-side drive signal g1 based on the rising edge flag of the primary-side drive signal g1, the current comparison signal, and the current drive states of the two secondary-side synchronous rectifier switches controlled by the secondary-side drive signals g5 and g6.

[0063] For the primary-side drive signal g2, the secondary-side synchronous rectifier switch controlled by the secondary-side drive signal g6 is the same as the secondary-side synchronous rectifier switch corresponding to the primary-side drive signal g2, and the secondary-side synchronous rectifier switch controlled by the secondary-side drive signal g5 is another secondary-side synchronous rectifier switch in the same secondary-side bridge arm. The second state machine FSM1 generates the state machine output signal corresponding to the primary-side drive signal g2 in the same way.

[0064] In one specific implementation, the first preset current threshold can be set to 0.2A, and the second preset current threshold can be set to 0A. The first preset current threshold is greater than the second preset current threshold, so that a higher current condition is required when the secondary-side synchronous rectifier switch is first turned on, while a lower current condition is required to maintain conduction after the secondary-side synchronous rectifier switch has been turned on. The first preset current threshold is used to determine whether the corresponding secondary-side synchronous rectifier switch meets the current condition required to start conducting, and the second preset current threshold is used to determine whether the already turned-on secondary-side synchronous rectifier switch meets the current condition required to continue conducting. In this embodiment, the first and second preset current thresholds are used to determine the conditions for the current comparison signal to enter and exit the valid state, respectively. When the secondary-side current reaches the first preset current threshold, the current comparison signal enters the valid state; after the current comparison signal enters the valid state, it remains valid until the secondary-side current drops to the second preset current threshold. Thus, the same current comparison signal can be used to determine the start-on condition and the conduction-maintaining condition of the secondary-side synchronous rectifier switch, respectively.

[0065] Reference Figure 4 This is a schematic diagram of the state machine output logic relationship provided in one embodiment of this application. Figure 4 Taking the first state machine FSM0 as an example, the output results corresponding to the output terminal Out, the next second state bit Next S0, and the next first state bit Next S1 are shown when the external input signal EXT_IN1, the external input signal EXT_IN0, the first state bit S1, and the second state bit S0 are in different state combinations.

[0066] Specifically, when the secondary current corresponding to the current comparison signal does not meet the corresponding conduction condition, the state machine output signal remains off. When the primary drive signal g1 is high and the first state bit S1 is currently 0, the next first state bit Next S1 outputs 1, making the rising edge flag valid. When the rising edge flag is valid, the secondary current meets the current condition corresponding to the first preset current threshold, and the synchronous rectifier switch of the other secondary side in the same secondary bridge arm is off, the output terminal Out and the next second state bit Next S0 form a corresponding conduction output, making the state machine output signal conduct and updating the second state bit S0 accordingly.

[0067] After the state machine output signal enters the on state, the second state bit S0 indicates that the corresponding secondary-side synchronous rectifier switch is currently in the on state. When the secondary-side current continues to meet the current condition corresponding to the second preset current threshold, and the other secondary-side synchronous rectifier switch in the same secondary-side bridge arm remains off, even if the first state bit S1 has returned to the unset state, the output terminal Out and the next second state bit Next S0 still maintain the corresponding on output, so that the state machine output signal continues to maintain the on state. When the corresponding secondary-side on condition is no longer met, the output terminal Out and the next second state bit Next S0 return to the off output, so that the state machine output signal switches from the on state to the off state.

[0068] It should be noted that the rising edge flag is used to record the change of the primary-side drive signal from low to high. After detecting the rising edge of the primary-side drive signal, the state machine can hold the rising edge flag in the valid state until the secondary-side synchronous rectifier switch corresponding to the primary-side drive signal enters the conducting state, and then restore the rising edge flag to the invalid state. Figure 4 The output logic of Next S1 is used to set, hold, and reset the rising edge flag. Holding the rising edge flag while the primary-side drive signal is continuously high does not mean that repeating the continuous high level is identified as a new rising edge.

[0069] thus, Figure 4 The different input and state combinations reflect the state change process of recognizing the rising edge of the primary-side drive signal, starting to conduct, maintaining conduction, and resuming off, so that the timing information of the primary-side drive signal, the secondary-side current comparison result, and the current drive state of the secondary-side synchronous rectifier switch jointly participate in the generation of the state machine output signal.

[0070] In one specific implementation, it can be based on Figure 4The output results corresponding to each input signal and state bit combination shown are used to encode and configure the state machine output logic. The output terminal Out uses the same output logic as the next second state bit Next S0. The output results corresponding to numbers 0 to 15 are 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 1, respectively. Encoding with the least significant bit corresponding to number 0 and the most significant bit corresponding to number 15 yields a 16-bit binary logic value 1110000011100000, with a corresponding hexadecimal configuration value of 0xE0E0. The output results corresponding to the next first state bit Next S1 are 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, and are encoded in the same way to obtain a 16-bit binary logic value 0101010100000000, with a corresponding hexadecimal configuration value of 0x5500. Therefore, the output logic of the state machine's output terminal Out and the next second state bit Next S0 can be configured as 0xE0E0, and the output logic of the next first state bit Next S1 can be configured as 0x5500 to achieve... Figure 4 The state machine judgment relationship is shown.

[0071] Step S300: Based on the current state of each primary side driving signal, perform output priority processing on the state machine output signal corresponding to the same secondary side bridge arm. When a simultaneous conduction conflict occurs, one path is kept in the conduction state and the conflicting path is turned off to obtain the secondary side driving signal.

[0072] In step S300, step S200 generates corresponding state machine output signals for different secondary-side synchronous rectifier switches in the same secondary-side bridge arm. Since a secondary-side synchronous rectifier switch that has already entered the conducting state can remain conducting when the second secondary-side conduction condition is met, during the conduction judgment process of different state machines, it is possible that two state machine output signals corresponding to the same secondary-side bridge arm may be in the conducting state simultaneously. If the two state machine output signals that are simultaneously in the conducting state are directly output as secondary-side drive signals, it may cause the two secondary-side synchronous rectifier switches in the same secondary-side bridge arm to conduct simultaneously. Therefore, further output priority processing of the state machine output signals is required.

[0073] To address the aforementioned simultaneous conduction conflict, one approach is to adjust both secondary-side drive signals to the off state when both state machine output signals corresponding to the same secondary-side bridge arm are detected to be in the on state. While this method avoids the simultaneous conduction of two secondary-side synchronous rectifier switches in the same secondary-side bridge arm, when both drives are simultaneously turned off, the secondary-side synchronous rectifier switch that originally met the conduction conditions will also be turned off. If the secondary-side current is still relatively high at this time, it will cause the corresponding secondary-side synchronous rectifier switch to prematurely end its conduction process relative to the secondary-side current change, thereby increasing turn-off losses and the voltage stress on the drain and source of the switching transistor.

[0074] Reference Figure 5 This is a waveform diagram of the secondary side drive being turned off in advance according to an embodiment of this application. Figure 5 In the diagram, the yellow waveform corresponds to channel 1, which is the current comparison signal used to reflect whether the secondary current meets the corresponding current comparison conditions; the green waveform corresponds to channel 2, which is the secondary drive signal used to reflect the on or off state of the corresponding secondary synchronous rectifier switch; the magenta waveform corresponds to channel 3, which is the primary drive signal, where a high level corresponds to the primary upper transistor being on, a low level corresponds to the primary lower transistor being on, and the intermediate state corresponds to the wave-locked interval; the cyan waveform corresponds to channel 4, which is the high-frequency sampling output signal of the current detection point used to reflect the actual change process of the secondary current.

[0075] like Figure 5 As indicated by the center marker, the secondary drive signal corresponding to the green waveform has switched from the on state to the off state. However, the secondary current detection result corresponding to the cyan waveform at this time shows that the secondary current is still in the current conduction process and has not decreased to a state suitable for ending conduction. In other words, the turn-off of the secondary drive signal here is not caused by the secondary current reaching the corresponding turn-off condition, but rather by a conflict arising from the simultaneous conduction of the two state machine outputs corresponding to the same secondary bridge arm. The conflicting outputs are turned off simultaneously, causing one secondary drive that should have continued to conduct to be turned off prematurely.

[0076] Therefore, when a simultaneous conduction conflict occurs, if only both secondary-side drivers are simultaneously adjusted to the off state, although this can prevent both secondary-side synchronous rectifier switches from conducting simultaneously, it will cause one of the secondary-side synchronous rectifier switches that should have remained on to prematurely exit the conducting state. Based on this, this embodiment determines the state machine output signal that needs to be retained when a conflict occurs by combining the current state of the primary-side drive signal. While shutting down the conflicting switch, it retains the switch that should currently continue to conduct.

[0077] Specifically, when any primary-side drive signal is low and the corresponding state machine output signal is on, the state machine output signal remains on. If the output signal of another state machine corresponding to the same secondary-side bridge arm is simultaneously on, the other state machine output signal is turned off to obtain the secondary-side drive signal. In other words, when a primary-side drive signal is low and the corresponding state machine output signal is already on, that state machine output signal has a corresponding output priority and remains on. If, at this time, the output signal of another state machine corresponding to the same secondary-side bridge arm is also on, a simultaneous on / off conflict occurs between the two state machine outputs. In this case, only the other state machine output signal is turned off, without simultaneously turning off both state machine outputs.

[0078] Taking the primary-side drive signal g1 and the secondary-side drive signals g5 and g6 as examples, the first state machine FSM0 generates the state machine output signal corresponding to the primary-side drive signal g1, and the second state machine FSM1 generates the state machine output signal corresponding to the synchronous rectifier switch of the other secondary side in the same secondary-side bridge arm. When the primary-side drive signal g1 is low, the state machine output signal corresponding to the first state machine FSM0 is in the on state, and the state machine output signal corresponding to the second state machine FSM1 is also in the on state at the same time. The state machine output signal corresponding to the first state machine FSM0 is kept in the on state, and the state machine output signal corresponding to the second state machine FSM1 is adjusted to the off state, thereby eliminating the simultaneous on-state conflict between the two state machine outputs.

[0079] Through the above output priority processing, when there is no simultaneous conduction conflict, the output signals of each state machine can participate in the generation of the secondary-side drive signal according to the corresponding state judgment result. When a simultaneous conduction conflict occurs, the current state of the primary-side drive signal is further used to determine the conduction branch that needs to be retained, and only the conflicting branch is shut down. Therefore, it is not necessary to eliminate the conflict by simultaneously shutting down both drives. While avoiding the simultaneous conduction of two secondary-side synchronous rectifier switches in the same secondary-side bridge arm, it can reduce the situation where the secondary-side synchronous rectifier switch that should still be conducted is turned off prematurely.

[0080] In one specific implementation, the above-mentioned output priority processing can be implemented using a look-up table in a configurable logic block. A look-up table (LUT) is a logic unit in a configurable logic block that can logically combine multiple input signals to form a corresponding output result based on a pre-configured correspondence between input state combinations and output states. In this embodiment, Figure 3 The output logic units connected to the output terminals of each state machine can be implemented using lookup tables.

[0081] Specifically, for each secondary-side synchronous rectifier switch in the same secondary-side bridge arm, a corresponding lookup table is configured. The primary-side drive signal used for output priority processing and the output signals of each state machine corresponding to the same secondary-side bridge arm are input into each lookup table. Through each lookup table, the output signals of each state machine are logically combined according to the current state of the primary-side drive signal to generate the secondary-side drive signal corresponding to each secondary-side synchronous rectifier switch. Each secondary-side synchronous rectifier switch in the same secondary-side bridge arm corresponds to a specific lookup table. Each lookup table receives the primary-side drive signal used for output priority processing and the output signals of each state machine corresponding to the same secondary-side bridge arm, and generates the corresponding secondary-side drive signal for the secondary-side synchronous rectifier switch according to the pre-configured input and output logic relationship. Therefore, the current state of the primary-side drive signal and the output signals of each state machine can be directly logically combined within the configurable logic block.

[0082] Taking the primary-side drive signal g1 and the first state machine FSM0 and the second state machine FSM1 as an example, the primary-side drive signal g1, the state machine output signal of the second state machine FSM1, and the state machine output signal of the first state machine FSM0 can be used as the three inputs of the lookup table. Specifically, the primary-side drive signal g1 provides the current state of the primary side required for output priority determination; the state machine output signal of the first state machine FSM0 corresponds to the secondary-side synchronous rectifier switch corresponding to the primary-side drive signal g1; and the state machine output signal of the second state machine FSM1 corresponds to the other secondary-side synchronous rectifier switch in the same secondary-side bridge arm.

[0083] Reference Figure 6 This is a schematic diagram of the lookup table output logic provided in one embodiment of this application. Figure 6 Taking the secondary bridge arm corresponding to the primary side drive signal g1 as an example, the calculation output results of the two secondary side drives are shown when the primary side drive signal and the two state machine output signals are in different combination states.

[0084] Figure 6 In this diagram, input IN2 is the primary-side drive signal g1; input IN1 is the state machine output signal generated by the second state machine FSM1, used to characterize the state machine output state of the other secondary-side synchronous rectifier switch in the same secondary-side bridge arm; input IN0 is the state machine output signal generated by the first state machine FSM0, used to characterize the state machine output state of the secondary-side synchronous rectifier switch corresponding to the primary-side drive signal g1. "Calculated output of the other secondary side in the same bridge arm" indicates the secondary-side drive output result of the other secondary-side synchronous rectifier switch in the same secondary-side bridge arm after logical combination; "Calculated output of the corresponding secondary side" indicates the secondary-side drive output result of the secondary-side synchronous rectifier switch corresponding to the primary-side drive signal g1 after logical combination.

[0085] exist Figure 6In the diagram, when IN2, IN1, and IN0 are 0, 1, and 1 respectively, it indicates that the primary-side drive signal g1 is at a low level. Simultaneously, the output signals of the state machines corresponding to the first state machine FSM0 and the second state machine FSM1 are both in the on state, meaning that the two state machine outputs corresponding to the same secondary-side bridge arm are simultaneously on and conflict. After output priority processing, the calculated output of the other secondary side in the same bridge arm is 0, and the calculated output of the corresponding secondary side is 1. Therefore, the secondary-side drive corresponding to the primary-side drive signal g1 remains on, while the other secondary-side drive in the same secondary-side bridge arm that conflicts with it is adjusted to the off state.

[0086] Accordingly, Figure 6 The other input combinations correspond to the output results when the primary-side drive signal and the two state machine output signals are in different states. By pre-determining the output states of the two secondary-side drives corresponding to different input combinations, the lookup table can logically combine the output results of the two state machines according to the current state of the primary-side drive signal. When the outputs of the two state machines conflict, one path is retained and the other is closed according to the preset output priority, instead of directly closing both secondary-side drives at the same time.

[0087] In one specific implementation, two lookup tables can be configured to generate secondary-side drive signals corresponding to the two secondary-side synchronous rectifier switches in the same secondary-side bridge arm. The inputs IN2, IN1, and IN0 of the lookup tables are configured as the primary-side drive signal g1, the state machine output signal of the second state machine FSM1, and the state machine output signal of the first state machine FSM0, respectively. The output logic of the two lookup tables can be configured as 0x2A and 0xC4, respectively, so that the combination of each input state forms a signal corresponding to the primary-side drive signal g1, the state machine output signal of the second state machine FSM1, and the state machine output signal of the first state machine FSM0. Figure 6 The corresponding secondary side drive output result.

[0088] Therefore, by first generating the conduction judgment results for each secondary-side synchronous rectifier switch through the state machine, and then combining the current state of the primary-side drive signal to perform output priority processing on the state machine output signal corresponding to the same secondary-side bridge arm, it is possible to retain the current path that should continue to conduct when a simultaneous conduction conflict occurs, and turn off the other path that conflicts with it. This ensures that the final secondary-side drive signal is constrained by both the secondary-side current and the conduction judgment results of the state machine, as well as by the current state of the primary-side drive. This avoids the simultaneous conduction conflict directly forming the final drive output and reduces the situation where the effective secondary-side drive is turned off prematurely due to conflict protection.

[0089] Step S400: Output the secondary-side drive signal through the configurable logic block to control the corresponding secondary-side synchronous rectifier switch to be turned on or off.

[0090] In step S400, the secondary-side drive signals obtained after output priority processing correspond to the secondary-side synchronous rectifier switches in the same secondary-side bridge arm. The configurable logic block transmits each secondary-side drive signal to the corresponding pulse width modulation output channel, which outputs a corresponding level according to the current state of the secondary-side drive signal, so as to convert the conduction or cutoff result formed inside the configurable logic block into the actual drive signal of the corresponding secondary-side synchronous rectifier switch.

[0091] Specifically, each secondary-side synchronous rectifier switch is configured with a corresponding pulse width modulation (PWM) output channel. The secondary-side drive signal output by the configurable logic block is transmitted to the corresponding PWM output channel. When the secondary-side drive signal is in the ON state, a high level is output through the corresponding PWM output channel to control the secondary-side synchronous rectifier switch to turn on. When the secondary-side drive signal is in the OFF state, a low level is output through the corresponding PWM output channel to control the secondary-side synchronous rectifier switch to turn off. Each secondary-side synchronous rectifier switch has a corresponding PWM output channel, allowing the secondary-side drive signals generated by the configurable logic block for different secondary-side synchronous rectifier switches to be transmitted to their respective drive paths. When the secondary-side drive signal is in the ON state, the corresponding PWM output channel generates a high-level drive, causing the corresponding secondary-side synchronous rectifier switch to turn on. When the secondary-side drive signal switches to the OFF state, the corresponding PWM output channel generates a low-level drive, causing the corresponding secondary-side synchronous rectifier switch to turn off. Thus, a one-to-one output control relationship is formed between the secondary drive signal generated by the configurable logic block and each secondary synchronous rectifier switch.

[0092] In one specific implementation, the pulse width modulation output channel can be implemented using an enhanced pulse width modulation (EPWM) output channel. The action limiting submodule AQ in the EPWM is used to control the output level of the corresponding EPWM output terminal. After the configurable logic block generates the secondary-side drive signal, the trigger input of the corresponding EPWM is configured via on-chip signal routing. This trigger input forces the level of the corresponding EPWM output terminal, thereby bypassing the output action of AQ. This allows the secondary-side drive signal, obtained through state machine judgment and output priority processing, to directly participate in the level control of the corresponding EPWM output terminal.

[0093] Taking secondary-side drive signals g5 and g6 as examples, corresponding pulse width modulation (PWM) output channels can be configured for each. After output priority processing in step S300, secondary-side drive signals for controlling the corresponding secondary-side synchronous rectifier switches are obtained. When secondary-side drive signal g5 is in the on state, a high level is output through the PWM output channel corresponding to secondary-side drive signal g5, turning on the secondary-side synchronous rectifier switch controlled by secondary-side drive signal g5; when secondary-side drive signal g5 is in the off state, the corresponding PWM output channel outputs a low level, turning off the secondary-side synchronous rectifier switch. Secondary-side drive signal g6 controls its corresponding secondary-side synchronous rectifier switch in the same way.

[0094] In the above manner, the conduction judgment result and output priority processing result generated by the aforementioned state machine can be directly converted into the actual conduction or cutoff control of the secondary-side synchronous rectifier switch. The state machine generates a state machine output signal based on the rising edge of the primary-side drive signal, the current comparison signal, and the current drive state of the secondary-side synchronous rectifier switch. The output priority processing further utilizes the current state of the primary-side drive signal to eliminate simultaneous conduction conflicts. The final secondary-side drive signal is then output to the secondary-side synchronous rectifier switch through the corresponding pulse width modulation output channel, thereby forming a hardware control link from signal judgment, state machine control, output priority processing to switch drive output.

[0095] Reference Figure 7 This is a synchronous rectification control waveform diagram provided in one embodiment of this application. Figure 7 In the diagram, the yellow waveform corresponds to channel 1, which is the current comparison signal; the green waveform corresponds to channel 2, which is the secondary drive signal for the upper transistor in the same secondary arm; the magenta waveform corresponds to channel 3, which is the secondary drive signal for the lower transistor in the same secondary arm; and the cyan waveform corresponds to channel 4, which is the high-frequency sampling output signal of the current detection point, used to reflect the actual change process of the secondary current.

[0096] from Figure 7 As shown in the waveform, the upper and lower drive signals of the same secondary bridge arm switch according to the corresponding control results, preventing the aforementioned simultaneous conduction conflict from being directly output to the secondary synchronous rectifier switch. Simultaneously, the turn-off of the secondary drive signal coordinates with the state change of the current comparison signal, ensuring that the established effective conduction branch remains on while the corresponding current condition is met, and switches to the off state after the current condition changes. Therefore, while using the primary drive signal to limit the secondary drive output relationship, the corresponding conduction holding and turn-off processes can be determined using the secondary current comparison results, thereby achieving hardware synchronous rectification control of the secondary synchronous rectifier switch.

[0097] Under the corresponding operating conditions, the above-mentioned synchronous rectification control can also coordinate the turn-on and turn-off processes of the secondary-side synchronous rectifier switch with the soft-switching process of the LLC resonant converter, so that the switching devices can meet the soft-switching conditions corresponding to zero-voltage turn-on (ZVS) or zero-current turn-off (ZCS), thereby helping to reduce switching losses and the electrical stress borne by the switching devices.

[0098] In summary, combining Figure 8 This application generates a current comparison signal by detecting the secondary-side current of the LLC resonant converter, and inputs the current comparison signal and the primary-side drive signal into a configurable logic block. The configurable logic block uses a state machine to identify the rising edge of each primary-side drive signal, and combines the rising edge flag, the current comparison signal, and the current drive state of each secondary-side synchronous rectifier switch in the same secondary-side bridge arm to generate a corresponding state machine output signal. This ensures that the start-on, holding-on, and turn-off of the secondary-side synchronous rectifier switch are simultaneously constrained by the primary-side drive timing, the secondary-side current state, and the current drive state of the bridge arm. Based on this, the output priority processing of the state machine output signal corresponding to the same secondary-side bridge arm is performed according to the current state of the primary-side drive signal. When a simultaneous conduction conflict occurs, the one that should continue to conduct is retained, and the conflicting one is turned off, forming the final secondary-side drive signal. This signal is then used to control the secondary-side synchronous rectifier switch to turn on or off through the corresponding pulse width modulation output channel. Thus, the current judgment, state machine conduction control, conflict arbitration, and final drive output in the secondary-side synchronous rectification process form a continuous hardware control link.

[0099] Based on the above control method, the turn-on timing of the synchronous rectifier switch does not need to be continuously calculated in real time by the processor based on the relationship between the secondary current and the phase shift angle in each switching cycle, nor does it need to establish and store the turn-on timing table in advance for different input voltages, output loads and switching frequencies. Instead, the configurable logic block directly completes the state judgment and drive output according to the pre-configured hardware logic. Therefore, it can reduce the processor's computing and storage resource occupation and avoid the adaptation burden caused by rebuilding the operating condition turn-on timing table after the hardware parameters change. At the same time, by using the primary-side drive signal and the secondary-side current comparison result together for state machine judgment, when the secondary-side current detection result fluctuates, the primary-side drive timing and the current state of the secondary-side synchronous rectifier switch can be further constrained. This reduces the possibility of false turn-on or repeated switching caused by relying on a single detection condition. When a shared secondary-side current detection path is adopted, the primary-side drive signal can also be used to distinguish the corresponding secondary-side conduction branch, reducing the need to set up detection circuits for different bridge arms.

[0100] Furthermore, when the state machine outputs of the same secondary-side bridge arm experience simultaneous conduction conflicts, the two drives are not simply turned off simultaneously. Instead, the current state of the primary-side drive is considered, retaining the one that should continue conducting while turning off the conflicting one. This avoids simultaneous conduction of the upper and lower transistors of the bridge arm and reduces turn-off losses and electrical stress on devices caused by premature turn-off of the effective secondary-side drive. By controlling the conduction and turn-off processes in conjunction with the secondary-side current comparison results, the switching process of the synchronous rectifier switch can be coordinated with the LLC resonant operation process, satisfying the soft-switching conditions corresponding to ZVS or ZCS under appropriate operating conditions. Therefore, this application can improve the reliability of secondary-side drive generation and output while reducing control resources and detection hardware usage, and also considers fast response, reduced switching losses, and improved control safety redundancy, thereby helping to ensure the stable operation of the synchronous rectification process.

[0101] One embodiment of this application also provides a CLB-based hardware synchronous rectification control system for executing the aforementioned CLB-based hardware synchronous rectification control method. The system includes an LLC resonant converter, a configurable logic block, and pulse width modulation output channels. The LLC resonant converter is provided with a primary-side switching circuit and a secondary-side synchronous rectification switch. The output terminal of the primary-side switching circuit is connected to the input terminal of the configurable logic block, the output terminal of the configurable logic block is connected to the input terminal of each pulse width modulation output channel, and the output terminal of each pulse width modulation output channel is connected to the driving terminal of the corresponding secondary-side synchronous rectification switch.

[0102] For relevant details, please refer to the above method implementation examples.

[0103] Figure 9 This is a block diagram of an electronic device provided in one embodiment of this application. The device includes at least a processor 901 and a memory 902.

[0104] Processor 901 may include one or more processing cores. Processor 901 may be implemented in at least one hardware form selected from DSP (Digital Signal Processor), FPGA (Field-Programmable Gate Array), and MCU (Microcontroller Unit). Processor 901 may also include a main processor and a coprocessor. The main processor performs the main control and data processing tasks during device operation, while the coprocessor assists in completing some signal processing or control tasks. In some embodiments, processor 901 may integrate configurable logic resources for implementing preset hardware logic to perform logical processing on the primary-side drive signal and current comparison signal, and generate the secondary-side drive signal in conjunction with the corresponding output channel.

[0105] The memory 902 may include one or more computer-readable storage media, which may be non-transitory computer-readable storage media. The memory 902 may also include high-speed random access memory and non-volatile memory, such as disk storage devices, flash memory devices, etc. In some embodiments, the non-transitory computer-readable storage media in the memory 902 are used to store at least one instruction or program, which is loaded and executed by the processor 901 to implement the CLB-based hardware synchronous rectification control method provided in the method embodiments of this application.

[0106] Optionally, this application also provides a computer-readable storage medium storing a program that is loaded and executed by a processor to implement the CLB-based hardware synchronous rectification control method of the above method embodiments.

[0107] Optionally, this application also provides a computer product including a computer-readable storage medium storing a program that is loaded and executed by a processor to implement the CLB-based hardware synchronous rectification control method of the above method embodiments.

[0108] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0109] The above embodiments merely illustrate several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A hardware synchronous rectification control method based on CLB, characterized in that, The control method, applied to an LLC resonant converter with configurable logic blocks, includes: The primary-side drive signal of the LLC resonant converter is acquired, and the secondary-side current of the LLC resonant converter is detected; a current comparison signal is generated based on the detected secondary-side current, and the primary-side drive signal and the current comparison signal are input to the configurable logic block. The rising edge of each primary-side drive signal is identified by the state machine in the configurable logic block to obtain the corresponding rising edge flag; the corresponding state machine output signal is generated based on the rising edge flag, the current comparison signal, and the current drive state of each secondary-side synchronous rectifier switch in the same secondary-side bridge arm. Based on the current state of each primary side driving signal, the output priority processing is performed on the state machine output signal corresponding to the same secondary side bridge arm. When a simultaneous conduction conflict occurs, one path is kept in the conduction state and the conflicting path is turned off to obtain the secondary side driving signal. The secondary-side drive signal is output through the configurable logic block to control the corresponding secondary-side synchronous rectifier switch to be turned on or off.

2. The hardware synchronous rectification control method based on CLB according to claim 1, characterized in that, The step of generating a corresponding state machine output signal based on the rising edge flag, the current comparison signal, and the current driving state of each secondary synchronous rectifier switch in the same secondary bridge arm includes: For each of the primary-side driving signals, determine the first secondary-side conduction condition and the second secondary-side conduction condition; The first secondary side conduction condition is: the rising edge flag of the primary side drive signal is in an active state, the current comparison signal indicates that the detected secondary side current is greater than the first preset current threshold, and the current drive state of the other secondary side synchronous rectifier switch in the same secondary side bridge arm is in an off state. The second secondary side conduction condition is as follows: the current comparison signal indicates that the detected secondary side current is greater than the second preset current threshold, the current driving state of the secondary side synchronous rectifier switch corresponding to the primary side drive signal in the same secondary side bridge arm is the on state, and the current driving state of the other secondary side synchronous rectifier switch in the same secondary side bridge arm is the off state. When the first secondary side conduction condition is met, the state machine output signal for the primary side drive signal is set to conduction state; when the second secondary side conduction condition is met, the state machine output signal for the primary side drive signal remains in conduction state; when neither the first secondary side conduction condition nor the second secondary side conduction condition is met, the state machine output signal for the primary side drive signal is set to de-conduction state.

3. The hardware synchronous rectification control method based on CLB according to claim 2, characterized in that, The step of generating a corresponding state machine output signal based on the rising edge flag, the current comparison signal, and the current driving state of each secondary synchronous rectifier switch in the same secondary bridge arm further includes: For each of the primary-side drive signals, a corresponding state machine is configured; each of the primary-side drive signals is input into the corresponding state machine, and the current comparison signal is input into each of the state machines; Each state machine identifies the rising edge of the corresponding primary-side drive signal, obtains the corresponding rising edge flag, and generates a state machine output signal corresponding to the primary-side drive signal.

4. The hardware synchronous rectification control method based on CLB according to claim 1, characterized in that, The step of identifying the rising edge of each primary-side driving signal through the state machine in the configurable logic block to obtain the corresponding rising edge flag includes: For each of the primary-side driving signals, the rising edge detection condition of the primary-side driving signal is that the primary-side driving signal is at a high level and its rising edge flag is not currently set. When the rising edge detection condition is met, a rising edge flag in a valid state is generated; when the rising edge detection condition is not met, a rising edge flag in an invalid state is generated.

5. The hardware synchronous rectification control method based on CLB according to claim 1, characterized in that, Based on the current state of each primary-side driving signal, the output priority processing is performed on the state machine output signal corresponding to the same secondary-side bridge arm. When a simultaneous conduction conflict occurs, one path is kept in the conducting state and the conflicting path is turned off, thus obtaining the secondary-side driving signal, including: When any of the primary-side driving signals is low and the state machine output signal corresponding to the primary-side driving signal is in the on state, the state machine output signal is kept in the on state. If the output signal of the other state machine corresponding to the same secondary side bridge arm is simultaneously in the on state, then the output signal of the other state machine is adjusted to the off state to obtain the secondary side drive signal.

6. The hardware synchronous rectification control method based on CLB according to claim 5, characterized in that, The method of prioritizing the output signals of the state machine corresponding to the same secondary bridge arm based on the current state of each primary side driving signal, retaining one path as the on state and turning off the conflicting path when a simultaneous conduction conflict occurs, to obtain the secondary side driving signal, further includes: For each secondary synchronous rectifier switch in the same secondary bridge arm, a corresponding lookup table is configured. The primary side drive signal used for the output priority processing and the output signals of each state machine corresponding to the same secondary side bridge arm are respectively input into each of the lookup tables; By using the lookup tables, the output signals of each state machine are logically combined according to the current state of the primary-side drive signal to generate a secondary-side drive signal corresponding to each secondary-side synchronous rectifier switch.

7. The hardware synchronous rectification control method based on CLB according to any one of claims 1 to 6, characterized in that, The step of outputting the secondary-side drive signal through the configurable logic block to control the corresponding secondary-side synchronous rectifier switch to be turned on or off includes: Configure a corresponding pulse width modulation output channel for each of the secondary-side synchronous rectifier switches; transmit the secondary-side drive signal output by the configurable logic block to the corresponding pulse width modulation output channel; When the secondary-side drive signal is in the ON state, a high level is output through the corresponding pulse width modulation output channel to control the secondary-side synchronous rectifier switch to be turned on; when the secondary-side drive signal is in the OFF state, a low level is output through the corresponding pulse width modulation output channel to control the secondary-side synchronous rectifier switch to be turned off.

8. A CLB-based hardware synchronous rectification control system, used to execute the CLB-based hardware synchronous rectification control method as described in any one of claims 1 to 7, characterized in that, The system includes an LLC resonant converter, a configurable logic block, and a pulse width modulation output channel; the LLC resonant converter is equipped with a primary-side switching circuit and a secondary-side synchronous rectifier switch. The output terminal of the primary-side switching circuit is connected to the input terminal of the configurable logic block, the output terminal of the configurable logic block is connected to the input terminal of each pulse width modulation output channel, and the output terminal of each pulse width modulation output channel is connected to the driving terminal of the corresponding secondary-side synchronous rectifier switch.

9. An electronic device, characterized in that, The device includes a processor and a memory; the memory stores a program that is loaded and executed by the processor to implement a CLB-based hardware synchronous rectification control method as described in any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that, The storage medium stores a program that, when executed by a processor, is used to implement a CLB-based hardware synchronous rectification control method as described in any one of claims 1 to 7.

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