Three-level module, three-level power conversion system and vehicle

Abstract

The present disclosure relates to a three-level module, a three-level power conversion system and a vehicle, the module comprising: a substrate, an upper surface of the substrate being provided with a plurality of power conductive regions insulated from each other; a plurality of signal lead-out units arranged above the substrate, an upper surface of each signal lead-out unit being provided with a plurality of signal conductive regions, each signal conductive region being provided with a signal terminal connector extending in a direction away from the upper surface of the substrate and perpendicular to a plane in which the signal lead-out unit is arranged; and a plurality of power switch chips, respectively constituting an upper bridge arm switch group, a lower bridge arm switch group and a clamping switch group, power terminals of the power switch chips of each switch group being connected to corresponding power conductive regions to complete interconnection conduction of a power loop, and signal terminals of the power switch chips of each switch group being connected to corresponding signal terminal connectors to receive driving signals, so that the three-level module selectively operates in a two-level inverter mode or a three-level inverter mode. The present disclosure reduces the overall size of the three-level module.

Description

Technical Field

[0001] This disclosure relates to the field of power module technology, and more particularly to a three-level module, a three-level power conversion system, and a vehicle. Background Technology

[0002] Currently, most mainstream high-voltage, high-current power modules adopt a two-level topology. While this has the advantages of simple structure and controllable packaging costs, it still suffers from inherent drawbacks such as high switching losses and high output harmonic content. The three-level module topology can specifically improve these problems; however, due to the inherent limitations of its conventional packaging design, the overall size of a single-phase three-level module is relatively large. Summary of the Invention

[0003] The first aspect of this disclosure provides a three-level module, comprising: A substrate, wherein the upper surface of the substrate is provided with a plurality of mutually insulated power conductive regions; Multiple signal lead-out units are disposed above the substrate. Each signal lead-out unit has multiple signal conductive areas on its upper surface. Each signal conductive area is provided with a signal terminal connector extending in a direction away from the upper surface of the substrate along a plane perpendicular to the plane where the signal lead-out unit is located. Multiple power switch chips constitute an upper bridge arm switch group, a lower bridge arm switch group, and a clamping switch group, respectively. The power terminals of the power switch chips in each switch group are connected to the corresponding power conductive areas to complete the interconnection and conduction of the power circuit. The signal terminals of the power switch chips in each switch group are connected to the corresponding signal terminal connectors to receive drive signals, so that the three-level module can selectively operate in a two-level inverter mode or a three-level inverter mode.

[0004] The second aspect of this disclosure provides a three-level power conversion system, comprising: the three-level module proposed in the first aspect embodiment.

[0005] A third aspect of this disclosure provides a vehicle comprising: a three-level module as described in the first aspect.

[0006] The technical solutions provided by the embodiments of this disclosure have at least the following beneficial effects: This disclosure discloses a three-level module, a three-level power conversion system, and a vehicle. The three-level module includes: a substrate with multiple mutually insulated power conductive regions on its upper surface; multiple signal lead-out units disposed above the substrate, each with multiple signal conductive regions on its upper surface, and each signal conductive region having a signal terminal connector extending away from the upper surface of the substrate along a plane perpendicular to the signal lead-out unit; and multiple power switch chips forming an upper bridge arm switch group, a lower bridge arm switch group, and a clamping switch group. The power terminals of the power switch chips in each switch group are connected to the corresponding power conductive regions to complete the interconnection and conduction of the power circuits. The signal terminals of the power switch chips in each switch group are connected to the corresponding signal terminal connectors to receive drive signals, enabling the three-level module to selectively operate in a two-level inverter mode or a three-level inverter mode. This disclosure leads the signal terminals out along the direction perpendicular to the substrate, saving a large amount of space in the horizontal plane, significantly reducing the overall size of the module, and solving the problem of the large size of traditional single-phase three-level modules.

[0007] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0008] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure, and are not intended to unduly limit this disclosure.

[0009] Figure 1 This is a topology diagram of a three-phase three-level power conversion system according to an embodiment of this disclosure; Figure 2 This is a topology diagram of a U-phase three-level module according to an embodiment of this disclosure; Figure 3 This is a schematic diagram of the layout of a three-level module according to an embodiment of the present disclosure; Figure 4 This is a layout schematic diagram of a three-level module according to another embodiment of this disclosure; Figure 5 This is a public response Figure 3 A schematic diagram showing the completed wiring status of the three-level module; Figure 6 This is a public response Figure 4 A schematic diagram showing the completed wiring status of the three-level module; Figure 7 This is a public response Figure 3 A schematic diagram of the structure of a three-level module; Figure 8 This is a public response Figure 4 A schematic diagram of the structure of a three-level module. Detailed Implementation

[0010] To enable those skilled in the art to better understand the technical solutions of this disclosure, the technical solutions in the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings.

[0011] It should be noted that the terms "first," "second," etc., used in the specification, claims, and accompanying drawings of this disclosure are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this disclosure described herein can be implemented in orders other than those illustrated or described herein. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this disclosure. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this disclosure as detailed in the appended claims.

[0012] The following description, with reference to the accompanying drawings, describes embodiments of a three-level module, a three-level power conversion system, and a vehicle.

[0013] Figure 1 This is a topology diagram of a three-phase three-level power conversion system according to an embodiment of the present disclosure.

[0014] like Figure 1 As shown, the three-phase three-level power conversion system of this disclosure includes: U-phase upper bridge arm switch group M1, U-phase lower bridge arm switch group M2, U-phase clamping switch group NP1 (including U-phase first switch group U1 and U-phase second switch group U2), V-phase upper bridge arm switch group M3, V-phase lower bridge arm switch group M4, V-phase clamping switch group NP2 (including V-phase first switch group U3 and V-phase second switch group U4), W-phase upper bridge arm switch group M3, W-phase lower bridge arm switch group M4, and W-phase clamping switch group NP3 (including W-phase first switch group U5 and W-phase second switch group U6). In the figure, P is the positive terminal of the DC bus, N is the negative terminal of the DC bus, U, V, and W are the three-phase AC output terminals, and UVW are connected to the three-phase lines of the motor.

[0015] This disclosure integrates all power devices of a single phase in a three-level power conversion system into an independent three-level module. Taking the U phase as an example, the U phase three-level module integrates the U phase upper bridge arm switch group M1, the U phase lower bridge arm switch group M2, and the U phase clamping switch group NP1 (including the U phase first switch group U1 and the U phase second switch group U2). The power terminals of this three-level module include the positive terminal P of the DC bus, the negative terminal N of the DC bus, the midpoint potential point M, and the AC output terminal AC. The signal terminals of this three-level module include the drain d1 of the upper bridge arm switch group M1, the gate g1 of the upper bridge arm switch group M1, the source s1 of the upper bridge arm switch group M1, the drain d2 of the lower bridge arm switch group M2, the gate g2 of the lower bridge arm switch group M2, the source s2 of the lower bridge arm switch group M2, the drain du1 of the first switch group U1, the drain du2 of the second switch group U2, the gate gu1 of the first switch group U1, the gate gu2 of the second switch group U2, the source su1 of the first switch group U1, and the source su2 of the second switch group U2. The topology of this single-phase three-level module is as follows: Figure 2 As shown.

[0016] The electrical connection relationship of the three-level module in this embodiment is as follows: the drain d1 of the upper bridge arm switch group M1 is electrically connected to the positive terminal P of the DC bus; the source s1 of the upper bridge arm switch group M1, the drain du2 of the second switch group U2, and the drain d2 of the lower bridge arm switch group M2 are all electrically connected to the AC output terminal AC; the drain du1 of the first switch group U1 is electrically connected to the midpoint potential point M; and the source su1 of the first switch group U1 is electrically connected to the source su2 of the second switch group U2.

[0017] Figure 3 This is a layout diagram of a three-level module according to an embodiment of this disclosure. Figure 4 This is a schematic diagram of the layout of a three-level module according to another embodiment of this disclosure.

[0018] like Figure 3 and Figure 4 As shown, the three-level module 1000 of this embodiment includes: a substrate 100, a plurality of signal output units 200 and a plurality of power switch chips 300.

[0019] The substrate 100 has multiple mutually insulated power conductive regions 110 on its upper surface. Multiple signal output units 200 are disposed above the substrate 100. Each signal output unit has multiple signal conductive regions on its upper surface, and each signal conductive region has a signal terminal connector (circular pattern in the figure) extending perpendicular to the plane of the signal output unit and away from the upper surface of the substrate 100. Multiple power switch chips 300 respectively constitute an upper bridge arm switch group M1, a lower bridge arm switch group M2, and a clamping switch group (including a first switch group U1 and a second switch group U2). The power terminals of the power switch chips in each switch group are connected to the corresponding power conductive regions to complete the interconnection and conduction of the power circuits. The signal terminals of the power switch chips in each switch group are connected to the corresponding signal terminal connectors to receive drive signals, enabling the three-level module 1000 to selectively operate in a two-level inverter mode or a three-level inverter mode.

[0020] For example, the substrate 100 adopts a high thermal conductivity AMB substrate. The top copper layer of the AMB under the power switch chip is not covered with any signal traces and is used entirely to carry high current power circuits. Based on the low impedance characteristics of the large area copper layer, the parasitic inductance of the power circuit can be minimized, and the direct coupling between the power circuit and the signal circuit is cut off from the physical path, which greatly reduces the risk of interference between the high-voltage circuit and the low-voltage signal.

[0021] The signal extraction unit 200 adopts an independent DBC structure. Along a direction perpendicular to the upper surface of the substrate 100 and away from the substrate 100, the signal extraction unit 200 is sequentially configured from bottom to top with a lower surface conductive metal layer (lower surface copper layer), an insulating dielectric layer, and an upper surface conductive metal layer (upper surface copper layer). In this way, the signal circuit is completely integrated within the upper surface copper layer of the DBC. Electrical isolation between the signal circuit and the underlying AMB power conductive layer is achieved based on the DBC's built-in insulating dielectric layer, eliminating the need for additional gaps for signal traces between the power conductive areas of the AMB substrate and significantly reducing the area occupied by the signal circuit on the substrate 100.

[0022] The signal terminals are led upwards perpendicularly to the upper surface of the DBC structure via signal terminal connectors (such as PIN pins), completely avoiding the routing paths of surrounding high-current power circuits. From a spatial routing perspective, this further reduces the probability of electromagnetic coupling between strong and weak current circuits. It should be noted that the schematic diagram in this disclosure is only an example with a minimum number of signal terminal connectors. In practical applications, more signal terminal connectors can be set. For example, a corresponding gate signal terminal connector and a Kelvin signal terminal connector can be set for every two power switching chips.

[0023] This disclosure employs a DBC stacked vertical pin design, shifting the signal arrangement requirements that would otherwise occupy a significant amount of space in the 100mm lateral plane of the substrate to the Z-axis space. This eliminates the need for additional lateral arrangement space for multiple drive signals in a three-level topology, significantly reducing the overall lateral size of the module and fundamentally solving the problem of excessively large size in traditional single-phase three-level modules. Simultaneously, the vertical pin exit completely avoids the area above the power switch chip; all interconnection paths of the drive circuit are completed within the signal conductive layer of the DBC structure. This avoids the defects of traditional packaging where signal leads (such as drive leads) are connected above the power circuit, further reducing parasitic coupling between the drive and power circuits. Furthermore, the top copper layer of the AMB substrate is entirely used for large-area copper interconnects in the power circuit, improving high-current carrying capacity while further optimizing the parasitic parameters of the module's power circuit, adapting to low-loss switching requirements under high-voltage, high-current conditions.

[0024] In some embodiments of this disclosure, such as Figure 3 and Figure 4 As shown, the plurality of power conductive regions 110 in this embodiment of the present disclosure include a DC bus positive terminal region 111, a DC bus negative terminal region 112, a midpoint potential region 113, an AC output terminal region 114, and an inter-bridge transition conductive region 115 for realizing power connection between adjacent bridge arms; wherein, along the longitudinal central axis of the substrate 100, the midpoint potential region 113 and the AC output terminal region 114 are respectively disposed on opposite sides of the substrate 100; the DC bus positive terminal region 111, the DC bus negative terminal region 112, and the inter-bridge transition conductive region 115 are disposed in the middle region between the midpoint potential region 113 and the AC output terminal region 114.

[0025] In some embodiments of this disclosure, such as Figure 3 and Figure 4 As shown, the bridge transition conductive region of this embodiment includes a first transition conductive region 1151 and a second transition conductive region 1152; wherein, the first transition conductive region 1151 is disposed adjacent to the midpoint potential region 113 and away from the AC output terminal region 114; the second transition conductive region 1152 is disposed adjacent to the AC output terminal region 114 and away from the midpoint potential region 113; the DC bus negative terminal region 112 is located within the intermediate accommodating space formed by the first transition conductive region 1151 and the second transition conductive region 1152; the DC bus positive terminal region 111 is located on the outer periphery of the second transition conductive region 1152 away from the first transition conductive region 1151.

[0026] This disclosure takes into account that the upper bridge arm switch group M1 and the lower bridge arm switch group M2 need to bear the peak current. Therefore, the main power circuit at the positive and negative ends of the DC bus adopts a dual-circuit form (configured with 2 positive DC bus terminals P). With the shortest path design of the main power circuit, the current loop area of ​​the main power circuit is compressed to the minimum, which greatly reduces the parasitic inductance of the main power circuit. This effectively reduces the loss and voltage spikes of the power switch chip in the clamping switch group (i.e., the first switch group U1 and the second switch group U2).

[0027] This disclosure differentiates the terminal positions based on the current load characteristics of different circuits. The positive terminal P, negative terminal N, and midpoint terminal M are placed in corresponding areas according to their respective current ratings, prioritizing the control of parasitic inductance in the main power circuit under high current conditions to a minimum. In this topology, the upper bridge arm switch group M1 and the lower bridge arm switch group M2 are bridge arms that bear peak high currents, and the control requirements for parasitic inductance of the main power circuit between the positive and negative terminals of the DC bus are relatively high. Therefore, the positive terminal P and the negative terminal N are arranged closer to the AC output terminal AC side.

[0028] In some embodiments of this disclosure, such as Figure 3 and Figure 4 As shown, the power terminal of the power switch chip in this embodiment includes a drain; wherein, the drain d1 of the power switch chip of the upper bridge arm switch group M1 is fixed in the positive terminal region 111 of the DC bus by sintering; the drain d2 of the power switch chip of the lower bridge arm switch group M2 is fixed in the second transition conductive region 1152 by sintering; the drain du1 of the power switch chip of the first switch group U1 in the clamping switch group is fixed in the midpoint potential region 113 by sintering, and the drain du2 of the power switch chip of the second switch group U2 in the clamping switch group is fixed in the first transition conductive region 1151 by sintering.

[0029] In some embodiments of this disclosure, such as Figure 3 As shown, multiple signal output units 200 are disposed on the upper surface of the substrate 100. The vertical projection of each signal output unit on the substrate (100) does not overlap with the switch group corresponding to the signal output unit, that is, the orthographic projection of each signal output unit on the substrate 100 does not cover the corresponding switch group.

[0030] like Figure 3As shown, the power terminal of the power switch chip in this embodiment of the present disclosure further includes a power source electrode; wherein, the power source electrode s1 of the power switch chip of the upper bridge arm switch group M1 is electrically connected to the AC output terminal region 114 and the second transition conductive region 1152 respectively through a copper clip connection assembly; the power source electrode s2 of the power switch chip of the lower bridge arm switch group M2 is electrically connected to the DC bus negative terminal region 112 through a copper clip connection assembly; the power source electrode su1 of the power switch chip of the first switch group U1 is electrically connected to the power source electrode su2 of the power switch chip of the second switch group U2 through a copper clip connection assembly.

[0031] To further reduce the length dimension of the three-level module and decrease the module size, such as... Figure 4 As shown, this disclosure arranges a plurality of signal lead-out units 200 above the substrate 100 and spaced apart from the upper surface of the substrate 100. The vertical projection of each signal lead-out unit on the substrate (100) overlaps at least partially with the switch group corresponding to the signal lead-out unit, that is, the orthographic projection of each signal lead-out unit on the substrate 100 covers a part of the corresponding switch group.

[0032] like Figure 4 As shown, the power terminal of the power switch chip in this embodiment further includes a power source electrode; wherein, the power source electrode s1 of the power switch chip of the upper bridge arm switch group M1 is connected to the lower surface of the signal lead-out unit corresponding to the upper bridge arm switch group M1 through a copper pad connection assembly, and the lower surface of the signal lead-out unit corresponding to the upper bridge arm switch group M1 is also electrically connected to the AC output terminal region 114 and the second transition conductive region 1152 respectively through a copper pad connection assembly; the power source electrode s2 of the power switch chip of the lower bridge arm switch group M2 is connected to the lower surface of the signal lead-out unit corresponding to the lower bridge arm switch group M2 through a copper pad connection assembly, and the lower surface of the signal lead-out unit corresponding to the lower bridge arm switch group M2 is also electrically connected to the DC bus negative terminal region 112 through a copper pad connection assembly; the power source electrode su1 of the power switch chip of the first switch group U1 and the power source electrode su2 of the power switch chip of the second switch group U2 are connected to the lower surface of the signal lead-out unit corresponding to the clamping switch group through a copper pad connection assembly. Figure 4 The power circuit shown utilizes the copper layer above the substrate 100 and the copper layer below the signal output unit (i.e., DBC). The large area of ​​copper interconnect reduces the parasitic inductance of the module.

[0033] In some embodiments of this disclosure, such as Figure 3 and Figure 4As shown, in this embodiment of the present disclosure, multiple signal output units 200 are arranged sequentially along the longitudinal central axis of the substrate as a first signal output unit 210, a second signal output unit 220, and a third signal output unit 230. The first signal output unit 210 is disposed above the first transition conductive region 1151 in the midpoint potential region 113 and the inter-bridge transition conductive region 115, and the power switch chips of the clamping switch group are symmetrically arranged along the longitudinal central axis of the substrate 100. The second signal output unit 220 is disposed above the second transition conductive region 1152 in the inter-bridge transition conductive region 115, and the power switch chips of the lower bridge arm switch group M2 are symmetrically arranged along the longitudinal central axis of the substrate 100. The third signal output unit 230 is disposed above the positive terminal region 111 of the DC bus, and the power switch chips of the upper bridge arm switch group M1 are symmetrically arranged along the longitudinal central axis of the substrate 100 on the left and right sides of the third signal output unit 230.

[0034] In some embodiments of this disclosure, such as Figure 3 As shown, the first signal output unit 210 is disposed on the upper surface of the first transition conductive region 1151 in the midpoint potential region 113 and the inter-bridge transition conductive region 115. The power switch chips of the clamping switch group are symmetrically arranged on the left and right sides of the first signal output unit 210. The second signal output unit 220 is disposed on the upper surface of the second transition conductive region 1152 in the inter-bridge transition conductive region 115. The power switch chips of the lower bridge arm switch group M2 are symmetrically arranged on the left and right sides of the second signal output unit 220. The third signal output unit 230 is disposed on the upper surface of the DC bus positive terminal region 111. The power switch chips of the upper bridge arm switch group M1 are symmetrically arranged on the left and right sides of the third signal output unit 230.

[0035] For example, such as Figure 3 As shown, in this embodiment, the two power switch chips of the first switch group U1 are mirror-symmetrically arranged on the left and right sides of the upper half of the first signal output unit 210 with the longitudinal center line of the first signal output unit 210 as the axis of symmetry; the two power switch chips of the second switch group U2 are mirror-symmetrically arranged on the left and right sides of the lower half of the first signal output unit 210 with the longitudinal center line of the first signal output unit 210 as the axis of symmetry; the four power switch chips of the lower bridge arm switch group M2 are symmetrically arranged in two groups, upper and lower, with the longitudinal center line of the second signal output unit 220 as the axis of symmetry, respectively mirror-symmetrically arranged on the left and right sides of the upper and lower half of the second signal output unit 220; the four power switch chips of the upper bridge arm switch group M1 are symmetrically arranged in two groups, upper and lower, with the longitudinal center line of the third signal output unit 230 as the axis of symmetry, respectively mirror-symmetrically arranged on the left and right sides of the upper and lower half of the third signal output unit 230.

[0036] In other embodiments of this disclosure, such as Figure 4 As shown, in this embodiment of the present disclosure, the first signal output unit 210 is disposed above the first transition conductive region 1151 in the midpoint potential region 113 and the inter-bridge transition conductive region 115, and the power switch chips of the clamping switch group are symmetrically arranged on the left and right sides of the longitudinal central axis along the longitudinal central axis of the substrate 100; the second signal output unit 220 is disposed above the second transition conductive region 1152 in the inter-bridge transition conductive region 115, and the power switch chips of the lower bridge arm switch group M2 are symmetrically arranged on the left and right sides of the longitudinal central axis along the longitudinal central axis of the substrate 100; the third signal output unit 230 is disposed above the DC bus positive terminal region 111, and the power switch chips of the upper bridge arm switch group M1 are symmetrically arranged on the left and right sides of the longitudinal central axis along the longitudinal central axis of the substrate 100.

[0037] The topology disclosed herein, combined with the actual operating conditions of the vehicle, differentiates and independently designs the main axle arm switch group (i.e., upper axle arm switch group M1 and lower axle arm switch group M2) from the clamping switch group: the power switching chips in the main axle arm switch tubes bear the peak high current output function, adopting a configuration with higher voltage specifications and more chips connected in parallel to ensure current carrying reliability under extreme operating conditions; the power switching chips in the clamping switch group only need to bear the current carrying requirements under medium and low current conditions, and can adopt a configuration with lower voltage specifications and fewer chips connected in parallel, minimizing costs while fully covering the performance requirements of all operating conditions. At the same time, this disclosure adopts a fully symmetrical design for chip layout, power circuit routing, and drive circuit paths, which can significantly improve the current sharing capability in scenarios with multiple power switching chips connected in parallel, ensure the transmission delay and amplitude consistency of each drive signal, effectively reduce the current imbalance loss of parallel chips, and further improve the long-term reliability of the three-level module.

[0038] In some embodiments of this disclosure, such as Figure 3 As shown, the signal terminal connector on the first signal output unit 210 of this embodiment includes a first signal terminal pin 211, a second signal terminal pin 212, and a third signal terminal pin 213 arranged sequentially along the longitudinal central axis of the first signal output unit 210. The first signal terminal pin 211 is used for electrical connection with the gate gu1 of the power switch chip of the first switch group U1 in the clamping switch group (e.g., a bonding wire can be used for bonding, the bonding wire being...). Figure 3 (The darker curved line in the middle), the second signal terminal pin 212 is used to electrically connect to the Kelvin source su1 of the power switch chip of the first switch group U1 and the Kelvin source su2 of the power switch chip of the second switch group U2 in the clamping switch group, and the third signal terminal pin 213 is used to electrically connect to the gate gu2 of the power switch chip of the second switch group U2. The signal terminal connector on the second signal output unit 220 includes a fourth signal terminal pin 221 and a fifth signal terminal pin 222 arranged sequentially along the longitudinal central axis of the second signal output unit 220. The fourth signal terminal pin 221 is used to electrically connect to the gate g2 of the power switch chip of the lower bridge arm switch group M2, and the fifth signal terminal pin 222 is used to electrically connect to the Kelvin source s2 of the power switch chip of the lower bridge arm switch group M2. The signal terminal connector on the third signal output unit 230 includes a sixth signal terminal pin 231 and a seventh signal terminal pin 232 arranged sequentially along the longitudinal central axis of the third signal output unit 230. The sixth signal terminal pin 231 is used to electrically connect to the gate g1 of the power switch chip of the upper bridge arm switch group M1, and the seventh signal terminal pin 232 is used to electrically connect to the Kelvin source s1 of the power switch chip of the upper bridge arm switch group M1.

[0039] In other embodiments of this disclosure, such as Figure 4 As shown, the signal terminal connector on the first signal output unit 210 of this embodiment includes a first signal terminal pin 211, a second signal terminal pin 212, and a third signal terminal pin 213 arranged sequentially along the transverse central axis of the first signal output unit 210. The first signal terminal pin 211 is used for electrical connection with the gate gu1 of the power switch chip of the first switch group U1 in the clamping switch group (e.g., a bonding wire can be used for bonding, the bonding wire being...). Figure 4 (The darker curved line in the middle), the second signal terminal pin 212 is used to electrically connect to the Kelvin source su1 of the power switch chip of the first switch group U1 and the Kelvin source su2 of the power switch chip of the second switch group U2 in the clamping switch group, and the third signal terminal pin 213 is used to electrically connect to the gate gu2 of the power switch chip of the second switch group U2. The signal terminal connector on the second signal output unit 220 includes a fifth signal terminal pin 222 and a fourth signal terminal pin 221 arranged sequentially along the transverse central axis of the second signal output unit 220. The fourth signal terminal pin 221 is used to electrically connect to the gate g2 of the power switch chip of the lower bridge arm switch group M2, and the fifth signal terminal pin 222 is used to electrically connect to the Kelvin source s2 of the power switch chip of the lower bridge arm switch group M2. The signal terminal connector on the third signal output unit 230 includes a seventh signal terminal pin 232 and a sixth signal terminal pin 231 arranged sequentially along the transverse central axis of the third signal output unit 230. The sixth signal terminal pin 231 is used to electrically connect to the gate g1 of the power switch chip of the upper bridge arm switch group M1, and the seventh signal terminal pin 232 is used to electrically connect to the Kelvin source s1 of the power switch chip of the upper bridge arm switch group M1.

[0040] In some embodiments of this disclosure, such as Figure 3 and Figure 4 As shown, the signal terminal connector in this embodiment of the present disclosure further includes an eighth signal terminal pin 241; wherein, the eighth signal terminal pin 241 is disposed on the first signal lead-out unit 210 or disposed on the fourth signal lead-out unit 240 disposed on the upper surface of the midpoint potential region 113, and is used to electrically connect to the drain du1 of the power switch chip of the first switch group U1.

[0041] In some embodiments of this disclosure, such as Figure 3 and Figure 4 As shown, the signal terminal connector of this embodiment further includes a ninth signal terminal pin 251; wherein, the ninth signal terminal pin 251 is disposed on the third signal lead-out unit 230 or disposed on the fifth signal lead-out unit 250 disposed on the upper surface of the DC bus positive terminal region 111, and is used to electrically connect with the drain d1 of the power switch chip of the upper bridge arm switch group M1.

[0042] In this embodiment, the gate signal terminal connectors and Kelvin source signal terminal connectors of the same group of power switch chips are arranged coaxially and adjacently along the longitudinal direction. This maximizes the compression of the trace length of a single drive circuit, significantly reduces the parasitic inductance of the drive circuit, and ensures the consistency of the transmission of each drive signal. Simultaneously, all signal terminals are neatly arranged in the central area of ​​the module, completely avoiding the strong interference areas of the peripheral high-current power circuits, thus significantly reducing the risk of coupling interference between strong and weak current circuits from a spatial layout perspective. Furthermore, the two newly added drain terminals enable real-time sampling of the corresponding chip's operating status, facilitating rapid monitoring and protection against overcurrent and overvoltage faults in the subsequent system, further improving the reliability of the module's operation.

[0043] In some embodiments of this disclosure, the power switch chip includes at least one of the following: Insulated-gate bipolar transistor; Metal-oxide-semiconductor field-effect transistor; Silicon carbide power devices.

[0044] The medium-power switching chip selection of the three-level module disclosed herein covers mainstream power chip types on the market, such as insulated gate bipolar transistors, metal-oxide-semiconductor field-effect transistors, and silicon carbide power devices. Without changing the overall packaging structure of the module, the corresponding chip can be flexibly replaced according to the actual needs of different scenarios.

[0045] It should be noted that, Figure 5 This is a public response Figure 3 A schematic diagram showing the completed wiring status of the three-level module; Figure 6 This is a public response Figure 4 A schematic diagram showing the completed wiring status of the three-level module; Figure 7 This is a public response Figure 3 A schematic diagram of the structure of a three-level module; Figure 8 This is a public response Figure 4 A schematic diagram of the structure of a three-level module is provided. Those skilled in the art can refer to this diagram. Figure 5 and Figure 7 Clearly and Figure 3 For a diagram showing the physical connections and locations of the corresponding components, please refer to... Figure 6 and Figure 8 Clearly and Figure 4 A schematic diagram showing the physical connection relationships and locations of the corresponding components.

[0046] In summary, the three-level module of this disclosure includes a substrate, multiple signal lead-out units, and multiple power switch chips. The upper surface of the substrate has multiple mutually insulated power conductive regions. Each signal lead-out unit is disposed on the upper surface of the substrate, and each signal lead-out unit has multiple signal conductive regions on its upper surface. Each signal conductive region has a signal terminal connector extending perpendicular to the plane of the signal lead-out unit and away from the upper surface of the substrate. The multiple power switch chips respectively constitute an upper bridge arm switch group, a lower bridge arm switch group, and a clamping switch group. The power terminals of the power switch chips in each switch group are connected to the corresponding power conductive regions to complete the interconnection and conduction of the power circuit. The signal terminals of the power switch chips in each switch group are connected to the corresponding signal terminal connectors to receive drive signals, enabling the three-level module to selectively operate in a two-level inverter mode or a three-level inverter mode. This disclosure leads the signal terminals out along the direction perpendicular to the substrate, saving a large amount of space in the horizontal plane, significantly reducing the overall size of the module, and solving the problem of the large size of traditional single-phase three-level modules.

[0047] For ease of subsequent use, it can be modified. Figure 3 and Figure 4 The three-level module shown is packaged, wherein the three-level module is provided with power terminal docking terminals (such as P, N, M) and signal terminal connectors extending along a direction perpendicular to the upper surface of the module body. This disclosure allows the DC bus positive terminal metal bus, DC bus negative terminal metal bus, and midpoint potential terminal metal bus in the metal bus assembly to be electrically connected to their respective power terminal docking terminals. Each metal bus has a first clearance hole corresponding to the position of the signal terminal connector. The signal terminal connector passes through the corresponding first clearance hole and extends to the outer region of the metal bus assembly away from the module body.

[0048] The metal busbar assembly disclosed herein allows three metal busbars to be directly covered above the module body, forming a tightly fitted stacked busbar structure. This significantly reduces stray inductance in the three-level topology, effectively suppresses voltage spikes during the switching process of the power switch chip, solves the current sharing problem of parallel three-level modules, avoids power overload of a single module, reduces the debugging difficulty of the parallel system, significantly reduces the overall height of the power circuit, and allows the signal terminals to be directly connected to the upper driver board without the need for additional adapter sockets.

[0049] In some embodiments of this disclosure, the metal bus assembly includes a DC bus positive end metal bus, a DC bus negative end metal bus, and a midpoint potential end metal bus arranged sequentially; wherein, the DC bus positive end metal bus is further provided with a second clearance hole corresponding to the position of the midpoint potential end docking end; the DC bus negative end metal bus is further provided with a third clearance hole corresponding to the position of the midpoint potential end docking end; the midpoint potential end docking end passes through the second clearance hole and the third clearance hole in sequence and is electrically connected to the midpoint potential end metal bus.

[0050] In some embodiments of this disclosure, the metal busbar assembly extends outward along the longitudinal central axis of the module body to form a metal busbar extension section. The extension section has pre-reserved welding joints for welding and fixing to the corresponding terminals of the external busbar capacitor. The longitudinally extending metal busbar extension section of this disclosure can be directly aligned with the external busbar capacitor for welding and fixing without additional adapters, significantly reducing stray inductance in the main power circuit, suppressing switching voltage spikes, and improving module operational reliability.

[0051] In some embodiments of this disclosure, the external busbar capacitors include a first capacitor (i.e., first capacitor C1) and a second capacitor (i.e., second capacitor C2). A first welding joint is reserved on the outer extension of the positive end metal busbar of the DC busbar, a second welding joint is reserved on the outer extension of the negative end metal busbar of the DC busbar, and a third welding joint is reserved on the outer extension of the midpoint potential end metal busbar. The two ends of the first capacitor are electrically connected to the first welding joint and the third welding joint, respectively; the two ends of the second capacitor are electrically connected to the second welding joint and the third welding joint, respectively. The potential structure of the two sets of capacitors connected across the positive-midpoint and negative-midpoint of this disclosure allows for a more balanced voltage distribution on the DC busbar, effectively reducing busbar voltage ripple.

[0052] Based on the above embodiments, this disclosure also proposes a three-level power conversion system, which includes any of the three-level modules described above. Furthermore, the three-level power conversion system supports parallel expansion of multiple modules. Depending on actual application requirements, the system can implement parallel connection of nine or twelve power chips to improve the system's current output capability, thereby adapting to application scenarios with various power levels.

[0053] Based on the above embodiments, this disclosure also proposes a vehicle that includes any of the above three-level modules.

[0054] The vehicle can be a hybrid vehicle, a non-hybrid vehicle, an electric vehicle, a fuel cell vehicle, or other types of vehicles. The three-level module of this disclosure can be used as a power conversion device for the vehicle to achieve power transmission and voltage matching between the power battery and the drive motor. Due to the use of the aforementioned three-level module, the vehicle of this disclosure has the advantages of a compact system structure, high power density, and a wide bus voltage adaptation range, enabling it to adapt to the needs of drive systems with different power levels.

[0055] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this disclosure. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0056] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this disclosure, "a plurality of" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0057] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This disclosure is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the appended claims.

[0058] It should be understood that this disclosure is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this disclosure is limited only by the appended claims.

Claims

1. A three-level module (1000), characterized in that, include: A substrate (100) has a plurality of power conductive regions (110) that are mutually insulated on its upper surface. Multiple signal lead-out units (200) are disposed above the substrate (100). Each signal lead-out unit has multiple signal conductive areas on its upper surface. Each signal conductive area is provided with a signal terminal connector extending in a direction perpendicular to the plane where the signal lead-out unit is located and away from the upper surface of the substrate (100). Multiple power switch chips (300) respectively constitute an upper bridge arm switch group (M1), a lower bridge arm switch group (M2) and a clamping switch group. The power terminals of the power switch chips in each switch group are connected to the corresponding power conductive areas to complete the interconnection and conduction of the power circuit. The signal terminals of the power switch chips in each switch group are connected to the corresponding signal terminal connectors to receive drive signals, so that the three-level module (1000) can selectively operate in a two-level inverter mode or a three-level inverter mode.

2. The three-level module (1000) according to claim 1, characterized in that, The plurality of power conductive regions (110) include a DC bus positive terminal region (111), a DC bus negative terminal region (112), a midpoint potential region (113), an AC output terminal region (114), and an inter-bridge transition conductive region (115) for realizing power connection between adjacent bridge arms; wherein, Along the longitudinal central axis of the substrate (100), the midpoint potential region (113) and the AC output terminal region (114) are respectively located on opposite sides of the substrate (100). The DC bus positive terminal region (111), the DC bus negative terminal region (112), and the inter-bridge transition conductive region (115) are located in the middle region between the midpoint potential region (113) and the AC output terminal region (114).

3. The three-level module (1000) according to claim 2, characterized in that, The inter-bridge transition conductive region (115) includes a first transition conductive region (1151) and a second transition conductive region (1152); wherein, The first transition conductive region (1151) is located adjacent to the midpoint potential region (113) and away from the AC output terminal region (114); The second transition conductive region (1152) is located adjacent to the AC output terminal region (114) and away from the midpoint potential region (113); The negative end region (112) of the DC bus is located within the intermediate accommodating space formed by the first transition conductive region (1151) and the second transition conductive region (1152); The positive end region (111) of the DC bus is located on the outer side of the second transition conductive region (1152) away from the first transition conductive region (1151).

4. The three-level module (1000) according to claim 3, characterized in that, The power terminal of the power switch chip includes a drain; wherein, The drain of the power switch chip of the upper bridge arm switch group (M1) is fixed in the positive terminal region (111) of the DC bus by sintering. The drain of the power switch chip of the lower bridge arm switch group (M2) is fixed in the second transition conductive region (1152) by sintering. The drain of the power switch chip of the first switch group (U1) in the clamping switch group is fixed in the midpoint potential region (113) by sintering, and the drain of the power switch chip of the second switch group (U2) in the clamping switch group is fixed in the first transition conductive region (1151) by sintering.

5. The three-level embedded mode (1000) according to claim 4, characterized in that, The plurality of signal extraction units (200) are disposed on the upper surface of the substrate (100), and the vertical projection of each signal extraction unit on the substrate (100) does not overlap with the switch group corresponding to the signal extraction unit; The power terminal of the power switch chip also includes a power source; wherein, The power source of the power switch chip of the upper bridge arm switch group (M1) is electrically connected to the AC output terminal area (114) and the second transition conductive area (1152) respectively through a copper clip connection assembly. The power source of the power switch chip of the lower bridge arm switch group (M2) is electrically connected to the negative terminal area (112) of the DC bus using a copper clip connection assembly. The power source of the power switch chip in the first switch group (U1) is electrically connected to the power source of the power switch chip in the second switch group (U2) using a copper clip connection assembly.

6. The three-level module (1000) according to claim 4, characterized in that, The plurality of signal extraction units (200) are disposed above the substrate (100) and spaced apart from the upper surface of the substrate (100), and the vertical projection of each signal extraction unit on the substrate (100) overlaps at least partially with the switch group corresponding to the signal extraction unit. The power terminal of the power switch chip also includes a power source; wherein, The power source of the power switch chip of the upper bridge arm switch group (M1) is connected to the lower surface of the signal output unit corresponding to the upper bridge arm switch group (M1) through a copper pad connection assembly. The lower surface of the signal output unit corresponding to the upper bridge arm switch group (M1) is also electrically connected to the AC output terminal area (114) and the second transition conductive area (1152) respectively. The power source of the power switch chip of the lower bridge arm switch group (M2) is connected to the lower surface of the signal output unit corresponding to the lower bridge arm switch group (M2) through a copper pad connection assembly. The lower surface of the signal output unit corresponding to the lower bridge arm switch group (M2) is also electrically connected to the negative terminal area (112) of the DC bus. The power source of the power switch chip in the first switch group (U1) and the power source of the power switch chip in the second switch group (U2) are both connected to the lower surface of the signal output unit corresponding to the clamping switch group through a copper pad connection assembly.

7. The three-level module (1000) according to claim 1, characterized in that, The plurality of signal extraction units (200) are arranged sequentially along the longitudinal central axis of the substrate (100) as a first signal extraction unit (210), a second signal extraction unit (220), and a third signal extraction unit (230); wherein, The first signal output unit (210) is disposed above the first transition conductive region (1151) in the midpoint potential region (113) and the inter-bridge transition conductive region (115), and the power switch chips of the clamping switch group are symmetrically arranged along the longitudinal central axis of the substrate (100). The second signal output unit (220) is disposed above the second transition conductive region (1152) in the inter-bridge transition conductive region (115), and the power switch chips of the lower bridge arm switch group (M2) are symmetrically arranged along the longitudinal central axis of the substrate (100). The third signal output unit (230) is located above the positive end region (111) of the DC bus, and the power switch chips of the upper bridge arm switch group (M1) are arranged symmetrically along the longitudinal central axis of the substrate (100).

8. The three-level module (1000) according to claim 7, characterized in that, The plurality of signal extraction units (200) are disposed on the upper surface of the substrate (100), and the vertical projection of each signal extraction unit on the substrate (100) does not overlap with the switch group corresponding to the signal extraction unit; wherein, The signal terminal connector on the first signal output unit (210) includes a first signal terminal pin (211), a second signal terminal pin (212), and a third signal terminal pin (213) arranged sequentially along the longitudinal central axis of the first signal output unit (210). The first signal terminal pin (211) is used to electrically connect to the gate of the power switch chip of the first switch group (U1) in the clamping switch group. The second signal terminal pin (212) is used to electrically connect to the Kelvin source of the power switch chip of the first switch group (U1) and the power switch chip of the second switch group (U2) in the clamping switch group. The third signal terminal pin (213) is used to electrically connect to the gate of the power switch chip of the second switch group (U2). The signal terminal connector on the second signal output unit (220) includes a fourth signal terminal pin (221) and a fifth signal terminal pin (222) arranged sequentially along the longitudinal central axis of the second signal output unit (220). The fourth signal terminal pin (221) is used to electrically connect to the gate of the power switch chip of the lower bridge arm switch group (M2), and the fifth signal terminal pin (222) is used to electrically connect to the Kelvin source of the power switch chip of the lower bridge arm switch group (M2). The signal terminal connector on the third signal output unit (230) includes a sixth signal terminal pin (231) and a seventh signal terminal pin (232) arranged sequentially along the longitudinal central axis of the third signal output unit (230). The sixth signal terminal pin (231) is used to electrically connect to the gate of the power switch chip of the upper bridge arm switch group (M1), and the seventh signal terminal pin (232) is used to electrically connect to the Kelvin source of the power switch chip of the upper bridge arm switch group (M1).

9. The three-level module (1000) according to claim 7, characterized in that, The plurality of signal extraction units (200) are disposed above the substrate (100) and spaced apart from the upper surface of the substrate (100), and the vertical projection of each signal extraction unit on the substrate (100) overlaps at least partially with the switch group corresponding to the signal extraction unit. The signal terminal connector on the first signal output unit (210) includes a first signal terminal pin (211), a second signal terminal pin (212) and a third signal terminal pin (213) arranged sequentially along the transverse central axis of the first signal output unit (210). The signal terminal connector on the second signal lead-out unit (220) includes a fifth signal terminal pin (222) and a fourth signal terminal pin (221) arranged sequentially along the transverse central axis of the second signal lead-out unit (220). The signal terminal connector on the third signal output unit (230) includes a seventh signal terminal pin (232) and a sixth signal terminal pin (231) arranged sequentially along the transverse central axis of the third signal output unit (230).

10. The three-level module (1000) according to claim 8 or 9, characterized in that, The signal terminal connector further includes an eighth signal terminal pin (241); wherein... The eighth signal terminal pin (241) is disposed on the first signal lead-out unit (210) or on the fourth signal lead-out unit (240) disposed on the upper surface of the midpoint potential region (113), and is used to electrically connect to the drain of the power switch chip of the first switch group (U1).

11. The three-level module (1000) according to claim 8 or 9, characterized in that, The signal terminal connector further includes a ninth signal terminal pin (251); wherein... The ninth signal terminal pin (251) is disposed on the third signal lead-out unit (230) or on the fifth signal lead-out unit (250) disposed on the upper surface of the DC bus positive terminal region (111), and is used to electrically connect to the drain of the power switch chip of the upper bridge arm switch group (M1).

12. The three-level module (1000) according to any one of claims 1-9, characterized in that, The signal extraction unit is provided with a lower surface conductive metal layer, an insulating dielectric layer and an upper surface conductive metal layer in a direction perpendicular to the upper surface of the substrate (100) and away from the upper surface of the substrate (100).

13. A three-level power conversion system, characterized in that, include: The three-level module as described in any one of claims 1-12.

14. A vehicle, characterized in that, include: The three-level module as described in any one of claims 1-12.

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