Control method, controller, circuit and device for a parallel interleaved circuit

Abstract

The application discloses a control method, a controller, a circuit and equipment of a parallel interleaved circuit. The target values of the respective inductor currents of two flying capacitor three-level circuits in the interleaved parallel circuit are determined by reference current values provided by a voltage outer loop. Before the reference current values are distributed to current inner loop controllers of the two flying capacitor three-level circuits based on a preset distribution coefficient, in order to ensure that the inductor current does not appear zero-crossing under light load or no-load conditions, according to the current direction corresponding to the reference current value, a preset circulating current value is superimposed on a first current value in the same direction to obtain a first target value, and the preset circulating current value is superimposed on a second current value in the opposite direction to obtain a second target value, so as to forcibly increase the inductor current of one of the flying capacitor three-level circuits and decrease the inductor current of the other flying capacitor three-level circuit, so that the collected value of the inductor current can correctly reflect the direction of the inductor current, and the problem of circuit control error caused by zero-crossing of the inductor current is avoided.

Description

Technical Field

[0001] This application relates to the field of electronic circuit technology, and in particular to a control method, controller, circuit and device for parallel interleaved circuits. Background Technology

[0002] The flying capacitor three-level circuit has multiple operating modes. Whether the duty cycle of the flying capacitor is greater than or less than 0.5, and whether the inductor current is in the forward or reverse direction, will affect the charging and discharging state of the flying capacitor. Correctly detecting the direction of the inductor current is the key to ensuring the voltage balance of the flying capacitor.

[0003] Current technology typically uses AD sampling of the inductor current to determine the charging and discharging state of the flying capacitor. However, AD sampling yields the average value of the inductor current. Therefore, under light load or no-load conditions, during the period when the inductor current waveform crosses zero, the flying capacitor experiences both charging and discharging periods. Controlling the charging and discharging of the flying capacitor based on the sign of the average inductor current will lead to voltage imbalance. Summary of the Invention

[0004] This application provides a control method, controller, circuit, and device for parallel interleaved circuits, which can ensure that the direction of inductor current is not misjudged.

[0005] In a first aspect, embodiments of this application provide a control method for a parallel interleaved circuit, wherein the interleaved parallel circuit includes a first flying capacitor three-level circuit and a second flying capacitor three-level circuit connected in parallel to the busbar; the control method includes:

[0006] Obtain the reference current value output by the outer voltage loop of the interleaved parallel circuit;

[0007] The reference current value is divided into a first current value and a second current value according to a preset allocation coefficient;

[0008] Based on the current direction corresponding to the reference current value, a first target value is obtained by superimposing a preset circulating current value on the first current value in the same direction, and a second target value is obtained by superimposing the preset circulating current value on the second current value in the opposite direction.

[0009] The first target value is sent to the first current inner loop controller of the first flying capacitor three-level circuit, and the second target value is sent to the second current inner loop controller of the second flying capacitor three-level circuit.

[0010] In some embodiments, dividing the reference current value into a first current value and a second current value according to a preset allocation coefficient includes:

[0011] The product of the preset allocation coefficient and the reference current value is used as the first current value;

[0012] The result of subtracting the first current value from the reference current value is taken as the second current value.

[0013] In some embodiments, the step of obtaining a first target value by superimposing a preset circulating current value on the first current value in the same direction to obtain a second target value, and superimposing the preset circulating current value on the second current value in the opposite direction to obtain a second target value, includes at least one of the following:

[0014] If the current direction corresponding to the reference current value is the first direction, add the first current value to the preset circulating current value to obtain the first target value, and subtract the preset circulating current value from the second current value to obtain the second target value;

[0015] If the current direction corresponding to the reference current value is the second direction, subtract the preset circulating current value from the first current value to obtain the first target value, and add the preset circulating current value to the second current value to obtain the second target value;

[0016] Wherein, the first direction is opposite to the second direction.

[0017] In some embodiments, the first direction is the current direction of the interleaved parallel circuit from the input side to the output side, and the second direction is the current direction of the interleaved parallel circuit from the output side to the input side.

[0018] In some embodiments, obtaining the reference current value of the outer voltage loop of the interleaved parallel circuit includes:

[0019] Obtain the output value of the outer voltage loop of the interleaved parallel circuit, and determine the reference current value based on the magnitude and direction of the output value;

[0020] The reference current value is determined to be within the hysteresis interval, which is used to limit the applicable range of superimposed preset circulating current value.

[0021] In some embodiments, the reference current value within the hysteresis interval satisfies:

[0022] If the current direction corresponding to the reference current value is the first direction, the preset circulating current value is superimposed on the first current value in the same direction to make the inductor current valley value of the first flying capacitor three-level circuit greater than 0, and the preset circulating current value is superimposed on the second current value in the opposite direction to make the inductor current peak value of the second flying capacitor three-level circuit less than 0.

[0023] Alternatively, if the current direction corresponding to the reference current value is the second direction, the preset circulating current value is superimposed on the first current value in the same direction to make the peak value of the inductor current of the first flying capacitor three-level circuit less than 0, and the preset circulating current value is superimposed on the second current value in the opposite direction to make the valley value of the inductor current of the second flying capacitor three-level circuit greater than 0.

[0024] In some embodiments, the two endpoints of the hysteresis interval are the preset circulation value and the opposite of the preset circulation value, respectively.

[0025] In a second aspect, embodiments of this application provide a controller including at least one processor and a memory for communicatively connecting to the at least one processor; the memory stores instructions executable by the at least one processor to enable the at least one processor to perform the method as described in the first aspect.

[0026] Thirdly, embodiments of this application provide a parallel interleaved circuit, including the controller described in the second aspect.

[0027] Fourthly, embodiments of this application provide an inverter device including the parallel interleaved circuit as described in the third aspect.

[0028] The control method, controller, circuit, and device for parallel interleaved circuits in this application have at least the following beneficial effects: The target value of the inductor current of each of the two flying capacitor three-level circuits in the interleaved parallel circuit is determined by the reference current value provided by the voltage outer loop. Before allocating the reference current value to the current inner loop controller of the two flying capacitor three-level circuits based on the preset allocation coefficient, in order to ensure that the inductor current does not cross zero under light load or no load conditions, according to the current direction corresponding to the reference current value, a first target value is obtained by superimposing a preset circulating current value in the same direction on the first current value, and a second target value is obtained by superimposing a preset circulating current value in the opposite direction on the second current value. This forces the inductor current of one flying capacitor three-level circuit to be raised and the inductor current of the other flying capacitor three-level circuit to be lowered, so that the collected value of the inductor current can correctly reflect the direction of the inductor current and avoid the problem of circuit control error caused by the inductor current crossing zero.

[0029] Other features and advantages of this application will be set forth in the following description and will be apparent in part from the description or may be learned by practicing the application. The objectives and other advantages of this application may be realized and obtained by means of the structures particularly pointed out in the description and the accompanying drawings. Attached Figure Description

[0030] Figure 1A schematic diagram of the circuit and circulating current structure of a parallel interleaved circuit provided in one embodiment of this application;

[0031] Figure 2 A timing diagram of the charging and discharging phase of a flying capacitor under normal operating conditions provided in an embodiment of this application;

[0032] Figures 3a-3e A schematic diagram of the current flow direction of a flying capacitor three-level circuit in different modes according to an embodiment of this application;

[0033] Figure 4 A timing diagram of the charging and discharging phase of a flying capacitor under no-load or light-load conditions provided in one embodiment of this application;

[0034] Figure 5 A flowchart illustrating the overall process of a control method for an interleaved parallel circuit provided in one embodiment of this application;

[0035] Figure 6 This is a timing diagram of the charging and discharging stages of the flying capacitor under no-load or light-load conditions after superimposing a preset circulating current value according to an embodiment of this application.

[0036] Figure 7 A flowchart for determining a first current value and a second current value is provided as an embodiment of this application;

[0037] Figure 8 A flowchart for determining a first target value and a second target value is provided as an embodiment of this application;

[0038] Figure 9 A flowchart based on the superposition of preset circulation values ​​in hysteresis intervals is provided as an embodiment of this application;

[0039] Figure 10a and 10b A schematic diagram showing the hysteresis interval in a coordinate system according to an embodiment of this application;

[0040] Figure 11 This is a schematic diagram of the connection structure of a controller provided in one embodiment of this application. Detailed Implementation

[0041] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application. Furthermore, the features, operations, or characteristics described in the specification can be combined in any suitable manner to form various implementations. Simultaneously, the steps or actions described in the method description can be rearranged or adjusted in a manner readily apparent to those skilled in the art. Therefore, the various orders in the specification and drawings are merely for the clear description of a particular embodiment and do not imply a mandatory order, unless otherwise stated that a particular order must be followed.

[0042] In the description of this application, "several" means one or more, "more than" means two or more, "greater than," "less than," and "exceeding" are understood to exclude the stated number, while "above," "below," and "within" are understood to include the stated number. The use of "first" and "second" in the description is merely for distinguishing technical features and should not be construed as indicating or implying relative importance, or implicitly indicating the number of indicated technical features, or implicitly indicating the order of the indicated technical features.

[0043] The serial numbers assigned to components in this document, such as "first" and "second," are used only to distinguish the described objects and have no sequential or technical meaning. The terms "connection" and "linkage" used in this application, unless otherwise specified, include both direct and indirect connections (linkages).

[0044] In a three-level circuit with a flying capacitor (e.g., a three-level flying capacitor topology), the voltage of the flying capacitor is a crucial parameter. Whether it can be controlled to half the input / output voltage is key to the successful application of this topology. If the voltage of the flying capacitor exceeds or falls below half the input / output voltage, the switching devices in the circuit will experience greater voltage stress. If the device selection does not have sufficient margin, it can easily lead to damage to the switching devices. Therefore, controlling the voltage balance of the flying capacitor is a critical issue that must be addressed. Ideally, the controller of the three-level flying capacitor circuit controls the switching devices to charge or discharge the flying capacitor based on the direction of the current inductor current (forward or reverse). The charging and discharging time is determined by the duty cycle, and the charge and discharge capacity of the flying capacitor is balanced, meaning the charging time is equal to the discharging time.

[0045] For bidirectional buck-boost converters, when using a flying capacitor bidirectional buck-boost topology, the inductor current generates a zero-crossing waveform under light load or no-load conditions. Related technologies control the voltage balance of the flying capacitor based on duty cycle compensation after detecting the inductor current direction. However, due to sampling errors and other reasons, the current inductor current direction cannot be accurately detected under light load or no-load conditions, leading to detection failure and unstable voltage of the flying capacitor. In severe cases, the voltage of the flying capacitor becomes severely unbalanced, causing the system to malfunction.

[0046] Based on this, embodiments of this application provide a control method, controller, circuit, and device for parallel interleaved circuits. The target values ​​of the inductor currents of the two flying capacitor three-level circuits in the interleaved parallel circuit are determined by the reference current value provided by the outer voltage loop. Before allocating the reference current value to the inner current loop controllers of the two flying capacitor three-level circuits based on a preset allocation coefficient, in order to ensure that the inductor current does not cross zero under light load or no load conditions, a first target value is obtained by superimposing a preset circulating current value in the same direction on the first current value according to the current direction corresponding to the reference current value, and a second target value is obtained by superimposing a preset circulating current value in the opposite direction on the second current value. This forces the inductor current of one flying capacitor three-level circuit to be increased and the inductor current of the other flying capacitor three-level circuit to be decreased, so that the collected inductor current value can correctly reflect the direction of the inductor current and avoid the problem of circuit control errors caused by the inductor current crossing zero.

[0047] The control method, controller, circuit, and equipment for parallel interleaved circuits are described below with reference to the accompanying drawings.

[0048] The control method for parallel interleaved circuits provided in this application is applied to interleaved parallel circuits, which include a first flying capacitor three-level circuit and a second flying capacitor three-level circuit connected in parallel to the busbar; the circuit diagram of the interleaved parallel circuit is shown below. Figure 1 As shown, the first flying capacitor three-level circuit corresponds to Figure 1 The upper part of the circuit corresponds to the second flying capacitor three-level circuit. Figure 2 The upper part of the circuit, the first flying capacitor three-level circuit and the second flying capacitor three-level circuit are both flying capacitor three-level bidirectional buck-boost converter circuits, both of which are coupled to the energy storage side on one side. Figure 1 (represented by Vbat in Chinese), the other side is coupled to the bus side ( Figure 1(Vbus is used in this context). Therefore, topologically, the first and second flying capacitor three-level circuits are in parallel. From a control perspective, their switching devices use interleaved outputs to reduce output ripple. The interleaved parallel circuit uses closed-loop control to adjust its operating state based on feedforward or feedback signals. Generally, the interleaved parallel circuit has an outer voltage loop and an inner current loop. The outer voltage loop controls the bus voltage, and the inner current loop controls the inductor current. The output of the outer voltage loop provides a reference current for the inner current loop. Each flying capacitor three-level circuit adjusts its duty cycle according to the received target value. Typically, the first and second flying capacitor three-level circuits use the same / similar circuit components and an interleaved control method, and they are assigned the same target value. This allows the first and second flying capacitor three-level circuits to alternately output the same voltage, facilitating control.

[0049] Figure 1 The flying capacitor three-level circuit of the three-level bidirectional buck-boost converter topology has multiple operating modes. Whether the duty cycle is greater than or less than 0.5 in the same operating mode, and whether the inductor current is forward or reversed, will affect the charging and discharging state of the flying capacitor. Taking the Buck operating mode, with a duty cycle greater than 0.5 and the inductor current in the forward direction (flowing from the left input to the right output) as an example, the driving waveform is as follows: Figure 2 As shown. In this case, both Q21 and Q22 of the upper tube of the right arm are fully conductive. The specific operating mode is as follows: during the t0-t1 stage, as... Figure 3a With both Q11 and Q12 on the left arm fully conducting, the flying capacitor is neither charging nor discharging; during the t1-t2 phase, as Figure 3b When Q11 on the left arm is turned off and Q12 is turned on, the flying capacitor is in a discharging state; during the t2-t3 stage, as Figure 3a On the left arm, both Q11 and Q12 are fully conducting, and the flying capacitor is neither charging nor discharging; during the t3-t4 stage, as Figure 3c When Q11 in the left arm is turned on and Q12 is turned off, the flying capacitor is charging. It should be noted that if the inductor current reverses, then during the t1-t2 phase, the flying capacitor will be charging. Figure 3d As shown; corresponding to the t3-t4 stage, the flying capacitor is in a discharging state, as... Figure 3e As shown. This also indicates that accurate detection of the inductor current direction is crucial for ensuring voltage balance of the flying capacitor. However, under light load or no-load conditions, because the inductor current waveform crosses zero, that is, during the t1-t2 period, the flying capacitor is not simply discharging (inductor current in the forward direction) or charging (inductor current in the reverse direction), but rather experiences both charging and discharging periods within this timeframe. Similarly, during the t3-t4 period, the flying capacitor also experiences both charging and discharging periods, as shown. Figure 4As shown.

[0050] As previously mentioned, in interleaved parallel circuits under light load or no-load conditions, there is a problem with the inductor current crossing zero points. Current technologies typically use DSP devices to sample the inductor current using an analog-to-digital converter (ADC). Essentially, the sampled value is the average inductor current. For the aforementioned zero-crossing situation, it's difficult to detect the instantaneous direction of the inductor current. This leads to situations where, under light load or no-load conditions, the flying capacitor should be charging but is instead being discharged, or vice versa, resulting in an imbalance in the flying capacitor voltage. To ensure that the instantaneous direction of the inductor current matches the direction determined by the sampled value, the average inductor current must be greater than or less than zero. Furthermore, considering the inductor current ripple, the average inductor current must be greater than or less than a certain value to guarantee that the instantaneous direction of the inductor current matches the direction determined by the sampled value.

[0051] In this regard, refer to Figure 5 As shown, the control method provided in this application embodiment includes, but is not limited to, the following steps:

[0052] Step S110: Obtain the reference current value of the voltage outer loop output of the interleaved parallel circuit;

[0053] Step S120: Divide the reference current value into a first current value and a second current value according to a preset allocation coefficient;

[0054] Step S130: Based on the current direction corresponding to the reference current value, a first target value is obtained by superimposing a preset circulating current value in the same direction on the first current value, and a second target value is obtained by superimposing a preset circulating current value in the opposite direction on the second current value.

[0055] Step S140: Send the first target value to the first current inner loop controller of the first flying capacitor three-level circuit, and send the second target value to the second current inner loop controller of the second flying capacitor three-level circuit.

[0056] according to Figure 1The circuit diagram of the interleaved parallel circuit shows that the control algorithm consists of one voltage outer loop and two current inner loops. The total current output from the voltage outer loop is used as the reference current value, which is then divided into a first current value and a second current value according to a preset allocation coefficient. When superimposing the preset circulating current value, the current direction needs to be considered. Taking a positive current direction (input from left to output) as an example, if the current direction corresponding to the reference current value is positive, then the first and second current values ​​are also positive. The first current value is increased by the preset circulating current value to obtain the first target value, and the second current value is decreased by the preset circulating current value to obtain the second target value. If the current direction corresponding to the reference current value is reversed, then the first and second current values ​​are also reversed. The first current value is decreased by the preset circulating current value to obtain the first target value, and the second current value is increased by the preset circulating current value to obtain the second target value. The first target value is then sent to the current inner loop controller of the first flying capacitor three-level circuit, and the second target value is sent to the current inner loop controller of the second flying capacitor three-level circuit. The two current inner loop controllers control the circuit according to their respective target values. It should be noted that the reference... Figure 1 As shown, the embodiments of this application utilize the topological characteristics of interleaved parallel circuits, which is equivalent to constructing a circulating current corresponding to a preset circulating current value between the first flying capacitor three-level circuit and the second flying capacitor three-level circuit. This circulating current has a unidirectional direction, allowing it to be superimposed in the same direction on the first flying capacitor three-level circuit and in the opposite direction on the second flying capacitor three-level circuit. Taking a Buck mode with a duty cycle greater than 0.5 as an example, the constructed circulating current is as follows: Figure 1 As shown by the blue line in the image, the inductor current waveform is as follows: Figure 6 As shown in the diagram, under no-load conditions, the inductor current in one of the three-level circuits of the flying capacitor is a positive current with an average value much greater than zero, while the inductor current in the other three-level circuit of the flying capacitor is a negative current with an average value much less than zero. Thus, determining the current direction based on the sampled inductor current value, i.e., the average inductor current, is definite, and consequently, controlling the charging and discharging state of the flying capacitor voltage is also definite. Incorrect current direction determination will not lead to incorrect charging and discharging states of the flying capacitor voltage, thus preventing voltage imbalance.

[0057] The preset allocation coefficient is a proportional coefficient used to divide the reference current value into two current inner loops; the preset circulating current value is set according to actual needs, such as considering the ripple size of the interleaved parallel circuit.

[0058] The above steps change the method of directly allocating the reference current value to the two current inner loop controllers according to the preset allocation coefficient. Instead, a step of superimposing the preset circulating current value is added. That is, by superimposing the preset circulating current value in the same direction and in opposite directions on the two flying capacitor three-level circuits respectively, the inductor current of one flying capacitor three-level circuit is increased and the inductor current of the other flying capacitor three-level circuit is decreased. This allows the sampled value of the inductor current to correctly reflect the direction of the inductor current and avoids the problem of circuit control errors caused by the inductor current crossing the zero point.

[0059] Reference Figure 7 As shown, in some embodiments, step S120 above, which divides the reference current value into a first current value and a second current value according to a preset allocation coefficient, includes:

[0060] Step S210: The product of the preset allocation coefficient and the reference current value is used as the first current value;

[0061] Step S220: Subtract the first current value from the reference current value to obtain the second current value.

[0062] Assume the reference current value is i ref If the preset allocation coefficient is k, then the first current value is k×i. ref The second current value is (1-k)×i ref In the actual calculation process, in addition to subtracting the current value as in step S220, it is also possible to calculate 1-k based on the preset allocation coefficient k and then compare it with the reference current value i. ref Multiplying them together gives the second current value.

[0063] Reference Figure 8 As shown, in some embodiments, the step S130 above, which involves superimposing a preset circulating current value on the first current value in the same direction to obtain a first target value and superimposing a preset circulating current value on the second current value in the opposite direction to obtain a second target value, includes at least one of the following:

[0064] Step S310: If the current direction corresponding to the reference current value is the first direction, add the first current value to the preset circulating current value to obtain the first target value, and subtract the preset circulating current value from the second current value to obtain the second target value.

[0065] Step S320: If the current direction corresponding to the reference current value is the second direction, subtract the preset circulating current value from the first current value to obtain the first target value, and add the preset circulating current value to the second current value to obtain the second target value.

[0066] The first direction is opposite to the second direction.

[0067] Taking the example of current flowing from the left input to the right output in a positive direction, the preset circulating current value is i. LOOPAssuming the first direction is the positive current direction and the reference current value is i ref If the corresponding current direction is also the first direction, then the first target value is the first current value superimposed with the preset circulating current value i in the first direction. LOOP Then we get k×i ref +i LOOP The second target value is obtained by superimposing a preset circulating current value i on the second current value in the second direction. LOOP Then we get (1-k)×i ref -i LOOP Assume the first direction is the positive current direction and the reference current value is i. ref If the corresponding current direction is the second direction, then the first target value is the first current value superimposed with a preset circulating current value i in the first direction. LOOP Then we get k×i ref -i LOOP The second target value is obtained by superimposing a preset circulating current value i on the second current value in the second direction. LOOP Then we get (1-k)×i ref +i LOOP .

[0068] It is worth noting that, Figure 1 The interleaved parallel circuit is a bidirectional buck-boost converter circuit. Therefore, the current direction is determined from the input side to the output side. Specifically, the first direction is the current direction from the input side to the output side, and the second direction is the current direction from the output side to the input side. When the energy storage side Vbat supplies power to the bus side Vbus, the first direction is from left to right; when the bus side Vbus supplies power to the energy storage side Vbat, the first direction is from right to left.

[0069] Reference Figure 9 As shown, in some embodiments, obtaining the reference current value of the outer voltage loop of the interleaved parallel circuit in step S110 includes:

[0070] Step S410: Obtain the output value of the outer voltage loop of the interleaved parallel circuit, and determine the reference current value based on the magnitude and direction of the output value;

[0071] Step S420: Determine that the reference current value is within the hysteresis interval. The hysteresis interval is used to limit the applicable range of the superimposed preset circulating current value.

[0072] The voltage outer loop can detect the magnitude and direction of the output value using methods such as Hall sensors, and then convert it into a reference current value i. ref The magnitude and direction of the voltage. The reference current value i of the outer voltage loop. ref With directionality, the outer voltage loop determines the reference current value i according to the first and second directions mentioned above. refThe corresponding current direction is determined, and the current is divided into a first current value and a second current value according to a preset allocation coefficient, and then the reference current value i is used. ref The corresponding current direction is achieved by superimposing a preset circulating current value i on the first current value and the second current value, respectively. LOOP In this embodiment, a preset circulation value i is superimposed. LOOP A condition has been added beforehand: first, the reference current value i is checked. ref Is it within the hysteresis interval? This hysteresis interval is used to avoid the following situation: assuming the reference current value i... ref If (1-k)×i is a positive value (in the first direction), then... ref and i LOOP When very close, the calculated second target value is (1-k)×i ref -i LOOP The calculated result is very small; similarly, assuming the reference current value i ref For negative values ​​(second direction), (1-k)×i ref +i LOOP The calculated result is very small. In both cases, the inductor current is in a zero-crossing waveform, which can lead to inaccurate current direction detection. The endpoint values ​​of the hysteresis interval can be set according to actual needs, as long as the final calculated inductor current is less than zero to a certain extent without causing misjudgment of current direction detection. In other words, the reference current value i ref Within the hysteresis interval, the preset circulation value i is superimposed in step S130 above. LOOp The steps, referencing the current value i ref Outside the hysteresis interval, the preset circulation value i is not superimposed. LOOP The first and second current values ​​are directly allocated to the corresponding current inner loop control in the conventional manner.

[0073] The hysteresis interval is used to ensure the superposition of the preset circulation value i LOOP The target value can help the system stably determine the direction of the inductor current. Specifically, refer to Figure 10a and Figure 10b As shown, the reference current value within the hysteresis interval satisfies:

[0074] If the current direction corresponding to the reference current value is the first direction, the preset circulating current value is superimposed on the first current value in the same direction to make the inductor current valley value of the first flying capacitor three-level circuit greater than 0, and the preset circulating current value is superimposed on the second current value in the opposite direction to make the inductor current peak value of the second flying capacitor three-level circuit less than 0.

[0075] Alternatively, if the current direction corresponding to the reference current value is the second direction, the inductor current peak value of the first flying capacitor three-level circuit is less than 0 after the preset circulating current value is superimposed on the first current value in the same direction, and the inductor current valley value of the second flying capacitor three-level circuit is greater than 0 after the preset circulating current value is superimposed on the second current value in the opposite direction.

[0076] In some embodiments, the two endpoints of the hysteresis interval are a preset circulation value and the opposite of the preset circulation value, respectively. That is, the hysteresis interval is [-i LOOP i LOOP ].

[0077] Through the above steps, the target values ​​of the inductor currents of the two flying capacitor three-level circuits in the interleaved parallel circuit are determined by the reference current value provided by the voltage outer loop. Before allocating the reference current value to the inner loop current controllers of the two flying capacitor three-level circuits based on the preset allocation coefficient, in order to ensure that the inductor current does not cross zero under light load or no load conditions, according to the current direction corresponding to the reference current value, a first target value is obtained by superimposing a preset circulating current value in the same direction on the first current value, and a second target value is obtained by superimposing a preset circulating current value in the opposite direction on the second current value. This forces the inductor current of one flying capacitor three-level circuit to be increased and the inductor current of the other flying capacitor three-level circuit to be decreased, so that the sampled value of the inductor current can correctly reflect the direction of the inductor current and avoid the problem of circuit control errors caused by the inductor current crossing zero.

[0078] The control method of the parallel interleaved circuit of this application will be described in detail below through a specific example.

[0079] Based on the characteristics of interleaved parallel topology, a circulating current is constructed between the two interleaved modules (flying capacitor three-level circuit) to solve the problem of voltage imbalance in the flying capacitor under light load or no-load conditions in the application of the flying capacitor three-level bidirectional buck-boost topology. The algorithm is illustrated using a Buck operating mode with a duty cycle greater than 0.5. It consists of an outer voltage loop and two inner current loops. The outer voltage loop controls the bus voltage Vbus, and the two inner current loops control the inductor currents of the two interleaved parallel modules respectively. The output value of the outer voltage loop is the total current reference value i. ref And the values ​​are positive, and are distributed to the target values ​​of the two inductor currents according to a certain proportional coefficient k. In this example, k = 5, and the preset circulating current value i is used. LOOP =3A; when the total current reference value i of the voltage outer loop output is... ref In [-i LOOP i LOOP When the current is between 0.5 and 1, the reference value (first target value) of the inductor current in the first flying capacitor three-level circuit is 0.5*i. ref+3A, the reference value (second target value) of the inductor current in the second flying capacitor three-level circuit is 0.5*i ref -3A; when the total current reference value of the voltage outer loop output is i ref More than [-i LOOP i LOOP When the current is within the specified range, circulating current is no longer constructed between the interleaved parallel modules. At this time, the reference value (first target value) of the inductor current of the first flying capacitor three-level circuit is 0.5*i. ref The reference value (second target value) of the inductor current in the second flying capacitor three-level circuit is 0.5*i. ref .

[0080] like Figure 11 As shown, Figure 11 This is a schematic diagram of a controller 1000 provided in one embodiment of this application.

[0081] The controller 1000 in this embodiment includes one or more processors 1001 and a memory 1002. Figure 11 The example uses a processor 1001 and a memory 1002.

[0082] Processor 1001 and memory 1002 can be connected via a bus or other means. Figure 11 Taking the example of a connection between China and Israel via a bus.

[0083] Memory 1002, as a non-transitory computer-readable storage medium, can be used to store non-transitory software programs and non-transitory computer-executable programs. Furthermore, memory 1002 may include high-speed random access memory, and may also include non-transitory memory, such as at least one disk storage device, flash memory device, or other non-transitory solid-state storage device. In some embodiments, memory 1002 may optionally include memory 1002 remotely located relative to processor 1001, and these remote memories can be connected to controller 1000 via a network. Examples of such networks include, but are not limited to, the Internet, intranets, local area networks, mobile communication networks, and combinations thereof.

[0084] Those skilled in the art will understand that Figure 11 The device structure shown does not constitute a limitation on the controller 1000 and may include more or fewer components than shown, or combine certain components, or have different component arrangements.

[0085] This application also provides an inverter device, including the aforementioned controller 1000.

[0086] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate; that is, they may be located in one place or distributed across multiple network nodes. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs.

[0087] It will be understood by those skilled in the art that all or some of the steps and systems in the methods disclosed above can be implemented as software, firmware, hardware, and suitable combinations thereof. Some or all of the physical components can be implemented as software executed by a processor, such as a central processing unit, digital signal processor, or microprocessor, or as hardware, or as an integrated circuit, such as an application-specific integrated circuit. Such software can be distributed on a computer-readable medium, which can include computer storage media (or non-transitory media) and communication media (or transient media). As is known to those skilled in the art, the term computer storage media includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules, or other data). Computer storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technologies, CD-ROM, digital versatile disc (DVD) or other optical disc storage, magnetic cartridges, magnetic tape, disk storage or other magnetic storage devices, or any other medium that can be used to store desired information and is accessible to a computer. Furthermore, as is known to those skilled in the art, communication media typically contain computer-readable instructions, data structures, program modules, or other data in modulated data signals such as carrier waves or other transmission mechanisms, and may include any information delivery medium.

[0088] It should be understood that in this application, "at least one (item)" means one or more, and "more than" means two or more. "And / or" is used to describe the relationship between related objects, indicating that three relationships can exist. For example, "A and / or B" can represent three cases: only A exists, only B exists, and both A and B exist simultaneously, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. "At least one (item) of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one (item) of a, b, or c can represent: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, and c can be single or multiple.

[0089] In the several embodiments provided in this application, it should be understood that the disclosed systems, instruments, and methods can be implemented in other ways. For example, the instrument embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the shown or discussed mutual couplings, direct couplings, or communication connections may be through some interfaces; indirect couplings or communication connections between instruments or units may be electrical, mechanical, or other forms. Units described as separate components may or may not be physically separate, and components shown as units may or may not be physical units, i.e., they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0090] It should also be understood that the various implementation methods provided in this application can be combined arbitrarily to achieve different technical effects.

[0091] The above is a detailed description of the preferred embodiments of this application. However, this application is not limited to the above embodiments. Those skilled in the art can make various equivalent modifications or substitutions without departing from the spirit of this application. All such equivalent modifications or substitutions are included within the scope defined by the claims of this application.

Claims

1. A control method for parallel interleaved circuits, characterized in that, The interleaved parallel circuit includes a first flying capacitor three-level circuit and a second flying capacitor three-level circuit connected in parallel to the busbar; the control method includes: Obtain the reference current value output by the outer voltage loop of the interleaved parallel circuit; The reference current value is divided into a first current value and a second current value according to a preset allocation coefficient; Based on the current direction corresponding to the reference current value, a first target value is obtained by superimposing a preset circulating current value on the first current value in the same direction, and a second target value is obtained by superimposing the preset circulating current value on the second current value in the opposite direction. The first target value is sent to the first current inner loop controller of the first flying capacitor three-level circuit, and the second target value is sent to the second current inner loop controller of the second flying capacitor three-level circuit.

2. The method according to claim 1, characterized in that, The step of dividing the reference current value into a first current value and a second current value according to a preset allocation coefficient includes: The product of the preset allocation coefficient and the reference current value is used as the first current value; The result of subtracting the first current value from the reference current value is taken as the second current value.

3. The method according to claim 1, characterized in that, The method of obtaining a first target value by superimposing a preset circulating current value on the first current value in the same direction to obtain a second target value, and the method of obtaining a second target value by superimposing the preset circulating current value on the second current value in the opposite direction to obtain a second target value, includes at least one of the following: If the current direction corresponding to the reference current value is the first direction, add the first current value to the preset circulating current value to obtain the first target value, and subtract the preset circulating current value from the second current value to obtain the second target value; If the current direction corresponding to the reference current value is the second direction, subtract the preset circulating current value from the first current value to obtain the first target value, and add the preset circulating current value to the second current value to obtain the second target value; Wherein, the first direction is opposite to the second direction.

4. The method according to claim 3, characterized in that, The first direction is the current direction of the interleaved parallel circuit from the input side to the output side, and the second direction is the current direction of the interleaved parallel circuit from the output side to the input side.

5. The method according to claim 3, characterized in that, Obtaining the reference current value of the outer voltage loop of the interleaved parallel circuit includes: Obtain the output value of the outer voltage loop of the interleaved parallel circuit, and determine the reference current value based on the magnitude and direction of the output value; The reference current value is determined to be within the hysteresis interval, which is used to limit the applicable range of superimposed preset circulating current value.

6. The method according to claim 5, characterized in that, The reference current value within the hysteresis interval satisfies: If the current direction corresponding to the reference current value is the first direction, the preset circulating current value is superimposed on the first current value in the same direction to make the inductor current valley value of the first flying capacitor three-level circuit greater than 0, and the preset circulating current value is superimposed on the second current value in the opposite direction to make the inductor current peak value of the second flying capacitor three-level circuit less than 0. Alternatively, if the current direction corresponding to the reference current value is the second direction, the preset circulating current value is superimposed on the first current value in the same direction to make the peak value of the inductor current of the first flying capacitor three-level circuit less than 0, and the preset circulating current value is superimposed on the second current value in the opposite direction to make the valley value of the inductor current of the second flying capacitor three-level circuit greater than 0.

7. The method according to claim 5 or 6, characterized in that, The two endpoints of the hysteresis interval are the preset circulation value and the opposite of the preset circulation value, respectively.

8. A controller, characterized in that, It includes at least one processor and a memory for communicatively connecting to the at least one processor; the memory stores instructions executable by the at least one processor to enable the at least one processor to perform the method as described in any one of claims 1 to 7.

9. A parallel interleaved circuit, characterized in that, Includes the controller as described in claim 8.

10. An inverter device, characterized in that, Includes the parallel interleaved circuit as described in claim 9.

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