Driving method, controller, circuit and device of flying capacitor three-level circuit

Abstract

The application discloses a flying capacitor three-level circuit driving method, a controller, a circuit and equipment. Based on a voltage feedforward module, on the basis of the voltage regulation amount output in the current inner loop and the output voltage of the flying capacitor three-level circuit, the preset layering coefficient is superimposed and processed to obtain a target modulation wave. Then, the target modulation wave is compared with a first carrier wave to obtain a first driving signal for driving a first bridge arm. The target modulation wave is subtracted by the preset layering coefficient and compared with a second carrier wave to obtain a second driving signal for driving a second bridge arm. By using the in-phase layering carrier wave technology, when the target modulation wave is compared with the second carrier wave, the second carrier wave is equivalent to being processed by upward layering, different driving signals are obtained by comparing one target modulation wave with two bridge arms respectively, the system operation mode can be automatically and smoothly switched under different input and output voltage conditions, and the stability and continuity of the system are improved.

Description

Technical Field

[0001] This application relates to the field of electronic circuit technology, and in particular to a driving method, controller, circuit and device for a flying capacitor three-level circuit. Background Technology

[0002] This bidirectional DC-DC converter, employing a flying capacitor three-level topology, needs to determine the battery voltage (input side relative to the converter) and the bus voltage (output side relative to the converter) to switch operating modes. When the battery voltage is lower than the bus voltage, the converter operates in Boost mode when the battery is discharging and in Buck mode when the battery is charging. When the battery voltage is higher than the bus voltage, the converter operates in Buck mode when the battery is discharging and in Boost mode when the battery is charging. When the battery voltage is close to the bus voltage, the converter operates in Buck-Boost mode.

[0003] Current technologies use voltage detection combined with logic judgment to switch modes of a flying capacitor three-level circuit. The switching process is not smooth and the stability of the circuit needs to be considered, making the control relatively complex. Summary of the Invention

[0004] This application provides a driving method, controller, circuit, and device for a flying capacitor three-level circuit, which can realize automatic and smooth switching of the working mode of the flying capacitor three-level circuit, thereby improving the stability and continuity of the system.

[0005] In a first aspect, embodiments of this application provide a driving method for a flying capacitor three-level circuit, the flying capacitor three-level circuit including a first bridge arm, a second bridge arm, and a voltage feedforward module; the driving method includes:

[0006] Obtain the voltage regulation amount of the inner current loop output;

[0007] The voltage feedforward module superimposes a preset layering coefficient onto the voltage regulation amount and the output voltage of the flying capacitor three-level circuit and processes them to obtain the target modulation wave; the preset layering coefficient is a value between 0 and 1.

[0008] The first carrier corresponding to the first bridge arm is compared with the target modulation wave to determine the first driving signal, and the second carrier corresponding to the second bridge arm is reduced by the preset stacking coefficient and then compared with the target modulation wave to determine the second driving signal.

[0009] The first bridge arm is driven according to the first drive signal, and the second bridge arm is driven according to the second drive signal.

[0010] In some embodiments, the inner current loop includes a subtractor and a proportional-integral controller. The subtractor is used to subtract the reference signal from the feedback signal of the flying capacitor three-level circuit. The output of the subtractor is connected to the input of the proportional-integral controller, and the output of the proportional-integral controller is used to output the voltage regulation amount.

[0011] In some embodiments, the step of superimposing a preset stacking coefficient on the voltage regulation amount and the output voltage of the flying capacitor three-level circuit and performing normalization processing to obtain the target modulation wave includes:

[0012] The product of the preset stacking coefficient and the output voltage is superimposed on the output voltage of the flying capacitor three-level circuit, and the product is added to the voltage adjustment amount to obtain the voltage output value;

[0013] The input voltage of the flying capacitor three-level circuit is obtained, and the voltage output value is normalized according to the input voltage and the output voltage to obtain the target modulation wave.

[0014] In some embodiments, the normalization process of the voltage output value based on the input voltage and the output voltage includes:

[0015] Determine the sum of the input voltage and the output voltage;

[0016] The target modulation wave is obtained by dividing the voltage output value by the sum of the voltages, and the target modulation wave is a value between 0 and 1+k.

[0017] In some embodiments, the flying capacitor three-level circuit further includes a normalization processing module, which includes a first adder, a second adder, and a divider. The first adder is used to superimpose the product of the preset stacking coefficient and the output voltage on the output voltage of the flying capacitor three-level circuit. The second adder is coupled to the output terminal of the first adder and is used to output the sum of the input voltage and the output voltage. The divider is coupled to the output terminal of the second adder and is used to divide the output voltage value by the sum of the voltages to obtain the target modulation wave.

[0018] In some embodiments, comparing the first carrier wave corresponding to the first bridge arm with the target modulation wave to determine the first driving signal includes:

[0019] Compare the amplitudes of the first carrier wave and the target modulated wave;

[0020] The high-level portion of the first driving signal is determined based on the time period during which the first carrier wave is lower than the target modulation wave, and the low-level portion of the first driving signal is determined based on the time period during which the first carrier wave is higher than the target modulation wave.

[0021] In some embodiments, the first carrier includes a complementary first waveform and a second waveform, and the first driving signal includes a first duty cycle signal corresponding to the first waveform and a second duty cycle signal corresponding to the second waveform;

[0022] The first bridge arm includes a first switch, a second switch, a third switch, and a fourth switch connected in series from the positive terminal to the negative terminal of the bus. The first duty cycle signal is used to drive the first switch, the second duty cycle signal is used to drive the second switch, the complementary signal of the first duty cycle signal is used to drive the fourth switch, and the complementary signal of the second duty cycle signal is used to drive the third switch.

[0023] In some embodiments, the step of comparing the second carrier corresponding to the second bridge arm with the target modulation wave after reducing the preset stacking coefficient to determine the second driving signal includes:

[0024] The third carrier is obtained by reducing the amplitude of the second carrier by the preset stacking coefficient;

[0025] Compare the amplitudes of the third carrier wave and the target modulation wave;

[0026] The low-level portion of the second driving signal is determined based on the time period during which the third carrier wave is lower than the target modulation wave, and the high-level portion of the second driving signal is determined based on the time period during which the third carrier wave is higher than the target modulation wave.

[0027] In some embodiments, the second carrier includes complementary third and fourth waveforms, and the second drive signal includes a third duty cycle signal corresponding to the third waveform and a fourth duty cycle signal corresponding to the fourth waveform;

[0028] The second bridge arm includes a fifth switch, a sixth switch, a seventh switch, and an eighth switch connected in series from the positive terminal to the negative terminal of the busbar. The third duty cycle signal is used to drive the fifth switch, the fourth duty cycle signal is used to drive the sixth switch, the complementary signal of the third duty cycle signal is used to drive the eighth switch, and the complementary signal of the fourth duty cycle signal is used to drive the seventh switch.

[0029] In a second aspect, embodiments of this application provide a controller including at least one processor and a memory for communicatively connecting to the at least one processor; the memory stores instructions executable by the at least one processor to enable the at least one processor to perform the method as described in the first aspect.

[0030] Thirdly, embodiments of this application provide a flying capacitor three-level circuit, including the controller as described in the second aspect.

[0031] In some embodiments, the flying capacitor three-level circuit is composed of two flying capacitor three-level bidirectional buck-boost circuits connected in parallel with alternating connections, and each of the two flying capacitor three-level bidirectional buck-boost circuits is applied to the method described in the first aspect through the controller.

[0032] Fourthly, embodiments of this application provide an inverter device including a flying capacitor three-level circuit as described in the third aspect.

[0033] The driving method, controller, circuit, and device for the flying capacitor three-level circuit of this application have at least the following beneficial effects: Based on the voltage feedforward module, the target modulation wave is obtained by superimposing a preset stacking coefficient on the voltage regulation amount output by the current inner loop and the output voltage of the flying capacitor three-level circuit. Then, the target modulation wave is compared with the first carrier of the first bridge arm to obtain the first driving signal for driving the first bridge arm. The target modulation wave is subtracted from the preset stacking coefficient and compared with the second carrier of the second bridge arm to obtain the second driving signal for driving the second bridge arm. The above driving method superimposes the preset stacking coefficient to obtain the target modulation wave. By using the in-phase stacked carrier technology, when the target modulation wave is compared with the second carrier, it is equivalent to stacking the second carrier upward. This realizes that one target modulation wave is compared with the carriers of the two bridge arms to obtain different driving signals. The target modulation wave is obtained based on the voltage regulation amount reflecting the current operating condition of the flying capacitor three-level circuit. Therefore, it can ensure that the system operating mode can be automatically and smoothly switched under different input and output voltage conditions, thereby improving the stability and continuity of the system.

[0034] Other features and advantages of this application will be set forth in the following description and will be apparent in part from the description or may be learned by practicing the application. The objectives and other advantages of this application may be realized and obtained by means of the structures particularly pointed out in the description and the accompanying drawings. Attached Figure Description

[0035] Figure 1 A circuit diagram of a flying capacitor three-level circuit provided in one embodiment of this application;

[0036] Figure 2This is an overall flowchart of a driving method provided in one embodiment of this application;

[0037] Figure 3 A circuit module connection diagram for outputting a target modulated wave is provided for one embodiment of this application;

[0038] Figure 4 A flowchart for determining a target modulation wave is provided in one embodiment of this application;

[0039] Figure 5 A flowchart illustrating the normalization process provided in one embodiment of this application;

[0040] Figure 6 A flowchart for determining the duty cycle of a first drive signal, provided as an embodiment of this application;

[0041] Figure 7 A flowchart for determining the duty cycle of a second drive signal, provided as an embodiment of this application;

[0042] Figure 8 A circuit module connection diagram for the output duty cycle signal provided in one embodiment of this application;

[0043] Figures 9a to 9c Timing diagrams for different modes provided in one embodiment of this application;

[0044] Figure 10 A coordinate graph showing the relationship between the target modulation wave and the duty cycle provided in one embodiment of this application;

[0045] Figure 11 This is a schematic diagram of the connection structure of a controller provided in one embodiment of this application. Detailed Implementation

[0046] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application. Furthermore, the features, operations, or characteristics described in the specification can be combined in any suitable manner to form various implementations. Simultaneously, the steps or actions described in the method description can be rearranged or adjusted in a manner readily apparent to those skilled in the art. Therefore, the various orders in the specification and drawings are merely for the clear description of a particular embodiment and do not imply a mandatory order, unless otherwise stated that a particular order must be followed.

[0047] In the description of this application, "several" means one or more, "more than" means two or more, "greater than," "less than," and "exceeding" are understood to exclude the stated number, while "above," "below," and "within" are understood to include the stated number. The use of "first" and "second" in the description is merely for distinguishing technical features and should not be construed as indicating or implying relative importance, or implicitly indicating the number of indicated technical features, or implicitly indicating the order of the indicated technical features.

[0048] The serial numbers assigned to components in this document, such as "first" and "second," are used only to distinguish the described objects and have no sequential or technical meaning. The terms "connection" and "linkage" used in this application, unless otherwise specified, include both direct and indirect connections (linkages).

[0049] Bidirectional buck-boost three-level circuits with flying capacitors are frequently used in products in the photovoltaic, energy storage, and other new energy industries. Energy storage products require bidirectional DC-DC conversion due to their charging and discharging needs. Furthermore, when the battery-side voltage (input relative to the converter) and the bus voltage (output relative to the converter) are at uncertain values, a bidirectional buck-boost topology is required. For example, when the battery voltage is less than the bus voltage, the converter's discharge (output power from the battery) is in Boost mode, and its charging (from external input power to the battery) is in Buck mode; when the battery voltage is greater than the bus voltage, the converter's discharge is in Buck mode, and its charging is in Boost mode; when the input and output voltages are close, the converter operates in Buck-Boost mode. Considering this scenario and the relatively high system voltage (up to 1500V), a bidirectional buck-boost DC-DC converter topology with flying capacitors is adopted, such as... Figure 1 As shown.

[0050] In practical operation, the flying capacitor three-level bidirectional buck-boost DC-DC converter switches between different modes. The switching state of the control transistors changes the current direction to correspond to different modes, and the switching state of the transistors is determined by the duty cycle of the PWM signal. Ideally, the transistors switch instantaneously according to the PWM signal; however, in reality, considering factors such as the switching time of the transistors, the switching between modes is not smooth. Currently, there is no technology in related fields to address smooth switching between modes.

[0051] Based on this, embodiments of this application provide a driving method, controller, circuit, and device for a flying capacitor three-level circuit. Based on a voltage feedforward module, a target modulation wave is obtained by superimposing a preset stacking coefficient on the voltage regulation output of the current inner loop and the output voltage of the flying capacitor three-level circuit. The target modulation wave is then compared with the first carrier wave of the first bridge arm to obtain a first driving signal for the first bridge arm. The target modulation wave is then subtracted from the preset stacking coefficient and compared with the second carrier wave of the second bridge arm to obtain a second driving signal for the second bridge arm. The above driving method superimposes a preset stacking coefficient to obtain the target modulation wave. Utilizing in-phase stacked carrier technology, when comparing the target modulation wave with the second carrier wave, it is equivalent to stacking the second carrier wave upwards. This achieves different driving signals obtained by comparing a target modulation wave with the carrier waves of the two bridge arms. The target modulation wave is obtained based on the voltage regulation reflecting the current operating condition of the flying capacitor three-level circuit. Therefore, it can ensure that the system operating mode can automatically and smoothly switch under different input and output voltage conditions, improving the stability and continuity of the system.

[0052] The following description, in conjunction with the accompanying drawings, explains the driving method, controller, circuit, and equipment of the flying capacitor three-level circuit.

[0053] Reference Figure 2 As shown, Figure 2 The driving method for the flying capacitor three-level circuit provided in this application embodiment includes a first bridge arm 11, a voltage feedforward module, and the following driving method:

[0054] Step S110: Obtain the voltage regulation amount δV of the inner current loop output;

[0055] Step S120: The target modulation wave is obtained by superimposing a preset stacking coefficient on the voltage regulation amount δV and the output voltage of the flying capacitor three-level circuit through the voltage feedforward module and processing it; the preset stacking coefficient is a value between 0 and 1.

[0056] Step S130: Compare the first carrier corresponding to the first bridge arm 11 with the target modulation wave to determine the first driving signal; reduce the second carrier corresponding to the first bridge arm 11 by a preset stacking coefficient and compare it with the target modulation wave to determine the second driving signal.

[0057] Step S140: Drive the first bridge arm 11 according to the first drive signal, and drive the first bridge arm 11 according to the second drive signal.

[0058] Both the first bridge arm 11 and the first bridge arm 11 are composed of multiple switches connected in series (if it is a three-level topology, the number of switches in each bridge arm is 4). Different flying capacitor three-level circuit topologies have different control loops. The control loop collects the operating point information set in the flying capacitor three-level circuit through sensors and other devices, and can realize feedforward control and feedback control. In this embodiment, the flying capacitor three-level circuit includes an inner current loop and an outer voltage loop. The outer voltage loop provides a reference signal for the inner current loop, and the inner current loop outputs a voltage regulation amount δV based on the reference signal. During operation, the control loop also collects the output voltage of the flying capacitor three-level circuit, and superimposes a preset stacking coefficient k on the voltage regulation amount δV and the output voltage. After superposition, the signal is further processed (e.g., normalization processing) to obtain the target modulation wave. Since the preset stacking coefficient k itself takes a value between 0 and 1 and is a unitless constant, the normalization process is actually performed on the voltage regulation amount δV and the output voltage. For example, the sum of the input voltage and output voltage of the flying capacitor three-level circuit is taken as 1 for normalization. The target modulation wave obtained in this way is equivalent to the preset stacking coefficient k being superimposed on the normalized voltage regulation amount δV and the output voltage, so that the value range of the target modulation wave is 0 to 1+k.

[0059] After obtaining the target modulated wave, it is compared with the first carrier and the second carrier, which can be sine waves or triangular waves. The duty cycle of the first driving signal is determined based on the magnitude relationship between the target modulated wave and the first carrier, and the duty cycle of the second driving signal is determined based on the magnitude relationship between the target modulated wave and the second carrier. For example, the portion of the first carrier that is greater than the target modulated wave corresponds to the low-level portion of the first driving signal, and the portion of the second carrier that is greater than the target modulated wave corresponds to the high-level portion of the second driving signal, and so on. The key difference lies in the comparison of the target modulated wave with the second carrier of the first bridge arm 11. Based on the in-phase stacking principle, the second carrier is reduced by a preset stacking coefficient k before being compared with the target modulated wave. The stacking range corresponding to the in-phase stacking principle is related to the preset stacking coefficient k (for example, the in-phase stacking coefficient is equal to the preset stacking coefficient k, or equal to the adjusted value obtained after adjusting the preset stacking coefficient k). In this way, the second driving signal corresponding to the second carrier is changed using the in-phase stacking method. This is reflected on the coordinate axis as follows: the positions of the first carrier and the target modulated wave remain unchanged, while the height of the second carrier is increased by a preset stacking coefficient k. Then, the first carrier and the increased second carrier are compared with the target modulated wave to obtain the corresponding duty cycle signal. Since both the first and second drive signals are obtained based on signal adjustment, they naturally reflect the current operating state of the flying capacitor three-level circuit. Different target modulated waves can be obtained in different modes, resulting in different drive signals. Therefore, by driving the first bridge arm 11 and its switching transistor based on the aforementioned first and second drive signals, smooth mode switching can be achieved.

[0060] It should be noted that, based on the operating mode of boost or buck, not all switches in the first bridge arm 11 are driven by the first drive signal, and not all switches in the first bridge arm 11 are driven by the second drive signal. Figure 1 Taking the flying capacitor three-level circuit with the three-level topology shown as an example, the first bridge arm 11's switch Q11 corresponds to the first driving signal. The duty cycles of switches Q11 and Q14 are complementary, the carriers of switches Q11 and Q12 are complementary, and the duty cycles of switches Q12 and Q13 are complementary. The first bridge arm 11's switch Q21 corresponds to the second driving signal. The duty cycles of switches Q21 and Q24 are complementary, the carriers of switches Q21 and Q22 are complementary, and the duty cycles of switches Q22 and Q23 are complementary. Therefore, based on the first carrier and the first driving signal, the driving signal of each switch in the first bridge arm 11 can be determined. Based on the second carrier and the second driving signal, the driving signal of each switch in the first bridge arm 11 can be determined.

[0061] It is worth noting that the above-mentioned in-phase stacking principle can be modified to some extent. For example, in step S120, the preset stacking coefficient k is superimposed in reverse. In step S130, the second carrier corresponding to the first bridge arm 11 is compared with the target modulation wave after the preset stacking coefficient k is added to determine the second driving signal. Another example is that the preset stacking coefficient k is negative, that is, the second carrier is stacked downwards.

[0062] In some embodiments, the inner current loop includes a subtractor and a proportional-integral controller. The subtractor is used to subtract the reference signal Ref from the feedback signal Fbk of the flying capacitor three-level circuit. The output of the subtractor is connected to the input of the proportional-integral controller, and the output of the proportional-integral controller is used to output the voltage regulation amount δV.

[0063] Reference Figure 3 As shown, the subtractor is connected to the proportional-integral controller (PI controller). The two input terminals of the subtractor are respectively input to the reference signal Ref and the feedback signal Fbk, and the difference between the reference signal Ref and the feedback signal Fbk is obtained. This difference is input to the proportional-integral controller for processing to obtain the voltage regulation amount δV.

[0064] Reference Figure 4 As shown, in some embodiments, step S130 above involves superimposing a preset stacking coefficient onto the voltage regulation amount δV and the output voltage of the flying capacitor three-level circuit, and then processing the result to obtain the target modulation wave, including:

[0065] Step S210: On the basis of the output voltage of the flying capacitor three-level circuit, the product of the preset stacking coefficient and the output voltage is superimposed, and the product is added to the voltage adjustment amount δV to obtain the voltage output value Vr;

[0066] Step S220: Obtain the input voltage of the flying capacitor three-level circuit, and normalize the voltage output value Vr according to the input voltage and output voltage to obtain the target modulation wave.

[0067] The product of the preset stacking coefficient k and the output voltage is calculated, and then the output voltage and voltage regulation amount δV are added to obtain the voltage output value Vr. Normalization is performed on the voltage output value Vr using the sum of the input and output voltages of the flying capacitor three-level circuit as 1, resulting in a target modulation wave with a value range between 0 and 1+k.

[0068] Reference Figure 5 As shown, in some embodiments, the normalization of the voltage output value Vr based on the input voltage and output voltage in step S220 includes:

[0069] Step S310: Determine the sum of the input voltage and the output voltage;

[0070] Step S320: Divide the voltage output value Vr by the total voltage to obtain the target modulation wave, which is a value between 0 and 1+k.

[0071] The specific calculation method can be found in the following formula:

[0072] V r =δV+(1+k)V Bus

[0073]

[0074] Where the voltage output value Vr is Vr, the voltage regulation is δV, the target modulation wave is Vm, and one of Vbat and Vbus is the input voltage, while the other is the output voltage (determined by the current flow direction). According to the above formula, the value of the target modulation wave changes with the input and output voltages. The above calculation process is based on the following principle:

[0075] Inductor voltage V L Based on the duty cycles of the first and second bridge arms, and obtained by subtracting the midpoint voltage of the second bridge arm from the midpoint voltage of the first bridge arm:

[0076] V L =D1V Bat -(1-D2)V Bus

[0077] The duty cycle of the first bridge arm is D1, the duty cycle of the second bridge arm is D2, and the target modulation wave V is within a certain range. m The duty cycle D2 is linearly related to the target modulation wave V. m After subtracting the preset stacking coefficient k, a linear relationship is observed (refer to...). Figure 10 As shown), then D1 = V m D2 = V m -k.

[0078] Therefore, the inductor voltage V in the above equation L It becomes:

[0079] V L =V m V Bat -(1-V m +k)V Bus

[0080]

[0081] Reference Figure 3As shown, in some embodiments, the flying capacitor three-level circuit further includes a normalization processing module. The normalization processing module includes a first adder, a second adder, and a divider. The first adder is used to superimpose a preset stacking coefficient and the product of the output voltage on the output voltage of the flying capacitor three-level circuit. The second adder is coupled to the output terminal of the first adder and is used to output the sum of the input voltage and the output voltage. The divider is coupled to the output terminal of the second adder and is used to divide the voltage output value Vr by the sum of the voltages to obtain the target modulation wave.

[0082] The system first calculates the result (1+k)V Bus The voltage is then fed into one input of the first adder, whose other input is connected to the voltage regulation value δV output from the proportional-integral controller. The first adder sums the data from the two inputs to obtain the voltage output value Vr. The second adder sums Vbat and Vbus to obtain the result Vbat + Vbus, which is used as the divisor and fed into the divider. The voltage output value Vr is used as the dividend and fed into the divider. Finally, the divider outputs the target modulation wave.

[0083] Reference Figure 6 As shown, in some embodiments, step S130 above, which compares the first carrier wave corresponding to the first bridge arm 11 with the target modulation wave to determine the first driving signal, includes:

[0084] Step S410: Compare the amplitudes of the first carrier wave and the target modulated wave;

[0085] Step S420: Determine the high-level portion of the first driving signal based on the time period when the first carrier wave is lower than the target modulation wave, and determine the low-level portion of the first driving signal based on the time period when the first carrier wave is higher than the target modulation wave.

[0086] The multiple switches of the first bridge arm 11 correspond to different duty cycle signals according to the actual situation. The duty cycle signal of each switch is obtained based on the first carrier wave and the first drive signal. In this embodiment, the first carrier wave is a triangular wave and the target modulation wave is a straight line. The part of the first carrier wave that is lower than the target modulation wave is determined as the high level part of the first duty cycle, and the part of the first carrier wave that is higher than the target modulation wave is determined as the low level part of the first duty cycle. Since the triangular wave is continuous in time, the obtained first duty cycle is also continuous, thereby obtaining the first drive signal.

[0087] Reference Figure 7 As shown, in some embodiments, step S130 above, which involves reducing the second carrier corresponding to the first bridge arm 11 by a preset stacking coefficient and comparing it with the target modulation wave to determine the second driving signal, includes:

[0088] Step S510: Reduce the amplitude of the second carrier by a preset stacking coefficient to obtain the third carrier;

[0089] Step S520: Compare the amplitudes of the third carrier wave and the target modulated wave;

[0090] The low-level portion of the second driving signal is determined based on the time period when the third carrier wave is lower than the target modulation wave, and the high-level portion of the second driving signal is determined based on the time period when the third carrier wave is higher than the target modulation wave.

[0091] The multiple switches of the first bridge arm 11 correspond to different duty cycle signals according to the actual situation. The duty cycle signal of each switch is obtained based on the second carrier and the second driving signal. In this embodiment, the second carrier is a triangular wave. The third carrier obtained by reducing the preset stacking coefficient k of the second carrier is also a triangular wave. The target modulation wave is a straight line. The part of the third carrier that is lower than the target modulation wave is determined as the low level part of the second duty cycle. The part of the third carrier that is higher than the target modulation wave is determined as the high level part of the second duty cycle. Since the triangular wave is continuous in time, the obtained second duty cycle is also continuous, thereby obtaining the second driving signal.

[0092] Actual circuit module processing reference Figure 8 The schematic diagram of the duty cycle processing module shown shows that the target modulation wave is divided into two inputs to two limiters. The two limiters output duty cycle signals to the DPS module. The first limiter inputs the target modulation wave and a triangular wave, and outputs the duty cycle signal D1 to the DPS module. A subtractor is set before the second limiter to subtract a preset stacking coefficient k from the target modulation wave. The resulting signal and the triangular wave are then input to the second limiter. The second limiter outputs the duty cycle signal D2 to the DPS module. Finally, the DPS module outputs a drive signal, or the DPS module provides a corresponding signal to the drive module of the switching transistor.

[0093] In some embodiments, the determination method of the first driving signal and the second driving signal is illustrated by taking a three-level flying capacitor three-level circuit with a three-level topology as an example.

[0094] Wherein, the first carrier includes a complementary first waveform and a second waveform, and the first driving signal includes a first duty cycle signal corresponding to the first waveform and a second duty cycle signal corresponding to the second waveform; the second carrier includes a complementary third waveform and a fourth waveform, and the second driving signal includes a third duty cycle signal corresponding to the third waveform and a fourth duty cycle signal corresponding to the fourth waveform;

[0095] The first bridge arm 11 includes a first switch Q11, a second switch Q12, a third switch Q13, and a fourth switch Q14 connected in series from the positive terminal to the negative terminal of the bus. A first duty cycle signal is used to drive the first switch Q11 to operate, a second duty cycle signal is used to drive the second switch Q12 to operate, a complementary signal of the first duty cycle signal is used to drive the fourth switch Q14 to operate, and a complementary signal of the second duty cycle signal is used to drive the third switch Q13 to operate.

[0096] The first bridge arm 11 includes a fifth switch Q21, a sixth switch Q22, a seventh switch Q23, and an eighth switch Q24 connected in series from the positive terminal to the negative terminal of the bus. A third duty cycle signal is used to drive the fifth switch Q21 to operate, a fourth duty cycle signal is used to drive the sixth switch Q22 to operate, a complementary signal of the third duty cycle signal is used to drive the eighth switch Q24 to operate, and a complementary signal of the fourth duty cycle signal is used to drive the seventh switch Q23 to operate.

[0097] As previously mentioned, a three-level circuit with a flying capacitor in a three-level topology includes four switching transistors. Taking the side containing the first bridge arm 11 as the input side and the side containing the first bridge arm 11 as the output side as an example, refer to... Figures 9a-9c The timing diagram shown depicts the first waveform as a green line, the second waveform as a cyan line (both are triangular waves with a 180° phase difference), the third waveform as a red line, and the fourth waveform as a purple line (both are triangular waves with a 180° phase difference). The first and third waveforms are in phase, as are the second and fourth waveforms. Although the second carrier wave needs to be subtracted from the preset stacking coefficient k in actual processing, if the target modulation wave remains unchanged, this is reflected on the coordinate axis as the positions of the first and target modulation waves remaining constant, while the height of the second carrier wave is increased by the preset stacking coefficient k. Then, the first carrier wave and the increased second carrier wave are compared with the target modulation wave to obtain the corresponding duty cycle signals.

[0098] Figure 9aThis is a timing diagram in Buck mode. With a preset stacking factor k = 0.9, the amplitudes of the third and fourth waveforms are increased by 0.9. Comparing the first waveform with the target modulation wave, the portion higher than the target modulation wave corresponds to the low-level portion of Q11, and the portion lower than the target modulation wave corresponds to the high-level portion of Q11. Comparing the second waveform with the target modulation wave, the portion higher than the target modulation wave corresponds to the low-level portion of Q12, and the portion lower than the target modulation wave corresponds to the high-level portion of Q12. The duty cycle signal of Q13 is complementary to the duty cycle signal of Q12, and the duty cycle signal of Q14 is complementary to the duty cycle signal of Q11. The third waveform is generally higher than the target modulation wave, so Q21 corresponds to a continuously high duty cycle signal. The fourth waveform is generally higher than the target modulation wave, so Q22 corresponds to a continuously high duty cycle signal. The duty cycle signal of Q23 is complementary to the duty cycle signal of Q22, so it corresponds to a continuously low duty cycle signal. The duty cycle signal of Q24 is complementary to the duty cycle signal of Q21, so it corresponds to a continuously low duty cycle signal.

[0099] Figure 9b This is the timing diagram in Boost mode. With a preset stacking factor k = 0.9, the amplitudes of the third and fourth waveforms are increased by 0.9. The first waveform is generally lower than the target modulation wave, therefore Q11 corresponds to a continuously high duty cycle signal. The second waveform is generally lower than the target modulation wave, therefore Q12 corresponds to a continuously high duty cycle signal. The duty cycle signal of Q13 is complementary to the duty cycle signal of Q12, therefore it corresponds to a continuously low duty cycle signal. The duty cycle signal of Q14 is complementary to the duty cycle signal of Q11, therefore it corresponds to a continuously low duty cycle signal. The third waveform is compared with the target modulation wave. The part higher than the target modulation wave corresponds to the high level part of Q21, and the part lower than the target modulation wave corresponds to the low level part of Q21. The fourth waveform is compared with the target modulation wave. The part higher than the target modulation wave corresponds to the high level part of Q22, and the part lower than the target modulation wave corresponds to the low level part of Q22. The duty cycle signal of Q23 is complementary to the duty cycle signal of Q22, and the duty cycle signal of Q24 is complementary to the duty cycle signal of Q21.

[0100] Figure 9cThis is a timing diagram in Buck-Boost mode. With a preset stacking factor k = 0.9, the amplitudes of the third and fourth waveforms are boosted by 0.9. Comparing the first waveform with the target modulation wave, the portion higher than the target modulation wave corresponds to the low-level portion of Q11, and the portion lower than the target modulation wave corresponds to the high-level portion of Q11. Similarly, comparing the second waveform with the target modulation wave, the portion higher than the target modulation wave corresponds to the low-level portion of Q12, and the portion lower than the target modulation wave corresponds to the high-level portion of Q12. The duty cycle signal of Q13 is complementary to the duty cycle signal of Q12, and the duty cycle signal of Q14 is complementary to the duty cycle signal of Q11. The third waveform is compared with the target modulation wave. The part higher than the target modulation wave corresponds to the high level part of Q21, and the part lower than the target modulation wave corresponds to the low level part of Q21. The fourth waveform is compared with the target modulation wave. The part higher than the target modulation wave corresponds to the high level part of Q22, and the part lower than the target modulation wave corresponds to the low level part of Q22. The duty cycle signal of Q23 is complementary to the duty cycle signal of Q22, and the duty cycle signal of Q24 is complementary to the duty cycle signal of Q21.

[0101] In summary, referring to Figure 10 The diagram showing the relationship between duty cycle and operating mode indicates that when the preset stacking coefficient k = 0.9, the green line represents the first driving signal corresponding to the first carrier, and the red line represents the second driving signal corresponding to the second carrier. As the system operating conditions change, the target modulation wave gradually increases, and the flying capacitor three-level circuit switches from Buck mode to Buck-Boost mode and then to Boost mode.

[0102] Furthermore, the driving method of this application embodiment can also be applied to interleaved parallel flying capacitor bidirectional buck-boost topologies. Each flying capacitor three-level circuit in the interleaved parallel flying capacitor bidirectional buck-boost topology is independently subject to the above driving method, and will not be repeated here.

[0103] In summary, based on the voltage regulation output from the voltage feedforward module and the output voltage of the flying capacitor three-level circuit, a target modulation wave is obtained after normalization by superimposing a preset stacking coefficient. Then, the target modulation wave is compared with the first carrier wave of the first bridge arm to obtain the first driving signal for the first bridge arm. The target modulation wave is then subtracted from the preset stacking coefficient and compared with the second carrier wave of the second bridge arm to obtain the second driving signal for the second bridge arm. This driving method superimposes a preset stacking coefficient to obtain the target modulation wave. Utilizing in-phase stacked carrier technology, when comparing the target modulation wave with the second carrier wave, it is equivalent to stacking the second carrier wave upwards. This achieves different driving signals obtained by comparing a target modulation wave with the carrier waves of the two bridge arms. Since the target modulation wave is obtained based on the voltage regulation reflecting the current operating condition of the flying capacitor three-level circuit, it ensures that the system operating mode can automatically and smoothly switch under different input and output voltage conditions, improving the system's stability and continuity.

[0104] The driving method of this application will be explained in detail below through a specific example.

[0105] Reference Figure 1 The three-level bidirectional buck-boost three-level circuit shown includes a first bridge arm 11 and a second bridge arm 11. The first bridge arm 11 corresponds to the first carrier and the second carrier, respectively. In-phase stacked carriers stack the first and second carriers in phase. The stacking range is set by a coefficient k; in this example, k = 0.9. Therefore, the system automatically operates in different states depending on the magnitude of the target modulation wave. (Refer to...) Figures 9a-9c As shown, the first waveform corresponding to carrier Q11 is represented by a green line, the second waveform corresponding to carrier Q12 is represented by a cyan line, and both waveforms are triangular waves with a 180° phase difference. The third waveform corresponding to carrier Q21 is represented by a red line, and the fourth waveform corresponding to carrier Q22 is represented by a purple line. Both waveforms are triangular waves with a 180° phase difference. The first and third waveforms are in phase, as are the second and fourth waveforms, and both waveforms are shifted upwards by 0.9.

[0106] Assuming the target modulated wave is less than 0.9 at this time, corresponding to Figure 9a As shown, the first and second waveforms are compared with the target modulation wave to obtain the duty cycle signals of Q11 and Q12, respectively. Correspondingly, the duty cycle signals of Q13 and Q14 are complementary signals to the duty cycle signals of Q11 and Q12, respectively. The third and fourth waveforms are always greater than the target modulation wave; therefore, the duty cycle signals of Q21 and Q22 remain high, and Q21 and Q22 are normally open. Correspondingly, the duty cycle signals of Q23 and Q24 remain low, and Q23 and Q24 are normally closed. At this time, the circuit operates in Buck mode. As the target modulation wave increases, the system automatically operates in Buck-Boost mode (corresponding to...). Figure 9c As shown), Boost mode (corresponding to) Figure 9b As shown in the image, this will not be elaborated upon here.

[0107] It should be noted that the preset stacking coefficient k can be set as needed. For example, in this example, k = 0.9, which means that when the target modulated wave is in the range [0.9, 1], the system operates in Buck-Boost mode. Similarly, assuming k = 0.8, when the target modulated wave is in the range [0.8, 1], the system operates in Buck-Boost mode. Furthermore, different values ​​of the target modulated wave mean that the input voltage and output voltage are at different values, and the target modulated wave value ranges from [0, 1 + k]. In actual circuit module processing, the carrier value generated by the DSP module can only be in the range [0, 1], therefore the target modulated wave needs to be processed and converted to the range [0, 1]. Therefore, in... Figures 9a-9c In this process, the second carrier is moved upward by a preset stacking coefficient k while keeping the position of the first carrier unchanged.

[0108] like Figure 11 As shown, Figure 11 This is a schematic diagram of a controller 1000 provided in one embodiment of this application.

[0109] The controller 1000 in this embodiment includes one or more processors 1001 and a memory 1002. Figure 11 The example uses a processor 1001 and a memory 1002.

[0110] Processor 1001 and memory 1002 can be connected via a bus or other means. Figure 11 Taking the example of a connection between China and Israel via a bus.

[0111] Memory 1002, as a non-transitory computer-readable storage medium, can be used to store non-transitory software programs and non-transitory computer-executable programs. Furthermore, memory 1002 may include high-speed random access memory, and may also include non-transitory memory, such as at least one disk storage device, flash memory device, or other non-transitory solid-state storage device. In some embodiments, memory 1002 may optionally include memory 1002 remotely located relative to processor 1001, and these remote memories can be connected to controller 1000 via a network. Examples of such networks include, but are not limited to, the Internet, intranets, local area networks, mobile communication networks, and combinations thereof.

[0112] Those skilled in the art will understand that Figure 11 The device structure shown does not constitute a limitation on the controller 1000 and may include more or fewer components than shown, or combine certain components, or have different component arrangements.

[0113] This application also provides a flying capacitor three-level circuit, including the aforementioned controller 1000.

[0114] In some embodiments, the above-mentioned flying capacitor three-level circuit is composed of two flying capacitor three-level bidirectional buck-boost circuits connected in parallel with alternating connections, and each of the two flying capacitor three-level bidirectional buck-boost circuits applies the above-mentioned driving method through the controller.

[0115] This application also provides an inverter device, including the aforementioned flying capacitor three-level circuit.

[0116] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate; that is, they may be located in one place or distributed across multiple network nodes. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs.

[0117] It will be understood by those skilled in the art that all or some of the steps and systems in the methods disclosed above can be implemented as software, firmware, hardware, and suitable combinations thereof. Some or all of the physical components can be implemented as software executed by a processor, such as a central processing unit, digital signal processor, or microprocessor, or as hardware, or as an integrated circuit, such as an application-specific integrated circuit. Such software can be distributed on a computer-readable medium, which can include computer storage media (or non-transitory media) and communication media (or transient media). As is known to those skilled in the art, the term computer storage media includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules, or other data). Computer storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technologies, CD-ROM, digital versatile disc (DVD) or other optical disc storage, magnetic cartridges, magnetic tape, disk storage or other magnetic storage devices, or any other medium that can be used to store desired information and is accessible to a computer. Furthermore, as is known to those skilled in the art, communication media typically contain computer-readable instructions, data structures, program modules, or other data in modulated data signals such as carrier waves or other transmission mechanisms, and may include any information delivery medium.

[0118] It should be understood that in this application, "at least one (item)" means one or more, and "more than" means two or more. "And / or" is used to describe the relationship between related objects, indicating that three relationships can exist. For example, "A and / or B" can represent three cases: only A exists, only B exists, and both A and B exist simultaneously, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. "At least one (item) of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one (item) of a, b, or c can represent: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, and c can be single or multiple.

[0119] In the several embodiments provided in this application, it should be understood that the disclosed systems, instruments, and methods can be implemented in other ways. For example, the instrument embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the shown or discussed mutual couplings, direct couplings, or communication connections may be through some interfaces; indirect couplings or communication connections between instruments or units may be electrical, mechanical, or other forms. Units described as separate components may or may not be physically separate, and components shown as units may or may not be physical units, i.e., they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0120] It should also be understood that the various implementation methods provided in this application can be combined arbitrarily to achieve different technical effects.

[0121] The above is a detailed description of the preferred embodiments of this application. However, this application is not limited to the above embodiments. Those skilled in the art can make various equivalent modifications or substitutions without departing from the spirit of this application. All such equivalent modifications or substitutions are included within the scope defined by the claims of this application.

Claims

1. A driving method for a flying capacitor three-level circuit, characterized in that, The flying capacitor three-level circuit includes a first bridge arm, a second bridge arm, and a voltage feedforward module; the driving method includes: Obtain the voltage regulation amount of the inner current loop output; The voltage feedforward module superimposes a preset layering coefficient onto the voltage regulation amount and the output voltage of the flying capacitor three-level circuit and processes them to obtain the target modulation wave; the preset layering coefficient is a value between 0 and 1. The first carrier corresponding to the first bridge arm is compared with the target modulation wave to determine the first driving signal, and the second carrier corresponding to the second bridge arm is reduced by the preset stacking coefficient and then compared with the target modulation wave to determine the second driving signal. The first bridge arm is driven according to the first drive signal, and the second bridge arm is driven according to the second drive signal.

2. The method according to claim 1, characterized in that, The inner current loop includes a subtractor and a proportional-integral controller. The subtractor is used to subtract the reference signal from the feedback signal of the flying capacitor three-level circuit. The output of the subtractor is connected to the input of the proportional-integral controller, and the output of the proportional-integral controller is used to output the voltage regulation amount.

3. The method according to claim 1, characterized in that, The process of superimposing a preset layering coefficient on the voltage regulation amount and the output voltage of the flying capacitor three-level circuit, and then processing them, to obtain the target modulation wave includes: The product of the preset stacking coefficient and the output voltage is superimposed on the output voltage of the flying capacitor three-level circuit, and the product is added to the voltage adjustment amount to obtain the voltage output value; The input voltage of the flying capacitor three-level circuit is obtained, and the voltage output value is normalized according to the input voltage and the output voltage to obtain the target modulation wave.

4. The method according to claim 3, characterized in that, The normalization process for the voltage output value based on the input voltage and the output voltage includes: Determine the sum of the input voltage and the output voltage; The target modulation wave is obtained by dividing the voltage output value by the sum of the voltages, and the target modulation wave is a value between 0 and 1+k.

5. The method according to claim 4, characterized in that, The flying capacitor three-level circuit further includes a normalization processing module, which includes a first adder, a second adder, and a divider. The first adder is used to superimpose the product of the preset stacking coefficient and the output voltage on the output voltage of the flying capacitor three-level circuit. The second adder is coupled to the output terminal of the first adder and is used to output the sum of the input voltage and the output voltage. The divider is coupled to the output terminal of the second adder and is used to divide the output voltage value by the sum of the voltages to obtain the target modulation wave.

6. The method according to claim 1, characterized in that, The step of comparing the first carrier wave corresponding to the first bridge arm with the target modulation wave to determine the first driving signal includes: Compare the amplitudes of the first carrier wave and the target modulated wave; The high-level portion of the first driving signal is determined based on the time period during which the first carrier wave is lower than the target modulation wave, and the low-level portion of the first driving signal is determined based on the time period during which the first carrier wave is higher than the target modulation wave.

7. The method according to claim 6, characterized in that, The first carrier includes a complementary first waveform and a second waveform, and the first driving signal includes a first duty cycle signal corresponding to the first waveform and a second duty cycle signal corresponding to the second waveform; The first bridge arm includes a first switch, a second switch, a third switch, and a fourth switch connected in series from the positive terminal to the negative terminal of the bus. The first duty cycle signal is used to drive the first switch, the second duty cycle signal is used to drive the second switch, the complementary signal of the first duty cycle signal is used to drive the fourth switch, and the complementary signal of the second duty cycle signal is used to drive the third switch.

8. The method according to claim 1, characterized in that, The step of determining the second driving signal by reducing the second carrier corresponding to the second bridge arm by the preset stacking coefficient and comparing it with the target modulation wave includes: The third carrier is obtained by reducing the amplitude of the second carrier by the preset stacking coefficient; Compare the amplitudes of the third carrier wave and the target modulation wave; The low-level portion of the second driving signal is determined based on the time period during which the third carrier wave is lower than the target modulation wave, and the high-level portion of the second driving signal is determined based on the time period during which the third carrier wave is higher than the target modulation wave.

9. The method according to claim 7, characterized in that, The second carrier includes complementary third and fourth waveforms, and the second drive signal includes a third duty cycle signal corresponding to the third waveform and a fourth duty cycle signal corresponding to the fourth waveform; The second bridge arm includes a fifth switch, a sixth switch, a seventh switch, and an eighth switch connected in series from the positive terminal to the negative terminal of the busbar. The third duty cycle signal is used to drive the fifth switch, the fourth duty cycle signal is used to drive the sixth switch, the complementary signal of the third duty cycle signal is used to drive the eighth switch, and the complementary signal of the fourth duty cycle signal is used to drive the seventh switch.

10. A controller, characterized in that, The method includes at least one processor and a memory for communicatively connecting to the at least one processor; the memory stores instructions executable by the at least one processor to enable the at least one processor to perform the method as described in any one of claims 1 to 9.

11. A flying capacitor three-level circuit, characterized in that, Includes the controller as described in claim 10.

12. The flying capacitor three-level circuit according to claim 11, characterized in that, The flying capacitor three-level circuit is composed of two flying capacitor three-level bidirectional buck-boost circuits connected in parallel with alternating connections. Each of the two flying capacitor three-level bidirectional buck-boost circuits is controlled by the controller and the method described in any one of claims 1 to 9 is applied.

13. An inverter device, characterized in that, Includes the flying capacitor three-level circuit as described in claim 11 or 12.

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