A multi-level inverter and inverter control method

Abstract

The application relates to the field of inverters, and discloses a multi-level inverter and an inverter control method. The inverter comprises a main circuit module, which comprises an energy storage unit and a switching unit. The energy storage unit is connected with a direct-current input power supply and is used for increasing the voltage of the direct-current input power supply in a charging mode and outputting a plurality of direct-current voltages with different amplitudes in a discharging mode. The switching unit is connected between the output end of the energy storage unit and a load and is used for alternately applying the plurality of direct-current voltages with different amplitudes to the load in a positive polarity or a negative polarity, so as to form a multi-level alternating current staircase wave on the load. The four times voltage gain and nine-level output are realized by only using two energy storage capacitors and ten switching tubes, the number of power devices and energy storage elements is reduced, and the system volume and manufacturing cost are reduced. The steady-state voltages of the first energy storage capacitor and the second energy storage capacitor are determined by the topological structure itself, and an additional dynamic voltage balancing algorithm or balancing circuit is not needed, so that the control difficulty is simplified.

Description

Technical Field

[0001] This invention relates to the field of inverters, and in particular to a multilevel inverter and an inverter control method. Background Technology

[0002] Currently, multilevel inverters (MLIs) are widely used in medium- and high-voltage high-power applications, such as electric drives, grid interfaces, and electric vehicles, due to their ability to generate near-sinusoidal output voltages with low total harmonic distortion (THD), reduce voltage stress on power devices, and decrease output filter size. Traditional solutions typically employ cascaded H-bridges or midpoint clamping structures, but these often require numerous independent DC power supplies or complex capacitor voltage balancing circuits. Among the many MLI topologies, switched-capacitor multilevel inverters (SC-MLIs) have attracted considerable attention in recent years. These inverters utilize the charging and discharging characteristics of capacitors to achieve voltage self-balancing and boost functions, thereby reducing the need for multiple isolated DC power supplies.

[0003] However, existing multilevel inverter technologies still face many significant limitations in practical engineering applications. First, traditional topologies, such as cascaded H-bridges, neutral-point clamping, and flying capacitor types, typically require a large number of power switching devices, clamping diodes, and energy storage capacitors due to limitations in their level generation mechanisms. For example, a seven-level NPC inverter requires at least 12 switching transistors and corresponding diodes and capacitors. This not only results in a large system hardware size and high manufacturing costs but also complicates the design of the gate drive circuit and the overall control logic. Second, the voltage gain capability of existing technologies is generally limited. The boost ratio of traditional structures is usually low (often less than 1.5 times), and even some existing switched-capacitor topologies can only achieve a 2x boost. Therefore, in applications targeting low-voltage DC sources such as photovoltaics, to obtain AC output voltage that meets grid connection requirements, it is often necessary to introduce multi-stage pre-boost circuits or add additional independent DC power supplies. This cascaded structure inevitably reduces the overall conversion efficiency of the system and limits its applicability in high-voltage scenarios. Summary of the Invention

[0004] Therefore, the technical problem to be solved by the present invention is that the existing inverter topology has the problems of a large number of devices, complex control, and the need for multiple independent DC sources or complex voltage equalization circuits.

[0005] The above-mentioned technical problems are solved by the following technical solution: This invention proposes a multi-level inverter, which includes, The main circuit module includes an energy storage unit and a switching unit; The energy storage unit is connected to a DC input power supply and is used to boost the voltage of the DC input power supply in the charging mode and output multiple DC voltages of different amplitudes in the discharging mode. The switching unit is connected between the output terminal of the energy storage unit and the load, and is used to alternately apply multiple DC voltages of different amplitudes to the load with positive or negative polarity to form a multi-level AC stepped wave on the load. The control circuit module includes a signal acquisition and processing unit and a drive output unit. The signal acquisition and processing unit acquires the output voltage and output current of the load and performs calculations with a reference voltage to generate a modulation signal. The drive output unit generates a switch control signal based on the modulation signal and outputs it to the switch unit. Specifically, the energy storage unit receives electrical energy from the DC input power supply and boosts its voltage in charging mode, and outputs the stored electrical energy in the form of multiple DC voltages of different amplitudes in discharging mode. The switching unit alternately applies multiple DC voltages of different amplitudes to the load with positive or negative polarity, thereby forming a multi-level AC stepped wave on the load. During this process, the control circuit module collects the output voltage and output current of the load in real time through the signal acquisition and calculation unit and performs calculations with the reference voltage to generate a modulation signal and output it to the drive output unit. The drive output unit generates a switching control signal based on the modulation signal and outputs it to the switching unit, thereby realizing closed-loop control of the main circuit module. This architecture achieves multi-level AC output with fewer power devices through the coordinated work of the energy storage unit and the switching unit, effectively reducing voltage harmonic content and voltage stress on power devices, while improving the dynamic response capability of the system under different load conditions.

[0006] In a preferred embodiment of the multilevel inverter of the present invention: the energy storage unit includes a first energy storage capacitor and a second energy storage capacitor; Specifically, by timing control of the charging and discharging states of the first and second energy storage capacitors, the energy storage unit can utilize the parallel charging characteristics of the capacitors to boost the voltage of the DC input power supply in the charging mode, and utilize the series discharging characteristics of the capacitors to output multiple DC voltages of different amplitudes in the discharging mode. This dual-capacitor structure only requires two energy storage capacitors to achieve voltage boosting and multi-level output. Compared with the traditional multi-level inverter topology that requires a large number of energy storage capacitors, this invention reduces the number of energy storage components, lowers the system size and manufacturing cost, and simplifies the complexity of capacitor voltage balance control.

[0007] In a preferred embodiment of the multilevel inverter of the present invention: the switching unit includes a first switch, a second switch, a third switch, a fourth switch, a fifth switch, and a sixth switch; The first switch and the second switch are connected in series and then connected in parallel with the first energy storage capacitor. One end of the first switch is connected to the positive terminal of the DC input power supply. The other end of the first switch and one end of the second switch are connected to the first node. The other end of the second switch is connected to the negative terminal of the DC input power supply. The first energy storage capacitor is connected between the first node and the other end of the second switch. One end of the third switch is connected to the negative terminal of the first energy storage capacitor, and the other end of the third switch and one end of the fourth switch are connected to the second node. The other end of the fourth switch is connected to the positive terminal of the second energy storage capacitor, and the negative terminal of the second energy storage capacitor is connected to the negative terminal of the DC input power supply. The fifth switch is connected between the second node and the positive terminal of the second energy storage capacitor; the sixth switch is connected between the negative terminal of the second energy storage capacitor and the first terminal of the load. Specifically, the first switch, the second switch, and the first energy storage capacitor form a first charging and discharging path. When the first switch is on and the second switch is off, the DC input power supply charges the first energy storage capacitor through the first switch. When the first switch is off and the second switch is on, the first energy storage capacitor outputs power in series with the DC input power supply through the second switch. The third switch serves as a discharge circuit control switch for the first energy storage capacitor, providing a conduction path when the first energy storage capacitor needs to discharge. The fourth switch, the fifth switch, and the second energy storage capacitor form a second charging and discharging path. The fourth switch controls the positive terminal of the second energy storage capacitor to be connected, the fifth switch controls the negative terminal of the second energy storage capacitor to be connected, and the sixth switch serves as the discharge circuit control switch for the second energy storage capacitor. By combining the on and off states of the first to sixth switches, the energy storage unit can switch to different charging and discharging modes, thereby outputting DC voltages of different amplitudes at different times. The first energy storage capacitor can be connected in series with the DC input power supply through the second switch, and the second energy storage capacitor can be further connected in series with the DC input power supply and the first energy storage capacitor through the fifth switch to improve voltage gain. This switch configuration uses six switching transistors to achieve independent charging and discharging control of the two energy storage capacitors, reducing the number of power devices while ensuring control flexibility, reducing conduction and switching losses, and thus improving the overall conversion efficiency of the system.

[0008] In a preferred embodiment of the multilevel inverter of the present invention: the switching unit further includes a seventh switch, an eighth switch, a ninth switch, and a tenth switch; The seventh switch is connected between the second node and the second end of the load; The eighth switch is connected between the negative terminal of the DC input power supply and the first terminal of the load. The ninth switch is connected between the second terminal of the load and the negative terminal of the DC input power supply; The tenth switch is connected between the first terminal of the load and the positive terminal of the DC input power supply; Specifically, the second node is the output terminal of the energy storage unit. When the seventh and tenth switches are on and the eighth and ninth switches are off, the first terminal of the load is connected to the second node and the second terminal is connected to the negative terminal of the DC input power supply, and the load bears a positive voltage; when the eighth and ninth switches are on and the seventh and tenth switches are off, the first terminal of the load is connected to the negative terminal of the DC input power supply and the second terminal is connected to the second node, and the load bears a reverse voltage; thus, flexible switching of the voltage polarity from the output to the load is achieved; this commutation structure, in conjunction with the front-stage boost network formed by the first to sixth switches, allows the positive voltage output from the front stage to form a symmetrical positive and negative multi-level stepped wave on the load after polarity switching, thereby achieving AC output with the fewest commutation switches, reducing switching losses in the commutation process while ensuring the quality of the output waveform.

[0009] In a preferred embodiment of the multilevel inverter of the present invention: the switching unit forms nine stepped voltage levels on the load through nine operating modes: In the first mode, the second switch, the fourth switch, the sixth switch, the ninth switch, and the tenth switch are turned on, and the output voltage is 0. In the second to fifth modes, the seventh and tenth switches are both turned on, and the remaining switches are turned on sequentially in the following combinations: the first, third, and fourth switches output +1VDC; the second, fourth, and sixth switches output +2VDC; the first, third, and fifth switches output +3VDC; and the second and fifth switches output +4VDC. In modes six through nine, the eighth and ninth switches are both turned on, and the remaining switches are turned on sequentially in the following combinations: the first, third, and fourth switches output -1VDC; the second, fourth, and sixth switches output -2VDC; the first, third, and fifth switches output -3VDC; and the second and fifth switches output -4VDC. Specifically, the first mode is the initial mode, in which the second, fourth, sixth, ninth, and tenth switches are turned on. At this time, the first energy storage capacitor is connected in series with the DC input power supply through the second switch. The two are superimposed to charge the second energy storage capacitor. The load terminals are short-circuited, and the output voltage is 0. The second to fifth modes are the positive half-cycle level output stages. The seventh and tenth switches are turned on together to apply a positive voltage to the load. By sequentially switching different conduction combinations of the first to sixth switches, +1VDC, +2VDC, and + are sequentially established on the load. The output waveform features stepped levels of 3VDC and +4VDC. Modes 6 through 9 represent the negative half-cycle output phase. Switches 8 and 9 conduct together to apply a negative voltage to the load. Through a switching combination symmetrical to the positive half-cycle, stepped levels of -1VDC, -2VDC, -3VDC, and -4VDC are sequentially established on the load. These nine levels are arranged sequentially according to the variation pattern of a sine wave, with a constant voltage difference of 1VDC between adjacent levels. This makes the output waveform closer to a sine wave, significantly reducing the total harmonic distortion of the output voltage and helping to reduce the size and cost of the output filter.

[0010] In a preferred embodiment of the multilevel inverter of the present invention: the signal acquisition and processing unit includes a voltage sampling terminal, a current sampling terminal, a voltage regulator, and a current regulator; the input terminals of the voltage sampling terminal and the current sampling terminal are respectively connected to the output terminal of the load, the output terminal of the voltage sampling terminal is connected to the input terminal of the voltage regulator, the voltage regulator is connected to the reference voltage, and the output terminal of the voltage regulator and the output terminal of the current sampling terminal are respectively connected to the input terminal of the current regulator; The drive output unit includes a sinusoidal pulse width modulation module and a drive terminal; the output terminal of the current regulator is connected to the input terminal of the sinusoidal pulse width modulation module, the output terminal of the sinusoidal pulse width modulation module is connected to the input terminal of the drive terminal, and the output terminal of the drive terminal is connected to the switching unit. Specifically, the voltage sampling terminal acquires the load's output voltage and sends it to the voltage regulator. The voltage regulator compares and adjusts the acquired voltage value with the reference voltage to generate a setpoint for the inner current loop. The current sampling terminal acquires the load's output current and sends it to the current regulator. The current regulator compares and adjusts the sampled current with the current setpoint output by the voltage regulator to generate a modulation signal. This modulation signal is processed sequentially by the sinusoidal pulse width modulation module and the driver terminal, then converted into a switching control signal and output to the switching unit. Through the dual closed-loop structure of the voltage outer loop and the current inner loop, the amplitude of the output voltage and the waveform quality of the output current can be controlled simultaneously. It can respond quickly and maintain stable output voltage during load changes, effectively suppressing output waveform distortion. In addition, the sinusoidal pulse width modulation module modulates the modulation signal with a high-frequency carrier, making the switching frequency much higher than the output frequency, thus improving the spectral characteristics of the output waveform.

[0011] In a preferred embodiment of the multilevel inverter of the present invention: the steady-state voltage of the first energy storage capacitor is 1VDC, and the steady-state voltage of the second energy storage capacitor is 2VDC. Specifically, during the cyclic switching of the nine operating modes, the first energy storage capacitor is repeatedly charged to 1 times the DC input power supply voltage, i.e., the steady-state voltage is 1VDC; the second energy storage capacitor is repeatedly charged by the series combination of the DC input power supply and the first energy storage capacitor, and its steady-state voltage is increased to 2 times the DC input power supply voltage, i.e., 2VDC. This asymmetric capacitor voltage distribution strategy of "1VDC+1VDC+2VDC" allows the DC input power supply, the first energy storage capacitor, and the second energy storage capacitor to be superimposed in series under the highest level output mode, resulting in an output voltage of 4VDC, achieving a fourfold voltage gain. This voltage gain can be achieved with a single-stage inverter topology without the need for additional boost circuits or transformers, reducing system energy conversion links, lowering power loss, and improving overall system efficiency. At the same time, this capacitor voltage distribution relationship is determined by the topology itself and can be naturally maintained in steady state without complex dynamic voltage balancing algorithms, improving system reliability.

[0012] The present invention also provides an inverter control method, applied to the aforementioned multilevel inverter, and further includes, The signal acquisition and processing unit acquires the output voltage and output current of the load, and the error between the output voltage and the reference voltage is processed by the voltage regulator and used as the current loop setpoint. The error between the output current and the current loop setpoint is processed by the current regulator and used to generate a modulation signal. The driving output unit generates a switching control signal from the modulation signal in a multi-carrier stacked sinusoidal pulse width modulation mode, and outputs it to the switching unit, so that the first switch to the tenth switch are turned on and off in nine working modes, forming nine stepped levels on the load. Specifically, firstly, the signal acquisition and processing unit acquires the output voltage and output current of the load in real time. The outer voltage loop uses the error between the acquired output voltage and the reference voltage as the setpoint for the inner current loop after proportional-integral calculation by the voltage regulator. The inner current loop generates a modulation signal after proportional calculation by the current regulator based on the error between the acquired output current and the setpoint of the current loop. This dual closed-loop control structure ensures accurate tracking of the system output voltage to the reference voltage and low distortion of the output current waveform. Even under conditions of sudden load changes or fluctuations in the DC input power supply, the system can still maintain stable output performance. Secondly, the drive output unit converts the modulation signal into a switching control signal using a multi-carrier stacked sinusoidal pulse width modulation method, and outputs... The switching unit controls the first to tenth switches to be turned on and off sequentially according to nine operating modes. The multi-carrier stacked modulation method uses multiple stacked triangular carriers to generate multiple sets of PWM pulses corresponding to the amplitude of the modulation signal within one modulation cycle. By cooperating with the above-mentioned nine operating mode switching table, the inverter synthesizes a high-quality nine-level stepped wave on the load. This method does not require complex space vector calculation or table lookup interpolation operations, has low computational load and fast response speed, and is suitable for real-time implementation of low-cost digital controllers. It does not contain an independent capacitor voltage balancing control subroutine. The capacitor voltage achieves hardware self-balancing through the cyclic switching of the nine operating modes, which reduces the development difficulty and operating burden of the control algorithm.

[0013] In a preferred embodiment of the inverter control method of the present invention: the voltage regulator adopts a proportional-integral (PI) regulation method to perform a proportional-integral operation on the error between the output voltage and the reference voltage to generate the current loop setpoint; the current regulator adopts a proportional regulation method to perform a proportional operation on the error between the output current and the current loop setpoint to generate a modulation signal. Specifically, the voltage regulator employs a proportional-integral (PI) control method. The proportional element provides an immediate response to the current voltage deviation, while the integral element accumulates historical deviations to eliminate steady-state errors. The outputs of both elements serve as the setpoint for the current loop. The current regulator employs a proportional control method to provide an immediate response to the current deviation signal, generating a modulation signal. The outer voltage loop uses PI control to ensure zero steady-state error tracking of the reference voltage, while the inner current loop uses P control, leveraging the fast response speed of the current loop and avoiding the phase lag introduced by the integral element. This combination balances the system's steady-state accuracy and dynamic response speed, enabling rapid recovery to steady state during sudden load changes.

[0014] In a preferred embodiment of the inverter control method of the present invention: the multi-carrier stacked sinusoidal pulse width modulation adopts eight triangular carriers of the same frequency stacked together, the modulation signal is compared with the eight triangular carriers of the same frequency, and the switch control signal corresponding to each of the nine working modes is output according to the comparison result by looking up a table, so as to drive the first switch to the tenth switch to operate according to the required combination of conduction and cutoff of each mode; Specifically, eight triangular carrier waves of the same frequency are vertically stacked in the voltage axis direction. The instantaneous value of the modulation signal is compared with each of the eight carrier waves one by one. The target level to be output is determined according to the amplitude range of the modulation signal. Then, the corresponding switch control signal is output by looking up a table according to the preset mode level mapping relationship. This modulation method converts the continuous modulation signal into a nine-level stepped wave control command. The logic is clear and the operation is simple, without the need for complex vector calculations. At the same time, the nine mode switch tables have clear regularity, and the storage and retrieval are efficient, which facilitates real-time control on low-cost controllers.

[0015] The beneficial effects of this invention are as follows: it achieves a fourfold voltage gain and nine-level output with only two energy storage capacitors and ten switching transistors, which significantly reduces the number of power devices and energy storage elements, and reduces the system size and manufacturing cost; at the same time, the steady-state voltage of the first energy storage capacitor and the second energy storage capacitor is determined by the topology itself, without the need for additional dynamic voltage balancing algorithms or balancing circuits, which simplifies the control difficulty. Attached Figure Description

[0016] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings of the embodiments of the present invention will be briefly described below. Obviously, the drawings described below only relate to some embodiments of the present invention and are not intended to limit the present invention.

[0017] Figure 1 The overall structure diagram of the multilevel inverter of the present invention is shown.

[0018] Figure 2 The modal equivalent circuit diagram of the present invention is shown.

[0019] Figure 3 The modal-two equivalent circuit diagram of the present invention is shown.

[0020] Figure 4 The modal three-equivalent circuit diagram of the present invention is shown.

[0021] Figure 5 The modal four equivalent circuit diagram of the present invention is shown.

[0022] Figure 6 The modal five equivalent circuit diagram of the present invention is shown.

[0023] Figure 7The equivalent circuit diagram of the modal six of the present invention is shown.

[0024] Figure 8 The equivalent circuit diagram of the modal seven of the present invention is shown.

[0025] Figure 9 The modal eight equivalent circuit diagram of the present invention is shown.

[0026] Figure 10 The equivalent circuit diagram of the nine modes of the present invention is shown.

[0027] Figure 11 A schematic diagram of the output waveform of the present invention is shown.

[0028] Figure 12 A schematic diagram of the switching state of the present invention is shown.

[0029] Figure 13 The control flowchart of the present invention is shown. Detailed Implementation

[0030] To enable those skilled in the art to better understand the present invention, the present invention will be further described in detail below with reference to specific embodiments and accompanying drawings.

[0031] The terminology used in this invention is that which is currently widely used in the art in consideration of the function of the invention; however, these terms may vary according to the intent of those skilled in the art, precedent, or new technology in the art. Furthermore, specific terms may be chosen by the applicant, and in such cases, their detailed meanings will be described in the detailed description of the invention. Therefore, the terms used in this specification should not be construed as simple names, but rather based on their meanings and the overall description of the invention.

[0032] Reference Figures 1-12 This embodiment provides a multilevel inverter, which includes, The main circuit module 1 includes an energy storage unit 11 and a switching unit 12; Energy storage unit 11 is connected to DC input power supply 100 and is used to boost the voltage of DC input power supply 100 in charging mode and output multiple DC voltages of different amplitudes in discharging mode. Switching unit 12 is connected between the output terminal of energy storage unit 11 and load Z and is used to alternately apply multiple DC voltages of different amplitudes to load Z with positive or negative polarity to form a multi-level AC stepped wave on load Z. Control circuit module 2 includes signal acquisition and processing unit 21 and drive output unit 22. Signal acquisition and processing unit 21 acquires the output voltage and output current of load Z and performs calculations with reference voltage 200 to generate a modulation signal. Drive output unit 22 generates a switching control signal according to the modulation signal and outputs it to switching unit 12. Energy storage unit 11 receives electrical energy from DC input power supply 100 and boosts its voltage in charging mode and outputs multiple DC voltages of different amplitudes in discharging mode. The stored electrical energy is output in the form of multiple DC voltages of different amplitudes; the switching unit 12 applies multiple DC voltages of different amplitudes alternately to the load Z with positive or negative polarity, thereby forming a multi-level AC stepped wave on the load Z; during this process, the control circuit module 2 collects the output voltage and output current of the load Z in real time through the signal acquisition and calculation unit 21 and performs calculation with the reference voltage 200 to generate a modulation signal and output it to the drive output unit 22. The drive output unit 22 generates a switching control signal according to the modulation signal and outputs it to the switching unit 12, thereby realizing closed-loop control of the main circuit module 1; this architecture achieves multi-level AC output with fewer power devices through the coordinated work of the energy storage unit 11 and the switching unit 12, effectively reducing the voltage harmonic content and the voltage stress of the power devices, while improving the dynamic response capability of the system under different load conditions.

[0033] In some embodiments, such as Figure 1 The energy storage unit 11 includes a first energy storage capacitor C1 and a second energy storage capacitor C2. By controlling the charging and discharging states of the first energy storage capacitor C1 and the second energy storage capacitor C2 in a timing sequence, the energy storage unit 11 can increase the voltage of the DC input power supply 100 by utilizing the parallel charging characteristics of the capacitors in the charging mode, and output multiple DC voltages of different amplitudes by utilizing the series discharging characteristics of the capacitors in the discharging mode. This dual-capacitor structure only requires two energy storage capacitors to achieve voltage boosting and multi-level output. Compared with the topology of traditional multi-level inverters that require a large number of energy storage capacitors, this invention reduces the number of energy storage components, reduces system size and manufacturing cost, and simplifies the complexity of capacitor voltage balance control.

[0034] In some embodiments, such as Figure 1The switching unit 12 includes a first switch S1, a second switch S2, a third switch S3, a fourth switch S4, a fifth switch S5, and a sixth switch S6. The first switch S1 and the second switch S2 are connected in series and then connected in parallel with the first energy storage capacitor C1. One end of the first switch S1 is connected to the positive terminal of the DC input power supply 100, and the other end of the first switch S1 and one end of the second switch S2 are connected to the first node. The other end of the second switch S2 is connected to the negative terminal of the DC input power supply 100. The first energy storage capacitor C1 is connected between the first node and the other end of the second switch S2. One end of the third switch S3 is connected to the negative terminal of the first energy storage capacitor C1. The other end of switch S3 and one end of the fourth switch S4 are connected to the second node. The other end of the fourth switch S4 is connected to the positive terminal of the second energy storage capacitor C2, and the negative terminal of the second energy storage capacitor C2 is connected to the negative terminal of the DC input power supply 100. The fifth switch S5 is connected between the second node and the positive terminal of the second energy storage capacitor C2. The sixth switch S6 is connected between the negative terminal of the second energy storage capacitor C2 and the first terminal of the load Z. The first switch S1, the second switch S2, and the first energy storage capacitor C1 form the first charging and discharging path. When the first switch S1 is turned on and the second switch S2 is turned off, the DC input power supply 100 charges the first energy storage capacitor C1 through the first switch S1. When the first switch S1 is off and the second switch S2 is on, the first energy storage capacitor C1 is connected in series with the DC input power supply 100 through the second switch S2 and outputs a superimposed output. The third switch S3 acts as the discharge circuit control switch for the first energy storage capacitor C1, providing a conduction path when the first energy storage capacitor C1 needs to discharge. The fourth switch S4, the fifth switch S5, and the second energy storage capacitor C2 form a second charging and discharging path. The fourth switch S4 controls the positive terminal of the second energy storage capacitor C2 to be connected, and the fifth switch S5 controls the negative terminal of the second energy storage capacitor C2 to be connected. The sixth switch S6 acts as the discharge circuit control switch for the second energy storage capacitor C2. The discharge circuit is controlled by the first switch S1 through the sixth switch S6. By combining the on and off states, the energy storage unit 11 can switch to different charging and discharging modes, enabling it to output DC voltages of different amplitudes at different times. The first energy storage capacitor C1 can be connected in series with the DC input power supply 100 via the second switch S2, and the second energy storage capacitor C2 can be further connected in series with the DC input power supply 100 and the first energy storage capacitor C1 via the fifth switch S5, thereby increasing the voltage gain. This switching configuration uses six switching transistors to achieve independent charging and discharging control of the two energy storage capacitors, reducing the number of power devices while ensuring control flexibility, lowering conduction losses and switching losses, and thus improving the overall conversion efficiency of the system.

[0035] In some embodiments, such as Figure 1The switching unit 12 also includes a seventh switch S7, an eighth switch S8, a ninth switch S9, and a tenth switch S10; the seventh switch S7 is connected between the second node and the second end of the load Z; the eighth switch S8 is connected between the negative terminal of the DC input power supply 100 and the first end of the load Z; the ninth switch S9 is connected between the second end of the load Z and the negative terminal of the DC input power supply 100; the tenth switch S10 is connected between the first end of the load Z and the positive terminal of the DC input power supply 100; the second node is the output terminal of the energy storage unit 11. When the seventh switch S7 and the tenth switch S10 are turned on, and the eighth switch S8 and the ninth switch S9 are turned off, the first end of the load Z is connected to the second node, and the second end is connected to the negative terminal of the DC input power supply 100, and the load Z is subjected to a positive voltage. When the eighth switch S8 and the ninth switch S9 are turned on, and the seventh switch S7 and the tenth switch S10 are turned off, the first end of the load Z is connected to the negative terminal of the DC input power supply 100, and the second end is connected to the second node, and the load Z is subjected to a reverse voltage. This achieves flexible switching of the voltage polarity from the output to the load Z. This commutation structure, in conjunction with the front-stage boost network formed by the first switch S1 to the sixth switch S6, allows the positive voltage output from the front stage to form a symmetrical positive and negative multi-level stepped wave on the load Z after polarity switching, thereby achieving AC output with the fewest possible commutation switches, reducing switching losses during the commutation process while ensuring the quality of the output waveform.

[0036] In some embodiments, such as Figures 2-10 The switching unit 12 generates nine stepped voltage levels on the load Z through nine operating modes: The first mode is the initial mode. In this mode, the second switch S2, the fourth switch S4, the sixth switch S6, the ninth switch S9 and the tenth switch S10 are turned on. At this time, the first energy storage capacitor C1 is connected in series with the DC input power supply 100 through the second switch S2. The two are superimposed to charge the second energy storage capacitor C2. The two ends of the load Z are short-circuited and the output voltage is 0. In the second to fifth modes, the seventh switch S7 and the tenth switch S10 are both turned on, and the remaining switches are turned on in the following combinations: the first switch S1, the third switch S3, and the fourth switch S4 output +1VDC; the second switch S2, the fourth switch S4, and the sixth switch S6 output +2VDC; the first switch S1, the third switch S3, and the fifth switch S5 output +3VDC; the second switch S2 and the fifth switch S5 output +4VDC. By turning on the seventh switch S7 and the tenth switch S10 together, a positive voltage is applied to the load Z. In conjunction with the sequential switching of the different turns-on combinations of the first switch S1 to the sixth switch S6, a stepped voltage of +1VDC, +2VDC, +3VDC, and +4VDC is established on the load Z in sequence. In modes six through nine, switches S8 and S9 are both turned on, and the remaining switches are turned on in the following combinations: switch S1, switch S3, and switch S4 output -1VDC; switch S2, switch S4, and switch S6 output -2VDC; switch S1, switch S3, and switch S5 output -3VDC; switch S2 and switch S5 output -4VDC. By turning on switches S8 and S9 together, a negative voltage is applied to the load Z, and with the switching combination symmetrical to the positive half-cycle, a stepped level of -1VDC, -2VDC, -3VDC, and -4VDC is established on the load Z in sequence. The nine voltage levels are arranged sequentially according to the variation pattern of a sine wave, and the voltage difference between adjacent levels is constant at 1VDC, which makes the output waveform closer to a sine wave, significantly reducing the total harmonic distortion rate of the output voltage, and helping to reduce the size and cost of the output filter.

[0037] In some embodiments, such as Figure 1 The signal acquisition and processing unit 21 includes a voltage sampling terminal 211, a current sampling terminal 212, a voltage regulator 213, and a current regulator 214. The input terminals of the voltage sampling terminal 211 and the current sampling terminal 212 are respectively connected to the output terminal of the load Z. The output terminal of the voltage sampling terminal 211 is connected to the input terminal of the voltage regulator 213. The voltage regulator 213 is connected to the reference voltage 200. The output terminals of the voltage regulator 213 and the current sampling terminal 212 are respectively connected to the input terminals of the current regulator 214. The drive output unit 22 includes a sinusoidal pulse width modulation module 221 and a drive terminal 222. The output terminal of the current regulator 214 is connected to the input terminal of the sinusoidal pulse width modulation module 221. The output terminal of the sinusoidal pulse width modulation module 221 is connected to the input terminal of the drive terminal 222. The output terminal of the drive terminal 222 is connected to the switching unit 12. The voltage sampling terminal 211 acquires the output voltage of the load Z and sends it to the voltage regulator. Voltage regulator 213 compares and adjusts the acquired voltage value with reference voltage 200 to generate a setpoint for the inner current loop. Current sampling terminal 212 acquires the output current of load Z and sends it to current regulator 214. Current regulator 214 compares and adjusts the sampled current with the setpoint output by voltage regulator 213 to generate a modulation signal. This modulation signal is processed sequentially by sinusoidal pulse width modulation module 221 and driver terminal 222, and then converted into a switching control signal and output to switching unit 12. Through the dual closed-loop structure of voltage outer loop and current inner loop, the amplitude of output voltage and waveform quality of output current can be controlled simultaneously. It can respond quickly and maintain output voltage stability when the load changes abruptly, effectively suppressing output waveform distortion. In addition, sinusoidal pulse width modulation module 221 modulates the modulation signal with a high-frequency carrier, making the switching frequency much higher than the output frequency, thus improving the spectral characteristics of the output waveform.

[0038] In some embodiments, such as Figures 1-10 The steady-state voltage of the first energy storage capacitor C1 is 1VDC, and the steady-state voltage of the second energy storage capacitor C2 is 2VDC. During the cyclic switching of the nine operating modes, the first energy storage capacitor C1 is repeatedly charged to twice the voltage of the DC input power supply 100, i.e., the steady-state voltage is 1VDC. The second energy storage capacitor C2 is repeatedly charged by the series combination of the DC input power supply 100 and the first energy storage capacitor C1, and its steady-state voltage is increased to twice the voltage of the DC input power supply 100, i.e., 2VDC. This asymmetrical capacitor voltage distribution strategy of "1VDC+1VDC+2VDC" The design incorporates a series connection of the DC input power supply 100, the first energy storage capacitor C1, and the second energy storage capacitor C2 in the highest output mode, resulting in an output voltage of 4VDC and achieving a fourfold voltage gain. This voltage gain can be achieved with a single-stage inverter topology without the need for additional boost circuits or transformers, reducing system energy conversion stages, lowering power losses, and improving overall system efficiency. Furthermore, the capacitor voltage distribution is determined by the topology itself and can be naturally maintained in steady state without the need for complex dynamic voltage balancing algorithms, thus enhancing system reliability.

[0039] In some embodiments, such as Figures 1-13 Furthermore, an inverter control method is provided for multi-level inverters. First, the signal acquisition and processing unit 21 acquires the output voltage and output current of the load Z in real time. The voltage outer loop calculates the error between the acquired output voltage and the reference voltage 200 using the proportional-integral operation of the voltage regulator 213, and uses this as the setpoint for the current inner loop. The current inner loop calculates the error between the acquired output current and the setpoint of the current loop using the proportional operation of the current regulator 214, and generates a modulation signal. This dual closed-loop control structure ensures accurate tracking of the system output voltage to the reference voltage 200 and low distortion of the output current waveform. Even under conditions of sudden load changes or fluctuations in the DC input power supply 100, the system can still maintain stable output performance. Second, the drive output unit 22 modulates the modulation signal with multi-carrier stacked sinusoidal pulse width modulation. The mode is converted into a switch control signal and output to the switch unit 12 to control the first switch S1 to the tenth switch S10 to turn on and off sequentially according to the nine working modes. The multi-carrier stacked modulation mode uses multiple stacked triangular carriers to generate multiple sets of PWM pulses corresponding to the amplitude of the modulation signal within one modulation cycle. By cooperating with the above-mentioned nine working mode switch tables, the inverter synthesizes a high-quality nine-level stepped wave on the load Z. This method does not require complex space vector calculation or table lookup interpolation operations, has low computational load and fast response speed, and is suitable for the real-time implementation of low-cost digital controllers. It does not contain an independent capacitor voltage balancing control subroutine. The capacitor voltage achieves hardware self-balancing through the cyclic switching of the nine working modes, which reduces the development difficulty and operating burden of the control algorithm.

[0040] In some embodiments, such as Figure 13 The voltage regulator 213 adopts a proportional-integral (PI) regulation method. The proportional element generates an instantaneous response to the current voltage deviation, while the integral element accumulates historical deviations to eliminate steady-state errors. The outputs of both are used as the setpoint for the current loop. The current regulator 214 adopts a proportional regulation method, generating an instantaneous response to the current deviation signal to generate a modulation signal. The outer voltage loop uses PI regulation to ensure that the system tracks the reference voltage 200 with zero steady-state error, while the inner current loop uses P regulation to take advantage of the fast response speed of the current loop and avoid the phase lag introduced by the integral element. The combination of the two measures both the steady-state accuracy and dynamic response speed of the system, and can quickly recover to steady state when the load changes abruptly.

[0041] In some embodiments, such as Figure 13 Eight triangular carrier waves of the same frequency are vertically stacked in the voltage axis direction. The instantaneous value of the modulation signal is compared with each of the eight carrier waves one by one. The target level to be output is determined according to the amplitude range of the modulation signal. Then, the corresponding switch control signal is output by looking up the table according to the preset mode level mapping relationship. This modulation method converts the continuous modulation signal into a nine-level stepped wave control command. The logic is clear and the operation is simple, without the need for complex vector calculations. At the same time, the nine mode switch tables have clear regularity, and the storage and retrieval are efficient, which facilitates real-time control on low-cost controllers.

[0042] In summary, the DC input power supply 100 charges the first energy storage capacitor C1 to 1VDC through the first switch S1. Subsequently, the DC input power supply 100 and the first energy storage capacitor C1 are connected in series to charge the second energy storage capacitor C2 to 2VDC. This voltage is determined by the topology itself and does not require a complex dynamic voltage balancing algorithm. The first switch S1 to the sixth switch S6 control the selective series connection of the DC input power supply 100, the first energy storage capacitor C1, and the second energy storage capacitor C2 through a combination of on and off states. They also coordinate with the seventh switch S7 to the tenth switch S10 to switch polarity switching, forming nine stepped voltage levels (0, ±1VDC, ±2VDC, ±3VDC, ±4VDC) on the load Z, with the highest level being... In output mode, the three components are superimposed in series to achieve a fourfold voltage gain without the need for an additional boost circuit. Simultaneously, the control circuit module 2 acquires the output voltage and current of the load Z, which are processed by the voltage regulator 213 and the current regulator 214 to generate a modulation signal. This signal is then converted into a switching control signal by the sinusoidal pulse width modulation module 221 and output to the switching unit 12, forming a dual closed-loop control to ensure that the output accurately tracks the reference voltage 200. This solution achieves a fourfold boost and nine-level output with only two energy storage capacitors and ten switching transistors, significantly reducing system cost, harmonic content, and device voltage stress. Furthermore, the capacitor voltage is self-balanced by hardware, making control simple and dynamic response fast, suitable for real-time implementation of low-cost digital controllers.

[0043] Finally, it should be noted that the methods and devices described in detail above are merely embodiments, and those skilled in the art can modify these embodiments in different ways as long as they do not depart from the scope of the present invention.

Claims

1. A multilevel inverter, characterized in that: include, The main circuit module (1) includes an energy storage unit (11) and a switching unit (12); The energy storage unit (11) is connected to the DC input power supply (100) and is used to boost the voltage of the DC input power supply (100) in the charging mode and output multiple DC voltages of different amplitudes in the discharging mode. The switching unit (12) is connected between the output terminal of the energy storage unit (11) and the load (Z) to apply multiple DC voltages of different amplitudes alternately to the load (Z) with positive or negative polarity to form a multi-level AC stepped wave on the load (Z). The control circuit module (2) includes a signal acquisition and calculation unit (21) and a drive output unit (22). The signal acquisition and calculation unit (21) acquires the output voltage and output current of the load (Z) and performs calculations with the reference voltage (200) to generate a modulation signal. The drive output unit (22) generates a switch control signal according to the modulation signal and outputs it to the switch unit (12).

2. The multilevel inverter according to claim 1, characterized in that: The energy storage unit (11) includes a first energy storage capacitor (C1) and a second energy storage capacitor (C2).

3. The multilevel inverter according to claim 2, characterized in that: The switching unit (12) includes a first switch (S1), a second switch (S2), a third switch (S3), a fourth switch (S4), a fifth switch (S5), and a sixth switch (S6). The first switch (S1) and the second switch (S2) are connected in series and then connected in parallel with the first energy storage capacitor (C1). One end of the first switch (S1) is connected to the positive terminal of the DC input power supply (100), and the other end of the first switch (S1) and one end of the second switch (S2) are connected to the first node. The other end of the second switch (S2) is connected to the negative terminal of the DC input power supply (100). The first energy storage capacitor (C1) is connected between the first node and the other end of the second switch (S2). One end of the third switch (S3) is connected to the negative terminal of the first energy storage capacitor (C1), and the other end of the third switch (S3) and one end of the fourth switch (S4) are connected to the second node. The other end of the fourth switch (S4) is connected to the positive terminal of the second energy storage capacitor (C2), and the negative terminal of the second energy storage capacitor (C2) is connected to the negative terminal of the DC input power supply (100). The fifth switch (S5) is connected between the second node and the positive terminal of the second energy storage capacitor (C2); the sixth switch (S6) is connected between the negative terminal of the second energy storage capacitor (C2) and the first terminal of the load (Z).

4. The multilevel inverter according to claim 3, characterized in that: The switching unit (12) also includes a seventh switch (S7), an eighth switch (S8), a ninth switch (S9), and a tenth switch (S10). The seventh switch (S7) is connected between the second node and the second end of the load (Z); The eighth switch (S8) is connected between the negative terminal of the DC input power supply (100) and the first terminal of the load (Z); The ninth switch (S9) is connected between the second terminal of the load (Z) and the negative terminal of the DC input power supply (100); The tenth switch (S10) is connected between the first end of the load (Z) and the positive terminal of the DC input power supply (100).

5. The multilevel inverter according to claim 4, characterized in that: The switching unit (12) generates nine stepped voltage levels on the load (Z) through nine operating modes: In the first mode, the second switch (S2), the fourth switch (S4), the sixth switch (S6), the ninth switch (S9), and the tenth switch (S10) are turned on, and the output voltage is 0. In the second to fifth modes, the seventh switch (S7) and the tenth switch (S10) are both turned on, and the remaining switches are turned on sequentially in the following combinations: the first switch (S1), the third switch (S3), and the fourth switch (S4) output +1VDC; the second switch (S2), the fourth switch (S4), and the sixth switch (S6) output +2VDC; the first switch (S1), the third switch (S3), and the fifth switch (S5) output +3VDC; the second switch (S2) and the fifth switch (S5) output +4VDC. In modes six through nine, the eighth switch (S8) and the ninth switch (S9) are both turned on, and the remaining switches are turned on in the following combinations: the first switch (S1), the third switch (S3), and the fourth switch (S4) output -1VDC; the second switch (S2), the fourth switch (S4), and the sixth switch (S6) output -2VDC; the first switch (S1), the third switch (S3), and the fifth switch (S5) output -3VDC; and the second switch (S2) and the fifth switch (S5) output -4VDC.

6. The multilevel inverter according to claim 5, characterized in that: The signal acquisition and processing unit (21) includes a voltage sampling terminal (211), a current sampling terminal (212), a voltage regulator (213), and a current regulator (214); the input terminals of the voltage sampling terminal (211) and the current sampling terminal (212) are respectively connected to the output terminal of the load (Z), the output terminal of the voltage sampling terminal (211) is connected to the input terminal of the voltage regulator (213), the voltage regulator (213) is connected to the reference voltage (200), and the output terminals of the voltage regulator (213) and the current sampling terminal (212) are respectively connected to the input terminal of the current regulator (214); The drive output unit (22) includes a sinusoidal pulse width modulation module (221) and a drive terminal (222); the output terminal of the current regulator (214) is connected to the input terminal of the sinusoidal pulse width modulation module (221), the output terminal of the sinusoidal pulse width modulation module (221) is connected to the input terminal of the drive terminal (222), and the output terminal of the drive terminal (222) is connected to the switch unit (12).

7. The multilevel inverter according to claim 6, characterized in that: The steady-state voltage of the first energy storage capacitor (C1) is 1VDC, and the steady-state voltage of the second energy storage capacitor (C2) is 2VDC.

8. An inverter control method, characterized in that: The multilevel inverter applied to claim 6 or 7 further includes, The signal acquisition and processing unit (21) acquires the output voltage and output current of the load (Z), and the error between the output voltage and the reference voltage (200) is calculated by the voltage regulator (213) and used as the current loop setpoint. The error between the output current and the current loop setpoint is calculated by the current regulator (214) and a modulation signal is generated. The driving output unit (22) generates a switch control signal by using a multi-carrier stacked sinusoidal pulse width modulation method, and outputs it to the switch unit (12) so that the first switch (S1) to the tenth switch (S10) are turned on and off in nine working modes, forming nine step levels on the load (Z).

9. The inverter control method according to claim 8, characterized in that: The voltage regulator (213) uses a proportional-integral (PI) regulation method to perform a proportional-integral operation on the error between the output voltage and the reference voltage (200) to generate the current loop setpoint; the current regulator (214) uses a proportional regulation method to perform a proportional operation on the error between the output current and the current loop setpoint to generate a modulation signal.

10. The inverter control method according to claim 9, characterized in that: The multi-carrier stacked sinusoidal pulse width modulation uses eight triangular carriers of the same frequency stacked together. The modulation signal is compared with the eight triangular carriers of the same frequency. Based on the comparison result, a table is looked up to output the switch control signal corresponding to each of the nine working modes, so as to drive the first switch (S1) to the tenth switch (S10) to operate according to the required combination of conduction and cutoff of each mode.

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