Three-level inverter circuit unit, three-level heric circuit and solid state transformer

Abstract

The application relates to the field of power electronics, and discloses a three-level inverter circuit unit, a three-level HERIC circuit and a solid-state transformer. The inverter midpoint of the three-level inverter bridge arm arranged in the three-level inverter circuit unit is used for outputting three levels. Compared with the inverter midpoint of a two-level inverter outputting two levels, the number of output levels is increased, AC fluctuation is reduced, the current ripple on the AC side is reduced, the current index can be improved, and in particular, the switching device of the auxiliary branch is not only connected in parallel between the inverter midpoints of the two three-level inverter bridge arms, but also has a series midpoint of the switching device of the auxiliary branch connected to the bus midpoint corresponding to the bus capacitor, so that the maximum voltage is clamped at half of the bus, the problem of inconsistent voltage sharing of the series connection of the auxiliary branch devices is solved, the stability is better, the selection of the switching device is facilitated, and the three-level inverter circuit unit is more suitable for high-voltage scenes.

Description

Technical Field

[0001] This invention relates to the field of power electronics technology, and in particular to a three-level inverter circuit unit, a three-level HERIC circuit, and a solid-state transformer. Background Technology

[0002] In many scenarios, inverters need to have auxiliary branches. For example, the HERIC inverter adds an auxiliary bypass to the full-bridge inverter. It can be seen as an improved topology that deeply optimizes two major pain points of traditional full-bridge inverters in transformerless photovoltaic grid-connected applications—efficiency bottleneck and leakage current problem. In the freewheeling stage, by short-circuiting the main bridge arm, the current flows back through a dedicated path with extremely low on-resistance, instead of flowing into the high-loss body diode, thereby halving the freewheeling loss. Such auxiliary branches of two-level inverters are quite common. However, for three-level inverters, if the three-level inverter uses the same two-level circuit, the switching devices of the auxiliary branch need to withstand greater voltage stress, which can easily lead to inconsistent device specifications or the lack of available devices. If a series structure of devices is used for voltage division, the large differences in the parasitic capacitance parameters of the switching devices can easily lead to uneven voltage stress distribution and damage. Summary of the Invention

[0003] This invention aims to at least partially solve one of the technical problems in related technologies. To this end, this invention proposes a three-level inverter circuit unit, a three-level HERIC circuit, and a solid-state transformer that offer good stability, facilitate device selection, and improve current performance.

[0004] In a first aspect, embodiments of the present invention provide a three-level inverter circuit unit, comprising: First DC port, second DC port, first AC port, and second AC port; The first three-level inverter bridge arm and the second three-level inverter bridge arm, the DC side of the first three-level inverter bridge arm and the DC side of the second three-level inverter bridge arm are both connected to the first DC port and the second DC port, the inverter midpoint of the first three-level inverter bridge arm is connected to the first AC port, and the inverter midpoint of the second three-level inverter bridge arm is connected to the second AC port. The positive bus capacitor and the negative bus capacitor are connected in series between the first DC port and the second DC port; The auxiliary branch includes a first switching unit and a second switching unit. One end of the first switching unit is connected in series with one end of the second switching unit. The midpoint of the series connection between the first switching unit and the second switching unit is connected to the midpoint of the series connection between the positive bus capacitor and the negative bus capacitor. The other end of the first switching unit is connected to the first AC port and the inverter midpoint of the first three-level inverter bridge arm, respectively. The other end of the second switching unit is connected to the second AC port and the inverter midpoint of the second three-level inverter bridge arm, respectively.

[0005] Optionally, in one embodiment of the present invention, the first three-level inverter bridge arm / the second three-level inverter bridge arm adopts an INPC three-level inverter structure, a TNPC three-level inverter structure, or a flying capacitor three-level inverter structure.

[0006] Optionally, in one embodiment of the present invention, the first switching unit includes a first switching element and a second switching element connected back-to-back in series, and the second switching unit includes a third switching element and a fourth switching element connected back-to-back in series; the second switching element is connected to the third switching element, and the midpoint of the series connection between the second switching element and the third switching element is connected to the midpoint of the series connection between the positive bus capacitor and the negative bus capacitor; the first switching element is connected to the first AC port and the inverter midpoint of the first three-level inverter bridge arm, respectively, and the fourth switching element is connected to the second AC port and the inverter midpoint of the second three-level inverter bridge arm, respectively.

[0007] Optionally, in one embodiment of the present invention, the first switching element, the second switching element, the third switching element and the fourth switching element are all MOSFETs or IGBTs of the same specifications.

[0008] Optionally, in one embodiment of the present invention, a relay is further included, the relay being connected in parallel between the first AC port and the second AC port.

[0009] Secondly, embodiments of the present invention provide a three-level HERIC circuit, comprising: The three-level inverter circuit unit as described in the first aspect; The first PFC inductor and the second PFC inductor are respectively connected to the power grid at one end and at one end of the first PFC inductor. The other end of the first PFC inductor is connected to the inverter midpoint of the first switching unit and the first three-level inverter bridge arm through the first AC port. The other end of the second PFC inductor is connected to the inverter midpoint of the second switching unit and the second three-level inverter bridge arm through the second AC port.

[0010] Thirdly, embodiments of the present invention provide an SST power module unit, comprising: The three-level inverter circuit unit as described in the first aspect; Isolated resonant cavity; An output-side rectifier circuit, wherein the output terminal of the output-side rectifier circuit is used to connect the positive terminal of the DC power supply and the negative terminal of the DC power supply; The three-level DC-DC circuit has its input terminals connected to the first DC port, the second DC port, and the midpoint of the series connection between the positive bus capacitor and the negative bus capacitor, respectively. The output terminal of the three-level DC-DC circuit is connected to the output-side rectifier circuit through the isolated resonant cavity.

[0011] Optionally, in one embodiment of the present invention, the three-level DC-DC circuit adopts an I-type three-level circuit, a T-type three-level circuit, or a four-switch three-level circuit.

[0012] Fourthly, embodiments of the present invention provide a solid-state transformer, comprising: Multiple SST power module units as described in the third aspect; The AC side of each SST power module unit is connected in series, and the DC side is connected in parallel.

[0013] The three-level inverter circuit unit, three-level HERIC circuit, and solid-state transformer proposed in this invention are used to output three levels at the inverter midpoint of the three-level inverter bridge arm in the three-level inverter circuit unit. Compared with the two-level inverter, the inverter midpoint outputs two levels, which increases the number of output levels, reduces AC fluctuations, lowers the current ripple on the AC side, and improves the current performance. In particular, the switching devices of the auxiliary branch are not only connected in parallel between the inverter midpoints of the two three-level inverter bridge arms, but also the series midpoint of the switching devices of the auxiliary branch is connected to the bus midpoint corresponding to the bus capacitor, thereby clamping the maximum voltage at half the bus and solving the problem of inconsistent voltage equalization of the series devices in the auxiliary branch. This results in better stability, facilitates the selection of switching devices, and is more suitable for high-voltage scenarios. Attached Figure Description

[0014] Figure 1 This is a circuit topology schematic diagram of a three-level inverter circuit unit provided in an embodiment of the present invention; Figure 2(a) is a circuit topology diagram of an INPC three-level inverter structure provided in an embodiment of the present invention; Figure 2(b) is a circuit topology schematic diagram of a TNPC three-level inverter structure provided in an embodiment of the present invention; Figure 2(c) is a circuit topology schematic diagram of a flying capacitor three-level inverter structure provided in an embodiment of the present invention; Figure 3This is a circuit topology diagram of a three-level inverter circuit unit using an INPC three-level inverter structure provided in an embodiment of the present invention; Figure 4 This is a circuit topology schematic diagram of a three-level inverter circuit unit provided in another embodiment of the present invention; Figure 5 This is a circuit topology schematic diagram of a three-level inverter circuit unit with a configured relay provided in another embodiment of the present invention; Figure 6 This is a circuit topology schematic diagram of a three-level HERIC circuit provided in an embodiment of the present invention; Figure 7 This is a circuit topology schematic diagram of an SST power module unit provided in an embodiment of the present invention; Figure 8 This is a circuit topology schematic diagram of an SST power module unit provided in another embodiment of the present invention. Detailed Implementation

[0015] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0016] Figure 1 The circuit topology diagram of a three-level inverter circuit unit provided in an embodiment of the present invention is shown.

[0017] like Figure 1 As shown, the three-level inverter circuit unit may include, but is not limited to, the following: First DC port DC1, second DC port DC2, first AC port AC1, and second AC port AC2; The first three-level inverter bridge arm and the second three-level inverter bridge arm, the DC side of the first three-level inverter bridge arm and the DC side of the second three-level inverter bridge arm are both connected to the first DC port DC1 and the second DC port DC2. The inverter midpoint of the first three-level inverter bridge arm is connected to the first AC port AC1, and the inverter midpoint of the second three-level inverter bridge arm is connected to the second AC port AC2. The positive bus capacitor C1 and the negative bus capacitor C2 are connected in series between the first DC port DC1 and the second DC port DC2. The auxiliary branch includes the first switching unit (corresponding to...) Figure 1 "S1" in the middle) and the second switching unit (corresponding to Figure 1In the “S2” section, one end of the first switching unit is connected in series with one end of the second switching unit, and the midpoint of the series connection between the first and second switching units is connected to the midpoint of the series connection between the positive bus capacitor C1 and the negative bus capacitor C2; the other end of the first switching unit is connected to the first AC port AC1 and the inverter midpoint of the first three-level inverter bridge arm, respectively, and the other end of the second switching unit is connected to the second AC port AC2 and the inverter midpoint of the second three-level inverter bridge arm, respectively.

[0018] It can be seen that the inverter midpoint of the three-level inverter bridge arm configured in the three-level inverter circuit unit is used to output three levels. Compared with the two-level inverter, the inverter midpoint outputs two levels, increasing the number of output levels, reducing AC fluctuations, lowering AC current ripple, and improving current performance. In particular, the switching devices of the auxiliary branch are not only connected in parallel between the inverter midpoints of the two three-level inverter bridge arms, but also in series at the midpoint of the auxiliary branch's switching devices (i.e., Figure 1 The “O” shown below (hereinafter the same, will not be elaborated further) is connected to the midpoint of the bus corresponding to the bus capacitor (i.e. Figure 1 (The “N” shown below is the same and will not be elaborated further.) This clamps the maximum voltage to the half busbar, solving the problem of inconsistent voltage equalization in the series connection of auxiliary branch devices. It has better stability, facilitates the selection of switching devices, and is more suitable for high-voltage scenarios.

[0019] Specifically, Figure 1 The working principle of part of the three-level inverter circuit unit shown is as follows: The inverter midpoint of the first three-level inverter bridge arm outputs three voltage levels: +Vbus / 2, 0V, and -Vbus / 2, where Vbus is the bus voltage. Since the first switching unit of the auxiliary branch is connected in parallel between the inverter midpoint of this inverter bridge arm and the corresponding bus midpoint, the absolute value of the voltage of the first switching unit is at most Vbus / 2. Similarly, the inverter midpoint of the second three-level inverter bridge arm also outputs three voltage levels: +Vbus / 2, 0V, and -Vbus / 2. Since the second switching unit of the auxiliary branch is connected in parallel between the inverter midpoint of this inverter bridge arm and the corresponding bus midpoint, the absolute value of the voltage of the second switching unit is at most Vbus / 2. The series midpoint of the first and second switching units of the auxiliary branch is connected to the bus midpoint N, forcibly pulling the potential of the series midpoint of the switching units to the midpoint potential, thereby avoiding midpoint potential drift due to parameter unevenness. Therefore, the voltage stress of any switching device in the auxiliary branch will not exceed the single-sided bus voltage, i.e., Vbus / 2.

[0020] In one embodiment, as shown in Figure 2(a), the first three-level inverter bridge arm / second three-level inverter bridge arm may, but is not limited to, adopt an INPC three-level inverter structure; or, as shown in Figure 2(b), may, but is not limited to, adopt a TNPC three-level inverter structure; or, as shown in Figure 2(c), may, but is not limited to, adopt a flying capacitor three-level inverter structure. The working principle of the above structures is well known to those skilled in the art, and the corresponding specifications and parameters can be set by themselves, and will not be elaborated here.

[0021] In one embodiment, in addition to the individual circuit structures shown in Figures 2(a), 2(b), and 2(c), the first three-level inverter bridge arm and the second three-level inverter bridge arm may also, but are not limited to, adopt the same circuit structure as described above. For example, both may adopt the INPC three-level inverter structure shown in Figure 2(a), or a combination of different circuit structures, with both adopting the INPC three-level inverter structure and the TNPC three-level inverter structure shown in Figures 2(a) and 2(b), respectively. To avoid redundancy, the following embodiments are mainly illustrated using the INPC three-level inverter structure, but are not intended to be the only limitation. Figure 3 As can be seen, both the first three-level inverter bridge arm and the second three-level inverter bridge arm adopt the INPC three-level inverter structure.

[0022] In one embodiment, such as Figure 4 As shown, the first switching unit may include, but is not limited to, a first switching element connected in series back-to-back (corresponding to...). Figure 4 "S1" in the second switching element (corresponding to Figure 4 In the context of “S1_1”, the second switching unit may, but is not limited to, include a third switching element connected in series back-to-back. Figure 4 "S2" in the text and the fourth switching element (corresponding to Figure 4 (S2_1 in the text); the second switching element is connected to the third switching element, and the midpoint of the series connection between the second and third switching elements is connected to the midpoint of the series connection between the positive bus capacitor C1 and the negative bus capacitor C2; the first switching element is connected to the inverter midpoint of the first AC port AC1 and the first three-level inverter bridge arm, respectively; and the fourth switching element is connected to the inverter midpoint of the second AC port AC2 and the second three-level inverter bridge arm, respectively.

[0023] Preferably, the first, second, third, and fourth switching elements can all be, but are not limited to, MOSFETs or IGBTs of the same specifications. Their specific parameters can be set according to the actual scenario and are not limited here.

[0024] Understandably, in practical applications, the switching transistors in the auxiliary branch are affected by parasitic parameters. When the auxiliary branch is in the off state, the current flowing through the parasitic capacitance of the auxiliary branch remains constant; for example... Figure 4 As shown, since the current flowing through the parasitic capacitances of the first, second, third, and fourth switching elements is the same, the voltage difference caused by the parasitic capacitance is inversely proportional to the parasitic capacitance. For example, when the bus input is 1500Vdc, assuming the parasitic capacitance of the first and second switching elements is 100pF and the parasitic capacitance of the third and fourth switching elements is 600pF, then for the device stress of the auxiliary branch, the first and second switching elements are 6 times that of the third and fourth switching elements. If the parasitic parameters are larger, the voltage of the switching tubes in the auxiliary branch will be more unbalanced. Based on the above, when the series midpoint of the auxiliary branch is connected to the corresponding bus midpoint, it is equivalent to the first and second switching elements being connected in parallel with the positive bus capacitor C1, and the third and fourth switching elements being connected in parallel with the negative bus capacitor C2. Therefore, the maximum voltage across the first and second switching elements is clamped across the positive bus capacitor C1, and the maximum voltage across the third and fourth switching elements is clamped across the negative bus capacitor C2. Even if the parasitic parameters are inconsistent, the maximum voltage of the auxiliary branch switching transistor can still be clamped.

[0025] In one embodiment, such as Figure 5 As shown, the three-level inverter circuit unit may also include, but is not limited to, a relay K1. Relay K1 is connected in parallel between the first AC port AC1 and the second AC port AC2. The type and parameters of relay K1 can be selected and set according to the specific scenario, without limitation. Based on the connection of the two switching units, in order to reduce a portion of the auxiliary branch, namely the first switching element (corresponding to...) Figure 5 "S1" in the middle), the second switching element (corresponding to Figure 5 The “S1_1” in the text, and another part, namely the third switching element (corresponding to Figure 5 "S2" in the middle), the fourth switching element (corresponding to Figure 5 The overall loss of “S2_1” in the bypass stage can be reduced by connecting the parallel relay K1 at both ends of the auxiliary branch to carry current. By connecting the parallel relay K1, the relay K1 can be used as the main current-carrying device, thereby reducing the circuit loss of the auxiliary branch. When closing the auxiliary branch, the specific action sequence can be: the drive signal simultaneously drives the first switch element, the second switch element, the third switch element, the fourth switch element, and the relay K1, causing the first switch element, the second switch element, the third switch element, and the fourth switch element to close. The above-mentioned switch elements will close faster than the relay K1. When opening the auxiliary branch, a drive turn-off signal is given, and a delay circuit is added to the first switch element, the second switch element, the third switch element, and the fourth switch element, so that the relay K1 is opened first, and then the individual switch elements are opened last.

[0026] like Figure 6As shown, another embodiment of the present invention also provides a three-level HERIC circuit, which may include, but is not limited to: The three-level inverter circuit unit shown in any of the above embodiments; The first PFC inductor L1 and the second PFC inductor L2 are respectively connected to the power grid. The other end of the first PFC inductor L1 is connected to the inverter midpoint of the first switching unit and the first three-level inverter bridge arm through the first AC port AC1. The other end of the second PFC inductor L2 is connected to the inverter midpoint of the second switching unit and the second three-level inverter bridge arm through the second AC port AC2.

[0027] In one embodiment, the specifications and parameters of the first PFC inductor L1 and the second PFC inductor L2 can be set according to the actual scenario and are not limited thereto.

[0028] In one embodiment, Figure 6 The three-level HERIC circuit shown can be controlled, but is not limited to, in the following ways: Switch S3 and switch S5 are complementary in conduction, switch S4 and switch S6 are complementary in conduction, switch S11 and switch S9 are complementary in conduction, switch S12 and switch S10 are complementary in conduction, the first three-level inverter bridge arm and the second three-level inverter bridge arm are out of phase by 180°, and the second switching element is consistent with the waveform of switch S9, the fourth switching element is consistent with the waveform of switch S9, the first switching element is consistent with the waveform of switch S5, and the third switching element is consistent with the waveform of switch S5.

[0029] like Figure 7 As shown, another embodiment of the present invention also provides a solid-state transformer (SST) power module unit, which may include, but is not limited to, the following: The three-level inverter circuit unit shown in any of the above embodiments; Isolated resonant cavity; The output side rectifier circuit, wherein the output terminal of the output side rectifier circuit is used to connect the positive terminal of the DC power supply and the negative terminal of the DC power supply, and may be, but is not limited to, a three-phase bridge rectifier circuit, etc. The three-level DC-DC circuit has its input terminals connected to the first DC port DC1, the second DC port DC2, and the midpoint of the series connection between the first bus capacitor and the second bus capacitor, respectively. The output terminal of the three-level DC-DC circuit is connected to the output-side rectifier circuit through an isolated resonant cavity.

[0030] In one embodiment, the three-level DC-DC circuit may, but is not limited to, adopt an I-type three-level circuit, a T-type three-level circuit, or a four-switch three-level circuit, etc. This part of the circuit is well known to those skilled in the art and will not be described in detail.

[0031] In one embodiment, reference is made to Figure 8 An isolated resonant cavity may include, but is not limited to, an isolation transformer and a resonant cavity connected in series (such as an LC resonant cavity circuit). One end of the isolation transformer is connected to the output of a three-level DC-DC circuit, and the other end is connected to the output-side rectifier circuit through the resonant cavity; wherein, except for Figure 8 The resonant cavity shown is located on the right side of the isolation transformer. It can also be located on the left side of the isolation transformer.

[0032] In one embodiment, the three-level DC-DC circuit can be adapted for single-phase configuration or for multi-phase interleaved configuration.

[0033] Another embodiment of the present invention also provides a solid-state transformer, which may include, but is not limited to: The SST power module unit shown in any of the above embodiments; The AC side of each SST power module unit is connected in series, and the DC side is connected in parallel.

[0034] The above-described embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention, and should all be included within the protection scope of the present invention.

Claims

1. A three-level inverter circuit unit, characterized in that, include: First DC port, second DC port, first AC port, and second AC port; The first three-level inverter bridge arm and the second three-level inverter bridge arm, the DC side of the first three-level inverter bridge arm and the DC side of the second three-level inverter bridge arm are both connected to the first DC port and the second DC port, the inverter midpoint of the first three-level inverter bridge arm is connected to the first AC port, and the inverter midpoint of the second three-level inverter bridge arm is connected to the second AC port. The positive bus capacitor and the negative bus capacitor are connected in series between the first DC port and the second DC port; The auxiliary branch includes a first switching unit and a second switching unit. One end of the first switching unit is connected in series with one end of the second switching unit. The midpoint of the series connection between the first switching unit and the second switching unit is connected to the midpoint of the series connection between the positive bus capacitor and the negative bus capacitor. The other end of the first switching unit is connected to the first AC port and the inverter midpoint of the first three-level inverter bridge arm, respectively. The other end of the second switching unit is connected to the second AC port and the inverter midpoint of the second three-level inverter bridge arm, respectively.

2. The three-level inverter circuit unit according to claim 1, characterized in that, The first three-level inverter bridge arm / the second three-level inverter bridge arm adopts an INPC three-level inverter structure, a TNPC three-level inverter structure, or a flying capacitor three-level inverter structure.

3. The three-level inverter circuit unit according to claim 1, characterized in that, The first switching unit includes a first switching element and a second switching element connected back-to-back in series. The second switching unit includes a third switching element and a fourth switching element connected back-to-back in series. The second switching element is connected to the third switching element, and the midpoint of the series connection between the second switching element and the third switching element is connected to the midpoint of the series connection between the positive bus capacitor and the negative bus capacitor. The first switching element is connected to the first AC port and the inverter midpoint of the first three-level inverter bridge arm, respectively. The fourth switching element is connected to the second AC port and the inverter midpoint of the second three-level inverter bridge arm, respectively.

4. The three-level inverter circuit unit according to claim 3, characterized in that, The first switching element, the second switching element, the third switching element, and the fourth switching element all use MOSFETs or IGBTs of the same specifications.

5. The three-level inverter circuit unit according to claim 3 or 4, characterized in that, It also includes a relay connected in parallel between the first AC port and the second AC port.

6. A three-level HERIC circuit, characterized in that, include: The three-level inverter circuit unit as described in any one of claims 1 to 5; The first PFC inductor and the second PFC inductor are respectively connected to the power grid at one end and at one end of the first PFC inductor. The other end of the first PFC inductor is connected to the inverter midpoint of the first switching unit and the first three-level inverter bridge arm through the first AC port. The other end of the second PFC inductor is connected to the inverter midpoint of the second switching unit and the second three-level inverter bridge arm through the second AC port.

7. An SST power module unit, characterized in that, include: The three-level inverter circuit unit as described in any one of claims 1 to 5; Isolated resonant cavity; An output-side rectifier circuit, wherein the output terminal of the output-side rectifier circuit is used to connect the positive terminal of the DC power supply and the negative terminal of the DC power supply; The three-level DC-DC circuit has its input terminals connected to the first DC port, the second DC port, and the midpoint of the series connection between the positive bus capacitor and the negative bus capacitor, respectively. The output terminal of the three-level DC-DC circuit is connected to the output-side rectifier circuit through the isolated resonant cavity.

8. The SST power module unit according to claim 7, characterized in that, The three-level DC-DC circuit adopts an I-type three-level circuit, a T-type three-level circuit, or a four-switch three-level circuit.

9. A solid-state transformer, characterized in that, include: Multiple SST power module units as described in claim 7 or 8; The AC side of each SST power module unit is connected in series, and the DC side is connected in parallel.

Images