Bidirectional ac-dc converter, converter system and method of operating the same

Abstract

A bidirectional AC-DC converter includes a plurality of inductors coupled to a plurality of power sources, respectively; a rectification circuit including a plurality of rectification switches and coupled to the inductors; a conversion circuit including a plurality of conversion switches and coupled to the rectification circuit; and a first controller configured to provide a plurality of first control signals and a plurality of second control signals to control the rectification switches and the conversion switches, respectively. The plurality of power sources are configured to provide a plurality of phase voltage signals and a plurality of current signals to the rectification circuit, and the first controller and the second controller are configured to provide the first control signals and the second control signals based on the phase voltage signals, the current signals, and a reference phase parameter when the current signals are converted from a DC form to an AC form during a discharging mode. The present disclosure also relates to a converter system and a method of operating the same.

Description

Technical Field

[0001] This disclosure relates to a bidirectional AC-DC converter, a converter system, and a method for operating the same. Background Technology

[0002] A conversion circuit is used to convert alternating current (AC) voltage signals to direct current (DC) voltage signals. When the conversion circuit is used to charge a load, it uses a rectifier to convert the input AC signal into an output DC signal. The control cycle of the switches in the conversion circuit is based on the voltage level of the output voltage signal. When the conversion circuit operates to supply power to a load, the length of the control cycle depends on the type of power supply and load. Summary of the Invention

[0003] This disclosure includes a bidirectional AC-DC converter, comprising: a plurality of inductors, each coupled to a plurality of power supplies; a rectifier circuit, including a plurality of rectifier switches and coupled to the inductors; a switching circuit, including a plurality of switching switches and coupled to the rectifier circuit; and a first controller for providing a plurality of first control signals and a plurality of second control signals to control the rectifier switches and switching switches respectively; wherein the power supplies provide a plurality of phase voltage signals and a plurality of current signals to the rectifier circuit, and when the current signal is converted from DC to AC during a discharge mode, the first controller provides the first control signals and the second control signals based on the phase voltage signals, the current signals, and a reference phase signal.

[0004] This disclosure includes a method of operating a converter system, comprising: calculating the polarity of the converter system based on a plurality of current signals; calculating the control period and duty cycle of the converter system based on the current signals and reference phase parameters; and controlling a plurality of switches of the converter system based on each of the polarity, control period, and duty cycle, wherein the converter system performs the following operations during a charging mode: when the polarity is positive biased, turning on each of a first switch and a second switch of the plurality of switches, and turning off each of a third switch and a fourth switch of the plurality of switches, and turning off a second switch after the first switch and the second switch are turned on, and before the first switch is turned off.

[0005] This disclosure includes a converter system comprising: a plurality of power supplies, each coupled to a plurality of inductors, the power supplies providing a plurality of phase voltage signals and a plurality of current signals; a rectifier circuit coupled to the inductors; a conversion circuit including a plurality of changeover switches, a first capacitor and a second capacitor, each of the first capacitor and the second capacitor being coupled to the rectifier circuit; and a first controller for calculating a plurality of reference current signals, a plurality of region current signals and a plurality of region reference current signals based on the phase voltage signals, the current signals and reference phase parameters. Attached Figure Description

[0006] The embodiments of this disclosure can be best understood by reading the following detailed description in conjunction with the accompanying drawings. It should be noted that, according to industry standard practice, the various features are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various features may be arbitrarily increased or decreased.

[0007] Figure 1 This is a schematic diagram of a converter system shown according to some embodiments of the present disclosure.

[0008] Figure 2 This is a schematic diagram of a controller in a converter system according to some embodiments of the present disclosure.

[0009] Figure 3 This is a flowchart illustrating a method for operating a converter system according to some embodiments of the present disclosure.

[0010] Figure 4 This is a flowchart illustrating an operational method for determining the polarity of a converter system using a selector, according to some embodiments of the present disclosure.

[0011] Figure 5 As shown in some embodiments according to this disclosure, corresponding to Figure 4 The waveform diagram of the reference current signal and polarity of the converter system in the diagram.

[0012] Figure 6A This is a timing diagram of the control signals for multiple switches of a control converter system shown in some embodiments of the present disclosure.

[0013] Figure 6B This is a timing diagram of the control signals for multiple switches of a control converter system shown in some embodiments of the present disclosure.

[0014] Figure 7A This is a timing diagram of the control signals for multiple switches of a control converter system shown in some embodiments of the present disclosure.

[0015] Figure 7BThis is a timing diagram of the control signals for multiple switches of a control converter system shown in some embodiments of the present disclosure.

[0016] Figure 8 This is a table of logic values ​​for control signals of a rectifier circuit shown in some embodiments of the present disclosure.

[0017] Explanation of reference numerals in the attached figures:

[0018] 100: Converter System

[0019] 101-103: Power Supply

[0020] 110: Power supply circuit

[0021] 120: Rectifier circuit

[0022] 130: Conversion circuit

[0023] 131: Selector

[0024] 132: Phase-locked loop

[0025] 133: Reference Value Calculator

[0026] 134: Mapping Calculator

[0027] 135: Voltage and Current Controller

[0028] 136: Selector

[0029] 140: Controller

[0030] 150: Energy System

[0031] 300: Method

[0032] 400: Operating Instructions

[0033] 401-405: Operation

[0034] 800: Form

[0035] COND1~COND3: Conditional signals

[0036] C PY C YN C PN C r1 C r2 Co: Capacitor

[0037] DA, DB, DC: Voltage phase parameters

[0038] DL, DM, DS: Regional phase parameters

[0039] D_REF: Reference phase parameter

[0040] DABC: Voltage Phase Parameters

[0041] DLMS: Region Phase Parameter

[0042] DPN: Duty Cycle

[0043] FSW: Switching Frequency

[0044] DCP, DCN, DDP, DDN: Working Cycle

[0045] IABC, IA, IB, IC: Current signals

[0046] IABC_REF, IA_REF, IB_REF, IC_REF: Reference current signals

[0047] ILMS, IL, IM, IS: Region current signals

[0048] ILMS_REF, IL_REF, IM_REF, IS_REF: Reference region current signals

[0049] IL, Im: Current signals

[0050] I_S1, I_S4, I_S9, I_S12, IC2: current signal

[0051] IOUT: Output current signal

[0052] L f1 L f2 L f3 L r L m Inductor

[0053] N1~N11: Nodes

[0054] N: Node

[0055] NM: Positive rational number

[0056] OP1~OP6: Operation

[0057] P: Node

[0058] P1~P4: Period

[0059] POL: Polarity

[0060] R L resistor

[0061] S1~S12: Switches

[0062] SR1~SR12: Switches

[0063] TR: Transformer

[0064] Ts: Control cycle

[0065] TC_P0~TC_P6: Time points

[0066] TC_N0~TC_N6: Time

[0067] TD_P0~TD_P6: Time

[0068] TD_N0~TD_N6: Time

[0069] U0: Load voltage signal

[0070] Uref: Reference voltage level

[0071] VABC, VA, VB, VC: Phase voltage signals

[0072] VS1~VS12: Control signals

[0073] VSR1~VSR12: Control signals

[0074] VH, VL: Voltage levels

[0075] Y: Node Detailed Implementation

[0076] The following disclosure provides numerous different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components and configurations are described below to simplify this disclosure. Of course, these components and configurations are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature on or thereon a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which an additional feature may be formed between the first and second features such that the first and second features are not in direct contact. Additionally, reference numerals and / or letters may be repeated in various instances of this disclosure. This repetition is for simplicity and clarity and does not, in itself, determine the relationship between the various embodiments and / or configurations discussed.

[0077] Additionally, for ease of description, spatial relative terms such as "below," "under," "lower," "above," "upper," "top," "bottom," and similar terms may be used herein to describe the relationship between one element or feature illustrated in the figures and one or more other elements or features. Besides the orientation depicted in the figures, spatial relative terms are intended to cover different orientations of elements in use or operation. Devices may be oriented in other ways (rotated 90 degrees or otherwise), and the spatial relative descriptive terms used herein will be interpreted accordingly.

[0078] Figure 1 This is a schematic diagram of a converter system 100 according to some embodiments of the present disclosure. Figure 1 As shown, the converter system 100 includes a power supply circuit 110, a rectifier circuit 120, a conversion circuit 130, a controller 140, and an energy system 150. The power supply circuit 110 includes power supplies 101-103 and an inductor L. f1 L f2 and L f3 The rectifier circuit 120 includes multiple switches SR1 to SR12. The converter circuit 130 includes multiple switches S1 to S12, a transformer TR, and a resistor R. L Inductor L r Inductor L m Capacitor C PY C YN C PN C r1 C r2 And Co.

[0079] In some embodiments, the power supply circuit 110 is used to transmit the phase voltage signal VABC and the current signal IABC to the controller 140. In some embodiments, the phase voltage signal VABC includes multiple phase voltage signals VA, VB, and VC. The phase voltage signals VA, VB, and VC are generated by power supplies 101 to 103, respectively. The current signal IABC includes multiple current signals IA, IB, and IC. The controller 140 is used to receive a reference phase parameter D_REF from the energy system 150. The controller 140 is further used to control each of the switches SR1 to SR12 in the rectifier circuit 120 and each of the switches S1 to S12 in the converter circuit 130 according to each of the phase voltage signal VABC, the current signal IABC, and the reference phase parameter D_REF. In some embodiments, the converter circuit 130 transmits a load voltage signal U0 to the controller 140 to adjust the switching sequence and timing of the switches S1 to S12 to stabilize the output voltage to a reference voltage level Uref. In some embodiments, the load voltage signal U0 is the output voltage signal of the converter system 100.

[0080] like Figure 1 As shown, power supply 101 is coupled to inductor L. f1 One end of the inductor is connected to node N1 and used to provide the phase voltage signal VA to the rectifier circuit 120. f1 The other end is coupled to each of switches SR1 and SR2 at node N4. Power supply 102 is coupled to inductor L. f2 One end of the inductor is connected to node N2 and used to provide the phase voltage signal VB to the rectifier circuit 120. f2The other end is coupled to each of switches SR3 and SR4 at node N5. Power supply 103 is coupled to inductor L. f3 One end of the inductor is connected to node N3 and used to provide the phase voltage signal VC to the rectifier circuit 120. f3 The other end is coupled to each of switches SR5 and SR6 at node N6. In some embodiments, phase voltage signals VA, VB, and VC are transmitted to controller 140 at nodes N1, N2, and N3, respectively. In some embodiments, each of nodes N1, N2, and N3 may be referred to as the neutral point of the power supply circuit.

[0081] like Figure 1 As shown, in the rectifier circuit 120, the first terminal of switch SR1 is coupled to inductor L. f1 And each of the first terminals of switch SR2 is connected to node N4. The second terminal of switch SR1 is coupled to capacitor C. PY The first terminal of switch SR2 is connected to node P. The second terminal of switch SR2 is coupled to capacitor C. YN The first terminal is at node N. The first terminal of switch SR3 is coupled to inductor L. f2 And each of the first terminals of switch SR4 is connected to node N5. The second terminal of switch SR3 is coupled to capacitor C. PY The first terminal is connected to node P. The second terminal of switch SR4 is coupled to capacitor C. YN The first terminal is at node N. The first terminal of switch SR5 is coupled to inductor L. f3 And each of the first terminals of switch SR6 is connected to node N6. The second terminal of switch SR5 is coupled to capacitor C. PY The first terminal is connected to node P. The second terminal of switch SR6 is coupled to capacitor C. YN The first end is at node N.

[0082] In some embodiments, in the rectifier circuit 120, the first terminal of the switch SR8 is coupled to the inductor L. f1 At node N4, the second terminal of switch SR8 is coupled to the first terminal of switch SR7. The second terminal of switch SR7 is coupled to capacitor C. PY The second terminal and capacitor C YN Each of the second terminals is at node Y. The first terminal of switch SR10 is coupled to inductor L. f2 At node N5, the second terminal of switch SR10 is coupled to the first terminal of switch SR9. The second terminal of switch SR9 is coupled to capacitor C. PY The second terminal and capacitor C YN Each of the second terminals is at node Y. The first terminal of switch SR12 is coupled to inductor L. f3 At node N6, the second terminal of switch SR12 is coupled to the first terminal of switch SR11. The second terminal of switch SR11 is coupled to capacitor C. PYThe second terminal and capacitor C YN- The second end is at node Y.

[0083] like Figure 1 As shown, in the conversion circuit 130, the first terminal of switch S5 is coupled to the rectifier circuit 120 at node Y. The second terminal of switch S5 is coupled to the first terminal of switch S6, and the second terminal of switch S6 is coupled to capacitor C. r1 The first terminal of switch S7 is connected to node N7. The first terminal of switch S7 is coupled to rectifier circuit 120 at node Y. The second terminal of switch S7 is coupled to the first terminal of switch S8, and the second terminal of switch S8 is coupled to inductor L. m The first terminal of switch S1 is coupled to node N8. The first terminal of switch S1 is coupled to the first terminal of switch S3 at node P, and the second terminal of switch S1 is coupled to the first terminal of switch S2 at node N7. The second terminal of switch S3 is coupled to the first terminal of switch S4 at node N8. The second terminal of switch S4 is coupled to the second terminal of switch S2 at node N.

[0084] In some embodiments, in the conversion circuit 130, capacitor C r1 The second end is coupled to inductor L r One end of the inductor L. r The other end is coupled to the dotted terminal of transformer TR and inductor L. m The second terminal. Inductor L m The first terminal is further coupled to the non-spotted terminal of transformer TR. The spotted terminal of transformer TR is coupled to capacitor C. r2 One end of the capacitor C r2 The other end is coupled to each of the first terminals of switch S9 and switch S10 at node N10. The second terminal of switch S9 is coupled to each of the first terminals of switch S11 and capacitor Co. The second terminal of switch S11 is coupled to each of the first terminals of switch S12 and the non-pointed terminals of transformer TR at node N11. The second terminal of switch S12 is coupled to each of the second terminals of switch S10 and capacitor Co. The first terminal of capacitor Co is further coupled to resistor R. L The first end of the capacitor Co, and the second end of the capacitor Co, are further coupled to the resistor R. L The second end.

[0085] In some embodiments, the control terminals of switches SR1 to SR12 are used to receive multiple control signals VSR1 to VSR12 respectively from selector 131 in controller 140. Therefore, each of switches SR1 to SR12 is controlled by selector 131. The control terminals of switches S1 to S12 are used to receive multiple control signals VS1 to VS12 respectively from selector 136 in controller 140. Therefore, each of switches S1 to S12 is controlled by selector 136. Further details regarding the control of switches SR1 to SR12 and S1 to S12 are provided in [the relevant documentation / documentation]. Figures 6A to 8 This will be discussed in the corresponding section of the instruction manual.

[0086] In some embodiments, the transformer TR includes an AC side coil and a DC side coil. The ratio of the number of turns in the AC side coil to the number of turns in the DC side coil is 1:NM, where NM is a positive rational number. In some embodiments, the ratio of the number of turns in the transformer TR is an approximation estimated using natural numbers representing the number of turns. Inductor L m The magnetizing inductance of transformer TR is used to represent the inductance of inductor L. r It can represent the leakage inductance of a transformer TR or a separate inductance.

[0087] In some embodiments, resistor R L The resistance of the load is used to represent the load, and the load can be implemented through an output device. For example, the output device can be a battery cell of an electric vehicle. In some embodiments, the reference voltage level Uref is determined by the controller 140 based on various types of loads, such as the battery cell of an electric vehicle. In other words, the reference voltage level Uref corresponds to the voltage required by the load. When the voltage level of the load voltage signal U0 is different from the reference voltage level Uref, the controller 140 adjusts the load voltage signal U0 to the reference voltage level Uref.

[0088] In some embodiments, the energy system 150 provides a reference phase parameter D_REF to the controller 140 based on the needs of the transmission network. The reference phase parameter D_REF provided to the controller 140 is used to adjust the phase shift of the current signal IABC and the phase voltage signal VABC generated when the power supply circuit 110 consumes current. Controlling the phase allows the power supply circuit 110 to change the power consumption ratio of the converter system 100 during startup and restart by altering the phase shift between the current signal IABC and the phase voltage signal VABC. In other words, the reference phase parameter D_REF sets a reference point for the phase difference between the voltage and the consumed current of the transmission network, which in turn changes the power consumption during startup / restart.

[0089] In some embodiments, each of power supplies 101-103 may be implemented using an alternating current power supply. The current level of the alternating current signal changes alternately over time. In some embodiments, each of switches SR1-SR12 may comprise an insulated-gate bipolar transistor (IGBT) connected in parallel with a diode, or may be implemented using an IGBT co-packaged with a freewheeling diode. Each of switches S1-S12 may be implemented using a silicon carbide (SiC) metal-oxide-semiconductor field-effect transistor (MOSFET). The SiC MOSFET comprises a body diode. In some embodiments, the SiC MOSFET is turned off when the control terminal has a voltage level VL, and turned on when the control terminal has a voltage level VH. In some embodiments, the IGBT is turned off when the control terminal has a voltage level VL, and turned on when the control terminal has a voltage level VH. In some embodiments, the voltage level VH is higher than the voltage level VL.

[0090] In some embodiments, when the converter system 100 is operating, each of the phase voltage signals VABC from the power supply circuit 110 is provided to the rectifier circuit 120. The rectifier circuit 120 is used to convert the phase voltage signals VABC, which are in alternating current form, to direct current form. The rectifier circuit 120 is used to perform commutation (or phase switching) on ​​the phase voltage signals VABC generated by the power supply circuit 110 at nodes P, Y, and N to capacitor C. PY C YN And C PN Up. Next, capacitor C PY C YN and C PNEach of the components, along with the power supply circuit 110 which alternates across the capacitor, provides a DC voltage, which is further alternately converted by the transformer TR of the conversion circuit 130. The supplied DC voltage is rectified by switches S9-S12 to generate a load voltage signal U0. The load (output) voltage signal U0 generates an output current signal IOUT at the load, which is reflected back to the resonant circuit to generate current. The reflected current is shaped by the duty cycle modulation and generates a current signal IABC, the amplitude of which depends on the load size. Each of the output current signal IOUT and the load voltage signal U0 is transmitted to the capacitor Co and the resistor R. L In other words, each of the output current signal IOUT and the load voltage signal U0 is used to supply power to the load. Therefore, the converter system 100 can be referred to as a bidirectional AC-DC converter. In some embodiments, the power of the power supply is based on the load voltage signal U0 and the resistor R. L The resistance value is determined and follows Ohm's law in circuit theory. In some embodiments, the resonant circuit corresponds to the portion of the switching circuit 130 that includes switches S1 to S8.

[0091] In some embodiments, the rectified voltage signal is generated by changes between phase voltage signals VA, VB, and VC, and by changes between switches SR1 to SR12, thereby generating noise. This noise can be transmitted through capacitor C. PY C PN And C YN Filtering.

[0092] In some methods, the converter system can operate in both charging and discharging modes. To achieve this, diodes in the converter system are replaced with semiconductor switches, and a special modulation mode is employed. However, when the converter system operates under high voltage variations, it cannot provide boost in discharging mode due to the use of LC or LLC circuits. Although a discharging mode has been proposed in previous methods, the modulation strategy of the converter system still cannot effectively operate over a wider power factor adjustment range.

[0093] Compared to the above approach, in the embodiments of this disclosure, the controller 140 in the converter system 100 calculates the switching frequency (FSW) and duty cycle (DPN) based on each of the phase voltage signal VABC, the current signal IABC, and the reference phase parameter D_REF. Each of the switches S1 to S12 is controlled based on the switching frequency FSW and the duty cycle DPN. Therefore, the converter system 100 can operate in charging and discharging modes based on different switching frequencies, duty cycles, and modulation strategies, and effectively operate within a wider power factor adjustment range.

[0094] In some embodiments, in response to the current signal IABC converting from DC to AC, the discharge mode can be represented as a DC-to-AC mode. Similarly, in response to the current signal IABC converting from AC to DC, the charging mode can be represented as an AC-to-DC mode.

[0095] In some embodiments, the duty cycle DPN is the duration for which switches S1 to S12 are turned on or off. Specifically, the duty cycle DPN is the capacitance C in the alternating current transformer TR. PN voltage or capacitor C PY and C YN The voltage period of one of the switches. The duty cycle DPN can adjust the voltage level applied to the transformer TR. When the duty cycle DPN is higher, the voltage level of the output voltage signal generated by the transformer TR is higher. In some embodiments, the period during which each of the switches S1 to S12 completes its turn-on and turn-off can be represented as the control period Ts. The control period Ts is the reciprocal of the switching frequency FSW.

[0096] Figure 2 This is a schematic diagram of a controller 140 in a converter system 100 according to some embodiments of the present disclosure. Figure 2 As shown, the controller 140 includes a selector 131, a phase-locked loop 132, a reference value calculator 133, a mapping calculator 134, a voltage and current controller 135, and a selector 136.

[0097] Reference Figure 1 and Figure 2 Selector 131 is used to receive phase voltage signals VABC from power supplies 101-103, and controls each of switches SR1-SR12 according to the phase voltage signals VABC. More details regarding the control of switches SR1-SR12 are available in... Figure 8 Further discussion will take place in the corresponding paragraphs of the instruction manual.

[0098] like Figure 2 As shown, the phase-locked loop 132 is used for self-locking Figure 1The power supplies 101-103 in the circuit receive the phase voltage signal VABC and generate the voltage phase parameter DABC. The phase-locked loop 132 further transmits the voltage phase parameter DABC to each of the reference value calculator 133 and the mapping calculator 134.

[0099] In some embodiments, the mapping calculator 134 is used to generate a region phase parameter DLMS based on the voltage phase parameter DABC, and transmit the region phase parameter DLMS to the reference value calculator 133. The mapping calculator 134 is further used to... Figure 1 The power supplies 101-103 receive each of the phase voltage signal VABC and the current signal IABC and generate the area current signal ILMS. The mapping calculator 134 transmits the area current signal ILMS to the voltage and current controller 135.

[0100] In some embodiments, the reference value calculator 133 receives each of the region phase parameter DLMS and the reference phase parameter D_REF for reference value calculation. After performing the reference value calculation, the reference value calculator 133 generates each of the reference current signal IABC_REF and the reference region current signal ILMS_REF, and transmits the reference current signal IABC_REF and the reference region current signal ILMS_REF to the selector 136 and the voltage and current controller 135, respectively. In some embodiments, the voltage and current controller 135 generates each of the switching frequency FSW and the duty cycle DPN based on each of the region current signal ILMS and the reference region current signal ILMS_REF. Further details regarding the generation of the region phase parameter DLMS, the region current signal ILMS, and the reference region current signal ILMS_REF are provided below. Figure 3 This will be discussed further in the corresponding instruction manual paragraphs.

[0101] In some embodiments, selector 136 is used to generate control signals VS1 to VS12 based on the switching frequency FSW and duty cycle DPN. In addition, selector 136 is used to determine the polarity POL of the converter system 100 (not shown) based on the reference current signal IABC_REF. Figure 2 (Middle). Next, selector 136 further controls switches S1 to S12 respectively via control signals VS1 to VS12 according to the polarity POL. More details on determining the polarity POL are in... Figure 4 and Figure 5 This will be discussed further in the corresponding instruction manual paragraphs.

[0102] In some embodiments, the voltage phase parameter DABC includes voltage phase parameters DA, DB, and DC corresponding to phase voltage signals VA, VB, and VC, respectively. The reference current signal IABC_REF includes reference current signals IA_REF, IB_REF, and IC_REF corresponding to current signals IA, IB, and IC, respectively.

[0103] In some embodiments, the region phase parameter DLMS includes region phase parameters DL, DM, and DS. The region current signal ILMS includes region current signals IL, IM, and IS. The reference region signal ILMS_REF includes reference region current signals IL_REF, IM_REF, and IS_REF.

[0104] Figure 3 This is a flowchart illustrating a method 300 of operating a converter system 100 according to some embodiments of the present disclosure. Figure 3 As shown, method 300 includes operations OP1 to OP6.

[0105] Reference Figure 2 and Figure 3 Operation OP1 corresponds to phase-locked loop 132. Operation OP2 corresponds to mapping calculator 134. Operation OP3 corresponds to reference value calculator 133. Operation OP4 corresponds to voltage and current controller 135. Operations OP5 and OP6 correspond to selector 136.

[0106] In operation OP1, phase-locked loop 132 performs phase-locking operation on the phase voltage signal VABC to determine the voltage phase parameter DABC of the phase voltage signal VABC. Specifically, phase-locked loop 132 is used to generate the voltage phase parameter DABC corresponding to the phase of the phase voltage signal VABC. Phase-locked loop 132 further transmits the voltage phase parameter DABC to each of the reference value calculator 133 and the mapping calculator 134. After completing operation OP1, converter system 100 performs operation OP2.

[0107] In operation OP2, the mapping calculator 134 modifies the coordinate domains of the voltage phase parameter DABC and the current signal IABC based on the phase voltage signal VABC to generate the region phase parameter DLMS and the region current signal ILMS, respectively. The mapping calculator 134 transmits the region phase parameter DLMS and the region current signal ILMS to the reference value calculator 133 and the voltage and current controller 135, respectively.

[0108] Specifically, the mapping calculator 134 receives phase voltage signals VA, VB and VC, current signals IA, IB and IC, and each of the voltage phase parameters DA, DB and DC, and measures the absolute values ​​of the phase voltage signals VA, VB and VC, |VA|, |VB| and |VC| respectively.

[0109] Next, the mapping calculator 134 assigns the absolute values ​​|VA|, |VB|, and |VC| as the minimum, intermediate, and maximum values, respectively. For example, when the absolute values ​​|VA|, |VB|, and |VC| have voltage levels of 20 volts, 15 volts, and 10 volts, respectively, the absolute value |VA| is assigned as the maximum value, the absolute value |VB| as the intermediate value, and the absolute value |VC| as the minimum value. After the absolute values ​​|VA|, |VB|, and |VC| are assigned as the minimum, intermediate, and maximum values, respectively, the absolute values ​​|IA|, |IB|, and |IC| corresponding to the current signals IA, IB, and IC are respectively converted into the regional current signals IL, IM, and IS. The voltage phase parameters DA, DB, and DC are respectively converted into the regional phase parameters DL, DM, and DS. In other words, the current signal IABC is mapped to the regional current signal ILMS, and the voltage phase parameter DABC is mapped to the regional phase parameter DLMS.

[0110] For example, when the absolute value |VA| is specified as the maximum value, the absolute value |VB| is specified as the intermediate value, and the absolute value |VC| is specified as the minimum value, the current signal IA is converted to the regional current signal IL, the current signal IB is converted to the regional current signal IM, and the current signal IC is converted to the regional current signal IS. Similarly, the voltage phase parameter DA is converted to the regional phase parameter DL, the voltage phase parameter DB is converted to the regional phase parameter DM, and the voltage phase parameter DC is converted to the regional phase parameter DS.

[0111] After the region current signal ILMS and the region phase parameter DLMS are generated, the mapping calculator 134 transmits the region phase parameter DLMS and the region current signal ILMS to the reference value calculator 133 and the voltage and current controller 135, respectively. The converter system 100 performs operation OP3 after completing operation OP2.

[0112] In operation OP3, the reference value calculator 133 receives each of the reference phase parameter D_REF, the voltage phase parameter DABC, and the region phase parameter DLMS, and calculates the reference current signal IABC_REF and the reference region current signal ILMS_REF. After calculating each of the reference current signal IABC_REF and the reference region current signal ILMS_REF, the reference value calculator 133 transmits the reference current signal IABC_REF and the reference region current signal ILMS_REF to the selector 136 and the voltage and current controller 135, respectively.

[0113] Specifically, the reference value calculator 133 calculates the sine values ​​of the voltage phase parameters DA, DB, and DC relative to the reference phase parameter D_REF, to generate reference current signals IA_REF, IB_REF, and IC_REF, respectively. The calculations of the reference current signals IA_REF, IB_REF, and IC_REF are shown in the following equations.

[0114] IA_REF = sin(DA + D_REF)

[0115] IB_REF = sin(DB + D_REF)

[0116] IC_REF = sin(DC + D_REF)

[0117] In addition, the reference value calculator 133 calculates the absolute values ​​of the sinusoidal values ​​of the region phase parameters DL, DM, and DS with respect to the reference phase parameter D_REF, to generate the reference region current signals IL_REF, IM_REF, and IS_REF, respectively. The calculation of the reference region current signals IL_REF, IM_REF, and IS_REF is shown in the following equations.

[0118] IL_REF = abs(sin(DL+D_REF))

[0119] IM_REF = abs(sin(DM+D_REF))

[0120] IS_REF = abs(sin(DS+D_REF))

[0121] In some embodiments, each of the voltage phase parameters DA, DB, and DC, the region phase parameters DL, DM, and DS, and the reference phase parameter D_REF is expressed in degrees. For example, when the reference phase parameter D_REF has 30 degrees and the voltage phase parameter DA has 45 degrees, the reference current signal IA_REF has a sinusoidal value of sin75°. In some embodiments, the reference phase parameter D_REF can be implemented at 0 degrees, 15 degrees, 30 degrees, -15 degrees, -30 degrees, or any other degree.

[0122] Next, the reference value calculator 133 transmits the reference current signals IA_REF, IB_REF, and IC_REF, and the reference region current signals IL_REF, IM_REF, and IS_REF to the selector 136 and the voltage and current controller 135, respectively. After completing operation OP3, the converter system 100 performs operation OP4.

[0123] In operation OP4, the voltage and current controller 135 calculates the switching frequency FSW and duty cycle DPN based on each of the area current signal ILMS and the reference area current signal ILMS_REF.

[0124] Specifically, the voltage and current controller 135 adjusts the region current signals IL, IM, and IS according to the reference region current signals IL_REF, IM_REF, and IS_REF, respectively. Next, the voltage and current controller 135 generates a switching frequency FSW and a duty cycle DPN based on the periods of the region current signal ILMS and the reference region current signal ILMS_REF. After the switching frequency FSW and duty cycle DPN are generated, the voltage and current controller 135 transmits them to the selector 136. Specifically, the switching frequency FSW is used to control the voltage level of the load voltage signal U0, and the duty cycle DPN is used to control the current signal IABC of the converter system 100, which represents the power factor of the converter system 100 and has a phase shift relative to the phase voltage signal VABC. The converter system performs operation OP5 after completing operation OP4.

[0125] In operation OP5, selector 136 receives reference current signal IABC_REF and uses it to determine the polarity POL of reference current signal IABC_REF and select the operating mode of converter system 100.

[0126] Specifically, selector 136 is used to determine whether the polarity POL is positively or negatively biased. In addition, selector 136 is further used to select the operating mode of converter system 100. More details regarding determining the polarity POL and selecting the operating mode are available in... Figures 4 to 7B This will be further discussed in the corresponding paragraphs of the instruction manual. The converter system performs operation OP6 after completing operation OP5.

[0127] In operation OP6, selector 136 generates control signals VS1 to VS12 to control the switches based on the switching frequency FSW, duty cycle DPN, operating mode, and polarity POL determined by voltage and current controller 135. Specifically, selector 136 selects the positive or negative control sequence of switches S1 to S12 in both charging and discharging modes. In some embodiments, the control of positive and negative terminals corresponds to positive bias and negative bias of the polarity.

[0128] In some embodiments, when the converter system 100 is operating in charging mode, each of the control signals VS9 to VS12 has a voltage level VL, causing each of the switches S9 to S12 to remain off. The selector 136 controls the switches S1 to S8 according to each of the switching frequency FSW, duty cycle DPN, and polarity POL.

[0129] In some embodiments, when the converter system 100 is operating in discharge mode, each of the control signals VS1 to VS4 has a voltage level VL, causing each of the switches S1 to S4 to remain off. The selector 136 controls switches S5 to S12 based on the switching frequency FSW, duty cycle DPN, and polarity POL.

[0130] Figure 4 This is a flowchart illustrating an operation method 400 for determining the polarity (POL) of a converter system 100 via selector 136, according to some embodiments of this disclosure. Figure 4 As shown, operation method 400 includes operations 401 to 405.

[0131] In operation 401, selector 136 receives the reference current signal IABC_REF generated by reference value calculator 133. Specifically, selector 136 receives each of the reference current signals IA_REF, IB_REF, and IC_REF generated by reference value calculator 133. Selector 136 performs operation 402 after completing operation 401.

[0132] In operation 402, selector 136 compares each of the reference current signals IA_REF, IB_REF, and IC_REF, and specifies the reference current signals IA_REF, IB_REF, and IC_REF as the maximum current, minimum current, and intermediate current, respectively.

[0133] Specifically, selector 136 compares the current levels of each of the reference current signals IA_REF, IB_REF, and IC_REF. Then, selector 136 designates the reference current signal IA_REF, IB_REF, and IC_REF with the highest current level as the maximum current. Selector 136 designates the reference current signal IA_REF, IB_REF, and IC_REF with an intermediate current level as the intermediate current. Selector 136 designates the reference current signal IA_REF, IB_REF, and IC_REF with the minimum current level as the minimum current.

[0134] For example, when the reference current signals IA_REF, IB_REF, and IC_REF have current levels of 1.0 amps, 0.8 amps, and 0.5 amps, respectively, the reference current signal IA_REF is designated as the maximum current. Similarly, the reference current signal IB_REF is designated as the intermediate current, and the reference current signal IC_REF is designated as the minimum current. Selector 136 performs operation 403 after completing operation 402.

[0135] In operation 403, selector 136 determines whether the current level of the intermediate value current is positive.

[0136] Specifically, when the reference current signal IB_REF is specified as an intermediate value current, selector 136 determines whether the current level of the reference current signal IB_REF has a positive value. When the current level of the intermediate value current is positive, selector 136 performs operation 404 after completing operation 403. When the current level of the intermediate value current is negative, selector 136 performs operation 405 after completing operation 403.

[0137] For example, when the reference current signal IB_REF has a current level of 0.8 amps, selector 136 performs operation 404 after completing operation 403. When the reference current signal IB_REF has a current level of -0.8 amps, selector 136 performs operation 405 after completing operation 403.

[0138] In operation 404, the selector determines that the converter system 100 is positively biased when the current level of the intermediate current is positive. For example, the converter system 100 is positively biased when the current level of the intermediate current is 0.8 amperes.

[0139] In operation 405, when the current level of the intermediate current is negative, the selector determines that the converter system 100 is negatively biased. For example, when the current level of the intermediate current is -0.8 amperes, the converter system 100 is negatively biased.

[0140] In some embodiments, the current level of each of the reference current signals IA_REF, IB_REF, and IC_REF changes over time. Therefore, when operation method 400 is completed, selector 136 repeats operations 401 to 403.

[0141] Figure 5 As shown in some embodiments according to this disclosure, corresponding to Figure 4 The waveforms of the reference current signals IA_REF, IB_REF, and IC_REF of the converter system 100, as well as the polarity POL, are shown. Figure 5 As shown, Figure 5 The reference current signals IA_REF, IB_REF, and IC_REF, as well as the polarity POL, are shown during the period P1 to P4.

[0142] During period P1, the reference current signal IC_REF has the highest current level. The reference current signal IA_REF has a middle current level. The reference current signal IB_REF has the lowest current level. For example, as Figure 5As shown, the reference current signal IC_REF has a current level in the range of approximately 0.6 amps to 0.8 amps. The reference current signal IB_REF has a current level below -0.8 amps. The reference current signal IA_REF has a current level in the range of approximately 0 amps to 0.4 amps.

[0143] At this time, the reference current signal IA_REF is an intermediate value current. The current level of the reference current signal IA_REF is positive, causing the polarity POL to have the logic value "TRUE". In response to the polarity POL having the logic value "TRUE", selector 136 determines that the converter system 100 is positively biased.

[0144] During period P2, the reference current signal IA_REF has the highest current level. The reference current signal IC_REF has a middle current level. The reference current signal IB_REF has the lowest current level. For example, as Figure 5 The reference current signal IA_REF has a current level ranging from approximately 0.4 amps to 0.8 amps. The reference current signal IC_REF has a current level ranging from approximately 0 amps to 0.4 amps. The reference current signal IB_REF has a current level below 0.8 amps.

[0145] At this time, the reference current signal IC_REF is an intermediate value current. The current level of the reference current signal IC_REF is positive, causing the polarity POL to have the logic value "TRUE". In response to the polarity POL having the logic value "TRUE", selector 136 determines that the converter system 100 is positively biased.

[0146] During period P3, the reference current signal IA_REF has the highest current level. The reference current signal IC_REF has a middle current level. The reference current signal IB_REF has the lowest current level. For example, as Figure 5 As shown, the reference current signal IA_REF has a current level higher than 0.8 amps. The reference current signal IC_REF has a current level in the range of approximately -0.4 amps to 0 amps. The reference current signal IB_REF has a current level in the range of approximately -0.8 amps to -0.4 amps.

[0147] At this time, the reference current signal IC_REF is an intermediate value current. The current level of the reference current signal IC_REF is negative, causing the polarity POL to have the logic value "FALSE". In response to the polarity POL having the logic value "FALSE", selector 136 determines that the converter system 100 has a negative bias.

[0148] During period P4, the reference current signal IA_REF has the highest current level. The reference current signal IB_REF has a middle current level. The reference current signal IC_REF has the lowest current level. For example, as Figure 5 As shown, the reference current signal IA_REF has a current level higher than 0.8 amps. The reference current signal IB_REF has a current level in the range of approximately -0.4 amps to 0 amps. The reference current signal IC_REF has a current level in the range of approximately -0.8 amps to -0.4 amps.

[0149] At this time, the reference current signal IB_REF is an intermediate value current. The current level of the reference current signal IB_REF is negative, causing the polarity POL to have the logic value "FALSE". In response to the polarity POL having the logic value "FALSE", selector 136 determines that the converter system 100 has a negative bias.

[0150] In some embodiments, the reference current signals IA_REF, IB_REF, and IC_REF exhibit periodic variations. Therefore, the polarity POL of the converter system 100 after period P4 is similar to that during the period between periods P1 and P4. For simplicity, the polarity POL variation after period P4 will not be described again.

[0151] Figure 6A The timing diagrams of the control signals VS1 to VS8 of the switches S1 to S8 of the control converter system 100 are shown in some embodiments according to the present disclosure. Figure 6A The changes in control signals VS1 to VS8 are shown between time TC_P0 and time TC_P6. In some embodiments, Figure 6A The control timing of switches S1 to S8 corresponds to the converter system 100 operating in charging mode and the polarity POL being positively biased.

[0152] Reference Figure 6A as well as Figure 1 When the converter system 100 operates in charging mode, capacitor C PY C YN And C PN Used to provide voltage filtering to filter the alternating transmission network voltages, such as the rectified voltage generated by power supply circuit 110.

[0153] During the period between TC_P0 and TC_P1, each of the control signals VS1 to VS8 has a voltage level VL, causing each of the switches S1 to S8 to be turned off. When capacitor C PY C YN And C PN When one of them performs an interactive conversion, inductor Lm The magnetic current signal Im from the inductor L r The current flows through inductor L m In this case, inductor L m The negative current signal Im forces the body diodes of switches S1 and S4 to conduct. The parasitic capacitances of switches S1 and S4 are discharged, thus enabling zero-voltage soft-switching in the next time interval.

[0154] At time TC_P1, each of control signals VS1 and VS4 changes from voltage level VL to voltage level VH, causing each of switches S1 and S4 to conduct. In response to the conduction of switches S1 and S4, the current in each of the current signals IL and Im begins to rise, following a resonant trajectory. On the other side of the transformer, when transformer TR transmits energy, each of the current signals I_S9 and I_S12 conducts through the body diodes of switches S9 and S12.

[0155] During the period between TC_P1 and TC_P2, each of control signals VS1 and VS4 has a voltage level VH, causing each of switches S1 and S4 to remain on. Each of control signals VS2, VS3, and VS5 through VS8 has a voltage level VL, causing each of switches S2, S3, and S5 through S8 to remain off. In response to the on of each of switches S1 and S4, each of the current signals IL, Im, I_S9, and I_S12 continuously increases. Capacitor C PN The voltage alternates between nodes N7 and N8.

[0156] At time TC_P2, control signal VS8 changes from voltage level VL to voltage level VH, causing switch S8 to turn on. This turn-on is a pre-turn-on of switch S8 at the middle leg. Since switch S4 has lower impedance, no current will flow through switch S8. Control signals VS2, VS3, and each of VS5-VS7 has a voltage level VL, causing each of switches S2, S3, and S5-S7 to remain off. Control signals VS1 and VS4 each have a voltage level VH, causing each of switches S1 and S4 to remain on. In some embodiments, the middle leg is used to represent the middle section of the converter system 100, located at capacitor C. PY C YN C PN And between switches S1 to S4. The intermediate pins of the converter system 100 include switches S5 to S8.

[0157] During the period between TC_P2 and TC_P3, each of the control signals VS1, VS4, and VS8 has a voltage level VH, causing each of the switches S1, S4, and S8 to remain on. Each of the control signals VS2, VS3, and VS5 through VS7 has a voltage level VL, causing each of the switches S2, S3, and S5 through S7 to remain off. In response to the on of each of the switches S1 and S4, the current level of the current signal Im continuously increases. When capacitor C... PN The voltage continues to alternate between nodes N7 and N8, and each of switches S1 and S4 remains on in response. The current levels of each of the current signals IL, I_S1, and I_S4 still follow the resonant trajectory, which at this time either continues to increase or has begun to decrease.

[0158] At time TC_P3, control signal VS4 changes from voltage level VH to voltage level VL, causing switch S4 to turn off. Control signals VS1 and VS8 each have a voltage level VH, causing switches S1 and S8 to remain on. At this time, the intermediate pin is switched alternately by the body diodes of switches S8 and S7, and capacitor C... PY The interaction and transformation occurs between nodes N7 and N8.

[0159] During the period between TC_P3 and TC_P4, each of control signals VS1 and VS8 has a voltage level VH, causing each of switches S1 and S8 to remain on. Each of control signals VS2 to VS7 has a voltage level VL, causing switches S2 to S7 to remain off. In response to the on of each of switches S1 and S8, the voltage level applied to the resonant circuit is reduced to the level of capacitor C. PY The voltage level. If the resonant circuit operates at the same or higher resonant frequency as switches S1 to S8, the current levels of current signals Im and IL will be the same, and the power transmitted to transformer TR will be terminated. The current signals I_S9 and I_S12 through the body diode will be reduced and maintained at zero, respectively. The body diode of switch S7 is turned on, so that the soft switching transition to zero potential is achieved at the next moment.

[0160] At time TC_P4, control signal VS7 changes from voltage level VL to voltage level VH, causing switch S7 to turn on. Control signals VS1 and VS8 each have a voltage level VH, causing switches S1 and S8 to remain on. Control signals VS2 through VS6 each have a voltage level VL, causing switches S2 through S6 to remain off.

[0161] During the period between TC_P4 and TC_P5, each of the control signals VS1, VS7, and VS8 has a voltage level VH, causing each of the switches S1, S7, and S8 to remain on. Each of the control signals VS2 to VS6 has a voltage level VL, causing each of the switches S2 to S6 to remain off. In response to the on of switch S7, conduction losses are reduced. The voltage switched to the resonant circuit is maintained at capacitor C. PY The voltage.

[0162] At time TC_P5, each of the control signals VS1, VS7, and VS8 changes from voltage level VH to voltage level VL, causing each of the switches S1, S7, and S8 to turn off. In other words, each of the switches S1 to S8 is turned off at time TC_P5.

[0163] In some embodiments, the control of switches S1 to S8 during the period between TC_P5 and TC_P6 is similar to that during the period between TC_P0 and TC_P5. The difference between the period between TC_P5 and TC_P6 and the period between TC_P0 and TC_P5 is that control signals VS1, VS4, VS7, and VS8 are replaced by control signals VS3, VS2, VS5, and VS6, respectively. Therefore, for the sake of brevity, the control of switches S1 to S8 after TC_P6 will not be described again.

[0164] In some embodiments, the period between times TC_P0 and TC_P5 is half a control cycle of switches S1 to S8. The period between TC_P0 and TC_P6 is one control cycle Ts for switches S1 to S8. Therefore, when the converter system 100 is running, the control of switches S1 to S8 will repeat for multiple control cycles Ts.

[0165] In some embodiments, the control of switches S1 to S8 during the duty cycle DCP between times TC_P0 and TC_P4 is determined by multiplying half a control cycle by the duty cycle DPN. In other words, the duty cycle DCP is equal to half a control cycle multiplied by the duty cycle DPN.

[0166] In some embodiments, the control period Ts corresponds to Figure 3 The switching frequency FSW is used in this context. Specifically, the control period Ts is the reciprocal of the switching frequency FSW.

[0167] Figure 6B This is a timing diagram of the control signals VS1 to VS8 controlling the switches S1 to S8 of the converter system 100 according to some embodiments of the present disclosure. Figure 6BThe changes in control signals VS1 to VS8 from time TC_N0 to time TC_N6 are shown. In some embodiments, Figure 6B This corresponds to the control of switches S1 to S8 when the polarity POL is negatively biased and the converter system 100 is operating in charging mode. In some embodiments, the control of switches S1 to S8 on the negative bias is similar to... Figure 6A The control of switches S1 to S8 under positive bias. Therefore, the following discussion only addresses this. Figure 6A and Figure 6B Differences.

[0168] When the polarity POL is negatively biased and the converter system 100 operates in charging mode, its operating principle is similar to that when the polarity POL is positively biased. The main difference between positive and negative bias is that when the polarity POL is negatively biased, each of switches S1 and S3 is controlled by the duty cycle DPN; conversely, when the polarity POL is positively biased, each of switches S2 and S4 is controlled by the duty cycle DPN. Another difference is that in negative bias, the conduction time of each of switches S2 and S4 is half a control cycle; in positive bias, each of switches S1 and S3 conducts for half a control cycle. In addition, in negative bias, pre-conduction is implemented by switches S5 and S7; in positive bias, pre-conduction is performed by switches S6 and S8.

[0169] In some embodiments, the period between times TC_N0 and TC_N5 is half a control cycle of switches S1 to S8. The period between TC_N0 and TC_N6 also represents one control cycle Ts for switches S1 to S8. Therefore, when the converter system 100 is running, the control of switches S1 to S8 will repeat for multiple control cycles Ts.

[0170] In some embodiments, the control of the duty cycle DCN of switches S1 to S8 between times TC_N0 and TC_N4 is determined by half a control cycle multiplied by the duty cycle DPN. In other words, the duty cycle DCN is equal to half a control cycle multiplied by the duty cycle DPN. In some embodiments, the duty cycle DCN is different from the duty cycle DCP.

[0171] Figure 7A This is a timing diagram of the control signals VS5 to VS12 controlling the switches S5 to S12 of the converter system 100 according to some embodiments of the present disclosure. Figure 7A The changes in control signals VS5 to VS12 between time TD_P0 and time TD_P5 are shown. In some embodiments, Figure 7A When the polarity POL is positively biased and the converter system 100 is in discharge mode, the switches S5 to S12 are controlled.

[0172] Reference Figure 7A and Figure 1 Similar to the charging mode, capacitor C PY C YN And C PN Each of these switches provides voltage filtering to filter the alternating transmission network voltages, such as the rectified voltage generated by power supply circuit 110. In contrast to the charging mode, in the discharging mode, the current flow is redirected from the battery to the grid. In other words, the current flows through conversion circuit 130 towards power supply circuit 110. The voltage of the battery and the output capacitor Co is applied to the CLLC filter on the DC side by the alternating switching of switches S9-S12. The energy flow of the CLLC filter in discharging mode is opposite to that in charging mode. In discharging mode, the current signal generated by the battery is converted by transformer TR and regulated by conversion circuit 130. The switching frequency FSW of switches S9-S12 is used to regulate the voltage on the DC side, and the duty cycle DPN of bidirectional switches S5-S8 is used to form the waveform of the current signal IABC and the phase shift of the phase voltage signal VABC.

[0173] During the period between TD_P0 and TD_P1, each of the control signals VS5 to VS12 has a voltage level VL, causing each of the switches S5 to S12 to turn off. The magnetic current signal Im flows in the same direction as in the previous period, and the alternating output of the capacitor causes the voltage between nodes N10 and N11 to be negative. In this case, the magnetic current signal Im has a negative value, forcing the body diodes of switches S9 and S12 to conduct. The conduction of the body diodes of switches S9 and S12 discharges the parasitic capacitances of switches S9 and S12, thus achieving zero-voltage soft-switching in the next time interval.

[0174] At time TD_P1, each of control signals VS9 and VS12 changes from voltage level VL to voltage level VH, causing each of switches S9 and S12 to turn on. Each of control signals VS5-VS8 and VS10-VS11 has voltage level VL, causing each of switches S5-S8 and S10-S11 to remain off.

[0175] At this time, in response to the conduction of each of switches S9 and S12, the positive voltage of the capacitor on the DC side is applied to the CLLC filter between nodes N10 and N11. The current level of the current signal IC2 begins to increase and flows into the transformer TR. The voltage on the AC side of the transformer and the magnetic current signal Im also begin to increase. The body diodes of switches S1 and S3 are not yet turned on before the magnetic current begins to remagnetize, and the resonant current signal IC2 on the DC side is higher than or equal to the magnetic current signal Im. In other words, when the current signal IC2 ≥ the magnetic current signal Im and the current signal IC2 < the magnetic current signal Im, the body diodes of switches S4 and S2 remain turned on.

[0176] During the period between TD_P1 and TD_P2, each of control signals VS9 and VS12 has a voltage level VH, causing each of switches S9 and S12 to remain on. Each of control signals VS5-VS8 and VS10-VS11 has a voltage level VL, causing each of switches S5-S8 and S10-S11 to remain off. The positive voltage of the DC-side capacitor Co is applied to the CLLC filter between nodes N10 and N11. The current levels of each of current signals IC2 and IL continuously increase. Initially, when the magnetic current Im is higher than the current IC2, the body diodes of switches S2 and S4 remain on. When the resonant current IC2 on the DC side increases and exceeds the magnetic current Im, the body diodes of switches S1 and S3 begin to conduct.

[0177] At time TD_P2, the control signal VS8 changes from voltage level VL to voltage level VH, causing switch S8 to turn on. Switch S8 is pre-turned on and undergoes a hard switching transition. The body diodes of switches S8 and S7 form the path for the resonant current IL.

[0178] During the period between TD_P2 and TD_P3, each of control signals VS8-VS9 and VS12 has a voltage level VH, causing each of switches S8-S9 and S12 to remain on. Each of control signals VS5-VS7 and VS10-VS11 has a voltage level VL, causing each of switches S5-S7 and S10-S11 to remain off. The current levels of each of current signals IC2 and Im continuously increase. The resonant current signal IL is redirected to the intermediate pin through the body diodes of switches S8 and S7. This redirected modulation allows current to flow through the inductor L of the converter system 100. f1 ~L f3 Generate. The voltage difference between nodes N10 and N11 is maintained equal to the voltage difference across capacitor Co.

[0179] At time TD_P3, the control signal VS7 changes from voltage level VL to voltage level VH, causing switch S7 to turn on. Since the body diode of switch S7 was turned on before time TD_P3, switch S7 undergoes a soft-switching transition.

[0180] During the period between TD_P3 and TD_P4, each of control signals VS7-VS9 and VS12 has a voltage level VH, causing each of switches S7-S9 and S12 to remain on. Each of control signals VS5-VS6 and VS10-VS11 has a voltage level VL, causing each of switches S5-S6 and S10-S11 to remain off. The redirected resonant current then flows through switches S7 and S8, reducing conduction losses.

[0181] At time TD_P4, each of the control signals VS7-VS9 and VS12 changes from voltage level VH to voltage level VL, causing each of the switches S7-S9 and S12 to turn off. The operation in the next period is similar to the operation described previously, with all switches S5-S12 turning off.

[0182] In some embodiments, the control of switches S5 to S12 during times TD_P4 to TD_P5 is similar to the control during times TD_P0 to TD_P4. Because a negative voltage is applied between nodes N10 and N11, the current continuously decreases.

[0183] In some embodiments, the period between times TD_P0 and TD_P4 is half a control cycle of switches S5 to S12. Similarly, the period between times TD_P0 and TD_P5 represents one control cycle Ts. Therefore, when the converter system 100 is running, the control of switches S5 to S12 will repeat for multiple control cycles Ts.

[0184] In some embodiments, the control of the duty cycle DDP of switches S5 to S12 between times TD_P0 and TD_P4 can be determined based on half a control cycle multiplied by the duty cycle DPN. In other words, the duty cycle DDP is equal to half a control cycle multiplied by the duty cycle DPN. In some embodiments, the duty cycle DDP is different from the duty cycle DCP and DCN.

[0185] Figure 7B This is a timing diagram of the control signals VS5 to VS12 controlling the switches S5 to S12 of the converter system 100 according to some embodiments of the present disclosure. Figure 7B The changes in control signals VS5 to VS12 from time TD_N0 to time TD_N5 are shown. In some embodiments, Figure 7BThis corresponds to the control of switches S5-S12 when the polarity POL is negatively biased and the converter system 100 operates in discharge mode. The main difference between positive and negative bias POL lies in the sequence of switch pre-conduction. In the case of a negatively biased POL, switches S8 and S5 are hard-switched on, and switches S6 and S7 are subsequently soft-switched on. As mentioned above, for a positively biased POL, switches S5 and S7 are pre-conducted, and switches S8 and S6 are subsequently soft-switched on. Other switches S9-S12 are as follows... Figure 7A The operation is as described. The operation of voltage and current is similar in both cases.

[0186] Figure 8 Table 800 shows the logic values ​​of control signals VSR1 to VSR12 of the rectifier circuit 120 according to some embodiments of this disclosure. Figure 8 As shown, Table 800 displays the logic values ​​of control signals VSR1 to VSR12 corresponding to each of the condition signals COND1 to COND3.

[0187] Reference Figure 8 as well as Figure 2 Selector 131 receives each of the phase voltage signals VA, VB, and VC and generates condition signals COND1 to COND3. Next, selector 131 performs logical operations on each of the condition signals COND1 to COND3 to determine the logic values ​​of control signals VSR1 to VSR12. When the logic values ​​of each of the control signals VSR1 to VSR12 are determined, selector 131 further controls each of the switches SR1 to SR12 according to Table 800.

[0188] Specifically, selector 131 generates condition signals COND1 to COND3 based on the voltage levels of phase voltage signals VA, VB, and VC. When the voltage level of phase voltage signal VA is higher than the voltage level of phase voltage signal VC, condition signal COND1 has a logic value of "1". When the voltage level of phase voltage signal VA is lower than the voltage level of phase voltage signal VC, condition signal COND1 has a logic value of "0". When the voltage level of phase voltage signal VA is higher than the voltage level of phase voltage signal VB, condition signal COND2 has a logic value of "1". When the voltage level of phase voltage signal VA is lower than the voltage level of phase voltage signal VB, condition signal COND2 has a logic value of "0". When the voltage level of phase voltage signal VB is higher than the voltage level of phase voltage signal VC, condition signal COND3 has a logic value of "1". When the voltage level of phase voltage signal VB is lower than the voltage level of phase voltage signal VC, condition signal COND3 has a logic value of "0".

[0189] In some embodiments, after the logic value of each of the condition signals COND1 to COND3 is determined, the selector 131 controls each of the switches according to the logic operation of the condition signals COND1 to COND3.

[0190] Specifically, the control of switch SR1 is determined by performing an AND operation on condition signals COND1 and COND2, i.e., COND1 AND COND2. The control of switch SR2 is determined by performing a NOT and AND operation on condition signals COND1 and COND2, i.e., NOT(COND1) AND NOT(COND2). The control of switch SR3 is determined by performing a NOT operation on condition signal COND2 and an AND operation on condition signals COND3 and COND2, i.e., COND3 AND NOT(COND2). The control of switch SR4 is determined by performing a NOT operation on condition signal COND3 and an AND operation on condition signals COND3 and COND2, i.e., NOT(COND3) AND COND2. The control of switch SR5 is determined by performing a NOT and AND operation on condition signals COND1 and COND3, i.e., NOT(COND1) AND NOT(COND3). The control of switch SR6 is determined by performing an AND operation on condition signals COND1 and COND3, i.e., COND1 AND COND3. The control of each of switches SR7 and SR8 is determined by XORing the condition signals COND1 and COND2, i.e., COND1 XOR COND2. The control of each of switches SR9 and SR10 is determined by XNORing the condition signals COND3 and COND2, i.e., COND3 XNOR COND2. The control of each of switches SR11 and SR12 is determined by XORing the condition signals COND1 and COND3, i.e., COND1 XOR COND3.

[0191] In some embodiments, when the logic operation of condition signals COND1 to COND3 is "TRUE", the control signals VSR1 to VSR12 corresponding to switches SR1 to SR12 have a logic value of "1". When the logic operation of condition signals COND1 to COND3 is "FALSE", the control signals VSR1 to VSR12 corresponding to switches SR1 to SR12 have a logic value of "0".

[0192] In some embodiments, when the control signals VSR1 to VSR12 have a logic value of "1", the control signals VSR1 to VSR12 have a voltage level VH. Correspondingly, when the control signals VSR1 to VSR12 have a logic value of "0", the control signals VSR1 to VSR12 have a voltage level VL.

[0193] like Figure 8 As shown, when each of the condition signals COND1 to COND3 has a logic value of "1", each of the control signals VSR1, VSR6, VSR9, and VSR10 has a logic value of "1", causing each of the switches SR1, SR6, SR9, and SR10 to be turned on. When each of the condition signals COND1 to COND3 has a logic value of "1", each of the control signals VSR2 to VSR5, VSR7 to VSR8, and VSR11 to VSR12 has a logic value of "0", causing each of the switches SR2 to SR5, SR7 to SR8, and SR11 to SR12 to be turned off.

[0194] In some embodiments, when each of condition signals COND1 and COND3 has a logic value of "1" and condition signal COND2 has a logic value of "0", control signals VSR3 and VSR6 to VSR8 each have a logic value of "1", causing switches SR3 and SR6 to SR8 to be turned on. When each of condition signals COND1 and COND3 has a logic value of "1" and condition signal COND2 has a logic value of "0", control signals VSR1 to VSR2, VSR4 to VSR5, and VSR9 to VSR12 each have a logic value of "0", causing switches SR1 to SR2, SR4 to SR5, and SR9 to SR12 to be turned off.

[0195] In some embodiments, when each of condition signals COND1 and COND2 has a logic value of "0" and condition signal COND3 has a logic value of "1", each of control signals VSR2-VSR3 and VSR11-VSR12 has a logic value of "1", causing each of switches SR2-SR3 and SR11-SR12 to be turned on. When each of condition signals COND1 and COND2 has a logic value of "0" and condition signal COND3 has a logic value of "1", each of control signals VSR1 and VSR4-VSR10 has a logic value of "0", causing each of switches SR1 and SR4-SR10 to be turned off.

[0196] In some embodiments, when each of the condition signals COND1 to COND3 has a logic value of "0", each of the control signals VSR2, VSR5, VSR9, and VSR10 has a logic value of "1", causing each of the switches SR2, SR5, SR9, and SR10 to be turned on. When each of the condition signals COND1 to COND3 has a logic value of "0", each of the control signals VSR1, VSR3 to VSR4, VSR6 to VSR8, and VSR11 to VSR12 has a logic value of "0", causing each of the switches SR1, SR3 to SR4, SR6 to SR8, and SR11 to SR12 to be turned off.

[0197] In some embodiments, when each of condition signals COND1 and COND3 has a logic value of "0" and condition signal COND2 has a logic value of "1", each of control signals VSR4-VSR5 and VSR7-VSR8 has a logic value of "1", causing each of switches SR4-SR5 and SR7-SR8 to be turned on. When each of condition signals COND1 and COND3 has a logic value of "0" and condition signal COND2 has a logic value of "1", each of control signals VSR1-VSR3, VSR6, and VSR9-VSR12 has a logic value of "0", causing each of switches SR1-SR3, SR6, and SR9-SR12 to be turned off.

[0198] In some embodiments, when each of condition signals COND1 and COND2 has a logic value of "1" and condition signal COND3 has a logic value of "0", each of control signals VSR1, VSR4, and VSR11 to VSR12 has a logic value of "1", causing each of switches SR1, SR4, and SR11 to SR12 to be turned on. When each of condition signals COND1 and COND2 has a logic value of "1" and condition signal COND3 has a logic value of "0", each of control signals VSR2 to VSR3 and VSR5 to VSR10 has a logic value of "0", causing each of switches SR2 to SR3 and SR5 to SR10 to be turned off.

[0199] In some embodiments, each of switches SR1 to SR12 is transmitted via... Figure 2 The selector 131 in the middle is controlled, and each of the switches S1 to S12 is controlled by... Figure 2 The selector 136 controls the switch. In other words, the control of each of the switches SR1 to SR12 is independent of the control of each of the switches S1 to S12.

[0200] The foregoing outlines the features of several embodiments, enabling those skilled in the art to better understand the implementation of this disclosure. Those skilled in the art will understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures for carrying out the same purpose and / or achieving the advantages of the embodiments described herein. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of this disclosure.

Claims

1. A bidirectional AC-DC converter, comprising: Multiple inductors are coupled to multiple power sources; A rectifier circuit comprising a plurality of rectifier switches and coupled to the inductors; A switching circuit comprising a plurality of switching switches and coupled to the rectifier circuit; and A first controller is configured to provide a plurality of first control signals and a plurality of second control signals to control the rectifier switches and the changeover switches respectively; These power supplies are used to provide multiple phase voltage signals and multiple current signals to the rectifier circuit, and When the current signals are switched from DC to AC during a discharge mode, the first controller provides the first control signals and the second control signals based on the phase voltage signals, the current signals and a reference phase signal.

2. The bidirectional AC-DC converter as claimed in claim 1, wherein the conversion circuit further comprises: A transformer, comprising an AC side and a DC side; A first capacitor is coupled to the AC side and a first portion of the changeover switches; A second capacitor is coupled to the DC side and a second part of the switching switches; as well as An inductor is coupled to the first capacitor and the transformer.

3. The bidirectional AC-DC converter as claimed in claim 1, wherein the first controller is further configured to: The polarity of the conversion circuit is determined based on these current signals; and A control cycle and a duty cycle are determined based on each of the current signals and a reference phase parameter to generate the second control signals.

4. The bidirectional AC-DC converter of claim 3, wherein during the discharge mode, each of a first switch, a second switch, a third switch, and a fourth switch of the switching switches is turned off.

5. The bidirectional AC-DC converter of claim 1, wherein when the current signals are converted from AC to DC during a charging mode, the first controller is further configured to control the rectifier switches according to each of a first condition signal, a second condition signal, and a third condition signal. When a first phase voltage signal of the given phase voltage signals is higher than a second phase voltage signal of the given phase voltage signals, the first condition signal has a first logic value. When the first phase voltage signal is lower than the second phase voltage signal, the first condition signal has a second logic value. When the first phase voltage signal is higher than a third phase voltage signal of the phase voltage signals, the second condition signal has the first logic value. When the first phase voltage signal is lower than the third phase voltage signal, the second condition signal has the second logic value. When the third phase voltage signal is higher than the second phase voltage signal, the third condition signal has the first logic value, and When the third phase voltage signal is lower than the second phase voltage signal, the third condition signal has the second logic value.

6. The bidirectional AC-DC converter of claim 5, wherein during the charging mode, each of the fifth switch, the sixth switch, the seventh switch, and the eighth switch of the switching switches is turned off.

7. The bidirectional AC-DC converter as described in claim 5, wherein... When each of the first condition signal, the second condition signal, and the third condition signal has the first logic value, each of the first switch, the second switch, the third switch, and the fourth switch of the rectifier switches is turned on. When each of the first condition signal, the second condition signal, and the third condition signal has the second logic value, the third switch, the fourth switch, the fifth switch, and the sixth switch of the rectifier switches are turned on. When each of the first condition signal and the third condition signal has the first logic value, and the second condition signal has the second logic value, each of the second switch, the seventh switch, the eighth switch, and the ninth switch of the rectifier switches is turned on. When each of the first condition signal and the second condition signal has the second logic value, and the third condition signal has the first logic value, each of the fifth switch, the seventh switch, the tenth switch, and the eleventh switch of the rectifier switches is turned on. When each of the first condition signal and the third condition signal has the second logic value, and the second condition signal has the first logic value, each of the twelfth switch, the sixth switch, the eighth switch, and the ninth switch of the rectifier switches is turned on, and When each of the first condition signal and the second condition signal has the first logic value, and the third condition signal has the second logic value, each of the fourth switch, the tenth switch, the eleventh switch, and the twelfth switch of the rectifier switches is turned on.

8. A method of operating a converter system, comprising: Calculate the polarity of a converter system based on a complex number of current signals; Based on these current signals and a reference phase parameter, a control cycle and a duty cycle of the converter system are calculated; and The converter system controls a plurality of switches based on each of the polarity, the control period, and the duty cycle. The converter system performs the following operations during a charging mode: When the polarity is positively biased, each of the first and second switches is turned on, and each of the third and fourth switches is turned off. After the first switch and the second switch are turned on, the second switch is turned off before the first switch is turned off.

9. The operating method as described in claim 8, further comprising: The converter system operates as follows during a discharge mode: When the polarity is positive biased, each of the fifth and sixth switches is turned on, and each of the seventh and eighth switches is turned off.

10. The operating method as described in claim 9, further comprising: When the polarity is the positive bias, the ninth switch and the tenth switch of these switches are turned on; as well as When the ninth and tenth switches are turned off, each of the eleventh and twelfth switches is turned on.

11. The operating method as described in claim 10, wherein After one working cycle, and after the fifth and sixth switches are turned on, the tenth switch is turned on, and The eleventh switch is turned on before the twelfth switch is turned on.

12. The operating method of claim 11, wherein the converter system, during the discharge mode, further comprises: When the polarity is negatively biased, each of the fifth, sixth, eleventh, and twelfth switches is turned on, and each of the seventh and eighth switches is turned off. When each of the eleventh and twelfth switches is turned off, each of the ninth and tenth switches is turned on.

13. The operating method as described in claim 12, wherein After this work cycle, and after the fifth and sixth switches are turned off, the twelfth switch is turned on, and The ninth switch is turned on before the tenth switch is turned on.

14. The operating method as described in claim 13, wherein The working cycle is equal to half of the control cycle multiplied by the duty cycle, and During the discharge mode, the first switch, the second switch, the third switch, and the fourth switch of the converter system are turned off.

15. A converter system, comprising: A plurality of power supplies are coupled to a plurality of inductors, which are used to provide a plurality of phase voltage signals and a plurality of current signals; A rectifier circuit is coupled to these inductors; A switching circuit includes a plurality of switching switches, a first capacitor and a second capacitor, each of the first capacitor and the second capacitor being coupled to the rectifier circuit. as well as A first controller is used to calculate a plurality of reference current signals, a plurality of regional current signals, and a plurality of regional reference current signals based on the phase voltage signals, the current signals, and a reference phase parameter.

16. The converter system of claim 15, further comprising: A phase-locked loop is used to perform a phase-locked operation on these phase voltage signals and generate a complex number of voltage phase parameters; A first calculator is used to calculate the region current signals and a plurality of region phase parameters based on each of the current signals, the phase voltage signals, and the voltage phase parameters; and A second calculator is used to calculate each of the reference current signals and the regional reference current signals.

17. The converter system of claim 16, further comprising: A second controller is used to calculate a switching frequency and a duty cycle based on each of the current signals of the regions and the reference current signals of the regions. as well as A first selector is used to control the switching switches based on the reference current signals, the switching frequency, and the duty cycle.

18. The converter system of claim 15, wherein This rectifier circuit is used to control a plurality of rectifier switches by performing a logic operation on these phase voltage signals. When a first phase voltage signal of the given phase voltage signals is higher than a second phase voltage signal of the given phase voltage signals, a first condition signal has a first logic value. When the first phase voltage signal is lower than the second phase voltage signal, the first condition signal has a second logic value. When the first phase voltage signal is higher than a third phase voltage signal of the phase voltage signals, a second condition signal has the first logic value. When the first phase voltage signal is lower than the third phase voltage signal, the second condition signal has the second logic value. When the third phase voltage signal is higher than the second phase voltage signal, a third condition signal has the first logic value. When the third phase voltage signal is lower than the second phase voltage signal, the third condition signal has the second logic value, and The first logical value is different from the second logical value.

19. The converter system of claim 18, wherein When each of the first condition signal, the second condition signal, and the third condition signal has the first logic value, each of the first switch, the second switch, the third switch, and the fourth switch of the rectifier switches is turned on. When each of the first condition signal, the second condition signal, and the third condition signal has the second logic value, each of the third, fourth, fifth, and sixth switches of the rectifier switches is turned on, and When each of the first condition signal and the third condition signal has the first logic value, and the second condition signal has the second logic value, each of the second switch, the seventh switch, the eighth switch, and the ninth switch of the rectifier switches is turned on.

20. The converter system of claim 19, wherein When each of the first condition signal and the second condition signal has the second logic value, and the third condition signal has the first logic value, each of the fifth switch, the seventh switch, the tenth switch, and the eleventh switch of the rectifier switches is turned on. When each of the first condition signal and the third condition signal has the second logic value, and the second condition signal has the first logic value, the twelfth switch, the sixth switch, the eighth switch, and the ninth switch of the rectifier switches are turned on, and When each of the first condition signal and the second condition signal has the first logic value, and the third condition signal has the second logic value, the fourth switch, the tenth switch, the eleventh switch, and the twelfth switch of the rectifier switches are turned on.

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