An integrated multi-channel motor drive system with cross-channel coordination management function

Abstract

The application provides an integrated multi-channel motor drive system with cross-channel cooperative management function, comprising a master control processing unit and multiple drive channels, each drive channel comprising an integrated drive chip for driving a motor and outputting a detection signal. The system further comprises a multi-channel state aggregation structure and a cooperative decision engine configured in the master control processing unit, the multi-channel state aggregation structure collects detection signals of each drive channel, and the cooperative decision engine determines output limiting parameters of each drive channel based on the collected detection signals. The system further comprises a load state discrimination module for determining a load state according to a statistical feature of the detection signal, and a hierarchical protection response module for performing at least two levels of hierarchical protection according to the load state. The system actively avoids the risk of thermal coupling and power competition before the internal protection trigger of the drive chip through cross-channel information aggregation and cooperative scheduling.

Description

Technical Field

[0001] This application relates to the field of motor drive control technology, and in particular to an integrated multi-channel motor drive system with cross-channel collaborative management function. Background Technology

[0002] In integrated multi-channel motor drivers, multiple integrated driver chips are laid out on the same board as the main control processing unit, and each channel shares the same input power supply. Existing drivers of this type generally adopt an architecture where each channel is controlled independently, and the detection signal of each drive channel is only used for overcurrent protection of that channel, with the status information between channels being invisible to each other.

[0003] The aforementioned architecture presents technical challenges during multi-channel parallel operation: the heat dissipation paths of each driver chip are coupled, the heat from high-load channels reduces the junction temperature margin of adjacent channels, and the system only passively responds after triggering internal thermal shutdown of the chip; when multiple channels start up simultaneously, they share a power supply to withstand instantaneous high current surges, which may cause a voltage drop leading to unexpected shutdown of all channels. Therefore, existing multi-channel motor drivers lack a cross-channel collaborative scheduling mechanism based on the aggregation of multi-channel detection signals. Summary of the Invention

[0004] To address the shortcomings of existing integrated multi-channel motor drivers, such as independent control of each drive channel and the lack of a collaborative scheduling mechanism based on detection signal aggregation, which leads to thermal coupling, lack of management, and lack of arbitration for power contention during parallel operation, this application provides an integrated multi-channel motor drive system with cross-channel collaborative management capabilities. This system aggregates detection signals from each drive channel by constructing a multi-channel state aggregation structure in the main control processing unit. A collaborative decision engine performs cross-channel resource scheduling and load status discrimination based on the aggregated information, and implements hierarchical protection responses for each drive channel. It can proactively perform collaborative scheduling before reaching the chip's internal protection threshold, upgrading the multi-channel driver from a simple superposition of independent channels to an integrated system with collaborative perception and adaptive scheduling capabilities. Specifically, this application provides the following technical solutions: This application provides an integrated multi-channel motor drive system with cross-channel collaborative management function, including a main control processing unit and multiple drive channels connected to the main control processing unit. Each drive channel includes an integrated drive chip for driving a motor and outputting detection signals. The system further includes: a multi-channel state aggregation structure configured in the main control processing unit for aggregating the detection signals of each drive channel; a collaborative decision engine configured in the main control processing unit for performing cross-channel resource scheduling based on the detection signals in the multi-channel state aggregation structure to determine the output limit parameters of each drive channel; a load state discrimination module for determining the load state based on the statistical characteristics of the detection signals of each drive channel; and a graded protection response module for performing at least two levels of graded protection on each drive channel based on the load state.

[0005] Optionally, the cross-channel resource scheduling includes: estimating the thermal state of each driving channel based on the historical values ​​of the detection signals of each driving channel, and reducing the output limiting parameters of the corresponding driving channel when the thermal state exceeds a preset threshold.

[0006] Optionally, estimating the thermal state of each driving channel based on the historical values ​​of the detection signals of each driving channel includes: determining the estimated junction temperature of each driving channel based on the exponentially weighted accumulation of the squared values ​​of the detection signals of each driving channel.

[0007] Optionally, the cross-channel resource scheduling further includes: when multiple drive channels request to start simultaneously, releasing the start permits of each drive channel in sequence according to preset rules.

[0008] Optionally, determining the load state based on the statistical characteristics of the detection signals of each of the driving channels includes: determining whether each of the driving channels is in at least one abnormal load state based on the mean and variability of the detection signals within a sliding window.

[0009] Optionally, the graded protection includes: channel-level protection, used to reduce the output limit parameter of the drive channel when the load state of the drive channel is abnormal; and cross-channel collaborative protection, used to redistribute the power margin released by the drive channel to the other drive channels when the drive channel enters shutdown protection.

[0010] Optionally, the system further includes a communication unit, which is used to receive external control commands and report the operating status of each of the drive channels.

[0011] Optionally, the communication unit is further configured to receive remote configuration parameters, which are then verified and written into a non-volatile memory.

[0012] This application also provides a computer-readable storage medium storing a computer program thereon, which, when executed by a processor, implements the functions of the collaborative decision engine, the load status discrimination module, and the hierarchical protection response module in the above system.

[0013] The integrated multi-channel motor drive system provided in this application has the following advantages: By setting up a multi-channel status aggregation structure in the main control processing unit, the detection signals of each drive channel, which were originally independent and invisible to each other, are unified and collected. This allows the collaborative decision engine to obtain the real-time operating status of all drive channels, thereby eliminating the information isolation barriers between channels in the prior art. The collaborative decision engine performs cross-channel resource scheduling based on the multi-channel aggregated information. It can proactively adjust the output limiting parameters of each drive channel before the internal protection circuits of each drive chip are triggered, transforming the passive, sudden chip-level protection response in the prior art into an active, gradual system-level collaborative scheduling. Simultaneously, by extracting statistical features from the detection signals to achieve load status discrimination, the same detection signal can provide load sensing information in addition to its current limiting function, realizing the functional reuse of the detection signal. The hierarchical protection response module executes at least two levels of protection actions based on the load status discrimination results. It can implement differentiated protection strategies at the channel level and cross-channel level. The power margin released by the faulty channel can be redistributed to the remaining normally operating drive channels, avoiding system-level cascading failures caused by a single channel failure. Attached Figure Description

[0014] Figure 1 This is a schematic diagram of the overall architecture of the integrated multi-channel motor drive system provided in the embodiments of this application.

[0015] Figure 2 This is a schematic diagram of the multi-channel state aggregation structure and collaborative decision engine data flow provided in the embodiments of this application.

[0016] Figure 3 The overall flowchart of cross-channel collaborative scheduling provided for the embodiments of this application is shown.

[0017] Figure 4 A flowchart for load status classification and discrimination provided in the embodiments of this application.

[0018] Figure 5 This is a schematic diagram of the hierarchical fault protection state transition provided in an embodiment of this application.

[0019] Figure 6 A flowchart of multi-channel staggered start-up scheduling provided for embodiments of this application.

[0020] Figure 7 This is a schematic diagram of the collaborative thermal estimation response curve based on the current detection signal provided in an embodiment of this application.

[0021] Figure 8 This is a schematic diagram of the spatial distribution of load state characteristics based on current statistical features, provided for an embodiment of this application.

[0022] Figure 9 This is a schematic diagram of the communication protocol message arrangement structure provided in the embodiments of this application.

[0023] Reference numerals: 100, Power Management Unit; 200, Main Control Processing Unit; 300, Multi-channel Drive Unit; 310, Drive Channel; 320, Integrated Drive Chip; 400, Encoder Feedback Unit; 500, Communication and Configuration Unit; 600, Cross-channel Collaborative Management Unit; 610, Multi-channel State Aggregation Structure; 620, Collaborative Decision Engine; M, Motor. Detailed Implementation

[0024] To make the objectives, technical solutions, and advantages of this application clearer, the technical solutions of this application will be clearly and completely described below in conjunction with the accompanying drawings and specific embodiments. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0025] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0026] The integrated multi-channel motor drive system provided in this application is applicable to various electronic devices requiring coordinated control of multiple motors, such as multi-axis sample processing platforms in medical diagnostic equipment, multi-station conveying devices on industrial automated production lines, multi-channel fluid control devices in laboratory analytical instruments, multi-axis sorting mechanisms in intelligent warehousing systems, multi-joint drive devices for collaborative robots, and multi-dimensional adjustment mechanisms in precision optical instruments. All of these devices share the common engineering characteristic of multiple motors sharing input power and heat dissipation paths, creating an objective need for coordinated scheduling and protection response among the various drive channels.

[0027] like Figure 1 As shown, the integrated multi-channel motor drive system provided in this application embodiment includes a power management unit 100, a main control processing unit 200, a multi-channel drive unit 300, an encoder feedback unit 400, a communication and configuration unit 500, and a cross-channel collaborative management unit 600.

[0028] The multi-channel drive unit 300 includes multiple drive channels 310, each drive channel 310 including an integrated drive chip 320 for driving motor M and outputting detection signals. The power management unit 100 provides power to the main control processing unit 200 and the multi-channel drive unit 300. The main control processing unit 200 is connected to each of the integrated drive chips 320 and is used to output control signals to each of the drive channels 310 and receive detection signals fed back by each of the drive channels 310. The cross-channel collaborative management unit 600 is configured in the main control processing unit 200 and includes a multi-channel state aggregation structure 610 and a collaborative decision engine 620. The multi-channel state aggregation structure 610 is used to aggregate the detection signals of each of the drive channels 310, and the collaborative decision engine 620 is used to perform cross-channel resource scheduling based on the detection signals in the multi-channel state aggregation structure 610. The encoder feedback unit 400 is connected to the output shaft of each motor M and provides position and speed feedback signals to the main control processing unit 200. The communication and configuration unit 500 is connected to the main control processing unit 200 and is used to receive external control commands and report the operating status of each drive channel 310.

[0029] In this embodiment, the integrated multi-channel motor drive system is described using four drive channels 310 as an example, with each drive channel 310 driving one motor M. Those skilled in the art will understand that the number of drive channels 310 is not limited to four, and can be set to two, three, six, or eight, or other numbers, depending on actual needs. When the number of drive channels 310 changes, the number of channel slots in the multi-channel state aggregation structure 610 is adjusted accordingly, and the traversal range of the collaborative decision engine 620 and the upper limit of the summation in the system total power calculation formula are updated accordingly. However, the algorithm logic for collaborative thermal estimation, power budget balancing, load state discrimination, and graded fault protection remains unchanged. The specific implementation methods of each unit are described in detail below.

[0030] The power management unit 100 is used to convert and distribute an external wide-voltage DC input into a multi-stage power supply required by the system. The input terminal of the power management unit 100 is connected to an external DC power supply, and the input voltage range is... to The power management unit 100 includes a power supply path, a logic power supply path, and a power voltage monitoring path.

[0031] In the power supply path, the external DC power supply is connected to the power supply bus after being protected by a reverse-connection P-channel MOSFET and a transient voltage suppression diode. The power supply bus is directly connected to the power input pins of each integrated driver chip 320, providing power to drive the motor M. An aluminum electrolytic capacitor and a high-frequency ceramic decoupling capacitor are connected in parallel on the power supply bus to suppress low-frequency pulsation and high-frequency switching noise, respectively. For example, the capacitance of the aluminum electrolytic capacitor is... Rated voltage is The capacitance of the high-frequency ceramic decoupling capacitor is Rated voltage is They are placed near the power input pin of each of the integrated driver chips 320.

[0032] In the aforementioned logic power path, the power supply bus is stepped down to voltage by a wide-input buck switching regulator. Intermediate power supply. The input voltage range of the wide-input buck switching regulator is: to The output voltage is The switching frequency is The above uses two output capacitors. With ceramic capacitors connected in parallel, the output ripple should not exceed [value missing]. Power is supplied to the encoder feedback unit 400. The intermediate power supply is then regulated by a linear regulator to... This refers to the main control processing unit 200. A ferrite bead is connected in series between the buck switching regulator and the linear regulator to isolate power stage switching noise from interfering with the logic power supply. For example, the buck switching regulator can be a wide-input buck chip such as TPS5430 or LMR14006, and the linear regulator can be a fixed-output linear regulator such as AMS1117-3.3.

[0033] In the power supply voltage monitoring path, the power supply bus is connected to the analog-to-digital converter input pin of the main control processing unit 200 through a precision resistor voltage divider network to realize power supply voltage monitoring. Real-time sampling. The voltage division ratio of the resistor voltage divider network. Designed to handle the highest input voltage Mapped to no more than the analog-to-digital converter reference voltage The range. For example, the resistor divider network consists of an upper arm resistor. and lower arm resistance Composition, partial pressure ratio parallel voltage divider nodes Filter capacitors are used to suppress high-frequency noise. The formula for converting power supply voltage is: in The raw readings of the analog-to-digital converter. This is the reference voltage for the analog-to-digital converter. For analog-to-digital converter resolution. For example, when hour, .

[0034] The main control processing unit 200 uses a microcontroller as the system's overall controller, responsible for instruction parsing, collaborative scheduling decisions, pulse width modulation signal generation, analog-to-digital conversion acquisition, encoder decoding, communication protocol processing, and fault management. In this embodiment, the microcontroller is an STM32G473 series microcontroller with a built-in ARM Cortex-M4F core and an operating frequency of [missing information]. It integrates a floating-point arithmetic unit and a mathematical operation accelerator.

[0035] The analog-to-digital converter (ADC) resources of the main control processing unit 200 are allocated as follows: The four channels of the first ADC of the microcontroller are respectively connected to the IPROPI current proportional output pins of the integrated driver chips 320 in each of the four drive channels 310, for acquiring the detection signals of each drive channel 310. One channel of the second ADC of the microcontroller is connected to the voltage divider sampling point of the power management unit 100, for monitoring the power supply voltage. The first analog-to-digital converter is configured in continuous scanning mode, sequentially scanning the four IPROPI channels. After each scan, a direct memory access transfer is triggered, writing the four sampled values ​​into the corresponding fields of the multi-channel state aggregation structure 610. The direct memory access uses a double-buffered mode to ensure that the analog-to-digital converter sampling is not interrupted by the data reading operations of the collaborative decision engine 620.

[0036] The timer resource allocation of the main control processing unit 200 is as follows: The first advanced timer of the microcontroller outputs four pulse width modulation signals to control the enable and direction pins of the integrated driver chip 320 of the first and second drive channels 310. The second advanced timer of the microcontroller outputs four pulse width modulation signals to control the integrated driver chip 320 of the third and fourth drive channels 310. The second to fifth general-purpose timers of the microcontroller are configured in encoder interface mode, each connected to a set of A-phase and B-phase signals of a quadrature encoder. The sixth basic timer of the microcontroller operates at a fixed period. An interrupt is generated to trigger the periodic execution of the collaborative decision engine 620. The microcontroller's seventh basic timer is used to trigger periodic status reporting.

[0037] In the general-purpose input / output interface of the main control processing unit 200, four push-pull outputs are respectively connected to the nSLEEP enable pin of each integrated driver chip 320, and four external interrupt inputs are respectively connected to the nFAULT fault output pin of each integrated driver chip 320. Regarding communication peripherals, the microcontroller's FDCAN peripheral is connected to the CAN bus transceiver in the communication and configuration unit 500, and the USART peripheral is connected to the host computer's serial interface.

[0038] The firmware of the main control processing unit 200 adopts a hybrid architecture combining timer interrupt-driven and main loop polling. The nFAULT external interrupt has the highest priority and is used for rapid fault response; the delay from pin triggering to interrupt service routine execution is no greater than [value missing]. The analog-to-digital converter direct memory access transfer completion interrupt is also of high priority and is used to detect signal data readiness notifications. The sixth basic timer interrupt is of medium priority and occurs in each... Within the cycle, thermal estimation updates, power budget calculations, load status assessment, and fault level determination are performed sequentially. FDCAN receive interrupts are of low priority and are used for command reception. The main loop executes motor drive control outputs and status reporting.

[0039] For example, the frequency of the pulse width modulation signal is Corresponding to pulse width modulation period The microcontroller clock frequency is At that time, the value of the automatic reload register of the advanced timer is... Pulse width modulation resolution approximately The execution cycle of the collaborative decision engine 620. Usually in to Within the scope, this embodiment takes That is, each A collaborative decision is executed once per pulse width modulation cycle. Main control cycle. Synchronized with the pulse width modulation period, for .

[0040] In another embodiment, the main control processing unit 200 may also be implemented using other microcontrollers with multi-channel analog-to-digital converters, multiple timer encoder interfaces and CAN bus peripherals, such as STM32H7 series microcontrollers or TIC2000 series digital signal processors, as long as the microcontroller has sufficient timer resources and computing power to support the periodic execution of the collaborative decision engine 620.

[0041] The multi-channel drive unit 300 includes four drive channels 310, and each drive channel 310 includes an integrated drive chip 320. The integrated drive chip 320 converts the low-power control signal output by the main control processing unit 200 into a power drive signal for the motor M winding, while also providing a detection signal proportional to the load current and various hardware protection functions. In this embodiment, the integrated drive chip 320 uses the DRV887x series integrated motor drive chip; the DRV8876 will be used as an example for specific explanation.

[0042] Each integrated driver chip 320 internally integrates a full-bridge driver circuit consisting of four N-channel metal-oxide-semiconductor field-effect transistors (MOSFETs), as well as a charge pump regulator, a current sensing mirror, and multiple protection circuits. The charge pump regulator provides sufficient gate drive voltage to the high-side MOSFETs of the full-bridge driver circuit, enabling the integrated driver chip 320 to support… Duty cycle operation. The power supply pin of the integrated driver chip 320 is connected to the power supply bus, and is placed nearby next to the pin. Ceramic decoupling capacitors and High-frequency decoupling capacitor. External charge pump pin. Bootstrap capacitor to power supply pin.

[0043] The integrated driver chip 320 adopts a PH / EN control mode. The PH pin controls the direction of motor M, and the EN pin receives the pulse width modulation signal output by the main control processing unit 200 to control the speed. When the PH pin is high, the first output terminal of the full-bridge driver circuit outputs a pulse width modulation power signal, the second output terminal is grounded, and motor M rotates forward. When the PH pin is low, the first output terminal is grounded, the second output terminal outputs a pulse width modulation power signal, and motor M rotates in reverse. When the EN pin is low, all field-effect transistors of the full-bridge driver circuit are turned off, and motor M is in a free-rotation state. The nSLEEP enable pin is connected to the push-pull output of the general-purpose input / output interface of the main control processing unit 200, through... Resistor pull-up A logic power supply is provided to prevent the chip's state from becoming uncertain due to floating pins during the microcontroller's initialization phase. The two power output terminals OUT1 and OUT2 of the full-bridge drive circuit are respectively connected to the two terminals of motor M.

[0044] The IPROPI current ratio output pin of the integrated driver chip 320 serves as the physical carrier of the detection signal. Internally, the integrated driver chip 320 integrates a detection field-effect transistor next to the low-side field-effect transistor in the full-bridge driver circuit. The channel area of ​​this detection field-effect transistor is a fraction of the channel area of ​​the power field-effect transistor. The current flowing through the detection field-effect transistor is twice that of the power field-effect transistor, and it shares the gate and source with the power field-effect transistor. Based on the physical characteristic that the current of a field-effect transistor is proportional to the channel area, the current flowing through the detection field-effect transistor satisfies a fixed proportional relationship with the load current: in The current proportionality coefficient is determined by the model of the integrated driver chip 320. An external sampling resistor is connected to the IPROPI current proportional output pin. To ground, the sampling resistor The voltage generated above is the detection signal: This voltage is sent to the input terminal of the analog-to-digital converter of the main control processing unit 200. After performing analog-to-digital conversion on this voltage, the main control processing unit 200 can calculate the load current. The sampling resistor The resistor value should be selected so that the IPROPI voltage corresponding to the full-scale load current is close to but does not exceed the analog-to-digital converter reference voltage. For example, the DRV8876's Select At that time, full-scale current The corresponding IPROPI voltage is Not exceeding the analog-to-digital converter reference voltage .

[0045] The nFAULT fault output pin of the integrated driver chip 320 is an open-drain output. During normal operation, the external... A pull-up resistor pulls the pin high. When the integrated driver chip 320 detects any of the faults of overcurrent, overtemperature, undervoltage, or charge pump undervoltage, the nFAULT pin is pulled low, triggering an external interrupt of the main control processing unit 200 to achieve rapid fault response.

[0046] The VREF pin of the integrated driver chip 320 is used to set the current limit value of each driver channel 310. The VREF pin is connected to the analog voltage generated by the pulse-width modulation output of the main control processing unit 200 after RC low-pass filtering. When the sampling resistor... When the voltage on the bridge reaches the VREF reference voltage, the current chopper circuit inside the integrated driver chip 320 automatically turns off the high-side MOSFET of the full-bridge driver circuit for a fixed time, and then turns it back on. Through repeated chopping, the average load current is limited to a set value. The current limit value... The relationship with the VREF reference voltage is as follows: For example, when it is necessary to limit the current to hour, The main control processing unit 200 sets the pulse width modulation output duty cycle of the corresponding channel to... After being low-pass filtered by RC, it generates at the VREF pin. DC voltage.

[0047] The integrated driver chip 320 also incorporates multiple hardware protection circuits, including power undervoltage lockout protection, charge pump undervoltage protection, overcurrent protection, and overheat shutdown protection. These hardware protection circuits cannot be disabled by software and serve as the system's final safety line. For example, the power undervoltage lockout threshold of the DRV8876 is approximately... The overheating shutdown threshold is approximately When any protection is triggered, the integrated driver chip 320 shuts down all outputs and notifies the main control processing unit 200 via the nFAULT pin.

[0048] In another embodiment, the integrated driver chip 320 can also be a pin-compatible integrated motor driver chip such as DRV8870 or A4950. Different models have different on-resistance and current ratings, which can adapt to application scenarios with different power requirements without changing the printed circuit board layout. In yet another embodiment, the detection signal can also be obtained by connecting a low-resistance current detection resistor in series in the drive circuit of the motor M and measuring the voltage drop across it. This method can also provide an analog signal proportional to the load current, which can be collected by the multi-channel state aggregation structure 610 to achieve cross-channel collaborative management.

[0049] The encoder feedback unit 400 includes four sets of incremental quadrature encoders, each mounted on the output shaft of one of the four motors M. Each quadrature encoder set contains two quadrature output signals, A-phase and B-phase. The A-phase and B-phase signals of each quadrature encoder are connected to the corresponding timer encoder interface of the main control processing unit 200 after passing through a signal conditioning circuit. The signal conditioning circuit includes pull-up resistors and filter capacitors; exemplarily, the pull-up resistors are... The filter capacitor is to The A-phase and B-phase signals of the first channel encoder are connected to the first and second channel inputs of the second general-purpose timer of the microcontroller, and the second to fourth channel encoders are connected to the third to fifth general-purpose timers in turn.

[0050] The timer encoder interface is configured in a dual-edge counting mode, counting on each rising and falling edge of the A-phase and B-phase signals to achieve quadruple frequency decoding. The position resolution after quadruple frequency decoding is four times the original encoder resolution. For example, when the encoder's pulse count per revolution... for At that time, the count value per revolution after quadruple frequency decoding is Each pulse. The timer / counter automatically increments or decrements as the motor M rotates. The direction of rotation is automatically determined by the hardware based on the phase relationship between phase A and phase B signals, without the need for a central processing unit.

[0051] The encoder feedback unit 400, through the software of the main control processing unit 200, at fixed time intervals... Internal read counter increment Calculate the rotational speed of motor M in each channel: in For the first Channel encoder at time interval The count increment within, The unit is RPM. The count increment... The speed is calculated by the difference between the current counter value and the counter value read last time. Signed arithmetic is used to handle counter overflow, ensuring that the speed calculation provides correct positive and negative results across the entire counter range. The direction of rotation is determined by... The sign is automatically determined; a positive value indicates clockwise rotation, and a negative value indicates counterclockwise rotation. For example, Usually in to Within the scope, this embodiment takes .when At that time, the lowest resolvable speed was After completing the above calculations in each speed calculation cycle, the main control processing unit 200 will output the calculated speed value. The corresponding channel slots of the multi-channel state aggregation structure 610 are written for the collaborative decision engine 620 and the motor drive control module to read and use.

[0052] In another embodiment, the encoder feedback unit 400 may also use a Hall encoder instead of an incremental quadrature encoder. Hall encoders have lower resolution but no contact wear. In yet another embodiment, an absolute encoder communicating via an SPI or SSI interface may also be used. Absolute encoders can acquire absolute position information without performing a zeroing operation after power-on.

[0053] The communication and configuration unit 500, as a specific implementation of the communication unit, provides a communication channel between the integrated multi-channel motor drive system and an external controller or host computer, supporting command reception, status reporting, and online parameter configuration. The communication and configuration unit 500 includes a CAN bus communication interface, a UART serial interface, and a DIP switch.

[0054] In the CAN bus communication interface, the transmit and receive pins of the FDCAN peripheral of the main control processing unit 200 are connected to the CAN bus transceiver, and the differential output terminals CAN_H and CAN_L of the CAN bus transceiver are connected to the CAN bus. One transceiver is configured at each end of the CAN bus. Termination resistor. For example, the CAN bus transceiver uses a TJA1042, with a supply voltage of... Support the highest Communication rate. In this embodiment, the default CAN bus baud rate is configured as follows: This can be modified via configuration commands. For example... Figure 9 As shown, the CAN bus communication interface uses the CAN 2.0B standard frame format, and different functions are implemented based on segmentation of the message based on the message identifier. The identifier range of the emergency fault frame is... to It has the highest priority. The identifier for the motion command frame is... Add equipment label The identifier for the configuration instruction frame is... add The identifier for the status reporting frame is... add .

[0055] The FDCAN peripheral has a built-in hardware message filter configured to only receive messages with the device identifier. Matched messages and broadcast frames are processed, while messages with other identifiers are automatically discarded by hardware. When the FDCAN peripheral receives a valid message, a receive interrupt is triggered. The interrupt service routine reads the message identifier and data field, and determines the instruction type based on the identifier category. The data field of the motion instruction frame contains the channel number, control mode, and target parameter value, which is parsed and written to the corresponding channel target parameter field of the multi-channel state aggregation structure 610. The interrupt service routine performs a validity check on the parsed motion instruction. The validity check includes: whether the channel number is within the valid range and whether the channel was marked as available during system initialization; whether the target parameter value is within the preset safety range; and whether the channel is currently in a hard fault lockout state. Instructions that fail the check are discarded and the corresponding error code is returned via a CAN response frame. To prevent rapidly arriving instructions from overwriting unexecuted preceding instructions, the main control processing unit 200 uses a circular buffer as an instruction queue to store parsed motion instructions. The capacity of the circular buffer is typically [missing information]. to Within the scope of the clauses, this embodiment takes At the beginning of each main control cycle, the motor drive control module reads and executes instructions from the head of the instruction queue. The data field of the configuration instruction frame contains the configuration type and configuration parameter values, which are then parsed and updated with the corresponding operating parameters.

[0056] In the UART serial interface, the USART peripheral of the main control processing unit 200 is connected to a USB-to-serial chip, communicating with the host computer via a USB interface. The baud rate of the UART serial interface is... It adopts a fixed-length frame format, and the frame header is It includes a length field, a command code field, a data field, and a CRC8 check field. The host computer can request real-time current waveform data streams through the UART serial interface. The main control processing unit 200 packages and sends the raw values ​​of each channel's analog-to-digital converter at fixed intervals. After receiving the data, the host computer converts it into physical quantities and plots real-time curves.

[0057] The DIP switch is a 4-bit binary coded switch, with its four pins connected to the general-purpose input / output interface of the main control processing unit 200, and internally enabled by pull-up resistors in the microcontroller. When the DIP switch is in the ON position, the corresponding pin is grounded and read as logic low; when it is in the OFF position, the corresponding pin is pulled up to a high level. The 4-bit binary encoding supports... to common A device address. When the system powers on, the main control processing unit 200 reads the state of the DIP switch as the default device identifier. During operation, the device identifier can be modified via CAN configuration command frames. The new identifier is written to non-volatile memory and takes effect upon the next power-on.

[0058] The cross-channel collaborative management unit 600 is a pure software module configured in the main control processing unit 200, without independent hardware components. For example... Figure 2 As shown, the cross-channel collaborative management unit 600 includes the multi-channel state aggregation structure 610 and the collaborative decision engine 620.

[0059] In this embodiment, the multi-channel state aggregation structure 610 is specifically implemented as a Channel State Aggregation Table (CSAT) in the microcontroller's random access memory. The CSAT contains four channel slots, each recording all runtime states of the corresponding drive channel 310. The CSAT serves as the sole data source for all collaborative decisions, enabling information sharing among the drive channels 310. Each channel slot includes the following fields: current-related fields, including the current... Average current Coefficient of variation and current history sliding window Motion-related fields, including encoder position. Encoder speed and target parameters; status flags field, including load status. Fault Level nFAULT hardware logo and thermal warning logo Collaborative output fields, including power limiting factor. and Startup license flag Thermal estimation field, including estimated junction temperature. and the cumulative square value of current .

[0060] The CSAT data writing sources include: an analog-to-digital converter direct memory access interrupt updating the current data corresponding to the detection signals of each channel; an encoder timer updating the position data; an instruction parsing module updating the target parameters; and an nFAULT interrupt updating the fault flag. The CSAT data reading consumers include: the collaborative decision engine 620 reading the status of all channels and executing collaborative decisions before writing the results back to the collaborative output field; and the motor drive control module reading the power limitation coefficient. and Startup license flag Used to adjust pulse width modulation output, the status reporting module reads all statuses for periodic reporting. The CSAT's read / write operations are protected against data contention via critical sections. During direct memory access interrupt writes to the analog-to-digital converter, the timer interrupt of the collaborative decision engine 620 is temporarily disabled, and restored after the write operation is complete. Since the write operation involves only a few 32-bit variables, the critical section duration is extremely short, having no impact on system real-time performance. For example, the CSAT's memory usage is approximately... Byte channel status data plus A sliding window buffer of bytes, totaling no more than [number] bytes. .

[0061] In another embodiment, the multi-channel state aggregation structure 610 can also be implemented through the shared register group of the microcontroller, mapping the key state parameters of each channel to the register address space, and achieving lock-free concurrent access through register-level atomic operations.

[0062] The collaborative decision engine 620 is driven by the sixth basic timer interrupt of the main control processing unit 200 in each collaborative decision cycle. It executes a fixed sequence of decisions. For example... Figure 3 As shown, the collaborative decision engine 620 in each Within the cycle, the following four collaborative decisions are executed sequentially: collaborative thermal estimation and active power reduction, power budget calculation and balancing, load status discrimination, and graded fault protection response. All four decisions use the multi-channel detection signals collected in the CSAT as input, and the decision results are written back to the collaborative output field of the CSAT, which is then read and executed by the motor drive control module in the next main control loop. The detection signals are reused multiple times in the above decision sequence: the current value of the same detection signal serves as the power consumption calculation input for collaborative thermal estimation, the total power calculation input for power budget, and the statistical feature extraction input for load status discrimination. This enables the detection signals to be reused and extended from a single current limiting function to multiple functions such as thermal management, power balancing, and load sensing.

[0063] The purpose of the collaborative thermal estimation is to estimate the thermal state of each integrated driver chip 320 using the detection signals of each of the driving channels 310. In this embodiment, the thermal state is estimated using the junction temperature. Quantitative characterization is performed to reflect the junction temperature variation trend of each integrated driver chip 320. Since the detection signal of the integrated driver chip 320 already provides real-time load current information, the junction temperature can be indirectly estimated based on this information without the need for an external temperature sensor. The collaborative thermal estimation adopts a discretized model of a first-order RC thermal equivalent circuit. The first-order RC thermal equivalent circuit analogizes the heat conduction process of the integrated driver chip 320 to a resistive-capacitive circuit, where the equivalent thermal resistance... Corresponding resistance, equivalent heat capacity The corresponding capacitor, power loss, and temperature difference correspond to the current source and voltage, respectively. The power loss of the full-bridge drive circuit inside the integrated driver chip 320 is mainly due to the on-resistance. The square of the current on the circuit is determined by the resistance value; therefore, the product of the square of the load current provided by the detection signal and the on-resistance is the driving force for the junction temperature rise. This model applies to each... The current squared exponent-weighted cumulative value is updated for each drive channel 310 within the cycle: in The exponential decay coefficient reflects the impact of the packaged thermal inertia of the integrated driver chip 320 on the thermal estimation update rate, and its value is close to... This means that the thermal time constant is much larger than the collaborative decision-making cycle, and the estimated junction temperature exhibits low-pass filtering characteristics for transient current fluctuations, tracking only the low-frequency trend of the current without being affected by high-frequency noise. This refers to the package thermal time constant of the integrated driver chip 320. From equivalent thermal resistance and equivalent heat capacity The product is determined. For the first The drive channel 310 in the first The load current value is obtained by converting the detection signal of each cycle. The estimated junction temperature of each drive channel 310 is calculated according to the following formula: in For ambient temperature, The junction-to-environment equivalent thermal resistance of the integrated driver chip 320 is given by [reference to ambient temperature]. This represents the on-resistance of the full-bridge drive circuit. For example, Usually in to Within the scope, this embodiment takes , , When all four drive channels 310 are operating at full-scale current... During operation, the total power consumption of the four integrated driver chips 320 is approximately All power consumption is dissipated through the printed circuit board's heat dissipation path, making coordinated thermal management a necessary condition for reliable system operation. Thermal time constant. Usually in to Within the scope, this embodiment takes ,when hour, .

[0064] When the estimated junction temperature of a certain channel Exceeding the preset heat warning threshold At this time, the collaborative decision engine 620 performs active power reduction on the channel, lowering the output limiting parameters of the channel. The thermal warning threshold... Set below the internal overheat shutdown threshold of the integrated driver chip 320 A temperature value with a certain margin. For example, The heat reduction power is achieved using a linear mapping method. and The output limit parameter is linearly reduced between these parameters. This design allows the system to proactively reduce power to zero before the estimated junction temperature reaches the internal overheat shutdown threshold of the integrated driver chip 320, thus preventing sudden shutdown of the motor M due to hardware thermal shutdown. Figure 7 As shown, the thermal estimation response curve illustrates the linear mapping relationship between the estimated junction temperature and the output limiting parameter. For example, when a channel continuously... When the current is running, under steady state Approaching Estimate junction temperature .because Triggering a heat warning The pulse width modulation duty cycle of this channel is limited to approximately the original value. This allows for smooth cooling before hardware thermal shutdown occurs. The cumulative squared current value increases as the load current of the channel decreases or external heat dissipation conditions improve. As the thermal limitation coefficient gradually decreases, the estimated junction temperature also decreases. It automatically recovers and can restore normal power output without manual intervention.

[0065] The power budget calculation and balancing are in each Calculate the total system power within the cycle and determine if it exceeds the power budget. The total system power is calculated using the following formula: when Exceeding the system's maximum power budget of At that time, the collaborative decision engine 620 performs proportional power reduction on all the drive channels 310. The warning threshold is set to reserve the system's maximum power budget. The margin is used to absorb transient power overshoot caused by the current rise slope during load changes, preventing the total system power from directly touching the power supply's rated capacity and causing a voltage drop. The proportional reduction method reduces the output limiting parameters of all drive channels 310 synchronously with the same proportional coefficient. Compared to prioritizing the cutoff of a channel's output, proportional reduction maintains the relative speed ratio between the drive channels 310, avoiding mechanical shock caused by a single channel suddenly stopping. This method is suitable for applications where there is motion coordination between the drive channels 310. The formula for calculating the power limiting coefficient is: The power limiting factor Heat extraction limiting factor and power limiting factor The smaller value ensures that both thermal safety constraints and power budget constraints are met simultaneously: For example, when , The currents of the four channels are respectively , , and hour, ,Exceed The power limiting factor The pulse width modulation duty cycle of all channels is multiplied by this coefficient to achieve proportional speed reduction.

[0066] like Figure 6 As shown, when multiple drive channels 310 request to start within the same control cycle, the collaborative decision engine 620 performs staggered start scheduling, releasing the start permits of each drive channel 310 sequentially according to a preset priority rule. The staggered start scheduling collects all channels requesting start and sorts them by priority, releasing the start permit of the channel with the highest priority. Then start a peak-shaving delay timer. During the peak-shaving delay... During this period, the startup permissions for the remaining channels remain unchanged. The peak-shifting delay Upon expiration, the collaborative decision engine 620 checks the power supply voltage. Has it been restored to the nominal value? The startup permission for the next channel is only released after confirming that the startup inrush current of the previous channel has decayed.

[0067] The starting inrush current originates from the direct application of voltage across the windings when the brushed motor starts from a standstill. At the moment of startup, the peak current, limited only by the winding resistance, can be several times the steady-state operating current. This starting current travels along a first-order circuit formed by the inductor and resistor with a time constant... The exponential decays to a steady-state value. The peak-shifting delay... The value is determined based on the equivalent time required for the starting current to decay to a steady-state value, and needs to cover several [time periods]. The time constant ensures that the startup transition process of the previous channel is essentially complete. If the power supply voltage expires after the peak-shaving delay... Still below the nominal value The collaborative decision engine 620 continues to use The power supply voltage is periodically polled until it recovers or exceeds a preset startup timeout threshold. After the timeout, the corresponding channel is marked as a startup failure and the anomaly is reported through the communication and configuration unit 500. For example, the peak-shaving delay... Usually in to Within the scope, this embodiment takes Channel priorities are arranged by default in ascending order of channel number, and can be modified online via the communication and configuration unit 500. When channel 1 and channel 4 request to start simultaneously, the staggered start scheduling first releases the start permission for channel 1, and waits... Check power supply voltage after peak shift delay It has been restored to the nominal value. The above steps are then followed by granting permission to start the fourth channel, thereby preventing the power supply voltage from dropping due to the superposition of current generated by the simultaneous startup of the two channels.

[0068] In another embodiment, the cross-channel resource scheduling can also be implemented using a priority-based allocation method. This involves assigning different power priorities to each drive channel 310. When the total power exceeds the budget, priority is given to ensuring the output of high-priority channels, and power balancing is achieved by reducing the output limit parameters of low-priority channels. In this method, the collaborative decision engine 620 allocates available power sequentially from high to low priority according to the priorities of each drive channel 310. The output limit parameters of high-priority channels remain unchanged at the constraint value of the collaborative thermal estimation, while the output limit parameters of low-priority channels are reduced according to the proportion of remaining available power to their required power. When the remaining power is insufficient to maintain the operation of the lowest-priority channel, the output limit parameter of that channel is reduced to zero. This method is suitable for application scenarios where the tasks undertaken by each drive channel 310 have significantly different importance.

[0069] like Figure 4 As shown, the load status determination function in the cross-channel collaborative management unit 600 is used to determine the load status based on the statistical characteristics of the detection signals of each drive channel 310. The load status determination is performed on each... During the cycle, statistical calculations and classification are performed on the detection signals of each drive channel 310.

[0070] The acquisition and conversion process of the detection signal is as follows: The analog voltage of the IPROPI current proportional output pin of each integrated driver chip 320 is sampled by the analog-to-digital converter of the main control processing unit 200, and then converted according to the conversion factor. Converted to actual load current value: in These are conversion factors that are calculated and cached once during system initialization. For example, That is, each least significant bit of an analog-to-digital converter corresponds to approximately The current value.

[0071] The load state determination uses a sliding window statistic for feature extraction. A length of [value missing] is maintained for each drive channel 310. Current history sliding window Each The cycle will display the latest current value. The data is written into the sliding window, overwriting the oldest sampled value. Simultaneously, an online update algorithm is used to update the mean and standard deviation, avoiding traversing the entire window each time. The online update algorithm maintains the current accumulation sum. and the sum of squared currents Two state variables are used. Each time an update occurs, the old value that was overwritten is subtracted and the new value is added. The average of these two values ​​is then calculated from the sum of the old and new values. and standard deviation Coefficient of variation Defined as the ratio of standard deviation to mean: when Below the noise floor threshold At that time, Set to zero to prevent division by zero exceptions. For example, Usually in to Within the scope, this embodiment takes ,when At that time, the sliding window covers The sampling history. The computational complexity of the online update algorithm is... Constant-time efficiency, compared to traditional window traversal. In the way, Time saving The computational load is several times that of the computer.

[0072] like Figure 8 As shown, the load state determination is based on the average current. and coefficient of variation The constructed two-dimensional feature space categorizes the load states of each drive channel 310 into four states: normal operation, no-load, stall, and gradual overload. The classification rule is: when... Below the no-load threshold and Below the low coefficient of variation threshold When this occurs, it is determined to be an unloaded state, corresponding to the light load or idling condition of motor M. When Exceeding the stall threshold and Below When this occurs, it is determined to be a stalled state, corresponding to the condition where motor M is locked by an external load and the current remains at a high level. In and When the average current value shows a continuous upward trend, it is determined to be a gradual overload state. The current trend detection divides the sliding window into a first half and a second half, and calculates the average current value of each half. and Calculate the current rise slope using the following formula: When the current rise slope Exceeding the gradual overload slope threshold When the load condition is reached, it is determined to be a gradual overload. All other conditions are considered normal operating conditions.

[0073] For example, Usually in to Within the scope, this embodiment takes . Usually in to Within the scope, this embodiment takes . Usually in to Within the scope, this embodiment takes . Usually in to Within the scope, this embodiment takes The aforementioned thresholds can all be modified online via the communication and configuration unit 500 to adapt to different types of motors M and application scenarios.

[0074] For example, when a certain channel motor M is running under normal load, , , ,because Greater than and less than , Greater than The channel is determined to be in normal operating condition. When the motor M stalls, the current is limited to a high level close to the current limit value by the chopper circuit of the integrated driver chip 320. , , ,because Greater than and Less than The channel is determined to be in a stalled state. As the load on a channel gradually increases, the average current in the first half of the sliding window... The average current in the second half The current rise slope was calculated. ,because Greater than The channel is determined to be in a gradual overload state. When motor M of a certain channel is idling, , ,because Less than and Less than The channel is determined to be in an unloaded state.

[0075] In another embodiment, the statistical features in the load condition discrimination can also use a combination of root mean square (RMS) value and peak factor instead of a combination of mean and coefficient of variation. The RMS value reflects the effective value of the current, and the peak factor reflects the degree of peaking of the current waveform, both of which can distinguish between normal operation, no-load, stalled rotor, and gradual overload load conditions.

[0076] like Figure 5 As shown, the graded protection response function in the cross-channel collaborative management unit 600 is used to perform at least two levels of graded protection on each of the drive channels 310 according to the load status. The graded protection response maintains an independent fault level state machine for each drive channel 310. The state machine includes four states: normal operation, early warning, soft shutdown, and hard fault. The protection action intensity of each state increases progressively.

[0077] Under normal operating conditions, the output limiting parameters of the drive channel 310 are not subject to fault protection restrictions, but are only constrained by the power budget and thermal estimation of the collaborative decision engine 620. When the load state determination result is stalled or gradual overload, or when the collaborative thermal estimation generates a thermal warning flag, the fault level state machine transitions from the normal operating state to the warning state. In the warning state, the output limiting parameters of this channel are forcibly reduced, exemplarily to [a lower value]. Simultaneously, an early warning frame is sent to the external controller via the communication and configuration unit 500. If the load state returns to normal operation and the thermal early warning flag of the collaborative thermal estimation is eliminated during the early warning state, the fault level state machine automatically returns from the early warning state to the normal operation state, and the output limiting parameters of this channel are no longer subject to fault protection constraints.

[0078] If the warning status continues for more than the preset duration threshold If the load condition does not return to normal, the fault level state machine transitions from the warning state to the soft shutdown state. In the soft shutdown state, the output limiting parameter of the channel drops to zero, the corresponding pulse width modulation output is cleared, and the motor M stops. However, the nSLEEP enable pin of the integrated driver chip 320 remains high to maintain the chip's online monitoring status. The communication and configuration unit 500 sends a shutdown frame to notify the external controller. In the soft shutdown state, the collaborative decision engine 620 continues to perform thermal estimation updates on the channel. When the estimated junction temperature drops below the thermal warning threshold and the external controller or host computer sends a recovery command, the fault level state machine transitions from the soft shutdown state back to the normal operation state. For example, Usually in to Within the scope, this embodiment takes .

[0079] When the integrated driver chip 320 of any of the drive channels 310 triggers an nFAULT hardware interrupt, the fault level state machine immediately transitions from any current state to a hard fault state. The nFAULT interrupt is the highest priority external interrupt, with a higher priority than the timer interrupt of the collaborative decision engine 620, ensuring that the hardware fault response is not blocked by the collaborative decision calculation. The interrupt service routine immediately disables the pulse width modulation output of the channel and sets the output limit parameter of the channel to zero, while simultaneously recording the fault event to the fault log buffer. The collaborative decision engine 620 in the next... After periodically reading the hard fault flag of the channel in the CSAT, subsequent processing is performed, including triggering cross-channel power reallocation and sending the highest priority fault frame through the communication and configuration unit 500. The fault log buffer is a circular buffer that stores the most recent faults. Each fault event record includes a timestamp, channel number, fault type, and current value at the time of the fault. In a hard fault state, the fault level state machine can only transition back to normal operation after a reset command is sent by an external controller or host computer and the nFAULT pin returns to a high level.

[0080] The tiered protection response also includes cross-channel collaborative protection functionality. When a channel transitions from normal operation to a soft shutdown or hard fault state, the power originally consumed by that channel is released. The collaborative decision engine 620 then... The system periodically recalculates its available power margin and redistributes the released power to the remaining normally operating drive channels 310 according to power budget rules, thereby relaxing the power dimension constraints of their output limiting parameters accordingly. This cross-channel power redistribution mechanism avoids system-level cascading failures caused by a single channel failure, ensuring that the operation of the remaining normal channels is not affected by the failed channel.

[0081] For example, when the second channel motor M stalls, the complete protection timing sequence is as follows. At that time, the second channel was operating normally, and the current... .exist At that time, the load suddenly increased. Rise to .exist At that time, the load status determination indicates that the second channel is in a stalled state. The fault level state machine transitions from normal operation to warning state. Down to Simultaneously, a warning frame is sent. At that time, the continuous warning exceeded If the fault is not resolved, the fault level state machine transitions to a soft shutdown state. Down to The pulse width modulation output of channel 2 is cleared to zero, and motor M stops. The power released by channel 2... Returning to the power budget pool, the power constraints of the remaining channels are relaxed accordingly.

[0082] The status reporting function of the communication and configuration unit 500 is periodically triggered by the 7th basic timer of the main control processing unit 200. The 7th basic timer generates an interrupt with a configurable reporting period. The interrupt service routine reads the current value, speed value, load status, fault level, and estimated junction temperature of each drive channel 310 from the CSAT, and packages the above data into multiple CAN data frames according to the message arrangement rules of the CAN bus communication interface, sending them sequentially to the external controller. Within each reporting period, the status reporting sequentially sends current frames, speed frames, system status frames, and load fault frames, carrying the physical quantity data and logical status data of each drive channel 310, respectively. The transmission of fault event frames is not constrained by periodic reporting. When the fault level of any drive channel 310 changes, the communication and configuration unit 500 immediately sends a fault event frame, which uses the highest priority message identifier to ensure priority transmission in CAN bus arbitration. The status reporting period is typically... to Within the scope, this embodiment takes .

[0083] The communication and configuration unit 500 also supports remote online configuration of operating parameters. When the FDCAN peripheral receives a configuration command frame, the main control processing unit 200 performs corresponding parameter modification operations according to the configuration type field. Configurable parameters include, but are not limited to: closed-loop control parameters, current limit threshold, load state discrimination threshold, thermal management parameters, channel priority, and device identifier. The remote configuration parameter writing process consists of two steps: first, the received parameter values ​​are validated for legality, including determining whether the parameter values ​​are within a preset legal range and whether there are logical contradictions between parameters. After successful validation, the parameters are written to random access memory and take effect immediately; then, the parameters are written to non-volatile memory to retain the configuration upon the next power-on. The non-volatile memory writing adopts a sector-based erase and write method. The main control processing unit 200 centrally stores all configurable parameters in a designated parameter area of ​​the non-volatile memory. Before each write, the sector containing the parameter area is erased, and then the entire parameter image in the random access memory is written. The starting position of the parameter area stores a checksum field. When the system powers on, the checksum is used to verify parameter integrity. If the checksum does not match, preset default parameters are loaded, and a parameter recovery event is reported through the communication and configuration unit 500. For example, the proportional gain of the closed-loop control parameters... The legal scope is Integral gain The legal scope is Configuration values ​​outside the specified range are rejected and an error response is returned. Equivalent thermal resistance in thermal management parameters. The legal scope is Heat warning threshold It must be less than the overheat shutdown threshold. Otherwise, the configuration will be rejected.

[0084] Upon receiving motion commands from each of the drive channels 310, the integrated multi-channel motor drive system executes corresponding control algorithms according to the control mode by the motor drive control module. Before executing the control algorithm, the motor drive control module first checks the start-up permission flag of the corresponding channel in the CSAT. Only when The channel is only allowed to transition from a stopped state to a running state when the off-peak start scheduling has not yet released the start permission for the channel, and will wait until the next control cycle to check again. The control modes include position mode, speed mode, and open-loop mode.

[0085] In position mode, the position feedback is provided by the encoder feedback unit 400. As input, with target location The difference between the actual position and the position is used as the position error, and the duty cycle increment for the current cycle is calculated by an incremental proportional-integral-derivative (PID) controller. The incremental PID controller operates in each main control cycle. Within this period, the duty cycle increment is calculated based on the difference between the current error and the errors of the previous two periods. This duty cycle increment includes a proportional term, an integral term, and a differential term. The sum of these three terms is added to the duty cycle of the previous period to obtain the original duty cycle of the current period. When the original duty cycle When the effective range is exceeded, the controller performs anti-integral saturation processing, pausing the accumulation of the integral term to prevent overshoot. In speed mode, the speed feedback is provided by the encoder feedback unit 400. As input, with target speed The difference between the actual and actual speeds is used as the speed error, and the duty cycle increment is calculated using an incremental proportional-integral-derivative (PID) controller. In open-loop mode, the target duty cycle is directly written into the pulse width modulation (PWM) comparator register, and closed-loop control is not executed. The original duty cycle calculated by the closed-loop controller... Multiplied by the power limitation factor Obtain the actual output duty cycle Write the corresponding advanced timer compare register. The power limiting factor... The introduction of this feature enables the cross-channel resource scheduling results of the collaborative decision engine 620 to directly constrain the actual output power of each drive channel 310, achieving closed-loop linkage from collaborative decision-making to drive execution. The direction signal is determined by the sign of the position error or the sign of the target speed, controlling the PH pin of the integrated drive chip 320 to determine the rotation direction of the motor M.

[0086] In one embodiment, the output limiting parameter can also be achieved by adjusting the current limiting reference voltage on the VREF pin of the integrated driver chip 320. The current limiting reference voltage on the VREF pin determines the trigger threshold of the internal current chopper circuit of the integrated driver chip 320. When the collaborative decision engine 620 needs to reduce the output power of a certain drive channel 310, it lowers the reference voltage on the VREF pin of that channel, causing the hardware current chopper of the integrated driver chip 320 to trigger at a lower current threshold, thereby limiting the maximum load current of that channel. The VREF reference voltage is generated by the pulse width modulation output of the main control processing unit 200 after being filtered by an RC low-pass filter. The value of the VREF reference voltage can be changed by adjusting the pulse width modulation duty cycle. This method is similar to the aforementioned method of adjusting the upper limit coefficient of the pulse width modulation duty cycle. The methods for achieving power limiting are independent of each other and can be used individually or in combination depending on the application scenario.

[0087] The working process of the integrated multi-channel motor drive system provided in this application embodiment can be summarized as follows. After the system is powered on, the main control processing unit 200 executes the initialization process, sequentially completing clock configuration, power supply voltage detection, peripheral initialization, device identification determination, loading of operating parameters from non-volatile memory, clearing of CSAT, wake-up and health check of the integrated driver chip 320 of each drive channel 310, and start-up of the timer of the collaborative decision engine 620. During the wake-up and health check process, the main control processing unit 200 sequentially pulls up the nSLEEP enable pin corresponding to each drive channel 310 to wake up the integrated driver chip 320. After waiting for the wake-up time, it checks whether the nFAULT pin of the channel is high to confirm that the driver chip has no power-up fault. At the same time, it samples the detection signal of the channel in the state where the motor M is not driven to confirm that its baseline value is within the normal range. Channels that pass the health check are marked as available, and channels that fail are marked as disabled. Disabling a channel does not affect the normal operation of the other channels. After initialization is completed, the system enters the normal operation state.

[0088] The communication and configuration unit 500 receives external motion commands and writes them into the CSAT. The collaborative decision engine 620 uses... The system periodically reads the detection signals from all channels in the CSAT, performs four decision-making processes: collaborative thermal estimation, power budget balancing, load condition discrimination, and graded fault protection, and adjusts the power limiting coefficient of each channel. and startup license Write back to the CSAT. The read / write operations of the CSAT utilize an interrupt masking mechanism to protect critical sections. When the direct memory access transfer of the analog-to-digital converter completes and requires writing new detection signal data to the CSAT, the timer interrupt of the collaborative decision engine 620 is temporarily masked to prevent read / write conflicts. The timer interrupt is immediately restored after the data is written. Since each write involves only a few memory units, the duration of the critical section is on the order of microseconds, which does not affect the system's real-time performance. The motor drive control module reads the power limiting coefficient. The signal is multiplied by the output of the closed-loop controller and then output as a pulse width modulation signal to each of the integrated driver chips 320. The communication and configuration unit 500 periodically reads all the status data in the CSAT and reports it via the CAN bus.

[0089] This application also provides a computer-readable storage medium storing a computer program thereon. When executed by a processor, the computer program implements the functions of the collaborative decision engine 620, the load state discrimination module, and the graded protection response module in the aforementioned integrated multi-channel motor drive system. The computer-readable storage medium includes, but is not limited to, flash memory, read-only memory, or erasable programmable read-only memory.

[0090] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit described above can be implemented in hardware.

[0091] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any changes or substitutions within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. An integrated multi-channel motor drive system with cross-channel collaborative management function, comprising a main control processing unit and multiple drive channels connected to the main control processing unit, each drive channel comprising an integrated drive chip for driving a motor and outputting a detection signal, characterized in that, The system also includes: A multi-channel state aggregation structure configured in the main control processing unit is used to collect the detection signals of each of the driving channels; The collaborative decision engine configured in the main control processing unit is used to perform cross-channel resource scheduling based on the detection signals in the multi-channel state aggregation structure in order to determine the output limit parameters of each driving channel. The load status determination module is used to determine the load status based on the statistical characteristics of the detection signals of each drive channel; And a graded protection response module, used to perform at least two levels of graded protection on each of the drive channels according to the load status.

2. The system according to claim 1, characterized in that, The cross-channel resource scheduling includes: estimating the thermal state of each driving channel based on the historical values ​​of the detection signals of each driving channel; and reducing the output limiting parameters of the corresponding driving channel when the thermal state exceeds a preset threshold.

3. The system according to claim 2, characterized in that, The step of estimating the thermal state of each driving channel based on the historical values ​​of the detection signals of each driving channel includes: determining the estimated junction temperature of each driving channel based on the exponential weighted accumulation of the squared values ​​of the detection signals of each driving channel.

4. The system according to claim 1, characterized in that, The cross-channel resource scheduling also includes: when multiple drive channels request to start simultaneously, releasing the start permits of each drive channel in sequence according to preset rules.

5. The system according to claim 1, characterized in that, The cross-channel resource scheduling further includes: calculating the total power of each of the drive channels, and when the total power exceeds a preset proportion of the system power budget, performing a proportional reduction on the output limit parameters of all the drive channels.

6. The system according to claim 1, characterized in that, The step of determining the load state based on the statistical characteristics of the detection signals of each of the driving channels includes: determining whether each of the driving channels is in at least one abnormal load state based on the mean and variability of the detection signals within a sliding window.

7. The system according to claim 1, characterized in that, The graded protection includes: Channel-level protection is used to reduce the output limit parameter of the drive channel when the load state of the drive channel is abnormal. Cross-channel collaborative protection is used to redistribute the power margin released by the drive channel to the other drive channels when the drive channel enters the shutdown protection.

8. The system according to claim 1, characterized in that, The system also includes a communication unit, which is used to receive external control commands and report the operating status of each drive channel.

9. The system according to claim 8, characterized in that, The communication unit is also used to receive remote configuration parameters, which are then verified and written into a non-volatile memory.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the functions of the collaborative decision engine, the load status discrimination module, and the hierarchical protection response module in the system described in any one of claims 1 to 9.

Images