A closed loop control circuit

Abstract

The application discloses a closed-loop control circuit, relates to the technical field of motor driving control, and aims to solve the technical problems of large chip layout area occupation and high manufacturing cost caused by independently configuring DACs for each phase of a motor. The closed-loop control circuit provided by the application is controlled by a state machine, so that a single DAC receives target current digital quantities of two phases in time and converts the target current digital quantities into reference voltages; a sample-and-hold circuit holds the reference voltages and actual feedback voltages to a target comparator, and three comparators work in rotation, so that two comparators provide current effective comparison results of two phases at any moment, and the other comparator waits to perform comparison of the corresponding phase in the next round; and an output selection circuit determines the effective comparison results and outputs continuous comparison feedback voltages. Finally, the single DAC cooperated with the sample-and-hold circuit and the three comparators replace the traditional multi-DAC scheme, the closed-loop control precision is ensured, the area of the chip is reduced, and the manufacturing cost is lowered.

Description

Technical Field

[0001] This invention relates to the field of motor drive control technology, and in particular to a closed-loop control circuit. Background Technology

[0002] In the field of motor drives, feedback signals are typically used to adjust the control signals of each phase in real time. Taking a two-phase stepper motor as an example, the stepper motor includes A-phase and B-phase windings, and the digital control module is connected to the motor through the drive circuit. During the closed-loop control of the current in the A-phase and B-phase windings, the digital control module adjusts the operating state of the drive circuit based on the target current digital value to adjust the current in the A-phase and B-phase windings. Specifically, the digital control module outputs the target current digital value to a digital-to-analog converter (DAC) to convert the target current digital value into a corresponding analog reference voltage. Subsequently, a comparator compares the analog reference voltage with the actual feedback voltage on the motor windings, and adjusts the operating state of the drive circuit according to the comparison result, so that the actual current in the A-phase and B-phase windings follows the target current change, thereby achieving closed-loop control.

[0003] To maintain continuous closed-loop regulation for each phase, existing technologies typically employ independent conversion and comparison paths for different control channels. For example, two independent DACs and two comparators are configured for phases A and B. The two DACs continuously receive the target current digital values ​​for phases A and B, respectively, and output continuous reference voltages for phases A and B. The two comparators then continuously compare these reference voltages with the actual feedback voltages for phases A and B. However, in chip layout design, DACs are analog circuits, and their chip area is typically significantly larger than that of ordinary digital logic circuits and comparators. The aforementioned approach, requiring multiple independent DACs to maintain reference voltages across multiple channels, drastically increases the overall chip layout area, leading to a significant increase in manufacturing costs. Summary of the Invention

[0004] The purpose of this invention is to provide a closed-loop control circuit to solve the technical problem that, in maintaining continuous closed-loop regulation of multi-phase loads, the need to independently configure analog DACs for each phase leads to an excessively large overall chip layout area and a significant increase in manufacturing costs.

[0005] To solve the above-mentioned technical problems, the present invention provides a closed-loop control circuit for a motor, including a DAC, three comparators, a sample-and-hold circuit, an output selection circuit, and a state machine; The DAC is connected to a state machine to receive the target current digital values ​​of the first phase and the second phase in a time-division multiplexing manner, and convert them into the corresponding first reference voltage and second reference voltage. The sample-and-hold circuit is connected to the output of the DAC, the winding current feedback voltage input of the motor, the state machine, and the input of the three comparators. Under the control of the state machine, it acquires the reference voltage output by the DAC and the actual feedback voltage corresponding to the reference voltage, holds them, and sends them to the two target comparators corresponding to the current cycle among the three comparators, so that the target comparators can compare the held reference voltage and the actual feedback voltage. Three comparators are used in turn under the control of the state machine to perform the comparison of the first phase, the comparison of the second phase, and the comparison of the corresponding phase waiting to be executed in the next round. In any round, two comparators serve as target comparators and are used to perform the comparison of the first and second phases of the current round, respectively, while the other comparator is used to wait to perform the comparison of the corresponding phase in the next round. The output selection circuit is connected to the output terminals of the state machine and the three comparators respectively. Under the control of the state machine, it determines the current valid comparison result of the first phase and the current valid comparison result of the second phase according to the comparison results of the two target comparators, and outputs the first comparison feedback voltage of the first phase and the second comparison feedback voltage of the second phase to the state machine.

[0006] Optional, also includes: The input selection circuit has a first input terminal for receiving the target current digital value of the first phase, a second input terminal for receiving the target current digital value of the second phase, an output terminal connected to a DAC, and a control terminal connected to a state machine. Under the control of the state machine, the target current digital values ​​of the first phase and the second phase are output to the DAC in a time-division manner.

[0007] Optionally, the sample-and-hold circuit includes a reference sample-and-hold branch and a feedback sample-and-hold branch, which are configured one-to-one with each comparator; The reference sample-and-hold branch includes a reference sampling switch and a reference holding capacitor: The first terminal of the reference sampling switch is connected to the output terminal of the DAC, the second terminal is connected to the first terminal of the reference holding capacitor, and the control terminal is connected to the state machine. When the switch is turned on under the control of the state machine, the reference voltage output by the DAC is input to the reference holding capacitor. The first terminal of the reference holding capacitor is connected to the second terminal of the reference sampling switch, and the second terminal is connected to the first input terminal of the corresponding comparator, which is used to hold the sampled reference voltage after the reference sampling switch is turned off. The feedback sample-and-hold branch includes a first feedback sampling switch, a second feedback sampling switch, and a feedback hold capacitor: The first terminal of the first feedback sampling switch is connected to the winding current feedback voltage input terminal of the first phase of the motor, the second terminal is connected to the first terminal of the feedback holding capacitor, and the control terminal is connected to the state machine. When the switch is turned on under the control of the state machine, the actual feedback voltage of the first phase is input to the feedback holding capacitor. The first terminal of the second feedback sampling switch is connected to the winding current feedback voltage input terminal of the second phase of the motor, the second terminal is connected to the first terminal of the feedback holding capacitor, and the control terminal is connected to the state machine. When the switch is turned on under the control of the state machine, the actual feedback voltage of the second phase is input to the feedback holding capacitor. The first end of the feedback holding capacitor is connected to the second end of the first feedback sampling switch and the second end of the second feedback sampling switch, respectively. The second end is connected to the second input of the corresponding comparator, which is used to hold the actual feedback voltage obtained by sampling after the corresponding feedback sampling switch is turned off.

[0008] Optionally, the reference sampling switch, the first feedback sampling switch, and the second feedback sampling switch are all CMOS gates; A CMOS gate includes a non-inverting control terminal and an inverting control terminal, both of which are connected to a state machine. They are used to receive the non-inverting control voltage and the inverting control voltage output by the state machine, respectively, so as to turn on or off under the drive of the non-inverting control voltage and the inverting control voltage.

[0009] Optionally, it may also include a first inverter and a second inverter; The input of the first inverter is connected to a state machine to output an inverting control voltage; The input terminal of the second inverter is connected to the output terminal of the first inverter to output a non-inverting control voltage.

[0010] Optionally, each of the three comparators includes an operational amplifier, a first CMOS gate, and an AND gate; The non-inverting input of the operational amplifier is connected to the second terminal of the corresponding reference holding capacitor, and the inverting input is connected to the second terminal of the corresponding feedback holding capacitor. The first CMOS gate is connected between the inverting input and output of the operational amplifier, and the control gate is connected to the state machine to be turned on under the control of the state machine to reset the operational amplifier. The first input of the AND gate is connected to the output of the operational amplifier, the second input is connected to the state machine, and the output is connected to the output selection circuit. Under the control of the state machine, the output of the operational amplifier is shielded during the conduction of the first CMOS gate to prevent invalid comparison results from being output to the output selection circuit.

[0011] Optionally, the reference sample-and-hold branch may also include a second CMOS gate, a third CMOS gate, and a voltage regulator capacitor; The first terminal of the second CMOS gate is connected to an analog reference voltage, the second terminal is connected to the first terminal of the reference holding capacitor, and the control terminal is connected to the state machine. The first terminal of the third CMOS gate is connected to the analog reference voltage, the second terminal is connected to the second terminal of the reference holding capacitor, and the control terminal is connected to the state machine; the second CMOS gate and the third CMOS gate are used to conduct under the control of the state machine to clamp the voltage across the reference holding capacitor to the analog reference voltage. The first terminal of the voltage regulator capacitor is connected to the second terminal of the reference holding capacitor, and the second terminal is grounded.

[0012] Optionally, the feedback sample-and-hold branch may also include a fourth CMOS gate and a fifth CMOS gate; The first terminal of the fourth CMOS gate is connected to the first terminal of the feedback holding capacitor, the second terminal is grounded, and the control terminal is connected to the state machine. It is used to turn on under the control of the state machine to discharge and clear the first terminal of the feedback holding capacitor. The first terminal of the fifth CMOS gate is connected to the common output terminal of the first feedback sampling switch and the second feedback sampling switch, the second terminal is connected to the first terminal of the feedback holding capacitor, and the control terminal is connected to the state machine. It is used to turn on or off under the control of the state machine to control the on / off state of the input circuit of the actual feedback voltage obtained by sampling to the feedback holding capacitor.

[0013] Optionally, the output selection circuit includes a first multiplexer and a second multiplexer: The multiple inputs of the first multiplexer are connected to the outputs of three comparators respectively, and the control terminal is connected to a state machine. Under the control of the state machine, the current valid comparison result of the first phase is selected from the comparison results of the three comparators, and the first comparison feedback voltage is output based on the current valid comparison result of the first phase. The multiple inputs of the second multiplexer are connected to the outputs of the three comparators, and the control terminal is connected to the state machine. Under the control of the state machine, the current valid comparison result of the second phase is selected from the comparison results of the three comparators, and the second comparison feedback voltage is output based on the current valid comparison result of the second phase.

[0014] Optional, also includes: The digital chopper circuit has its input terminal connected to the output terminal of the output selection circuit. It is used to receive the first comparison feedback voltage and the second comparison feedback voltage respectively, and output the chopper drive voltage of the corresponding phase. The drive circuit has its input terminal connected to the output terminal of the digital chopper circuit, and its output terminal connected to the first phase winding and the second phase winding of the motor, respectively. The drive circuit contains multiple switching transistors, which are used to turn on or off under the action of the chopper drive voltage to adjust the current in the first phase winding and the second phase winding, respectively.

[0015] This invention provides a closed-loop control circuit, including a state machine, a DAC, a sample-and-hold circuit, three comparators, and an output selection circuit. Through timing control of the state machine, a single DAC receives the target current digital quantities of the first and second phases in a time-sharing manner and converts them into corresponding first and second reference voltages. Furthermore, the sample-and-hold circuit physically holds the time-sharing output reference voltages and corresponding actual feedback voltages to the target comparator. The three comparators establish a rotating operating state, ensuring that at any given time, two comparators continuously provide the current valid comparison results for the first and second phases, while the third comparator waits to perform the next round of comparison for the corresponding phase. Finally, the output selection circuit determines the valid comparison result to output continuous first and second comparison feedback voltages to the state machine, thereby overcoming the discontinuous regulation problem caused by single DAC multiplexing and ensuring the stability and reliability of the closed-loop control. As can be seen, the closed-loop control circuit provided by the present invention, by introducing a sample-and-hold circuit and an additional comparator that occupy a smaller chip layout area, can replace multiple independent analog DACs in the traditional scheme with a single DAC. This effectively reduces the overall layout area of ​​the chip without affecting the closed-loop control accuracy, and significantly reduces the chip manufacturing cost. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings used in the prior art and embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 A structural diagram of a closed-loop control circuit provided by the present invention; Figure 2 A structural diagram of another closed-loop control circuit provided by the present invention; Figure 3 A timing waveform diagram for a DAC time-division multiplexing provided by the present invention; Figure 4 A structural diagram of another closed-loop control circuit provided by the present invention; Figure 5 A structural diagram of a sample-and-hold circuit provided by the present invention; Figure 6 A structural diagram of an output selection circuit provided by the present invention; Figure 7 A structural diagram of a digital chopper circuit and a driving circuit provided by the present invention; Figure 8 A chopper state diagram of a digital chopper circuit provided by the present invention; Figure 9 A timing diagram of a closed-loop control circuit provided by the present invention; Figure 10 The waveforms of motor current and feedback voltage in the closed-loop control circuit provided by this invention are shown. Detailed Implementation

[0018] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0019] This invention provides a closed-loop control circuit for a motor, such as... Figure 1 As shown, Figure 1 The present invention provides a structural diagram of a closed-loop control circuit. This closed-loop control circuit includes a DAC2, three comparators, a sample-and-hold circuit 3, an output selection circuit 7, and a state machine 1. DAC2 is connected to state machine 1 and is used to receive the target current digital quantity of the first phase and the target current digital quantity of the second phase in a time-division manner, and convert them into the corresponding first reference voltage and second reference voltage. The sample-and-hold circuit 3 is connected to the output of DAC2, the winding current feedback voltage input of the motor, the state machine 1, and the input of the three comparators. Under the control of the state machine 1, it acquires the reference voltage output by DAC2 and the actual feedback voltage corresponding to the reference voltage and holds it. It then sends the data to the two target comparators corresponding to the current cycle among the three comparators so that the target comparators can compare the held reference voltage and the actual feedback voltage. Three comparators are used, under the control of state machine 1, to take turns comparing the first phase, comparing the second phase, and waiting to compare the corresponding phase in the next round. In any round, two comparators serve as target comparators, used to compare the first and second phases of the current round, respectively, while the other comparator waits to compare the corresponding phase in the next round. The output selection circuit 7 is connected to the output terminals of state machine 1 and the three comparators, respectively. Under the control of state machine 1, it determines the current valid comparison result of the first phase and the current valid comparison result of the second phase based on the comparison results of the two target comparators, and outputs the corresponding first comparison feedback voltage and second comparison feedback voltage to state machine 1.

[0020] Specifically, this embodiment introduces a state machine 1 within the digital control module to control the overall timing of the closed-loop control circuit. Under the control of state machine 1, a single DAC performs time-division multiplexing, alternately receiving multi-bit target current digital quantities of the first and second phases, and converting them into corresponding first and second reference voltages, respectively. Subsequently, the sample-and-hold circuit 3 acquires and holds the reference voltage output from DAC 2 (time-division multiplexing) and the corresponding actual feedback voltage output from the motor, and sends them to the two target comparators currently in the comparison cycle. The first comparator 4, the second comparator 5, and the third comparator 6 operate in rotation under the scheduling of state machine 1, ensuring that in any given cycle, two comparators always act as target comparators, comparing the first and second phases and outputting the comparison results, while the remaining comparator is in a reset or sampling phase, waiting to execute the next round of comparison. For example, in a certain working cycle, the first comparator 4 performs the comparison of the first phase, the second comparator 5 performs the comparison of the second phase, and the third comparator 6 is in the reset or sampling stage. In the next working cycle, the third comparator 6 completes the reset and sampling successively, and begins to perform the comparison of the first phase. At this time, the first comparator 4 switches to perform the comparison of the second phase, while the second comparator 5 enters the reset or sampling stage. Finally, the output selection circuit 7 extracts the currently valid comparison results of the first and second phases from the three comparators. Since the valid comparison results of the first and second phases are obtained without interruption throughout the time axis during the above comparator switching process, a continuous first comparison feedback voltage and second comparison feedback voltage can be spliced ​​and output.

[0021] Furthermore, the comparison feedback voltage is fed back to the digital control module for use as an external closed-loop drive. For example, the chopping state of the subsequent digital chopper circuit is switched according to the feedback signal, thereby controlling the switching of the power transistor in the drive circuit so that the actual current of the motor is maintained at the value corresponding to the target reference voltage.

[0022] It should be noted that although using a single DAC for time-division multiplexing will result in time-division switching in the transmission path, the channel switching frequency of the time-division output of DAC2 controlled by state machine 1 is much higher than the fundamental frequency corresponding to the two-phase target current of the motor. Furthermore, this embodiment uses a sample-and-hold circuit 3 to ensure that the reference voltage and the actual feedback voltage maintain stable voltage values ​​for a period of time before being input to the operational amplifier inside the comparator. Therefore, with the rotation of the three comparators, this embodiment can ensure that any input has a corresponding comparator for comparison at any time, overcoming the signal dispersion defects caused by time-division multiplexing of single-channel analog devices and meeting the closed-loop control accuracy requirements of the motor.

[0023] Furthermore, the aforementioned digital control module and its internal state machine 1 can actually be implemented using purely hardware digital circuits, such as D flip-flops and logic gates, which trigger the parallel output of control commands via a clock signal. Compared to using a microcontroller or software code to implement time-sharing control, digital circuits not only offer faster response times and no instruction cycle delays, but also avoid the complexity of software implementation. Simultaneously, the increased chip layout area is smaller compared to that occupied by a DAC, thus significantly reducing the overall chip layout area.

[0024] As can be seen, the closed-loop control circuit provided in this embodiment utilizes the timing control of state machine 1 and the hardware coordination of sample-and-hold circuit 3 and three comparators to replace the traditional dual-DAC architecture with a single DAC. While maintaining the closed-loop control accuracy and continuity of each phase, it reduces the chip layout area and lowers the overall hardware manufacturing cost.

[0025] Based on the above embodiments: As an optional embodiment, such as Figure 2 As shown, Figure 2 A structural diagram of another closed-loop control circuit provided by the present invention. This closed-loop control circuit further includes: Input selection circuit 8 has a first input terminal for receiving the target current digital value of the first phase, a second input terminal for receiving the target current digital value of the second phase, an output terminal connected to DAC2, and a control terminal connected to state machine 1. Under the control of state machine 1, it outputs the target current digital values ​​of the first phase and the target current digital values ​​of the second phase to DAC2 in a time-division manner.

[0026] In traditional dual-DAC closed-loop control circuits for stepper motors, the target current digital values ​​of the first and second phases are input to their respective DACs via independent data buses. However, this embodiment uses a single DAC. Since it only has one common digital-to-analog conversion input port, directly connecting the digital transmission buses of the two phases would lead to digital signal level conflicts and logic errors.

[0027] Based on this, an input selection circuit 8 is added in this embodiment. Specifically, the first input terminal and the second input terminal of the input selection circuit 8 continuously receive the target current digital value of the first phase and the target current digital value of the second phase, respectively. Figure 3 As shown, Figure 3This invention provides a timing waveform diagram for a time-division multiplexed DAC. State machine 1 outputs an alternating selection signal DAC_AB_choc to the control terminal of input selection circuit 8 according to the current time-division working sequence. Input selection circuit 8 performs channel switching based on this selection signal DAC_AB_choc: in the first phase transition, it connects the first input terminal and the output terminal, inputting the target current digital quantity of the first phase to DAC2; in the second phase transition, it connects the second input terminal and the output terminal, inputting the target current digital quantity of the second phase to DAC2. Through the above process, time-division multiplexing transmission of two digital signals to a single DAC input port is achieved.

[0028] It should be noted that, as Figure 4 As shown, Figure 4 This is a structural diagram of another closed-loop control circuit provided by the present invention. The target current digital quantity input to DAC2 is typically a multi-bit parallel digital signal (i.e., composed of multiple data lines, each carrying a specific high or low level). Accordingly, the above-mentioned input selection circuit 8 can be specifically implemented using a 2-to-1 multiplexer in digital logic circuits. Using a 2-to-1 multiplexer enables synchronous and seamless switching of multiple parallel data ports under the control of the state machine 1 selection signal DAC_AB_choc. Since it is a pure digital gate circuit structure, the channel switching response speed is synchronized with the output clock of state machine 1, and no physical delay in data transmission is generated, thus providing a reliable data source for the subsequent accurate output of the first reference voltage or the second reference voltage by DAC2.

[0029] As can be seen, this embodiment solves the problem of time-sharing input of the digital quantity of the two-phase target current by introducing the input selection circuit 8 and using the data selector in conjunction with the timing control of the state machine 1, thus avoiding data conflicts and providing a data foundation for the stable operation of the closed-loop control circuit of the single DAC.

[0030] As an optional embodiment, such as Figure 5 As shown, Figure 5 This invention provides a structural diagram of a sample-and-hold circuit. The sample-and-hold circuit 3 includes a reference sample-and-hold branch and a feedback sample-and-hold branch, each corresponding to one of the comparators. The reference sample-and-hold branch includes the reference sampling switch K1 and the reference holding capacitor C1: The first terminal of the reference sampling switch K1 is connected to the output terminal of DAC2, the second terminal is connected to the first terminal of the reference holding capacitor C1, and the control terminal is connected to state machine 1. When the switch is turned on under the control of state machine 1, the reference voltage output by DAC2 is input to the reference holding capacitor C1. The first terminal of the reference holding capacitor C1 is connected to the second terminal of the reference sampling switch K1, and the second terminal is connected to the first input terminal of the corresponding comparator, which is used to hold the sampled reference voltage after the reference sampling switch K1 is turned off. The feedback sample-and-hold branch includes a first feedback sampling switch K2, a second feedback sampling switch K3, and a feedback holding capacitor C2. The first terminal of the first feedback sampling switch K2 is connected to the winding current feedback voltage input terminal of the first phase of the motor, the second terminal is connected to the first terminal of the feedback holding capacitor C2, and the control terminal is connected to the state machine 1. When the switch is turned on under the control of the state machine 1, the actual feedback voltage of the first phase is input to the feedback holding capacitor C2. The first end of the second feedback sampling switch K3 is connected to the winding current feedback voltage input terminal of the second phase of the motor, the second end is connected to the first end of the feedback holding capacitor C2, and the control terminal is connected to the state machine 1. When the switch is turned on under the control of the state machine 1, the actual feedback voltage of the second phase is input to the feedback holding capacitor C2. The first end of the feedback holding capacitor C2 is connected to the second end of the first feedback sampling switch K2 and the second end of the second feedback sampling switch K3, respectively. The second end is connected to the second input of the corresponding comparator, which is used to hold the actual feedback voltage obtained by sampling after the corresponding feedback sampling switch is turned off.

[0031] In a closed-loop control circuit using a single DAC with time-division multiplexing, DAC2 can only output the reference voltage of one phase at a time. When DAC2 switches to output the reference voltage of another phase, the reference voltage input of the previous phase is disconnected. If the input of the comparator is directly connected to the output of DAC2, as the input selection circuit switches the input channel time-division, DAC2 will alternately output reference voltages of different phases. This will cause the voltage at the comparator input to become discontinuous and abrupt, resulting in the comparator being unable to obtain a stable comparison result throughout the entire control cycle.

[0032] Based on this, this embodiment independently configures a reference sample-and-hold branch and a feedback sample-and-hold branch for each comparator. Specifically, when DAC2 outputs the first reference voltage of the first phase, state machine 1 controls the reference sampling switch K1 of the corresponding comparator to turn on, charging the reference holding capacitor C1; after the sampling sequence ends, the reference sampling switch K1 turns off, and the reference holding capacitor C1 holds the first reference voltage across its terminals based on the charge it stores. Similarly, state machine 1 controls the first feedback sampling switch K2 to turn on according to the current phase sequence, charging the feedback holding capacitor C2 with the actual feedback voltage of the first phase of the motor, and then turns it off to maintain the voltage. Through the above on and off actions, the current comparator can perform a stable voltage comparison using the voltage values ​​held on the two holding capacitors.

[0033] It should be noted that, combined with the timing control logic of state machine 1, state machine 1 can output independent and parallel control voltages to each control terminal to control the on / off state of the aforementioned switches. For the feedback sample-and-hold branch, state machine 1 can switch the actual feedback voltage signal that needs to be injected into the feedback holding capacitor C2 by adjusting the high and low level states of the voltage output to the control terminal. For example, a high level can correspond to the first feedback sampling switch K2 being turned on to sample the first phase, and a low level can correspond to the second feedback sampling switch K3 being turned on to sample the second phase. In addition, by utilizing the physical characteristic of capacitors storing charge for voltage holding, the discrete analog quantity of the transient output of DAC2 can be converted into a relatively smooth holding voltage, providing ample comparison time for the comparator, thereby ensuring that a single DAC can also achieve seamless switching of multiple channels.

[0034] As can be seen, this embodiment introduces a sample-and-hold circuit 3 that combines a controlled switch with a capacitor to convert the discrete voltage output by DAC2 in a time-division multiplexing manner into a stable holding voltage at the input of the comparator. This effectively solves the signal discontinuity problem caused by the multiplexing of the analog converter and provides reliable physical hardware support for the independent and stable operation of each comparator.

[0035] As an optional embodiment, the reference sampling switch K1, the first feedback sampling switch K2, and the second feedback sampling switch K3 are all CMOS gates; The CMOS gate includes a non-inverting control terminal and an inverting control terminal, both of which are connected to state machine 1. They are used to receive the non-inverting control voltage U2 and the inverting control voltage U1 output by state machine 1, respectively, so as to turn on or off under the drive of the non-inverting control voltage U2 and the inverting control voltage U1.

[0036] In the analog voltage sample-and-hold circuit 3, due to the inherent threshold voltage drop characteristic of semiconductor devices, signal attenuation occurs when transmitting analog voltages close to high-level power supplies or low-level ground potentials. This voltage transmission attenuation introduced by the switching elements will cause errors in the reference voltage or actual feedback voltage sampled on the holding capacitor, thus affecting the accuracy of the comparator's judgment.

[0037] Based on this, the reference sampling switch K1, the first feedback sampling switch K2, and the second feedback sampling switch K3 in this embodiment are all implemented using CMOS gates. A CMOS gate, or CMOS transmission gate, is typically composed of a PMOS transistor and an NMOS transistor connected in anti-parallel. The NMOS transistor can transmit low-level signals with almost no attenuation, while the PMOS transistor can transmit high-level signals with almost no attenuation. Specifically, state machine 1 synchronously outputs a pair of in-phase control voltages U2 and U1 with opposite high and low levels, which are applied to the in-phase control terminal and the in-phase control terminal of the CMOS gate, respectively. Under the drive of these complementary control voltages, the two switches inside the CMOS gate are simultaneously turned on, forming a low-impedance transmission channel, thereby accurately transmitting the reference voltage output by DAC2 or the actual feedback voltage of the motor to the corresponding holding capacitor for storage.

[0038] It should be noted that the aforementioned in-phase control voltage U2 and in-phase control voltage U1 can preferably be directly generated by the digital logic gate circuit inside state machine 1, so that the two are synchronously inversely phased in timing. This complementary driving method can ensure the rapid opening and closing of CMOS gates, and reduce the charge injection interference generated on the holding capacitor during the switching on and off moments through the mutual cancellation of the parasitic capacitances of NMOS and PMOS transistors.

[0039] As can be seen, this embodiment uses CMOS gates driven by complementary in-phase control voltage U2 and in-phase control voltage U1 as sampling switches in each sample-and-hold branch, which enables both high and low level voltage signals to be accurately transmitted, thereby improving the accuracy and stability of the closed-loop control circuit during the sampling stage.

[0040] As an optional embodiment, it also includes a first inverter INV1 and a second inverter INV2; The input terminal of the first inverter INV1 is connected to state machine 1 and is used to output the inverting control voltage U1; The input terminal of the second inverter INV2 is connected to the output terminal of the first inverter INV1, and is used to output the in-phase control voltage U2.

[0041] Considering that when a CMOS gate is used as a sampling switch in the aforementioned embodiments, a pair of in-phase control voltages U2 and U1 with strictly complementary high and low levels are required for driving.

[0042] Based on this, in this embodiment, the complementary in-phase control voltage U2 and inverted control voltage U1 are generated by connecting the first inverter INV1 and the second inverter INV2 in series. Specifically, state machine 1 outputs a single-channel initial control voltage to the input terminal of the first inverter INV1, which flips the voltage level and outputs the inverted control voltage U1. Simultaneously, the second inverter INV2 receives the inverted control voltage U1 and flips it again, outputting the in-phase control voltage U2. In the above process, the voltage signal generated by the series inverters has a small delay and a fixed structure, ensuring that the generated inverted control voltage U1 and in-phase control voltage U2 remain complementary, thus improving their stability.

[0043] As can be seen, this embodiment utilizes the first inverter INV1 and the second inverter INV2 to directly generate complementary in-phase control voltage U2 and in-phase control voltage U1 from a single signal, thereby achieving strict synchronization of the CMOS gate drive signal with a simple logic circuit and avoiding sampling errors caused by timing deviations.

[0044] As an optional embodiment, each of the three comparators includes an operational amplifier, a first CMOS gate K5, and an AND gate K4; The non-inverting input of the operational amplifier is connected to the second terminal of the corresponding reference holding capacitor C1, and the inverting input is connected to the second terminal of the corresponding feedback holding capacitor C2. The first CMOS gate K5 is connected between the inverting input and output of the operational amplifier. The control terminal is connected to state machine 1 and is used to turn on under the control of state machine 1 to reset the operational amplifier. The first input terminal of AND gate K4 is connected to the output terminal of the operational amplifier, the second input terminal is connected to state machine 1, and the output terminal is connected to output selection circuit 7. Under the control of state machine 1, the output of the operational amplifier is shielded during the conduction of the first CMOS gate K5 to prevent invalid comparison results from being output to output selection circuit 7.

[0045] Considering that during the process of the three comparators taking turns to perform sampling, comparison and reset operations, when a comparator finishes the comparison task of the current round and is ready to enter the next round, the operational amplifier and its input terminal may still have charge from the previous round.

[0046] Based on this, in this embodiment, a first CMOS gate K5 is connected across the inverting input and output of the operational amplifier, and an AND gate K4 is connected in series on the output path to perform a controllable reset of the operational amplifier. Specifically, state machine 1 outputs a control signal to turn on the first CMOS gate K5, connecting the output of the operational amplifier to the inverting input, thereby quickly dissipating residual charge and completing the physical reset of the operational amplifier. Simultaneously, state machine 1 outputs a low level to the second input of the AND gate K4, making the output of the AND gate K4 low, isolating the operational amplifier from the back-end circuit, so that no erroneous output is generated during the reset process. After the reset is completed and the operational amplifier enters the normal voltage comparison stage, state machine 1 turns off the first CMOS gate K5 and outputs a high level to the second input of the AND gate K4, so that the operational amplifier can output a reliable comparison result.

[0047] As can be seen, this embodiment achieves fast reset of the operational amplifier and output isolation during the reset process through the first CMOS gate K5 and AND gate K4, avoiding interference from residual charge from the previous cycle and preventing false triggering during reset, thereby improving the accuracy and reliability of the comparator during rotation.

[0048] As an optional embodiment, the reference sample-and-hold branch also includes a second CMOS gate K6, a third CMOS gate K7, and a voltage regulator capacitor C3; The first terminal of the second CMOS gate K6 is connected to the analog reference voltage U3, the second terminal is connected to the first terminal of the reference holding capacitor C1, and the control terminal is connected to state machine 1. The first terminal of the third CMOS gate K7 is connected to the analog reference voltage U3, the second terminal is connected to the second terminal of the reference holding capacitor C1, and the control terminal is connected to state machine 1; the second CMOS gate K6 and the third CMOS gate K7 are used to be turned on under the control of state machine 1 to clamp the voltage across the reference holding capacitor C1 to the analog reference voltage U3. The first terminal of the voltage regulator capacitor C3 is connected to the second terminal of the reference holding capacitor C1, and the second terminal is grounded.

[0049] Considering that if there is an unknown charge remaining on the reference holding capacitor C1 before the reference voltage of DAC2 is accurately sampled, the voltage of the subsequent input comparator may not accurately reflect the reference voltage of DAC2.

[0050] Based on this, in this embodiment, a reset circuit for the reference holding capacitor C1 is constructed using the second CMOS gate K6 and the third CMOS gate K7. Before the sampling operation begins, state machine 1 controls the second CMOS gate K6 and the third CMOS gate K7 to be turned on simultaneously, directly connecting both the first and second terminals of the reference holding capacitor C1 to the internal analog reference voltage U3. Through this operation, the voltage across the reference holding capacitor C1 is clamped to the fixed analog reference voltage U3, thereby clearing the residual voltage difference and establishing a stable sampling reference. Subsequently, the second CMOS gate K6 and the third CMOS gate K7 are turned off, and the reference sampling switch K1 is turned on for normal sampling. At the same time, the voltage regulator capacitor C3 is connected to the second terminal of the reference holding capacitor C1 through its first terminal, providing an AC ground loop. During this process, the voltage regulator capacitor C3 can absorb high-frequency switching noise in the circuit when the reference sampling switch K1 operates frequently, preventing the potential of the reference holding capacitor C1 from fluctuating.

[0051] As can be seen, this embodiment utilizes the controlled second and third CMOS gates K7 in conjunction with the voltage regulator capacitor C3 to provide reference clamping and filtering for the reference holding capacitor C1 before sampling, thus providing an accurate reference voltage input for the comparator.

[0052] As an optional embodiment, the feedback sample-and-hold branch also includes a fourth CMOS gate K8 and a fifth CMOS gate K9; The first terminal of the fourth CMOS gate K8 is connected to the first terminal of the feedback holding capacitor C2, the second terminal is grounded, and the control terminal is connected to state machine 1. It is used to conduct under the control of state machine 1 to discharge and clear the first terminal of the feedback holding capacitor C2. The first terminal of the fifth CMOS gate K9 is connected to the common output terminal of the first feedback sampling switch K2 and the second feedback sampling switch K3. The second terminal is connected to the first terminal of the feedback holding capacitor C2. The control terminal is connected to state machine 1 and is used to turn on or off under the control of state machine 1 to control the on / off state of the input circuit of the actual feedback voltage obtained by sampling to the feedback holding capacitor C2.

[0053] Considering that in a single DAC time-division multiplexing scenario, the feedback holding capacitor C2 needs to alternately store the actual feedback voltages of the first and second phases, it is necessary to reset the feedback holding capacitor C2 to prevent crosstalk between the feedback voltage of the previous phase and the feedback voltage of the new phase. Furthermore, to prevent reverse charge flow from the capacitor during the comparison phase, controllable physical isolation is required.

[0054] Based on this, in this embodiment, a fourth CMOS gate K8 and a fifth CMOS gate K9 are added to the front end of the feedback holding capacitor C2. When state machine 1 issues a global reset signal, the fourth CMOS gate K8 is turned on first, directly grounding the first terminal of the feedback holding capacitor C2, thereby quickly discharging and clearing the residual charge of the previous phase. When entering the sampling stage, the fourth CMOS gate K8 is turned off, and the fifth CMOS gate K9 is turned on, allowing the actual feedback voltage to be connected to the feedback holding capacitor C2; when sampling ends and the comparison and hold stage begins, the fifth CMOS gate K9 is turned off, cutting off the path of the actual feedback voltage input to the feedback holding capacitor C2. The controllable physical isolation between the feedback voltage and the feedback holding capacitor C2 is achieved through the aforementioned fifth CMOS gate K9.

[0055] It should be noted that the fifth CMOS gate K9 is equivalent to a switch here. It forms a series control with the aforementioned first feedback sampling switch K2 or second feedback sampling switch K3, which further reduces the leakage current during the holding phase and makes the latched voltage more stable.

[0056] As can be seen, this embodiment uses the fourth CMOS gate K8 to perform discharge clearing and the fifth CMOS gate K9 to perform circuit isolation, which can avoid crosstalk between the actual feedback voltages of different phases and improve the independence and accuracy of the actual feedback voltage acquisition of each phase.

[0057] As an optional embodiment, such as Figure 6 As shown, Figure 6 The present invention provides a structural diagram of an output selection circuit. The output selection circuit 7 includes a first multiplexer MUX1 and a second multiplexer MUX2: The multiple input terminals of the first multiplexer MUX1 are respectively connected to the output terminals of three comparators, and the control terminal is connected to state machine 1. Under the control of state machine 1, it is used to select the current valid comparison result of the first phase from the comparison results of the three comparators, and output the first comparison feedback voltage based on the current valid comparison result of the first phase. The multiple inputs of the second multiplexer MUX2 are connected to the outputs of the three comparators respectively, and the control terminal is connected to state machine 1. Under the control of state machine 1, it selects the current valid comparison result of the second phase from the comparison results of the three comparators, and outputs the second comparison feedback voltage based on the current valid comparison result of the second phase.

[0058] Considering that the three comparators operate in a rotating manner under the control of state machine 1—that is, each comparator alternates between comparing the first phase, comparing the second phase, and resetting—the comparator that outputs the valid comparison result for the first phase changes continuously at different times, and the same applies to the second phase. However, the subsequent motor drive requires continuous and independent feedback for both the first and second phases.

[0059] Based on this, this embodiment introduces a first multiplexer MUX1 and a second multiplexer MUX2 to achieve the selection and recombination of comparison results. Specifically, state machine 1 outputs a control voltage reflecting the current operating state of the comparators to the control terminals of the two multiplexers. The three input terminals of the first multiplexer MUX1 and the second multiplexer MUX2 are respectively connected to the output terminals of the three comparators. Under the control of the control voltage output by state machine 1, the first multiplexer MUX1 selects the comparator currently in the first phase comparison operating state in real time, connecting its output terminal to its own output terminal, thereby synthesizing a continuous first comparison feedback voltage. Similarly, the second multiplexer MUX2 tracks the comparator currently in the second phase comparison operating state in real time, connecting its output terminal and synthesizing a continuous second comparison feedback voltage. Through the above process, the comparison results can be selected and redistributed, providing continuous and independent first and second phase feedback for subsequent circuits.

[0060] It should be noted that the first multiplexer MUX1 and the second multiplexer MUX2 mentioned above are pure digital logic devices, such as preferably three-to-one data selectors. Their channel switching actions strictly follow the timing control of state machine 1, thereby enabling the discrete outputs of the three comparators to be spliced ​​into a continuous signal output.

[0061] As can be seen, this embodiment, by configuring two multiplexers controlled by state machine 1, realizes the extraction and splicing of the comparator's rotating output results through hardware circuitry, thus improving the signal transmission path between the single DAC time-division multiplexing structure and the subsequent independent closed-loop drive.

[0062] As an optional embodiment, such as Figure 7 As shown, Figure 7 A structural diagram of a digital chopper circuit and a drive circuit provided by the present invention. The closed-loop control circuit provided by the present invention further includes: The digital chopper circuit has its input terminal connected to the output terminal of the output selection circuit 7. It is used to receive the first comparison feedback voltage and the second comparison feedback voltage respectively, and output the chopper drive voltage of the corresponding phase. The drive circuit has its input terminal connected to the output terminal of the digital chopper circuit, and its output terminal connected to the first phase winding and the second phase winding of the motor, respectively. The drive circuit contains multiple switching transistors, which are used to turn on or off under the action of the chopper drive voltage to adjust the current in the first phase winding and the second phase winding, respectively.

[0063] Considering that the above embodiment has obtained continuous first comparison feedback voltage and second comparison feedback voltage through DAC time-division multiplexing structure, sample-and-hold comparison structure and output selection circuit 7, in order to form a complete closed loop, it is also necessary to convert it into a power switching signal that can directly drive the high current operation of the motor coil to control the motor to operate.

[0064] Based on this, this embodiment introduces a subsequent digital chopper circuit and a drive circuit. Specifically, the digital chopper circuit internally includes a D flip-flop and logic circuitry. It determines the relative magnitude of the actual motor current and the target current based on the received levels of the first and second comparison feedback voltages, and then switches the corresponding chopping state, such as... Figure 8 As shown, Figure 8 This invention provides a chopping state diagram for a digital chopper circuit. The chopping states include on, fast decay, or slow decay states, and output corresponding chopping drive voltages. Multiple switching transistors within the drive circuit (such as the first power NMOS transistor SW1, the second power NMOS transistor SW2, the third power NMOS transistor SW3, and the fourth power NMOS transistor SW4 in an H-bridge structure) are turned on or off under the control of the chopping drive voltage to adjust the supply voltage and current direction of the first and second phase windings of the motor. The drive circuit also includes a sensing resistor R connected in series in the winding circuit. As the winding current dynamically changes, the actual feedback voltage SENSE reflected by this sensing resistor is updated synchronously and transmitted to the sample-and-hold circuit 3 and the comparator for the next round of comparison.

[0065] As can be seen, this embodiment uses a digital chopper circuit and a drive circuit to drive the switching transistor based on the voltage comparison result of the previous stage, thus completing a complete closed-loop feedback control process from the digital input of the target current to the feedback of the winding current, and realizing the closed-loop adjustment of the actual operating current of the motor to the digital target current.

[0066] As a more specific embodiment, such as Figure 9 As shown, Figure 9This invention provides a timing diagram of a closed-loop control circuit. Under the control of state machine 1, DAC2 first outputs the reference voltages of the first and second phases in a time-division multiplexing manner. Simultaneously, state machine 1 controls three comparators to perform reset, sampling, and comparison operations in turn. During the working cycle of a single comparator, state machine 1 first outputs a reset signal DAC_CLK to clear the holding capacitor and residual charge inside the comparator. Then, it synchronously holds the current reference voltage and the actual feedback voltage of the corresponding phase in the corresponding holding capacitor for comparison. By controlling the staggered overlap of the working timing of the three comparators, two comparators always stably provide the current valid comparison results of the first and second phases at any given time, while the third comparator is in a reset or preparing for a new round of sampling. Finally, the output selection circuit 7 extracts and splices the discrete comparison results alternately generated by the three comparators in real time, synthesizing a continuous first comparison feedback voltage and a second comparison feedback voltage. Thus, by relying on digital sequential logic, the time delay caused by the time-division multiplexing of a single DAC is compensated at the physical level, completing continuous closed-loop control.

[0067] Furthermore, such as Figure 10 As shown, Figure 10 The waveforms of motor current and feedback voltage in the closed-loop control circuit provided by this invention are shown. Wherein, as... Figure 10 As shown in the upper part, under the above timing control, the first phase winding current (i.e., phase A current) and the second phase winding current (i.e., phase B current) of the motor can exhibit a continuous and smooth alternating waveform. For example... Figure 10 The lower half of the magnified waveform shows that within a single chopping cycle, the actual feedback voltage (i.e., the SENSE waveform) collected in the winding circuit fluctuates in a sawtooth pattern as the switching transistor operates. When the actual feedback voltage reaches the reference voltage of the DAC's time-division output (i.e., the DAC step waveform), the corresponding comparator flips its level, generates a feedback signal, and triggers the digital chopping circuit to switch the corresponding chopping state.

[0068] It should be noted that, in this specification, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0069] The above description of the disclosed embodiments enables those skilled in the art to make or use the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A closed-loop control circuit for a motor, characterized in that, It includes a DAC, three comparators, a sample-and-hold circuit, an output selection circuit, and a state machine; The DAC is connected to the state machine and is used to receive the target current digital quantity of the first phase and the target current digital quantity of the second phase in a time-division manner, and convert them into the corresponding first reference voltage and second reference voltage. The sample-and-hold circuit is connected to the output of the DAC, the winding current feedback voltage input of the motor, the state machine, and the input of the three comparators. Under the control of the state machine, it acquires and holds the reference voltage output by the DAC and the actual feedback voltage corresponding to the reference voltage, and sends it to the two target comparators corresponding to the current cycle among the three comparators, so that the target comparators compare the held reference voltage and the actual feedback voltage. The three comparators are used, under the control of the state machine, to take turns comparing the first phase, comparing the second phase, and waiting to compare the corresponding phase in the next round; wherein, in any round, two of the comparators serve as target comparators and are used to perform the comparison of the first phase and the second phase in the current round, respectively, while the other comparator is used to wait to perform the comparison of the corresponding phase in the next round. The output selection circuit is connected to the output terminals of the state machine and the three comparators respectively. Under the control of the state machine, it determines the current valid comparison result of the first phase and the current valid comparison result of the second phase according to the comparison results of the two target comparators, and outputs the first comparison feedback voltage of the first phase and the second comparison feedback voltage of the second phase to the state machine.

2. The closed-loop control circuit as described in claim 1, characterized in that, Also includes: An input selection circuit is provided, wherein a first input terminal is used to receive the target current digital quantity of the first phase, a second input terminal is used to receive the target current digital quantity of the second phase, an output terminal is connected to the DAC, and a control terminal is connected to the state machine. The circuit is used to output the target current digital quantities of the first phase and the second phase to the DAC in a time-division manner under the control of the state machine.

3. The closed-loop control circuit as described in claim 1, characterized in that, The sample-and-hold circuit includes a reference sample-and-hold branch and a feedback sample-and-hold branch, which are configured to correspond one-to-one with each of the comparators. The reference sample-and-hold branch includes a reference sampling switch and a reference holding capacitor. The first terminal of the reference sampling switch is connected to the output terminal of the DAC, the second terminal is connected to the first terminal of the reference holding capacitor, and the control terminal is connected to the state machine. When the state machine controls the switch to be turned on, the reference voltage output by the DAC is input to the reference holding capacitor. The first end of the reference holding capacitor is connected to the second end of the reference sampling switch, and the second end is connected to the first input end of the corresponding comparator, which is used to hold the sampled reference voltage after the reference sampling switch is turned off. The feedback sampling and holding branch includes a first feedback sampling switch, a second feedback sampling switch, and a feedback holding capacitor. The first terminal of the first feedback sampling switch is connected to the winding current feedback voltage input terminal of the first phase of the motor, the second terminal is connected to the first terminal of the feedback holding capacitor, and the control terminal is connected to the state machine. When the state machine controls the switch to conduct, the actual feedback voltage of the first phase is input to the feedback holding capacitor. The first end of the second feedback sampling switch is connected to the winding current feedback voltage input terminal of the second phase of the motor, the second end is connected to the first end of the feedback holding capacitor, and the control terminal is connected to the state machine. When the switch is turned on under the control of the state machine, the actual feedback voltage of the second phase is input to the feedback holding capacitor. The first end of the feedback holding capacitor is connected to the second end of the first feedback sampling switch and the second end of the second feedback sampling switch, respectively. The second end is connected to the second input terminal of the corresponding comparator, which is used to hold the actual feedback voltage sampled after the corresponding feedback sampling switch is turned off.

4. The closed-loop control circuit as described in claim 3, characterized in that, The reference sampling switch, the first feedback sampling switch, and the second feedback sampling switch are all CMOS gates; The CMOS gate includes a non-inverting control terminal and an inverting control terminal, both of which are connected to the state machine. They are used to receive the non-inverting control voltage and the inverting control voltage output by the state machine, respectively, so as to turn on or off under the drive of the non-inverting control voltage and the inverting control voltage.

5. The closed-loop control circuit as described in claim 4, characterized in that, It also includes a first inverter and a second inverter; The input terminal of the first inverter is connected to the state machine for outputting the inverting control voltage; The input terminal of the second inverter is connected to the output terminal of the first inverter, and is used to output the in-phase control voltage.

6. The closed-loop control circuit as described in claim 3, characterized in that, Each of the three comparators includes an operational amplifier, a first CMOS gate, and an AND gate; The non-inverting input terminal of the operational amplifier is connected to the second terminal of the corresponding reference holding capacitor, and the inverting input terminal is connected to the second terminal of the corresponding feedback holding capacitor. The first CMOS gate is connected between the inverting input and output of the operational amplifier, and the control terminal is connected to the state machine to be turned on under the control of the state machine to reset the operational amplifier. The first input terminal of the AND gate is connected to the output terminal of the operational amplifier, the second input terminal is connected to the state machine, and the output terminal is connected to the output selection circuit. Under the control of the state machine, the output of the operational amplifier is shielded during the conduction of the first CMOS gate to prevent invalid comparison results from being output to the output selection circuit.

7. The closed-loop control circuit as described in claim 3, characterized in that, The reference sample-and-hold branch also includes a second CMOS gate, a third CMOS gate, and a voltage regulator capacitor; The first terminal of the second CMOS gate is connected to an analog reference voltage, the second terminal is connected to the first terminal of the reference holding capacitor, and the control terminal is connected to the state machine. The first terminal of the third CMOS gate is connected to the analog reference voltage, the second terminal is connected to the second terminal of the reference holding capacitor, and the control terminal is connected to the state machine; the second CMOS gate and the third CMOS gate are used to conduct under the control of the state machine to clamp the voltage across the reference holding capacitor to the analog reference voltage; The first terminal of the voltage regulator capacitor is connected to the second terminal of the reference holding capacitor, and the second terminal is grounded.

8. The closed-loop control circuit as described in claim 3, characterized in that, The feedback sample-and-hold branch also includes a fourth CMOS gate and a fifth CMOS gate; The first terminal of the fourth CMOS gate is connected to the first terminal of the feedback holding capacitor, the second terminal is grounded, and the control terminal is connected to the state machine. It is used to conduct under the control of the state machine to discharge and clear the first terminal of the feedback holding capacitor. The first end of the fifth CMOS gate is connected to the common output terminal of the first feedback sampling switch and the second feedback sampling switch, the second end is connected to the first end of the feedback holding capacitor, and the control terminal is connected to the state machine. It is used to turn on or off under the control of the state machine to control the on / off state of the input circuit of the actual feedback voltage obtained by sampling to the feedback holding capacitor.

9. The closed-loop control circuit as described in claim 1, characterized in that, The output selection circuit includes a first multiplexer and a second multiplexer. Multiple input terminals of the first multiplexer are respectively connected to the output terminals of the three comparators, and the control terminal is connected to the state machine. Under the control of the state machine, the first multiplexer selects the current valid comparison result of the first phase from the comparison results of the three comparators and outputs the first comparison feedback voltage based on the current valid comparison result of the first phase. The multiple inputs of the second multiplexer are respectively connected to the outputs of the three comparators, and the control terminal is connected to the state machine. Under the control of the state machine, the current valid comparison result of the second phase is selected from the comparison results of the three comparators, and the second comparison feedback voltage is output based on the current valid comparison result of the second phase.

10. The closed-loop control circuit according to any one of claims 1 to 9, characterized in that, Also includes: A digital chopper circuit, wherein the input terminal of the digital chopper circuit is connected to the output terminal of the output selection circuit, and is used to receive the first comparison feedback voltage and the second comparison feedback voltage respectively, and output the chopper drive voltage of the corresponding phase; The driving circuit has its input terminal connected to the output terminal of the digital chopper circuit, and its output terminal connected to the windings of the first phase and the second phase of the motor, respectively. The driving circuit contains multiple switching transistors, which are used to turn on or off under the action of the chopper driving voltage to adjust the current in the windings of the first phase and the second phase, respectively.

Images