A phase current reconstruction method for permanent magnet synchronous traction variable frequency speed regulation

Abstract

The application relates to the technical field of variable frequency speed regulation of alternating current motors, and discloses a phase current reconstruction method for permanent magnet synchronous traction variable frequency speed regulation, which comprises the following steps: collecting bus voltage and metal oxide semiconductor field effect tube shell temperature to calculate junction temperature, determining parasitic oscillation decay duration and accumulating hardware delay to calculate an effective sampling window threshold value; when the effective vector duration is smaller than the threshold value, the difference between the total duration of turn-off and turn-on conversion is calculated as a transient transition time asymmetric difference amount, the turn-on time of a driving pulse is moved forward, and a reverse volt-second balance cut-off after deducting the difference amount is applied in a compensation period; after oscillation decay, a single sampling resistor signal is collected to solve three-phase stator current, the application corrects compensation timing according to device switching transition characteristics, eliminates end voltage volt-second integral deviation and stator flux linkage drift introduced by pulse width microshift, suppresses torque ripple, and widens the linear modulation range.

Description

Technical Field

[0001] This invention belongs to the field of AC motor frequency conversion speed regulation technology, and particularly relates to a phase current reconstruction method for permanent magnet synchronous traction frequency conversion speed regulation. Background Technology

[0002] In permanent magnet synchronous motor traction drive systems, metal oxide semiconductor field-effect transistor inverter bridges are typically used to drive the motor. The bus current is collected using a single sampling resistor on the DC bus to reconstruct the stator phase current. This method can reduce the hardware size and wiring complexity, while eliminating the inherent temperature drift and zero-point drift effects of current sensors. When performing single-resistor sampling, the bus current is collected during the action of two adjacent effective voltage vectors based on the correspondence between the inverter bridge switching state and the bus return current. Then, the phase current that is not directly measured is calculated by combining the three-phase current balance relationship of the stator.

[0003] During the switching instant of a metal-oxide-semiconductor (MOSFET), the parasitic capacitance charging and discharging, combined with the stray inductance of the circuit, generates a high-frequency oscillating current. Under this influence, the signal across the bus sampling resistor typically enters a stable current plateau after experiencing drive delay, current rise, and parasitic oscillation attenuation. When the motor is operating at low speed and light load or with a low modulation ratio, the theoretical duration of the effective voltage vector is significantly shortened. If this duration is less than the sum of the oscillation attenuation time and the analog-to-digital conversion sampling time, it will fall into the sampling dead zone, resulting in the inability to form a stable reading window across the sampling resistor. To widen the sampling window, existing technologies typically move the edge of the drive pulse within the modulation period and make symmetrical adjustments according to the ideal square wave switching process to maintain volt-second balance. However, due to the influence of the Miller plateau and junction capacitance, there is an inherent difference between the turn-on and turn-off transition times of the MOSFET. If the adjustment is still made according to the symmetrical relationship of the ideal pulse, the difference between the actual turn-on and turn-off transition times will be ignored, causing a residual deviation in the volt-second integral of the motor terminal voltage. After this deviation accumulates, it will cause stator flux drift and torque pulsation.

[0004] Therefore, the technical problem to be solved by this invention is to combine the actual switching transient characteristics of metal-oxide-semiconductor field-effect transistors to reduce the error caused by the asymmetry of the turn-on and turn-off transition times during the micro-shift of the drive pulse, and to achieve stable phase current reconstruction under different operating conditions while maintaining the volt-second balance of the inverter bridge terminal voltage. Summary of the Invention

[0005] To address the problems in the background art, the technical solution of the present invention is as follows: A phase current reconstruction method for permanent magnet synchronous traction variable frequency speed regulation, comprising the following steps:

[0006] Step S1: Collect the DC bus voltage and the metal-oxide-semiconductor field-effect transistor case temperature to calculate the internal junction temperature. Combine the DC bus voltage and the internal junction temperature to determine the high-frequency parasitic oscillation decay time. Accumulate the drive delay time, current rise time, high-frequency parasitic oscillation decay time and sampling hold time to determine the effective sampling window threshold.

[0007] Step S2: Obtain the theoretical duration of the two effective voltage vectors of space vector modulation;

[0008] Step S3: When the effective voltage vector theoretical duration is less than the effective sampling window threshold, determine the pulse width deficit. Calculate the difference between the total turn-off transition time and the total turn-on transition time of the target phase metal-oxide-semiconductor field-effect transistor as the transient transition time asymmetry difference. Move the turn-on time of the target phase driving pulse forward by the pulse width deficit. Apply a reverse volt-second balance truncation with a truncation duration equal to the pulse width deficit minus the transient transition time asymmetry difference during the compensation period.

[0009] Step S4: After the high-frequency parasitic oscillation decays to the steady-state threshold, a single-sample resistor signal is acquired in the action range of the two effective voltage vectors to obtain the first bus current and the second bus current.

[0010] Step S5: Based on the inverter bridge conduction topology, the first bus current and the second bus current are converted into two-phase stator currents. The third-phase stator current is calculated based on the fact that the sum of the three-phase stator currents is zero, and then output to the vector control loop.

[0011] Preferably, step S1, which combines the DC bus voltage and the internal junction temperature to determine the high-frequency parasitic oscillation decay time, includes: step S11, calculating the internal junction temperature based on the metal-oxide-semiconductor field-effect transistor case temperature using a transient thermal resistance model; step S12, extracting the drain-source parasitic output capacitance value based on the DC bus voltage and the internal junction temperature, and determining the high-frequency oscillation frequency and decay time constant by combining it with the stray inductance of the inverter bridge bus circuit; and step S13, calculating the time it takes for the high-frequency oscillation current amplitude to decay to within the least significant bit conversion threshold of the analog-to-digital converter, and determining this as the high-frequency parasitic oscillation decay time.

[0012] Preferably, step S3, calculating the difference between the total turn-off transition time and the total turn-on transition time of the target phase MOSFET as the transient transition time asymmetry difference, includes: step S31, extracting the gate turn-on propagation delay time and drain current rise time of the target phase MOSFET under the current DC bus voltage and internal junction temperature, and adding the two to obtain the total turn-on transition time; step S32, extracting the gate turn-off propagation delay time and drain current fall time of the target phase MOSFET under the current DC bus voltage and internal junction temperature, and adding the two to obtain the total turn-off transition time; step S33, calculating the time difference obtained by subtracting the total turn-on transition time from the total turn-off transition time, and determining it as the transient transition time asymmetry difference.

[0013] Preferably, step S2, obtaining the theoretical duration of the two effective voltage vectors of space vector modulation, includes: step S21, obtaining the stator reference voltage vector amplitude and spatial electrical angle sent by the traction speed regulation current loop regulator at the start of the current pulse width modulation carrier period; step S22, determining the basic hexagonal sector of the space hexagonal segment where the stator reference voltage vector is located based on the spatial electrical angle; and step S23, calculating the theoretical duration of the first effective voltage vector and the theoretical duration of the second effective voltage vector of the current sector required to synthesize the stator reference voltage vector based on the spatial voltage vector pulse width modulation projection geometry.

[0014] Preferably, in step S4, after the high-frequency parasitic oscillation decays to the steady-state threshold, the single-sample resistor signal is acquired within the two effective voltage vector action intervals, including: step S41, within the first effective voltage vector action interval after micro-shift adjustment, the sampling trigger time is set at the stable current plateau segment after the switch state transition ends and after the drive delay time, current rise time, and high-frequency parasitic oscillation decay time, triggering the analog-to-digital converter to read the voltage across the single-sample resistor and calculate the first bus current; step S42, within the second effective voltage vector action interval after micro-shift expansion, after the drain-source high-frequency oscillation amplitude decays into the least effective bit conversion threshold of the analog-to-digital converter, triggering the analog-to-digital converter to read the voltage across the single-sample resistor and calculate the second bus current.

[0015] Preferably, step S5 converts the first bus current and the second bus current into two-phase stator currents based on the inverter bridge conduction topology, including: step S51, reading the switching state combination of the current pulse width modulation cycle, and determining the bus current return path according to the physical on / off state of the metal-oxide-semiconductor field-effect transistors of the upper and lower arms of the three-phase inverter bridge; step S52, when the first effective voltage vector is the basic effective vector of the I-th sector, assigning the measured first bus current to the A-phase stator current of the motor; step S53, when the second effective voltage vector is the adjacent effective vector of the I-th sector, assigning the measured reverse polarity value of the second bus current to the C-phase stator current of the motor; step S54, calculating the B-phase stator current based on the constraint that the algebraic sum of the three-phase instantaneous currents is always zero, satisfied by the three-phase stator winding neutral point floating structure of the motor.

[0016] Preferably, in step S3, when the theoretical duration of the first effective voltage vector and the theoretical duration of the second effective voltage vector are both less than the effective sampling window threshold, the method includes: step S34, within the current pulse width modulation carrier cycle, applying unilateral widening only to the phase bridge arm drive pulse corresponding to the first effective voltage vector so that the duration of the first effective voltage vector reaches the effective sampling window threshold, and collecting the first bus current within the range of action of the first effective voltage vector; step S35, within the immediately following pulse width modulation carrier cycle, applying unilateral widening only to the phase bridge arm drive pulse corresponding to the second effective voltage vector so that the duration of the second effective voltage vector reaches the effective sampling window threshold, and collecting the second bus current within the range of action of the second effective voltage vector.

[0017] Preferably, the dual-cycle alternating measurement step further includes: step S341, within the current pulse width modulation carrier cycle, correcting the pulse cutoff time according to the transient transition time asymmetry difference of the corresponding cycle, and applying a virtual anti-phase vector; step S351, within the immediately following pulse width modulation carrier cycle, correcting the pulse cutoff time according to the transient transition time asymmetry difference of the corresponding cycle, and applying a virtual anti-phase vector in the opposite direction to counteract the stator synthesized flux linkage position offset.

[0018] Preferably, step S4, which involves acquiring a single-sample resistor signal, further includes: step S43, continuously reading discrete sampling points within the analog-to-digital converter conversion window; step S44, calculating the absolute value of the difference slope between adjacent discrete sampling points; step S45, when the absolute value of the difference slope is continuously less than a preset steady-state threshold, outputting the current bus current to the subsequent topology mapping step; and when the absolute value of the difference slope is greater than or equal to the preset steady-state threshold, maintaining the phase current output value of the previous pulse width modulation cycle.

[0019] Compared with existing technologies, the phase current reconstruction method for permanent magnet synchronous traction variable frequency speed regulation of the present invention has the following advantages:

[0020] 1. In the phase current reconstruction of permanent magnet synchronous traction variable frequency speed regulation, the high-frequency parasitic oscillation decay time is determined according to the DC bus voltage and the actual temperature state of the metal oxide semiconductor field-effect transistor, and the effective sampling window threshold is adjusted accordingly. This allows the sampling timing to change with the operating conditions. Compared with setting a fixed delay according to the most unfavorable operating conditions, this can avoid switching transient oscillations while reducing unnecessary pulse width adjustments and reducing the impact on the effective voltage vector action time, thereby widening the linear modulation range of the inverter bridge.

[0021] 2. In response to the situation where the effective voltage vector falls into the sampling blind zone, the actual difference between the turn-on and turn-off switching times of the metal-oxide-semiconductor field-effect transistor is considered, and this difference is used to correct the pulse adjustment process. This can reduce the residual deviation of the terminal voltage volt-second integration caused by the micro-shift of the drive pulse, avoid the continuous accumulation of this deviation, and thus suppress the stator flux drift and phase current waveform distortion during low-frequency operation.

[0022] 3. Determine the sampling trigger time based on the drive delay, current rise time, and the time required for high-frequency parasitic oscillation decay. This ensures that the single-sample resistor signal is acquired as soon as possible after the current enters a stable state. This avoids the influence of switching spikes and high-frequency oscillations on sampling too early, and also avoids unnecessary pulse broadening caused by sampling too late. This is beneficial for obtaining more stable bus current sampling values ​​with less interference and reduces the impact of transient noise on the traction vector control current closed loop. Attached Figure Description

[0023] Figure 1 This is a flowchart of the switching transient asymmetry compensation and phase current reconstruction of the present invention;

[0024] Figure 2 This is a schematic diagram illustrating the causal relationship between the key control elements and physical constraint parameters of this invention. Detailed Implementation

[0025] The technical solutions of the embodiments of this application will be clearly described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of this application are within the scope of protection of this application.

[0026] A method for reconstructing the phase current of permanent magnet synchronous traction variable frequency speed regulation includes the following steps:

[0027] Step S1: Collect the DC bus voltage and the metal-oxide-semiconductor field-effect transistor case temperature to calculate the internal junction temperature. Combine the DC bus voltage and the internal junction temperature to determine the high-frequency parasitic oscillation decay time. Accumulate the drive delay time, current rise time, high-frequency parasitic oscillation decay time and sampling hold time to determine the effective sampling window threshold.

[0028] Step S2: Obtain the theoretical duration of the two effective voltage vectors of space vector modulation;

[0029] Step S3: When the effective voltage vector theoretical duration is less than the effective sampling window threshold, determine the pulse width deficit. Calculate the difference between the total turn-off transition time and the total turn-on transition time of the target phase metal-oxide-semiconductor field-effect transistor as the transient transition time asymmetry difference. Move the turn-on time of the target phase driving pulse forward by the pulse width deficit. Apply a reverse volt-second balance truncation with a truncation duration equal to the pulse width deficit minus the transient transition time asymmetry difference during the compensation period.

[0030] Step S4: After the high-frequency parasitic oscillation decays to the steady-state threshold, a single-sample resistor signal is acquired in the action range of the two effective voltage vectors to obtain the first bus current and the second bus current.

[0031] Step S5: Based on the inverter bridge conduction topology, the first bus current and the second bus current are converted into two-phase stator currents. The third-phase stator current is calculated based on the fact that the sum of the three-phase stator currents is zero, and then output to the vector control loop.

[0032] Preferably, step S1, which combines the DC bus voltage and the internal junction temperature to determine the high-frequency parasitic oscillation decay time, includes: step S11, calculating the internal junction temperature based on the metal-oxide-semiconductor field-effect transistor case temperature using a transient thermal resistance model; step S12, extracting the drain-source parasitic output capacitance value based on the DC bus voltage and the internal junction temperature, and determining the high-frequency oscillation frequency and decay time constant by combining it with the stray inductance of the inverter bridge bus circuit; and step S13, calculating the time it takes for the high-frequency oscillation current amplitude to decay to within the least significant bit conversion threshold of the analog-to-digital converter, and determining this as the high-frequency parasitic oscillation decay time.

[0033] Preferably, step S3, calculating the difference between the total turn-off transition time and the total turn-on transition time of the target phase MOSFET as the transient transition time asymmetry difference, includes: step S31, extracting the gate turn-on propagation delay time and drain current rise time of the target phase MOSFET under the current DC bus voltage and internal junction temperature, and adding the two to obtain the total turn-on transition time; step S32, extracting the gate turn-off propagation delay time and drain current fall time of the target phase MOSFET under the current DC bus voltage and internal junction temperature, and adding the two to obtain the total turn-off transition time; step S33, calculating the time difference obtained by subtracting the total turn-on transition time from the total turn-off transition time, and determining it as the transient transition time asymmetry difference.

[0034] Preferably, step S2, obtaining the theoretical duration of the two effective voltage vectors of space vector modulation, includes: step S21, obtaining the stator reference voltage vector amplitude and spatial electrical angle sent by the traction speed regulation current loop regulator at the start of the current pulse width modulation carrier period; step S22, determining the basic hexagonal sector of the space hexagonal segment where the stator reference voltage vector is located based on the spatial electrical angle; and step S23, calculating the theoretical duration of the first effective voltage vector and the theoretical duration of the second effective voltage vector of the current sector required to synthesize the stator reference voltage vector based on the spatial voltage vector pulse width modulation projection geometry.

[0035] Preferably, in step S4, after the high-frequency parasitic oscillation decays to the steady-state threshold, the single-sample resistor signal is acquired within the two effective voltage vector action intervals, including: step S41, within the first effective voltage vector action interval after micro-shift adjustment, the sampling trigger time is set at the stable current plateau segment after the switch state transition ends and after the drive delay time, current rise time, and high-frequency parasitic oscillation decay time, triggering the analog-to-digital converter to read the voltage across the single-sample resistor and calculate the first bus current; step S42, within the second effective voltage vector action interval after micro-shift expansion, after the drain-source high-frequency oscillation amplitude decays into the least effective bit conversion threshold of the analog-to-digital converter, triggering the analog-to-digital converter to read the voltage across the single-sample resistor and calculate the second bus current.

[0036] Preferably, step S5 converts the first bus current and the second bus current into two-phase stator currents based on the inverter bridge conduction topology, including: step S51, reading the switching state combination of the current pulse width modulation cycle, and determining the bus current return path according to the physical on / off state of the metal-oxide-semiconductor field-effect transistors of the upper and lower arms of the three-phase inverter bridge; step S52, when the first effective voltage vector is the basic effective vector of the I-th sector, assigning the measured first bus current to the A-phase stator current of the motor; step S53, when the second effective voltage vector is the adjacent effective vector of the I-th sector, assigning the measured reverse polarity value of the second bus current to the C-phase stator current of the motor; step S54, calculating the B-phase stator current based on the constraint that the algebraic sum of the three-phase instantaneous currents is always zero, satisfied by the three-phase stator winding neutral point floating structure of the motor.

[0037] Preferably, in step S3, when the theoretical duration of the first effective voltage vector and the theoretical duration of the second effective voltage vector are both less than the effective sampling window threshold, the method includes: step S34, within the current pulse width modulation carrier cycle, applying unilateral widening only to the phase bridge arm drive pulse corresponding to the first effective voltage vector so that the duration of the first effective voltage vector reaches the effective sampling window threshold, and collecting the first bus current within the range of action of the first effective voltage vector; step S35, within the immediately following pulse width modulation carrier cycle, applying unilateral widening only to the phase bridge arm drive pulse corresponding to the second effective voltage vector so that the duration of the second effective voltage vector reaches the effective sampling window threshold, and collecting the second bus current within the range of action of the second effective voltage vector.

[0038] Preferably, the dual-cycle alternating measurement step further includes: step S341, within the current pulse width modulation carrier cycle, correcting the pulse cutoff time according to the transient transition time asymmetry difference of the corresponding cycle, and applying a virtual anti-phase vector; step S351, within the immediately following pulse width modulation carrier cycle, correcting the pulse cutoff time according to the transient transition time asymmetry difference of the corresponding cycle, and applying a virtual anti-phase vector in the opposite direction to counteract the stator synthesized flux linkage position offset.

[0039] Preferably, step S4, which involves acquiring a single-sample resistor signal, further includes: step S43, continuously reading discrete sampling points within the analog-to-digital converter conversion window; step S44, calculating the absolute value of the difference slope between adjacent discrete sampling points; step S45, when the absolute value of the difference slope is continuously less than a preset steady-state threshold, outputting the current bus current to the subsequent topology mapping step; and when the absolute value of the difference slope is greater than or equal to the preset steady-state threshold, maintaining the phase current output value of the previous pulse width modulation cycle.

[0040] Example 1: In a permanent magnet synchronous traction drive system, the three-phase two-level inverter bridge consists of six metal-oxide-semiconductor field-effect transistors (MOSFETs). The DC bus operating voltage is 600V, and the space voltage vector pulse width modulation carrier period is... The value is 100μs, corresponding to a switching frequency of 10kHz. When the traction motor is in a low-speed, stable starting condition, the stator reference voltage vector amplitude decreases, and the time allocated to the effective voltage vector by the space voltage vector pulse width modulation is shortened. A non-inductive manganese-copper alloy sampling resistor with a series resistance of 5mΩ is used at the low end of the inverter bridge DC bus. It is used to obtain the bus return current. Since the metal-oxide-semiconductor field-effect transistor is a majority carrier device, the switching process is accompanied by the drain-source voltage change rate and current change rate. The inherent nonlinear drain-source output capacitance of the transistor and the stray inductance of the inverter bridge bus circuit generate high-frequency underdamped resonance, which generates a high-frequency current spike and oscillation envelope lasting for hundreds of nanoseconds at both ends of the sampling resistor. When the effective voltage vector duration is less than the sum of the high-frequency parasitic oscillation decay time and the sampling and holding aperture time of the analog-to-digital converter, the sampling resistor cannot present a smooth current plateau, forming a small vector sampling blind zone. The symmetrical pulse width micro-shift mechanism ignores the transient transition time asymmetry formed during the gate charging and discharging and Miller plateau stages of the power switch switching. It generates a residual deviation of the terminal voltage volt-second integral within the carrier period, which accumulates and causes distortion of the stator flux linkage trajectory and low-frequency pulsation of the electromagnetic torque of the traction motor.

[0041] To eliminate the compression of the inverter bridge's linear modulation range by the fixed delay margin, the microprocessor reads the output signal of the DC bus voltage sampling and conditioning circuit to obtain the measured value of the bus voltage. The voltage is 600V; the signal from the thermistor mounted on the heat sink of the power transistor is read to obtain the case temperature. The real-time temperature of the PN junction inside the power switch transistor was calculated based on a transient thermal resistance model using a first-order transient thermal resistance network from the chip to the casing, with a value of 75℃. The temperature is 92℃. In the discrete control timing, the junction temperature calculation adopts a discrete cycle single-step delay decoupling mechanism to remove the timing cycle dependency between the preceding and following operations. In the initial power-on cycle of the inverter, before the armature current is established, the microprocessor directly sets the initial value of the conduction current to 0. At the beginning of the subsequent steady-state operation cycle, the microprocessor reads the effective value of the three-phase stator phase current that has been calculated in the previous carrier cycle from the on-chip historical data buffer, and uses it as the current reference input for calculating the transient conduction loss in the current cycle. Since the thermal capacity time constant of the power device is on the order of tens of milliseconds, while the pulse width modulation carrier cycle is only 100μs, the thermal temperature rise lag caused by the 100μs control cycle results in a temperature difference fluctuation of less than 0.01℃ in the millisecond-level thermal steady-state network. Using the reconstructed current input from the previous cycle can fully meet the engineering accuracy of the junction temperature calculation in the current cycle, thereby blocking the timing closed-loop correlation synthesis between the preceding and following operations. For 600V and Under 92℃ operating conditions, the depletion layer of a metal-oxide-semiconductor field-effect transistor expands under reverse bias, and the drain-source parasitic output capacitance value... The inductance drops to 180pF and is compared with the stray inductance of the inverter bridge bus circuit at 35nH. A high-frequency resonance is formed, which is attenuated by a driving damping network. The microprocessor uses the peak value of the high-frequency oscillation current envelope after the switching transition ends and the damping attenuation phase begins as the initial amplitude. Based on the ratio of this initial amplitude to the least significant bit conversion threshold of the analog-to-digital converter and the attenuation time constant, the microprocessor calculates the time required for the high-frequency oscillation current amplitude to decay to within the threshold, and determines this time as the high-frequency parasitic oscillation attenuation time. The least significant bit conversion threshold of the 12-bit analog-to-digital converter is set to 0.024A, corresponding to half of the least significant bit, under the current operating conditions. It is 0.8μs; combined with the inherent gate drive propagation delay time of the hardware. The drain-source current rise time is 0.3μs. For 0.1μs and the hardware sampling hold aperture time of the analog-to-digital converter The effective sampling window threshold of the stable reading platform is 0.6 μs. The calculation formula is as follows: ,in, For the transmission delay time of the gate drive circuit, The drain current rise time is denoted as . The decay time of high-frequency parasitic oscillations. For the hardware sampling and holding aperture time of the analog-to-digital converter, To determine the effective sampling window threshold, substitute the corresponding values ​​to calculate the effective sampling window threshold under the current operating condition. It is 0.3μs+0.1μs+0.8μs+0.6μs=1.8μs.

[0042] At the start of each pulse width modulation carrier cycle, the current loop regulator outputs the stator reference voltage vector amplitude. The voltage is 20V, and the spatial electric angle is located inside the I-th sector of the spatial hexagon, relative to the fundamental effective vector. Spatial electric angle 4°; modulation ratio coefficient The calculation formula is as follows: ,in, The magnitude of the stator reference voltage vector. This is the DC bus voltage. The modulation ratio coefficient is denoted as ; substituting the values, the modulation ratio coefficient is obtained. for Based on the spatial voltage vector pulse width modulation projection geometry, the theoretical duration of the first effective voltage vector in the I-th sector required to synthesize the reference voltage vector is determined. With the theoretical duration of the second effective voltage vector The calculation formula is as follows: , ,in, The modulation ratio coefficient; For pulse width modulation carrier period, The stator reference voltage vector is relative to the base effective vector. Spatial electric angle, The theoretical duration of the first effective voltage vector. The theoretical duration of the second effective voltage vector is substituted into the numerical calculation to obtain... 0.0577×100μs× =4.78μs, 0.0577×100μs× =0.4μs; through numerical comparison, the theoretical duration of the first effective voltage vector is... The duration is 4.78 μs, which is greater than the effective sampling window threshold. At 1.8μs, the first effective voltage vector is in the safe sampling region; It is 0.4 μs, which is less than At 1.8μs, it is determined that the second effective voltage vector falls into the sampling blind zone; the pulse width deficit corresponding to the second effective voltage vector. The calculation formula is as follows: ,in, To set an effective sampling window threshold, The theoretical duration of the second effective voltage vector. The pulse width deficit is calculated by substituting the numerical values. The time is 1.8μs - 0.4μs = 1.4μs.

[0043] In the inverter bridge conduction topology, the second effective voltage vector When the upper arm MOSFETs of phases A and B are turned on and the lower arm MOSFET of phase C is turned on, the DC bus current corresponds to the reverse polarity of the stator current of phase C; extended second effective voltage vector. During the effective range, asymmetric micro-shifting is applied to the B-phase bridge arm drive pulse to extract the physical switching transition parameters of the metal-oxide-semiconductor field-effect transistor under the conditions of a bus voltage of 600V and a real-time internal PN junction temperature of 92℃. The gate turn-on propagation delay time caused by the change in the gate turn-on threshold is measured. The drain-source current rise time is 0.3 μs. The turnaround time is 0.1 μs, and the total turn-on conversion time is [not specified]. The gate turn-off propagation delay time is 0.4 μs. The drain-source current fall time is 0.35 μs. The turn-off switching time is 0.08 μs. The transient transition time difference is 0.43 μs due to the Miller effect and gate charge / discharge asymmetry. The calculation formula is as follows: ,in, This represents the total duration of the shutdown transition. The total conversion time is as follows: The transient transition time asymmetry difference is substituted into the numerical calculation to obtain... The pulse width deficit is 0.43μs - 0.4μs = 0.03μs; in the first half of the current carrier cycle, the pulse width deficit is shifted forward by the turn-on time of the upper bridge arm drive pulse of phase B. That is, 1.4 μs, to make the second effective voltage vector The conduction time of the bus sampling circuit reaches 1.8μs; in the symmetrical second half, the turn-off time of the upper bridge arm of phase B is cut off in advance, and the duration corresponding to the reverse volt-second balance cut-off is... The calculation formula is as follows: ,in, This refers to the pulse width deficit. This refers to the asymmetric difference in transient transition time. The duration corresponding to the reverse volt-second balance cutoff is calculated by substituting the numerical values. The time is 1.4μs - 0.03μs = 1.37μs, which cancels out the voltage element disturbance introduced by the asymmetrical transition time of the power transistor switch. The polarity correction of the reverse volt-second balance cutoff is based on the equivalent compensation mechanism of the volt-second integral of the terminal voltage during the power transistor switch transition process. During the turn-on stage of the power switch, the drain-source voltage experiences a linear decrease and a Miller plateau delay. Its actual output voltage loses the triangular voltage integral area determined by the total turn-on time during the rise edge establishment process. During the turn-off stage, the decrease in drain current and the hysteresis of voltage rise... The aftereffect causes the output voltage to form an additional trapezoidal tail delay area at the turn-off edge. When the drive pulse slightly shifts at the leading edge to widen the pulse width deficit, the turn-on delay itself reduces the effective conduction volt-second integral. When the turn-off is truncated at the trailing edge, the turn-off transition is prolonged, which postpones the physical turn-off. After deducting the transient transition time asymmetry difference from the truncation duration, the actual voltage time integral eliminated by the trailing edge truncation is equal in absolute algebraic value to the effective voltage time integral increased by the slight shift at the leading edge, thus eliminating the infinitesimal deviation introduced by the asymmetry of the trapezoidal transition waveform of the output voltage.

[0044] In the reorganized switch-drive timing, the microprocessor's on-chip timing comparator sets the hardware interrupt trigger time for the analog-to-digital converter; in the first effective voltage vector... Within the effective range, the trigger point is set 1.5μs after the vector start time to avoid the 1.2μs transient interference period caused by propagation delay, current rise, and oscillation decay. The analog-to-digital converter converts the voltage at the sampling resistor to obtain the first bus current. Its instantaneous sampling value is 45.2A; according to the inverter bridge conduction topology, the first effective voltage vector Under these conditions, the bus current flows directly into the A-phase winding, and the stator current of the motor's A-phase can be obtained. The value is 45.2A; in the extended second effective voltage vector Within the effective range, the trigger point is set 1.4 μs after the vector start time. At this time, the amplitude of the high-frequency parasitic oscillation has decayed to within the least significant bit conversion threshold of the analog-to-digital converter, and is in the stable current plateau segment. The analog-to-digital converter then converts the current to obtain the second bus current. Its instantaneous sampling value is 18.6A; according to the inverter bridge conduction topology, the bus current flows from phase C through the lower bridge arm back to the DC negative bus, and the stator current of phase C of the motor is obtained. The current is -18.6A. Based on Kirchhoff's current law for a three-phase symmetrical stator winding with the neutral point suspended, the formula for calculating the stator current of the third phase (B phase) is as follows: ,in, This refers to the stator current of phase A. This refers to the C-phase stator current. The B-phase stator current is obtained by substituting the values ​​into the numerical calculation. The current is -45.2A - (-18.6A) = -26.6A; the algebraic sum of the instantaneous currents of the three-phase stator satisfies 45.2A + (-26.6A) + (-18.6A) = 0A, which satisfies the constraint relationship of the algebraic sum of the instantaneous currents of the stator circuit. The reconstructed three-phase stator current is directly output to the inner loop of the field-oriented vector control current of the traction speed regulation system.

[0045] Based on the real-time temperature of the PN junction inside the power transistor and the DC bus voltage, the effective sampling window threshold is dynamically adjusted to reduce the pulse spread amplitude of the effective voltage vector under low modulation ratio conditions, thereby widening the linear modulation range of the inverter bridge. Combined with the correction of transient transition time asymmetry difference to eliminate the residual integral deviation of stator terminal voltage caused by drive pulse micro-shift, a low-distortion stator phase current continuous feedback signal is output under the DC bus single sampling resistor topology, suppressing stator flux drift and low-frequency electromagnetic torque pulsation, and maintaining stable torque output of the permanent magnet synchronous traction motor under low-speed starting conditions.

[0046] Example 2: On a permanent magnet synchronous traction transmission test platform, the controlled object is an AC permanent magnet synchronous traction motor with a rated power of 75kW. The rotor is rigidly connected to an AC dynamometer as a variable load source. The three-phase two-level inverter bridge uses six metal-oxide-semiconductor field-effect transistors with a rated withstand voltage of 1200V. The DC bus operating voltage is set to 600V, and the space voltage vector pulse width modulation carrier period is... The switching frequency is 100μs, corresponding to a switching frequency of 10kHz; a non-inductive manganese-copper alloy sampling resistor with a series resistance of 5mΩ and a parasitic inductance of less than 1nH is connected to the low-side busbar of the DC bus. It is used to collect bus return current. The microprocessor adopts a motor-specific digital signal processor that integrates a complementary pulse width modulation generator and a 12-bit analog-to-digital converter, and the aperture time conversion is... The differential nonlinearity error is less than half of the least significant bit, with a value of 0.6 μs. Three Hall effect current sensors with a measurement accuracy of 0.05% and a signal bandwidth of 100 kHz are connected in series at the three-phase stator output of the motor to synchronously record the three-phase physical current of the motor as a reference comparison signal. During the test, a power frequency fluctuation with a peak value of 15V and a frequency of 50Hz is superimposed on the DC bus voltage, and a Gaussian white noise interference signal with a signal-to-noise ratio of 25dB is injected at the input of the bus current sampling circuit to verify the working characteristics and filtering suppression performance of the system under non-ideal industrial environment.

[0047] The test conditions are adjusted according to a gradient, and the DC bus voltage is... Take 585V, 600V and 615V, power switch transistor case temperature The real-time internal PN junction temperatures were calculated using a first-order thermal impedance model at 35℃, 75℃, and 105℃. The temperatures are 48℃, 92℃, and 128℃, respectively; the stator reference voltage vector amplitude... The modulation ratio coefficient is adjustable within the range of 2V to 28V. The spatial electric angle is in the range of 0.0058 to 0.0808. Selected within the range of 2° to 30°, the sample group of this invention updates the effective sampling window threshold based on the real-time temperature of the internal PN junction and the DC bus voltage. And utilize the transient transition time asymmetry difference Corrected reverse volt-second balance cutoff duration Control group 1 uses the same dynamic effective sampling window threshold as the sample group of this invention, but lets... Control group 2 used an effective sampling window threshold of 2.2 μs, fixed under high temperature and high pressure conditions, and similarly set... Each group reads the signal across the single sampling resistor to calculate the three-phase stator current, then compares it with the reference current measured by the Hall effect current sensor, and records the maximum phase current reconstruction error, the total harmonic distortion rate of the stator current, and the electromagnetic torque ripple rate.

[0048] With a DC bus voltage of 600V and a modulation ratio coefficient The electric angle in space is 0.0577. The theoretical duration of the second effective voltage vector is 4°. Under the condition of 0.4 μs, the sampling timing was observed to change with temperature by first changing the power switch housing temperature. When the housing temperature was 35℃, the effective sampling window threshold of the sample group of this invention was 1.71 μs, the transient transition time asymmetry difference was 0.02 μs, the reverse volt-second balance cutoff time was 1.29 μs, corresponding to a maximum phase current reconstruction error of 0.62 A, a stator current total harmonic distortion rate of 2.15%, and an electromagnetic torque ripple rate of 3.2%. When the housing temperature rose to 75℃, the effective sampling window threshold was 1.8 μs, the transient transition time asymmetry difference was 0.03 μs, the reverse volt-second balance cutoff time was 1.37 μs, the maximum phase current reconstruction error was 0.68 A, and the stator current total harmonic distortion rate was... The electromagnetic torque ripple rate is 3.4% and the effective sampling window threshold is 1.87μs when the housing temperature rises to 105℃. The transient transition time asymmetry difference is 0.04μs, the reverse volt-second balance cutoff time is 1.43μs, the maximum phase current reconstruction error is 0.74A, the stator current total harmonic distortion rate is 2.41%, and the electromagnetic torque ripple rate is 3.6%. Within the above temperature range, the charging and discharging time constant of the parasitic capacitance of the metal oxide semiconductor field-effect transistor increases with the increase of junction temperature. The time required for the high-frequency parasitic oscillation to decay to within the least effective bit conversion threshold of the analog-to-digital converter also increases. The change in the Miller plateau duration is also reflected in the change in the transient transition time asymmetry difference.

[0049] Under the same 600V DC bus voltage, 0.0577 modulation ratio, 4° spatial electrical angle, and 0.4μs theoretical duration of the second effective voltage vector, control group 1 uses the same dynamic effective sampling window threshold as the sample group of this invention, but does not take into account the transient transition time asymmetry difference. When the shell temperature is 35°C, the effective sampling window threshold is 1.71μs. The value is 0, the reverse volt-second balance cutoff time is 1.31 μs, the maximum phase current reconstruction error is 1.84 A, the stator current total harmonic distortion rate is 5.12%, and the electromagnetic torque ripple rate is 8.7%; when the shell temperature is 75℃, the effective sampling window threshold is 1.8 μs. The value is 0, the reverse volt-second balance cutoff time is 1.4 μs, the maximum phase current reconstruction error is 2.36 A, the stator current total harmonic distortion rate is 6.45%, and the electromagnetic torque ripple rate is 11.2%; when the shell temperature is 105℃, the effective sampling window threshold is 1.87 μs. The value is 0, the reverse volt-second balance cutoff time is 1.47μs, the maximum phase current reconstruction error is 3.12A, the stator current total harmonic distortion rate is 8.23%, and the electromagnetic torque ripple rate is 14.6%. In this timing sequence, the switching transition delay difference is not deducted. The unidirectional integral bias of the terminal voltage generated after the drive pulse micro-shift accumulates with the increase of temperature. The corresponding phase current reconstruction error, stator current total harmonic distortion rate and electromagnetic torque ripple rate increase synchronously.

[0050] When changing the DC bus voltage and modulation state, under the conditions of a DC bus voltage of 585V, a casing temperature of 75℃, a modulation ratio of 0.0288, and a spatial electrical angle of 2°, the theoretical duration of the second effective voltage vector is 0.1μs, the effective sampling window threshold is 1.78μs, the transient transition time asymmetry difference is 0.03μs, and the reverse volt-second balance cutoff time is 1.65μs. Based on this, the maximum phase current reconstruction error is 0.81A, the stator current total harmonic distortion rate is 2.65%, and the electromagnetic torque is... The ripple rate is 3.9%. When the DC bus voltage is adjusted to 615V, the casing temperature is still 75℃, the modulation ratio is increased to 0.0808, and the spatial electric angle is 6°, the theoretical duration of the second effective voltage vector is 0.85μs, the effective sampling window threshold is 1.82μs, the transient transition time asymmetry difference is 0.03μs, the reverse volt-second balance cutoff duration is 0.94μs, the maximum phase current reconstruction error is 0.58A, the stator current total harmonic distortion rate is 2.08%, and the electromagnetic torque ripple rate is 3.1%.

[0051] Control group 2, under the conditions of DC bus voltage 600V, modulation ratio coefficient 0.0577, spatial electrical angle 4°, and theoretical duration of the second effective voltage vector 0.4μs, fixed an effective sampling window threshold of 2.2μs, and set... When the voltage is 0 and the casing temperature is 35℃, the reverse volt-second balance cutoff time is 1.8μs, the maximum phase current reconstruction error is 2.95A, the stator current total harmonic distortion rate is 7.82%, and the electromagnetic torque ripple rate is 13.8%. When the casing temperature is 75℃, the reverse volt-second balance cutoff time is still 1.8μs, the maximum phase current reconstruction error is 3.48A, the stator current total harmonic distortion rate is 8.96%, and the electromagnetic torque ripple rate is 15.4%. The fixed, longer effective sampling window threshold increases the pulse width expansion in the normal temperature and low load range, resulting in a decrease in the fundamental frequency utilization of the output voltage and an increase in harmonic components.

[0052] Under extremely low-speed, heavy-load conditions, the DC bus voltage is 600V, the casing temperature is 75℃, and the modulation ratio is... The voltage drop was reduced to 0.0058, the spatial electric angle was 30°, and the theoretical duration of both effective voltage vectors was shortened to 0.29 μs. Control group 1 also used a dual-cycle alternating pulse extension timing sequence to obtain the signals at both ends of the bus sampling resistor, but the transient transition time asymmetry difference was made to 0 during pulse truncation. The Hall effect current sensor at the output of the three-phase stator of the motor synchronously inputs the reference physical current signal into the digital oscilloscope. The digital oscilloscope captures the continuous stator physical current waveform and compares it with the three-phase reconstructed current discrete sequence obtained by solving the topology matrix based on the single sampling resistor signal through time axis synchronous interpolation. The discrete values ​​between the measured physical current and the reconstructed current are calculated point by point. In terms of absolute error, the effective sampling window threshold of the sample group of this invention under this operating condition is 1.8 μs, the transient transition time asymmetry difference is 0.03 μs, the reverse volt-second balance cutoff time is 1.48 μs, the maximum phase current reconstruction error is 0.95 A, the stator current total harmonic distortion rate is 2.89%, and the electromagnetic torque ripple rate is 4.2%. The effective sampling window threshold of control group 1 is also 1.8 μs, the transient transition time asymmetry difference is 0, the reverse volt-second balance cutoff time is 1.51 μs, the maximum phase current reconstruction error is 4.25 A, the stator current total harmonic distortion rate is 11.42%, and the electromagnetic torque ripple rate is 19.8%.

[0053] As the power switch housing temperature and DC bus voltage change, the sample group of this invention updates the effective sampling window threshold according to the real-time internal PN junction temperature and DC bus voltage, and corrects the reverse volt-second balance cutoff time based on the transient transition time asymmetry difference, so that the pulse width adjustment in the small vector interval is kept within the time range required to meet steady-state sampling, reducing the modulation range compression caused by excessive fixed delay margin; the reverse volt-second balance cutoff is used to offset the voltage integral residual bias formed at the end of the motor stator winding by the drive pulse micro-shift, reducing stator flux drift and phase current waveform distortion. Under low modulation ratio conditions, the dual-cycle alternating reconstruction and reverse flux bias compensation continue to be used to complete the bus current sampling and phase current reconstruction; the single sampling resistor signal is converted into stator phase current through the inverter bridge conduction topology and then compared synchronously with the reference physical current. The resulting reconstruction error, stator current total harmonic distortion rate and electromagnetic torque ripple rate show corresponding changes with the sampling sequence and compensation method of each group, and are used for phase current reconstruction and low harmonic closed-loop control in the entire operating range.

[0054] Example 3: The current permanent magnet synchronous traction motor frequency conversion speed control system adopts a three-phase two-level inverter bridge. The inverter bridge is composed of six metal-oxide-semiconductor field-effect transistors with a rated withstand voltage of 1200V. The rated operating voltage of the DC bus is set to 600V, and the space voltage vector pulse width modulation carrier period is... The switching frequency is 100μs, corresponding to a switching frequency of 10kHz; a non-inductive manganese-copper alloy sampling resistor with a series resistance of 5mΩ and a parasitic inductance of less than 1nH is connected to the low-side circuit of the DC bus. It is used to collect bus return current; the microprocessor is a dedicated digital signal processor for motors that integrates a complementary pulse width modulation generator and a 12-bit high-speed analog-to-digital converter. The analog-to-digital converter has a bidirectional sampling range of -100A to +100A, and the input signal conversion aperture time is... With a pulse width modulation (PWM) of 0.6 μs and a current resolution of 0.0488 A corresponding to the least significant bit, the theoretical duration of the effective voltage vector is compressed when the traction motor is in a low-speed, stable start-up or light-load speed regulation condition. The high-frequency switching of the metal-oxide-semiconductor field-effect transistor (MOSFET) is accompanied by rapid changes in drain-source voltage and current. The drain-source parasitic output capacitance and the stray inductance of the inverter bridge bus circuit exhibit high-frequency underdamped resonance, generating a continuous oscillating current spike lasting hundreds of nanoseconds across the sampling resistor, making it difficult to form a stable current plateau in the small vector range. Simultaneously, the power switch's turn-on and turn-off processes are affected by the gate charging and discharging impedance and the Miller plateau duration, resulting in a transient transition time asymmetry. After the drive pulse is symmetrically shifted, a residual deviation in the volt-second integral of the terminal voltage is generated. Based on this, the microprocessor combines the high-frequency parasitic oscillation decay time, the transient transition time asymmetry, and the sampling steady-state discrimination result to reconstruct the phase current.

[0055] The microprocessor reads the output of the DC bus voltage sampling and conditioning circuit at the beginning of each switching cycle to obtain the measured value of the bus voltage. Simultaneously, the signal from the thermistor mounted on the copper substrate for heat dissipation of the power switching transistor is read to obtain the case temperature. The transient thermal resistance model employs a first-order transient thermal impedance discrete update structure. It calculates transient conduction losses based on the on-current and on-resistance of the power switch, and combines this with the switching frequency and switching energy to calculate transient switching losses. Finally, it substitutes the heat generated by the losses into the relationship between thermal resistance and the time constant of thermal capacity, and applies this to the casing temperature. Perform temperature rise correction and calculate the real-time temperature of the PN junction inside the power switch transistor. The process involves equating the chip to the heat sink substrate as a first-order thermal network composed of parallel thermal resistance and thermal capacitance. The equivalent junction-to-case thermal resistance is preset to 0.32℃ / W, and the equivalent thermal capacitance time constant is 18ms. At the start of the current carrier cycle, the microprocessor extracts the effective value of the three-phase stator current reconstructed in the previous switching cycle and uses it as the on-state current input for the current cycle. The square of the on-state current is multiplied by the on-resistance of the power transistor to obtain the transient on-state loss, which is then added to the off-state loss to obtain the total power loss. The total power loss is multiplied by the equivalent junction-to-case thermal resistance to obtain the steady-state temperature rise component. This component is then combined with the estimated junction temperature increment from the previous discrete cycle and the first-order discrete attenuation coefficient determined by the thermal capacitance time constant to perform differential recursive filtering, resulting in the transient temperature rise of the chip relative to the substrate. This temperature rise is then superimposed on the measured casing temperature to obtain the real-time temperature of the internal PN junction. .

[0056] At the current bus voltage Real-time temperature of internal PN junction Under these conditions, the microprocessor extracts the drain-source parasitic output capacitance value of the metal-oxide-semiconductor field-effect transistor. The capacitor has a 35nH stray inductance in the inverter bridge bus circuit. and the high-frequency equivalent damping resistance of the bus circuit is 0.088Ω. Constructing a second-order series resonant damped system, the decay time constant The stray inductance is 0.795 μs, obtained by dividing twice the stray inductance by the damping resistance. The stray inductance and high-frequency equivalent damping resistance of the inverter bridge bus circuit are obtained through offline calibration of the high-frequency impedance characteristics at the factory: all decoupling capacitor pins at the DC bus end of the inverter bridge are physically shorted using low-resistance silver-plated copper busbars. A precision impedance analyzer is connected to both ends of the copper busbars of the upper and lower bridge arms DC input busbars, and a frequency sweep measurement is performed under a 10MHz high-frequency sinusoidal excitation signal. The impedance analyzer extracts the measured inductive reactance component and divides it by the angular frequency to obtain the equivalent series stray inductance of the circuit, 35nH. At the same time, the real resistance component formed by the skin effect of the high-frequency current and the contact resistance of the copper busbars at this frequency is extracted to obtain the equivalent damping resistance, 0.088Ω. The above calibration values ​​are written as constants into the microprocessor parameter storage space.

[0057] The microprocessor uses the attenuation of the high-frequency parasitic oscillation current envelope amplitude to below half the least significant bit conversion threshold of the analog-to-digital converter (ADC), 0.0244A, as the steady-state sampling condition. After entering the free damping stage dominated by busbar parasitic parameters, the peak value of the oscillation envelope at the beginning of this stage is taken as the initial oscillation spike current peak value. The ratio of this to the conversion threshold is taken as the natural logarithm, and then divided by the decay time constant. Multiplying these together yields the decay time of the high-frequency parasitic oscillations. ; at bus voltage 600V, internal PN junction real-time temperature The drain-source parasitic output capacitance value at 92℃ The calibration is 180pF, corresponding to the high-frequency parasitic oscillation decay time. Within the initial 200ns of the switching transition, the drain-source voltage of the power switch is established at 0.8μs. The gate push-pull transistor in the drive circuit operates in the active variable resistance region and provides dynamic damping, suppressing the initial high-frequency current surge amplitude of tens of amperes to below 0.15A. 0.15A is the upper limit of the envelope amplitude before entering the subsequent free damping stage. Under this upper limit condition, the residual oscillation current envelope can decay to below the 0.024A transition threshold after about twice the time constant. This is used to verify the decay boundary of the free damping stage. The actual high-frequency parasitic oscillation decay time is still calculated based on the envelope peak value obtained at the beginning of the free damping stage and the 0.0244A transition threshold, thus corresponding to the 0.8μs calculation result under the current operating condition. The microprocessor will then use the gate drive propagation delay time. The drain-source current rise time is 0.3μs. The decay time of high-frequency parasitic oscillations is 0.1 μs. For 0.8μs and the hardware sampling hold aperture time of the analog-to-digital converter The effective sampling window threshold is obtained by incrementing the threshold by 0.6 μs. It is 1.8 μs.

[0058] At the start of each pulse width modulation carrier cycle, the microprocessor acquires the stator reference voltage vector amplitude. and its spatial electric angle The theoretical duration of the first effective voltage vector of the current sector is calculated based on the spatial voltage vector pulse width modulation projection geometry. Second effective voltage vector theoretical duration ,Will and respectively with the effective sampling window threshold In comparison, when the theoretical duration of the target effective voltage vector is less than At that time, with The difference obtained by subtracting the theoretical duration is used as the pulse width deficit. To correct the volt-second integral deviation caused by the slight shift of the drive pulse edge, the microprocessor calls the two-dimensional discrete mapping grid of the device switching transition delay pre-stored in the on-chip memory, using the real-time bus voltage... Real-time temperature of internal PN junction To retrieve the index, extract the total turn-on switching time of the target phase metal-oxide-semiconductor field-effect transistor at the current operating point. Total duration of shutdown transition The total turn-on transition time is comprised of the gate turn-on propagation delay time. With drain-source current rise time The total turn-off transition time is obtained by summing up the gate turn-off propagation delay time. With drain-source current fall time The summation is then used to subtract the total activation time from the total shutdown conversion time to obtain the transient transition time asymmetry difference. The differential value is based on the forward flow of the stator phase current out of the inverter bridge arm as the physical reference direction. In each cycle, the microprocessor adaptively assigns a sign to this differential value based on the current phase current polarity. When the phase current is forward flowing out, the total turn-off time is greater than the total turn-on time, and a positive value of 0.03 μs is taken. When the reverse freewheeling condition causes the total turn-on time to be greater than the total turn-off time, a negative differential value is adaptively output and converted into an equivalent algebraic sum in the cutoff timing. Simultaneously, the microprocessor sets a numerical limiting boundary of 0 μs to 0.1 μs to prevent the physical quantity from exceeding the limit. At a bus voltage of 600V and a real-time internal PN junction temperature of 92℃, the total turn-on conversion time is read. The total turn-off switching time is 0.4 μs. The transient transition time asymmetry difference was obtained at 0.43 μs. It is 0.03 μs.

[0059] For the target effective voltage vector falling into the sampling blind zone, the microprocessor slightly shifts the turn-on time of the target phase MOSFET drive pulse forward by a pulse width deficit during the first half of the current carrier cycle. This expands the physical conduction window of the target effective voltage vector in the bus circuit to the effective sampling window threshold. The space voltage vector pulse width modulation employs a seven-segment symmetrical timing sequence. The reference conduction sequence within a sector is symmetrically composed of a zero vector, a first effective voltage vector, a second effective voltage vector, and a central zero vector. During the first half-cycle, when the turn-on time of the B-phase drive pulse is slightly shifted forward by a pulse width deficit, the corresponding time is obtained from the duration of the adjacent zero vector to complete the broadening of the second effective voltage vector, while the duration of the first effective voltage vector remains unchanged. During the symmetrical second half-cycle, when the B-phase drive pulse is prematurely truncated, the deducted time is returned to the adjacent zero vector interval. The switching times of the A-phase and C-phase drive pulses remain at their original calculated values ​​throughout the entire cycle. This ensures that the line voltage volt-second integral of the three-phase phase voltages throughout the entire switching cycle corresponds to the theoretical projected area of ​​the original reference voltage vector on the two orthogonal coordinate axes. Simultaneously, during the symmetrical second half-cycle of the current cycle, a reverse volt-second balance truncation is applied to the slightly shifted phase bridge arm drive pulse, with a duration equal to the pulse width deficit. Deducting transient transition time asymmetry difference The result It is used to correct the residual bias of voltage integral formed at the stator end of the motor by the micro-shift of the drive pulse.

[0060] In the microprocessor's underlying register configuration, the timer / counter adopts a symmetrical increment / decrement counting mode. The first comparison matching register is used for the turn-on edge control during the triangular wave increment counting phase, and the second comparison matching register is used for the turn-off edge control during the triangular wave decrement counting phase. In the interrupt event when the counter reaches the bottom of the cycle, the preset value of the first comparison matching register is subtracted from the clock pulse counting step size corresponding to the pulse width deficit, causing the turn-on comparison event to occur earlier and complete the leading edge broadening. In the interrupt event when the counter reaches the top of the cycle, the preset value of the second comparison matching register is increased by the clock pulse counting step size corresponding to the reverse volt-second balance truncation duration, causing the turn-off comparison event to be triggered earlier and complete the finishing edge truncation. The hardware dead-time generation unit built into the pulse width modulation module maintains complementary output latch-up throughout the entire drive timing and automatically inserts a preset dead-time at the switching transition edge, so that the upper and lower power switches of the same bridge arm remain interlocked during the asymmetric modulation of the drive edge.

[0061] Within the stable operating range of the effective voltage vector after micro-shift adjustment, the on-chip timing comparison unit of the microprocessor ends at the drive transition edge and passes through... After a timing accumulation delay, a hardware sampling interrupt trigger signal is issued. The analog-to-digital converter (ADC) then starts continuous discrete conversion, continuously reading eight discrete current sampling points at a sampling frequency of 20MHz within the conversion time window. The time interval between adjacent discrete sampling points is 50ns. The microprocessor sequentially calculates the absolute value of the current difference between adjacent discrete sampling points, divides it by the 50ns sampling time interval to obtain the absolute value of the difference slope, and compares it with the preset steady-state threshold of 0.5A / μs. The preset steady-state threshold of 0.5A / μs is determined based on the transient current change boundary of the traction motor stator winding and the quantization noise amplitude of the ADC. The stator phase leakage inductance of the traction motor is 4.2mH. Under full voltage loading conditions of 600V DC bus voltage, the maximum theoretical rise slope of the stator armature physical current during the effective voltage vector action period is 0.143A / μs. The current resolution of the 12-bit analog-to-digital converter is 0.0488A. Under a sampling period of 50ns, the upper limit of the discrete difference slope corresponding to half of the least significant bit quantization white noise is 0.244A / μs. The linear superposition of the two yields the total fluctuation limit of 0.387A / μs in the normal stable phase, which is then adjusted upward to 0.5A / μs according to 1.3 times the industrial disturbance rejection safety margin.

[0062] When the absolute value of the slope of the difference between three consecutive sampling points in the discrete sampling sequence is continuously less than the preset steady-state threshold of 0.5A / μs, the microprocessor will take the arithmetic mean of the discrete sampling points within the threshold and output the resulting bus current to the subsequent topology mapping step; when the absolute value of the slope of the difference between adjacent discrete sampling points is greater than or equal to the preset steady-state threshold of 0.5A / μs, the current sampling conversion value is filtered out, and the phase current output value of the previous pulse width modulation cycle is maintained to avoid transient high-frequency spikes from entering the traction motor vector control current closed loop.

[0063] During the zero-speed heavy-load torque holding phase or the initial phase of low-speed smooth start-up, the modulation ratio coefficient Approaching zero, the theoretical duration of the first effective voltage vector With the theoretical duration of the second effective voltage vector At the same time, it is less than the effective sampling window threshold. The control system performs a two-cycle alternating measurement, in the first cycle... Within each pulse width modulation carrier cycle, the original pulse width of the second effective voltage vector remains unchanged, and only the phase bridge arm drive pulse corresponding to the first effective voltage vector is subjected to unilateral widening, so that the duration of the first effective voltage vector reaches the effective sampling window threshold. Within this effective range, the first bus current is collected based on the comparison between the absolute value of the difference slope and the preset steady-state threshold. ; in the adjacent first Within each pulse width modulation carrier cycle, the original pulse width of the first effective voltage vector remains unchanged, and unilateral widening is applied only to the phase bridge arm drive pulse corresponding to the second effective voltage vector, so that the duration of the second effective voltage vector reaches the effective sampling window threshold. And collect the second bus current within this operating range. .

[0064] In the Within each carrier cycle, the microprocessor calculates the transient transition time asymmetry difference based on the current calculation. Correct the pulse cutoff time and apply a virtual inverted vector; at the... Within each carrier cycle, the transient transition time asymmetry difference is also calculated based on the current period's solution. The pulse cutoff time is corrected, and a virtual antiphase vector in opposite directions is applied. The virtual antiphase vectors in two consecutive carrier cycles act in opposite directions, causing the volt-second effects of the line voltage formed in the two cycles to cancel each other out. This limits the accumulation of stator synthetic flux position shift caused by single-cycle unilateral broadening and ensures that the first bus current obtained under low modulation ratio conditions is... Second bus current It can continue to be used for three-phase stator current reconfiguration.

[0065] Example 4: This example combines Figures 1 to 2 This paper describes a phase current reconstruction method for permanent magnet synchronous traction variable frequency speed regulation, such as... Figure 1 As shown, in step S1, the DC bus voltage and the metal-oxide-semiconductor (MOSFET) casing temperature are collected to calculate the internal junction temperature. The high-frequency parasitic oscillation decay time is determined by combining the DC bus voltage and the internal junction temperature. The drive delay time, current rise time, high-frequency parasitic oscillation decay time, and sampling and holding time are accumulated to determine the effective sampling window threshold. In step S2, the theoretical duration of the two effective voltage vectors of space vector modulation is obtained. In step S3, when the theoretical duration of the effective voltage vectors is less than the effective sampling window threshold, the pulse width deficit is determined, and the total turn-off transition time and total turn-on transition time of the target phase MOSFET are calculated. The difference is used as the transient transition time asymmetry difference. The pulse width deficit is shifted forward by the turn-on time of the target phase drive pulse. During the compensation period, a reverse volt-second balance cutoff is applied with a cutoff duration equal to the pulse width deficit minus the transient transition time asymmetry difference. In step S4, after the high-frequency parasitic oscillation decays to the steady-state threshold, a single-sample resistor signal is acquired in the action interval of the two effective voltage vectors to obtain the first bus current and the second bus current. In step S5, the first bus current and the second bus current are converted into two-phase stator currents according to the inverter bridge conduction topology. The third-phase stator current is calculated based on the fact that the sum of the three-phase stator currents is zero and output to the vector control loop.

[0066] like Figure 2As shown, the DC bus voltage and the temperature of the metal-oxide-semiconductor field-effect transistor casing, together with the high-frequency parasitic oscillation decay time, jointly determine the effective sampling window threshold. The total turn-off transition time and the total turn-on transition time are used to calculate the transient transition time asymmetry difference, and combined with the transient transition time asymmetry difference, the reverse volt-second balance cutoff is determined. The stator reference voltage vector amplitude and the spatial electric angle are used in space vector modulation to calculate and determine the theoretical duration of the first effective voltage vector. Based on the absolute value of the difference slope, the single sampling resistor signal is sampled and judged to be stable. The acquired current is combined with the inverter bridge conduction topology and the algebraic sum of the three-phase instantaneous current is always zero for calculation. The above control elements work together to realize the phase current reconstruction of permanent magnet synchronous traction variable frequency speed regulation.

[0067] Example 5: The current inverter system uses a metal-oxide-semiconductor field-effect transistor (MOSFET) dual-pulse inductive load test circuit during the factory calibration and initial control parameter installation stage. The test circuit is placed in a temperature-controlled test chamber. The DC bus power supply output voltage is discretely scanned in 20V steps within the range of 540V to 660V. The temperature-controlled test chamber is kept constant in 25℃ increments within the range of 25℃ to 150℃. The test system uses a high-voltage differential voltage probe and a coaxial shunt to collect the transient waveforms of the gate-source voltage, drain-source voltage, and drain current of the MOSFET.

[0068] For each voltage and temperature cross-test node, the microprocessor records the time from the rising edge of the drive signal crossing the threshold to the drain-source voltage dropping to 90% of the steady-state value, which is used as the gate turn-on propagation delay time. Record the time it takes for the drain current to rise from 10% to 90% of its steady-state value as the drain-source current rise time. The total activation and conversion time is obtained by adding the two together. The microprocessor simultaneously records the time from the falling edge of the drive signal crossing the threshold to the drain-source voltage rising to 10% of the steady-state value, as the gate turn-off propagation delay time. Record the time it takes for the drain current to decrease from 90% to 10% of its steady-state value; this is taken as the drain-source current fall time. The sum of the two yields the total shutdown transition time. At the test node with a DC bus voltage of 600V and a real-time internal PN junction temperature of 92℃, the gate turn-on propagation delay time was measured. The drain-source current rise time is 0.3 μs. The value is 0.1 μs. Substituting this into the formula, we obtain the total activation and conversion time. The gate turn-off propagation delay time was measured to be 0.3μs + 0.1μs = 0.4μs. The drain-source current fall time is 0.35 μs. The value is 0.08 μs. Substituting this into the formula, we obtain the total turn-off transition time. The time difference is 0.35μs + 0.08μs = 0.43μs; subtracting the two gives the transient transition time asymmetry difference. The result is 0.43μs - 0.4μs = 0.03μs.

[0069] The total turn-on transition time, total turn-off transition time, and high-frequency parasitic oscillation decay time under different reverse bias voltage and temperature conditions were obtained from each test node. The data is compiled into a two-dimensional calibration lookup grid and pre-written into the non-volatile memory of the main control chip for real-time linear interpolation. In the offline dual-pulse test circuit, a non-inductive metal film drive resistor with a series resistance of 5.1Ω is used for the gate of the power switch. The drive chip adopts push-pull output with a maximum transient sink-pull current specification of 4A. The two-dimensional calibration lookup grid has 7 sampling nodes from 540V to 660V in the voltage dimension and 6 sampling nodes from 25℃ to 150℃ in the temperature dimension, thus forming 42 calibration grid cells. During the online operation of the variable frequency speed control, the microprocessor extracts the DC bus voltage and the real-time temperature of the internal PN junction of the current cycle, locks the 4 neighboring calibration coordinates surrounding the current operating point in the two-dimensional calibration lookup grid, and then uses a bilinear interpolation algorithm to perform linear weighted calculations on the voltage axis and temperature axis in sequence to obtain the total turn-on transition time and the total turn-off transition time under the current operating condition.

[0070] During the initialization preparation phase of each power-on start-up of the traction inverter before the output of drive pulses, the microprocessor sends a 000 zero-vector control timing signal (all lower bridge arms are turned on) to the inverter bridge, causing the current flowing through the single sampling resistor on the DC bus to... The physical current is in a zero-input reference state; the on-chip analog-to-digital converter continuously samples the output voltage of the conditioning channel across the sampling resistor at a sampling frequency of 20MHz, obtaining a total of 64 discrete points. The voltage of the 64 sampling points is accumulated and divided by the number of sampling points 64 to obtain the hardware zero-point bias voltage value. The value is stored in the static bias correction register. During the closed-loop operation of the traction variable frequency speed control, whenever the space voltage vector pulse width modulation enters the zero vector duration interval, the microprocessor periodically triggers a single sampling and uses a moving window smoothing filter to dynamically refresh the bias voltage value. It is used to subtract the analog front-end temperature drift bias caused by temperature accumulation and device aging.

[0071] Within the zero-vector pure noise floor range, the microprocessor calculates the envelope of the ratio of the current jump amplitude of adjacent discrete sampling points to the 50ns sampling interval, extracts the peak noise fluctuation slope under the current electromagnetic interference environment, and uses a safety margin coefficient to verify the preset steady-state threshold of 0.5A / μs used to determine the sampling steady state during the effective voltage vector action period, in order to adapt to the individual discreteness of hardware devices and long-term environmental changes. In this verification process, the safety margin coefficient is preset to 2.8; during the zero-vector period when all lower bridge arms of the inverter bridge are in conduction, the current of the discrete sampling points with floor noise generated by thermal noise and spatial electromagnetic radiation. In the slope envelope, the measured peak slope of the background noise is in the range of 0.14 A / μs to 0.17 A / μs. Multiplying the measured peak slope of the background noise by a safety margin factor of 2.8, the resulting dynamic product is in the range of 0.392 A / μs to 0.476 A / μs, which is less than the preset steady-state threshold of 0.5 A / μs. At this time, the preset steady-state threshold of 0.5 A / μs is kept unchanged. When a strong external sudden interference causes the product value to exceed 0.5 A / μs, the microprocessor updates the preset steady-state threshold upward to the product value, so that the sampling steady-state criterion adapts to the current environmental background noise level.

[0072] Example 6: After the permanent magnet synchronous traction variable frequency speed control system enters the near-zero speed heavy load condition, the modulation ratio coefficient Approaching zero, the magnitude of the stator reference voltage vector Drop to 2V, space electric angle 30°, DC bus voltage 600V, space voltage vector pulse width modulation carrier period 100μs; theoretical duration of the first effective voltage vector With the theoretical duration of the second effective voltage vector All are 0.29 μs, less than the effective sampling window threshold of 1.8 μs. When two effective voltage vectors simultaneously enter the sampling dead zone during the current switching cycle, the pulse width deficit is... and The duration is 1.8μs - 0.29μs = 1.51μs. To reduce the repeated switching between single-vector micro-shift and dual-cycle alternating measurement near the switching boundary, the control system sets a switching hysteresis half-width of 0.1μs. When the theoretical duration of both effective voltage vectors is less than 1.7μs, dual-cycle alternating measurement is entered until the theoretical duration of at least one effective voltage vector rises back to above 1.9μs, at which point the system exits. This 0.1μs hysteresis half-width is determined based on the discrete jitter amplitude of the output voltage vector in steady-state control by the current loop regulator. When the traction inverter performs current loop closed-loop calculation at a frequency of 10kHz, the DC bus power frequency fluctuation and rotor magnetic pole harmonics cause the calculated value of the stator reference voltage vector to fluctuate between adjacent carrier cycles. The maximum random jitter amplitude of the corresponding effective voltage vector theoretical duration is 0.038μs. The 0.1μs hysteresis half-width is approximately 2.6 times the single-cycle timing disturbance limit amplitude and accounts for only 0.1% of the 100μs modulation carrier cycle.

[0073] In the During each pulse width modulation carrier cycle, the microprocessor maintains the second effective voltage vector in state 110. The duration of action remains unchanged, only affecting the first effective voltage vector with a state of 100. A unilateral broadening is applied, extending its duration to 1.8 μs, and the first bus current is sampled within the first effective voltage vector's action interval. Subsequently, a virtual inverted vector with a state of 011 is inserted. Its duration of action is 1.51 μs pulse width deficit minus 0.03 μs transient transition time asymmetry difference. The obtained 1.48 μs, in the adjacent first... Maintain the first effective voltage vector within each pulse width modulation carrier cycle. The original duration of action remains unchanged, only the second effective voltage vector A unilateral broadening is applied, extending its duration to 1.8 μs, and the second bus current is sampled within the second effective voltage vector's action range. The insertion direction within this period is the same as the first... The virtual inversion vectors of opposite directions are used in two consecutive carrier cycles. Their switching state is 100 and their duration is also 1.48μs. Thus, the virtual inversion vectors used in two consecutive carrier cycles are in opposite directions.

[0074] In the driving timing implementation, the pulse width modulation generator inserts a virtual inverted vector during the zero-vector period of the symmetrical transmission interval. The microprocessor, by reloading the phase bridge arm comparison matching register, enables the three-phase bridge arms to sequentially perform switching transitions after the corresponding effective voltage vector sampling is completed, and loads the preset virtual inverted vector switching state to the drive output pin. During state switching, the hardware dead-time generation unit inserts a 300ns hardware blanking dead time between the complementary drive signals of the upper and lower bridge arms, so that the upper and lower power switches of the same bridge arm remain interlocked. The duration of the virtual inverted vector is locked to 1.48μs by the auxiliary timing comparator. After the set time is reached, the switching state switching with dead-time protection is performed again and the system returns to the zero-vector platform. The virtual inverted vectors with opposite directions in two consecutive carrier cycles form line voltage volt-second effects of opposite polarities, so that the compensation effects of the two cycles cancel each other out and limit the accumulation of stator synthetic flux position offset caused by the double-cycle single-sided broadening.

[0075] Under extremely low modulation ratio conditions, the fundamental frequency of the motor stator current is typically below 3Hz, with a fundamental period exceeding 330ms, while the modulation carrier period is 100μs. The 100μs time difference between two consecutive carrier periods accounts for less than 0.03% of the motor's electrical time scale. Simultaneously, the traction motor stator winding exhibits smoothing inductance characteristics of tens of mH, and the stator physical current changes continuously and gradually within adjacent switching cycles. When the microprocessor combines the bus current obtained from two consecutive carrier periods, it uses first-order Taylor linear interpolation to perform phase normalization and alignment of the current values ​​of the two periods, obtaining the transient three-phase balance value corresponding to the same moment. The duration of the virtual anti-phase vector within a single period is 1.48μs. Under the combined action of the motor's mechanical inertia and the stator winding inductance, the resulting high-frequency torque ripple is superimposed on the stator flux linkage. The high-frequency components cancel each other out after reverse compensation in two consecutive carrier periods, and the fundamental flux linkage trajectory remains continuous.

[0076] To address the interference caused by transient voltage fluctuations on the bus during traction operation, the analog-to-digital converter continuously reads eight discrete current sampling points at a sampling frequency of 20MHz within the effective sampling window, with a time interval of 50ns between adjacent sampling points. The microprocessor calculates the absolute value of the current difference between adjacent sampling points, divides it by 50ns to obtain the absolute value of the difference slope, and then compares it with a preset steady-state threshold of 0.5A / μs. When the absolute value of the difference slope is greater than or equal to 0.5A / μs, the microprocessor filters out the current sampled conversion value and resets the continuous abnormal cycle counter. Increment by 1 and maintain the phase current output value of the previous cycle within the current carrier cycle; continuous abnormal cycle tolerance threshold. Set to 3, when If the value does not exceed 3, the historical effective phase current output will continue to be maintained.

[0077] When the continuous abnormal cycle tolerance threshold is set to 3, at a switching frequency of 10kHz, three abnormal cycles correspond to 300μs. The electrical time constant of the traction motor stator winding is greater than 15ms, and the current loop closed-loop step response time constant is approximately 2.5ms. The 300μs historical data hold time accounts for approximately 12% of this step response time constant. Within this time window, the actual physical current amplitude drift of the motor stator is less than 0.5%. When the continuous abnormal cycle tolerance threshold is less than 3, the hold period for single pulse spike interference is correspondingly shortened. When the threshold is greater than 3, the historical current hold time continues to extend, increasing the possibility of current loop regulation overshoot. Therefore, in this embodiment, the continuous abnormal cycle tolerance threshold is... 3.

[0078] When the continuous abnormal cycle counter When the value exceeds 3, the microprocessor switches to the state estimation logic based on the motor back EMF equation. The estimated phase current participates in the closed-loop speed regulation. The state estimation logic operates in the two-phase stationary coordinate system, extracts the stator reference voltage component of the current cycle, subtracts the impedance voltage drop caused by the motor stator rated resistance and stator transient inductance, and differentially calculates the discrete integral value of the back EMF vector on each coordinate axis. Combined with the initial flux linkage constant of the permanent magnet rotor, the current state estimation component in the stator rotating coordinate system is recursively obtained. Then, the estimated three-phase stator current is output through coordinate inverse transformation and used as the continuous feedback input of the inner loop of vector control.

[0079] During subsequent sampling, when the absolute value of the slope of the difference between three consecutive sampling points remains less than 0.5 A / μs, the microprocessor determines that the bus current has returned to a stable state and clears the continuous abnormal cycle counter. The system switches back to the phase current reconstruction link with a single sampling resistor. During the switching process, the current estimated current value is used as a reference, and a linear weight transition is adopted in the next 5 carrier cycles. The weighting ratio of the actual sampling reconstruction current increases by 20% per cycle, and the weight of the estimated current decreases synchronously until the actual sampling reconstruction current completely replaces the estimated current, thereby reducing the current step caused by direct switching between the two current feedbacks.

[0080] The embodiments of this application have been described above with reference to the accompanying drawings. Unless otherwise specified, the embodiments and features in the embodiments of this application can be combined with each other. This application is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many other forms under the guidance of this application without departing from the spirit of this application and the scope of protection of this invention, and all of these forms are within the protection scope of this application.

Claims

1. A method for reconstructing phase current in permanent magnet synchronous traction variable frequency speed regulation, characterized in that, Includes the following steps: Step S1: Collect the DC bus voltage and the metal-oxide-semiconductor field-effect transistor case temperature to calculate the internal junction temperature. Combine the DC bus voltage and the internal junction temperature to determine the high-frequency parasitic oscillation decay time. Accumulate the drive delay time, current rise time, high-frequency parasitic oscillation decay time and sampling hold time to determine the effective sampling window threshold. Step S2: Obtain the theoretical duration of the two effective voltage vectors of space vector modulation; Step S3: When the effective voltage vector theoretical duration is less than the effective sampling window threshold, determine the pulse width deficit. Calculate the difference between the total turn-off transition time and the total turn-on transition time of the target phase metal-oxide-semiconductor field-effect transistor as the transient transition time asymmetry difference. Move the turn-on time of the target phase driving pulse forward by the pulse width deficit. Apply a reverse volt-second balance truncation with a truncation duration equal to the pulse width deficit minus the transient transition time asymmetry difference during the compensation period. Step S4: After the high-frequency parasitic oscillation decays to the steady-state threshold, a single-sample resistor signal is acquired in the action range of the two effective voltage vectors to obtain the first bus current and the second bus current. Step S5: Based on the inverter bridge conduction topology, the first bus current and the second bus current are converted into two-phase stator currents. The third-phase stator current is calculated based on the fact that the sum of the three-phase stator currents is zero, and then output to the vector control loop.

2. The phase current reconstruction method for permanent magnet synchronous traction variable frequency speed regulation according to claim 1, characterized in that, Step S1 combines the DC bus voltage and internal junction temperature to determine the high-frequency parasitic oscillation decay time, including: Step S11, calculating the internal junction temperature based on the metal-oxide-semiconductor field-effect transistor case temperature using a transient thermal resistance model; Step S12, extracting the drain-source parasitic output capacitance value based on the DC bus voltage and internal junction temperature, and determining the high-frequency oscillation frequency and decay time constant by combining it with the stray inductance of the inverter bridge bus circuit; Step S13, calculating the time it takes for the high-frequency oscillation current amplitude to decay to within the least significant bit conversion threshold of the analog-to-digital converter, and determining this as the high-frequency parasitic oscillation decay time.

3. The phase current reconstruction method for permanent magnet synchronous traction variable frequency speed regulation according to claim 1, characterized in that, Step S3 calculates the difference between the total turn-off transition time and the total turn-on transition time of the target phase MOSFET as the transient transition time asymmetry difference, including: Step S31, extracting the gate turn-on propagation delay time and drain current rise time of the target phase MOSFET under the current DC bus voltage and internal junction temperature, and adding the two to obtain the total turn-on transition time; Step S32, extracting the gate turn-off propagation delay time and drain current fall time of the target phase MOSFET under the current DC bus voltage and internal junction temperature, and adding the two to obtain the total turn-off transition time; Step S33, calculating the time difference obtained by subtracting the total turn-on transition time from the total turn-off transition time, and determining it as the transient transition time asymmetry difference.

4. The phase current reconstruction method for permanent magnet synchronous traction variable frequency speed regulation according to claim 1, characterized in that, Step S2 involves obtaining the theoretical durations of the two effective voltage vectors in space vector modulation, including: Step S21, obtaining the stator reference voltage vector amplitude and spatial electrical angle sent by the traction speed regulation current loop regulator at the start of the current pulse width modulation carrier period; Step S22, determining the basic hexagonal sector in space where the stator reference voltage vector is located based on the spatial electrical angle; Step S23, calculating the theoretical durations of the first and second effective voltage vectors in the current sector required to synthesize the stator reference voltage vector based on the geometric relationship of the space voltage vector pulse width modulation projection.

5. The phase current reconstruction method for permanent magnet synchronous traction variable frequency speed regulation according to claim 1, characterized in that, In step S4, after the high-frequency parasitic oscillation decays to the steady-state threshold, a single-sample resistor signal is acquired within the two effective voltage vector action intervals. This includes: Step S41, within the first effective voltage vector action interval after micro-shift adjustment, setting the sampling trigger time to the stable current plateau segment after the switch state transition ends and after the drive delay time, current rise time, and high-frequency parasitic oscillation decay time, triggering the analog-to-digital converter to read the voltage across the single-sample resistor and calculate the first bus current; Step S42, within the second effective voltage vector action interval after micro-shift expansion, after the drain-source high-frequency oscillation amplitude decays into the least effective bit conversion threshold of the analog-to-digital converter, triggering the analog-to-digital converter to read the voltage across the single-sample resistor and calculate the second bus current.

6. The phase current reconstruction method for permanent magnet synchronous traction variable frequency speed regulation according to claim 1, characterized in that, Step S5 converts the first bus current and the second bus current into two-phase stator currents based on the inverter bridge conduction topology, including: Step S51, reading the switching state combination of the current pulse width modulation cycle, and determining the bus current return path according to the physical on / off state of the metal-oxide-semiconductor field-effect transistors of the upper and lower arms of the three-phase inverter bridge; Step S52, when the first effective voltage vector is the basic effective vector of the I-th sector, assigning the measured first bus current to the A-phase stator current of the motor; Step S53, when the second effective voltage vector is the adjacent effective vector of the I-th sector, assigning the measured reverse polarity value of the second bus current to the C-phase stator current of the motor; Step S54, calculating the B-phase stator current based on the constraint that the algebraic sum of the three-phase instantaneous currents is always zero, satisfied by the floating structure of the neutral point of the three-phase stator windings of the motor.

7. The phase current reconstruction method for permanent magnet synchronous traction variable frequency speed regulation according to claim 1, characterized in that, In step S3, when the theoretical duration of the first effective voltage vector and the theoretical duration of the second effective voltage vector are both less than the effective sampling window threshold, the following steps are included: Step S34, within the current pulse width modulation carrier cycle, applying unilateral widening only to the phase bridge arm drive pulse corresponding to the first effective voltage vector so that the duration of the first effective voltage vector reaches the effective sampling window threshold, and collecting the first bus current within the range of action of the first effective voltage vector; Step S35, within the immediately following pulse width modulation carrier cycle, applying unilateral widening only to the phase bridge arm drive pulse corresponding to the second effective voltage vector so that the duration of the second effective voltage vector reaches the effective sampling window threshold, and collecting the second bus current within the range of action of the second effective voltage vector.

8. The phase current reconstruction method for permanent magnet synchronous traction variable frequency speed regulation according to claim 7, characterized in that, The dual-cycle alternating measurement steps further include: step S341, within the current pulse width modulation carrier cycle, correcting the pulse cutoff time according to the transient transition time asymmetry difference of the corresponding cycle, and applying a virtual anti-phase vector; step S351, within the immediately following pulse width modulation carrier cycle, correcting the pulse cutoff time according to the transient transition time asymmetry difference of the corresponding cycle, and applying a virtual anti-phase vector in the opposite direction to counteract the stator composite flux position offset.

9. The phase current reconstruction method for permanent magnet synchronous traction variable frequency speed regulation according to claim 1, characterized in that, Step S4, which involves acquiring a single-sample resistor signal, also includes: step S43, continuously reading discrete sampling points within the analog-to-digital converter conversion window; step S44, calculating the absolute value of the slope difference between adjacent discrete sampling points; step S45, when the absolute value of the slope difference is continuously less than a preset steady-state threshold, outputting the current bus current to subsequent topology mapping steps; and when the absolute value of the slope difference is greater than or equal to a preset steady-state threshold, maintaining the phase current output value of the previous pulse width modulation cycle.

Images