Circuit arrangement and vibration device

Abstract

A circuit device and a vibration device are provided. The circuit device (10) includes a MIM capacitor (CM) having a substrate (PSB) of a first conductivity type, a well (PWL) of the first conductivity type provided in the substrate (PSB), a well (NWL) of a second conductivity type provided in the substrate (PSB), a pad (PD), an electrode (ELA), an electrode (ELB), and a dielectric layer (IS) provided between the electrode (ELA) and the electrode (ELB). The well (NWL) and the pad (PD) are electrically connected by a first conductive path (PT1). One of the electrode (ELA) and the electrode (ELB) is electrically connected to the pad (PD) by a second conductive path (PT2), and the other of the electrode (ELA) and the electrode (ELB) is electrically connected to the well (PWL) by a third conductive path (PT3). Furthermore, a resistance value (R2) of the second conductive path (PT2) is larger than a resistance value (R1) of the first conductive path (PT1).

Description

Technical Field

[0001] This invention relates to circuit devices and vibration devices, etc. Background Technology

[0002] Patent Document 1 discloses a circuit device comprising: a pad on which a signal is input; an analog circuit that performs analog processing on the signal input via the pad; and a MIM capacitor disposed between the signal input node of the analog circuit and the pad. Furthermore, in this circuit device, the pad and one end of the MIM capacitor are connected via pad wiring formed by the uppermost metal layer.

[0003] Patent Document 1: Japanese Patent Application Publication No. 2011-109074

[0004] However, in the wiring connection as described in Patent Document 1, it was determined that the MIM capacitor may be affected by static electricity. Summary of the Invention

[0005] One aspect of the present invention is a circuit device comprising: a substrate of a first conductivity type; a first well of the first conductivity type disposed on the substrate; a second well of a second conductivity type disposed on the substrate; a pad; and a MIM capacitor having a first electrode, a second electrode, and a dielectric layer disposed between the first electrode and the second electrode, wherein the second well is electrically connected to the pad via a first conductive path, one of the first electrode and the second electrode is electrically connected to the pad via a second conductive path, and the other of the first electrode and the second electrode is electrically connected to the first well via a third conductive path, wherein the resistance value of the second conductive path is greater than the resistance value of the first conductive path.

[0006] Furthermore, another aspect of this disclosure relates to a circuit device comprising: a substrate of a first conductivity type; a first well of the first conductivity type disposed on the substrate; a second well of a second conductivity type disposed on the substrate; a pad; and a MIM capacitor having a first electrode, a second electrode, and a dielectric layer disposed between the first electrode and the second electrode, wherein the second well is electrically connected to the pad via a first conductive path, one of the first electrode and the second electrode is electrically connected to the pad via a second conductive path, and the other of the first electrode and the second electrode is electrically connected to the first well via a third conductive path, wherein the second conductive path comprises: a first wiring of a metal layer of the same or upper layer as the metal layer of the first electrode; and a second wiring of a metal layer of the lower layer of the metal layer of the first electrode.

[0007] Furthermore, another aspect of this disclosure relates to a vibration device comprising: the circuit arrangement described above; a through electrode disposed on the substrate of the circuit arrangement; a vibration element electrically connected to the through electrode; and a cover that, together with the substrate, houses the vibration element. Attached Figure Description

[0008] Figure 1 This is a cross-sectional view of the circuit device of this embodiment.

[0009] Figure 2 This is a sectional view of a comparative example.

[0010] Figure 3 This is a diagram illustrating the problem points of the comparative example.

[0011] Figure 4 This is an explanatory diagram of the electrostatic discharge path in the circuit device of this embodiment.

[0012] Figure 5 This is a cross-sectional view showing another example of the configuration of the MIM capacitor in the circuit arrangement.

[0013] Figure 6 This is a plan view showing the ALE wiring of the circuit device.

[0014] Figure 7 This is a plan view showing the MIM configuration of the circuit device.

[0015] Figure 8 This is a plan view showing the ALD wiring of the circuit device.

[0016] Figure 9 This is a plan view showing the MIM configuration of the circuit device.

[0017] Figure 10 This is a plan view showing the ALC wiring of the circuit device.

[0018] Figure 11 This is a plan view showing the ALB wiring of the circuit device.

[0019] Figure 12 This is a plan view showing the ALA wiring of the circuit device.

[0020] Figure 13 This is a diagram showing a detailed structural example of the circuit device according to this embodiment.

[0021] Figure 14 This is a cross-sectional view showing a structural example of the vibration device according to this embodiment.

[0022] Figure 15 This is a flowchart illustrating an example of the manufacturing process of a vibrating device.

[0023] Figure 16 This is a flowchart illustrating an example of the manufacturing process of a vibrating device.

[0024] Figure 17 This is a flowchart illustrating an example of the manufacturing process of a vibrating device.

[0025] Figure 18 This is a flowchart illustrating an example of the manufacturing process of a vibrating device.

[0026] Figure 19 This is a flowchart illustrating an example of the manufacturing process of a vibrating device.

[0027] Figure 20 This is a flowchart illustrating an example of the manufacturing process of a vibrating device.

[0028] Figure 21 This is a flowchart illustrating an example of the manufacturing process of a vibrating device.

[0029] Label Explanation

[0030] 1…vibrating device, 2…base, 3…cover, 5…vibrating element, 8…reconfiguration wiring layer, 9…circuit device, 10…circuit device, 11…oscillation circuit, 12…output circuit, 13…control circuit, 14…power supply circuit, 15…temperature compensation circuit, 16…temperature sensor circuit, 17…memory, 19…integrated circuit, 20…substrate, 21…first surface, 22…second surface, 30…recess, 32…sidewall portion, 33…sidewall portion, 34, 35…end face, 36, 37…joint portion, 40…through electrode, 41…through hole, 42…insulating film, 60…Joint, 80…Reference voltage generation circuit, 81…Voltage regulator circuit, 86…Variable capacitor circuit, 91, 92…External connection terminals, 120…First semiconductor wafer, 130…Second semiconductor wafer, 132…Metal film, ALA, ALB, ALC, ALD, ALE…Metal layer, CA…Capacitor, CK…Clock signal, CM…Capacitor, DR1, DR2, DR3…Direction, ELA, ELB…Electrodes, IL0, IL1, IL2, IL3, IL4…Insulating layer, IS…Dielectric layer, NWL…Trap OE… Output enable signal, PCK, PD, PD2, PGND, POE, PVDD, PX1, PX2… Pads, PSB… Substrate, PSV… Passivation film, PT1… First conductive path, PT2… Second conductive path, PT3… Third conductive path, SD1, SD2, SD3, SD4… Edge, SP… Storage space, TCK, TGND, TOE, TVDD… Terminal, VA0~VA4, VB1~VB4, VC0~VC4… Through hole, WL1, WL2, WL3, WL4, WL5… Wiring. Detailed Implementation

[0031] The following describes this embodiment. It is important to note that the embodiments described below are not intended to unduly limit the scope of the claims. Furthermore, not all structures described in this embodiment are necessarily essential components. Additionally, some components are sometimes omitted from the accompanying drawings for ease of explanation. Also, the dimensions of the components in the drawings differ from the actual dimensions for clarity.

[0032] 1. Circuit device

[0033] Figure 1 This is a cross-sectional view showing an example of the structure of the circuit device 10 according to this embodiment. Figure 1 As shown, the circuit device 10 includes a substrate PSB, a well PWL, a well NWL, a pad PD, and a MIM capacitor CM. Figure 1 In the diagram, directions DR1 and DR2 are along the surfaces of the PSB substrate, and they are orthogonal to each other. Additionally, direction DR3 is orthogonal to the PSB substrate, and it is also orthogonal to both directions DR1 and DR2. Figure 1 This is a cross-sectional view of the circuit device 10 when viewed from the side along direction DR2. Directions DR1, DR2, and DR3 are the first direction, the second direction, and the third direction, respectively. Furthermore, in this embodiment, orthogonality includes approximately orthogonality.

[0034] The substrate PSB is a substrate of a first conductivity type, specifically, for example, a P-type substrate. The well PWL is a first well of the first conductivity type disposed on the substrate PSB, specifically, for example, a P-type well. The well NWL is a second well of the second conductivity type disposed on the substrate PSB, specifically, for example, an N-type well. Furthermore, in this embodiment, the case where the first conductivity type is P-type and the second conductivity type is N-type is mainly described as an example, but variations where the first conductivity type is N-type and the second conductivity type is P-type can also be implemented.

[0035] The P-type substrate PSB is a semiconductor substrate, and for example, a P-type diffusion region (not shown) is set to a potential of GND, which is ground. GND is the power supply potential on the low-potential side, also known as VSS. A P-type well PWL is formed on the substrate PSB, and for example, a P-type diffusion region P+ is set to a potential of GND. An N-type well NWL is formed on the substrate PSB, and for example, an N-type diffusion region N+ is set to a potential of VDD. VDD is the power supply potential on the high-potential side.

[0036] The circuit device 10 has multiple metal layers ALA, ALB, ALC, ALD, and ALE. These metal layers are, for example, aluminum metal layers, with ALA being the bottommost metal layer and ALE being the topmost metal layer. The topmost metal layer ALE is thicker than the other metal layers ALA, ALB, ALC, and ALD. Insulating layers IL1, IL2, IL3, and IL4 are provided between each of the metal layers ALA, ALB, ALC, ALD, and ALE. Furthermore, an insulating layer IL0 is provided between metal layer ALA and the substrate PSB, well PWL, and NWL. In this embodiment, the example is described with five metal layers, but it is not limited to this; it can also have four or fewer metal layers, or six or more metal layers.

[0037] A MIM capacitor CM is a capacitor having a metal-insulator-metal structure and including electrodes ELA, ELB, and a dielectric layer IS disposed between electrodes ELA and ELB. Electrode ELA is the first electrode and, for example, the lower electrode of the MIM capacitor CM. Figure 1 In this design, electrode ELA is composed of a metal layer ALD. Electrode ELB is the second electrode, for example, the upper electrode of a MIM capacitor CM. Electrode ELB is composed of a metal layer for MIM disposed between the metal layer ALE and the metal layer ALD. That is, electrode ELB is composed of a metal layer for MIM consisting of an insulating layer IL4 disposed between the metal layer ALE and the metal layer ALD. In the MIM capacitor CM, since the thickness of the dielectric layer IS, which serves as the insulating layer, can be reduced, it has the advantage of obtaining a large capacitance value with a small layout area. Furthermore, the MIM capacitor CM can be formed by effectively utilizing the space above circuit elements or circuit wiring, thus having the advantage of obtaining a large capacitance value while suppressing an increase in the layout area of ​​the circuit device 10. In addition, the MIM capacitor CM has low voltage dependence, thus having the advantage of good analog characteristics such as noise characteristics.

[0038] Furthermore, in this embodiment, the MIM capacitor CM is used as, for example, a power supply capacitor between VDD and GND. That is, the MIM capacitor CM is used as, for example, a bypass capacitor disposed between VDD and GND.

[0039] The pad PD is, for example, a terminal of the circuit device 10 of the semiconductor chip, and is a terminal for external connection. For example, in the area of ​​the pad PD, the metal layer ALE is exposed from the passivation film PSV, which is an insulating layer, and the exposed metal layer ALE, etc., constitutes the pad PD as a terminal of the circuit device 10. The pad PD is a pad that is supplied with the power supply voltage VDD when the circuit device 10 is in operation.

[0040] Moreover, in Figure 1 In this embodiment, the well NWL and the pad PD are electrically connected through a first conductive path PT1. The conductive path can be, for example, a path based on conductive components such as metal layers or vias. For example, the first conductive path PT1 includes vias VA0, VA1, VA2, VA3, and VA4, through which the pad PD is electrically connected to the well NWL. Vias VA1, VA2, VA3, and VA4 are respectively vias connecting metal layers ALA and ALB, ALB and ALC, ALC and ALD, and ALD and ALE, implemented, for example, using tungsten plugs. Via VA0 connects metal layer ALA to diffusion layer N+, and is also called a contact hole. Furthermore, the pad PD is electrically connected to the well NWL via vias VA4, VA3, VA2, VA1, VA0, and diffusion layer N+. In addition, the connection in this embodiment is also an electrical connection unless otherwise specified. An electrical connection refers to a connection that can transmit electrical signals, enabling information transmission based on electrical signals. Electrical connections can also be connections via passive components, etc.

[0041] Furthermore, in this embodiment, one of the electrodes ELA and ELB of the MIM capacitor CM is electrically connected to the pad PD via a second conductive path PT2. Figure 1 In this configuration, one electrode is electrode ELA, and electrode ELA of capacitor CM is electrically connected to pad PD via a second conductive path PT2. Figure 1 In the diagram, the second conductive path PT2 includes wiring WL1, vias VB3, VB2, VB1, wiring WL2, and vias VA1, VA2, VA3, and VA4. Wiring WL1 is the first wiring, for example, a wiring of the metal layer ALD. That is, wiring WL1 is a wiring of the metal layer ALD, which is on the same layer as the metal layer of electrode ELA. Wiring WL2 is the second wiring, for example, a wiring of the metal layer ALA. That is, wiring WL2 is a wiring of the metal layer ALA, which is below the metal layer ALD of electrode ELA. Metal layer ALA is, for example, the bottommost metal layer. Vias VB3, VB2, and VB1 are through holes connecting metal layers ALD and ALC, ALC and ALB, and ALB and ALA, respectively. Vias VA1, VA2, VA3, and VA4 are through holes connecting metal layers ALA and ALB, ALB and ALC, ALC and ALD, and ALD and ALE, respectively.

[0042] Furthermore, in this embodiment, another electrode of the MIM capacitor CM, either electrode ELA or electrode ELB, is electrically connected to the trap PWL via a third conductive path PT3. Figure 1 In the middle, the other electrode is electrode ELB, and electrode ELB of capacitor CM is electrically connected to the trap PWL through a third conductive path PT3. Figure 1In the diagram, the third conductive path PT3 includes via VB4, wiring WL3, via VC4, VC3, VC2, VC1, and VC0. Via VB4 connects electrode ELB to wiring WL3. Wiring WL3 is the wiring for metal layer ALE. That is, wiring WL3 is the wiring for metal layer ALE, which is the uppermost metal layer above metal layer ALD of electrode ELA. Via ALE is the topmost metal layer. Vias VC4, VC3, VC2, and VC1 connect metal layers ALE to ALD, ALD to ALC, ALC to ALB, and ALB to ALA, respectively. Via VC0 connects metal layer ALA to diffusion layer P+ and is also called a contact hole. Furthermore, electrode ELB of capacitor CM is electrically connected to well PWL via via VB4, wiring WL3, via VC4, VC3, VC2, VC1, VC0, and diffusion layer P+.

[0043] Furthermore, in this embodiment, the resistance value R2 of the second conductive path PT2 is greater than the resistance value R1 of the first conductive path PT1, and the relationship R2>R1 holds true. The resistance value R1 is, for example, the resistance value generated by the parasitic resistance of vias VA0, VA1, VA2, VA3, and VA4. The resistance value R2 is, for example, the resistance value generated by the parasitic resistance of wirings WL1 and WL2, vias VB3, VB2, VB1, VA1, VA2, VA3, and VA4. Additionally, when the resistance value of the third conductive path PT3 is set to R3, it is also possible that R2+R3>R1.

[0044] For example, Figure 2 This is a cross-sectional view showing a structural example of the circuit device 9 in a comparative example of this embodiment. Figure 2 In the comparative example, the electrode ELA of the MIM capacitor CM is electrically connected to the pad PD via wiring WL4 and via VA4 of the metal layer ALD. Additionally, the electrode ELB of the capacitor CM is electrically connected to the well PWL via wiring WL5 and vias VC4, VC3, VC2, VC1, and VC0 of the metal layer ALE.

[0045] That is, in Figure 1 In this embodiment, the second conductive path PT2 connecting the electrode ELA of capacitor CM to pad PD becomes a path including wiring WL1, vias VB3, VB2, VB1, wiring WL2, and vias VA1, VA2, VA3, and VA4. In contrast, Figure 2 In the comparative example, the second conductive path PT2 is a path containing only wiring WL4 and via VA4. Therefore, the resistance value R2 of the second conductive path PT2 in the comparative example is smaller than the resistance value R2 of the second conductive path PT2 in this embodiment. Therefore, in Figure 1 In this embodiment, the relationship R2>R1 holds true, but... Figure 2In the comparison examples, the relationship R2 > R1 does not hold. As a result, it was determined that the generation... Figure 3 The issues explained in the text.

[0046] exist Figure 3 In this process, charge is accumulated in the substrate PSB by the substrate becoming charged. For example, in the following description... Figure 14 In such a WLP vibrating device 1, during its manufacturing process, charge is accumulated on the substrate PSB of the circuit device 10 via the cover 3, etc. Furthermore, in Figure 3 The diagram shows the case where positive charges are accumulated on the PSB substrate, but the accumulated charges can also be negative.

[0047] Moreover, in Figure 3 In this configuration, the pad PD is set to the potential of GND, so the charge accumulated in the substrate PSB discharges along the path shown in A1. For example, due to Figure 14 One of the external connection terminals 91 and 92 is electrically connected to the pad PD. Therefore, when this external connection terminal comes into contact with an object at the potential of GND, an electrostatic charge will be generated. Figure 3 The discharge occurs in the path shown in A1. For example, when the pad PD is set to GND potential, the potential of electrode ELA of the MIM capacitor CM decreases via the second conductive path PT2, and the potential difference between electrode ELA and electrode ELB increases. Moreover, when the potential difference between electrode ELA and electrode ELB exceeds the withstand voltage of the insulating layer IS, which serves as the dielectric layer of capacitor CM, insulation failure occurs. Thus, as... Figure 3 As shown in A1, the charge generated by the substrate PSB is discharged to GND through the well PWL, vias VC0, VC1, VC2, VC3, VC4, wiring WL5, MIM capacitor CM, wiring WL4, via VA4, and pad PD.

[0048] For example, a MIM-structured capacitor CM in circuit device 10 is useful for its noise immunity and ability to reduce chip area. However, conventionally, one electrode of the MIM capacitor CM is connected to the power supply pad PD of VDD via a low-resistance path, which is a potential different from that of the substrate PSB. Therefore, when the pad PD is grounded and discharged, the electrostatic charge accumulated in the substrate PSB is discharged through the low-voltage MIM capacitor CM, causing electrostatic damage to the MIM capacitor. Especially as... Figure 14 In devices like the WLP vibrating device 1, where the cover 3 is joined to the back side of the circuit device 10, charge tends to accumulate on the substrate PSB, causing significant problems.

[0049] Regarding this point, in this embodiment, as Figure 1As explained, the resistance value R2 in the second conductive path PT2, which connects one electrode ELA of the MIM capacitor CM to the pad PD, is, for example, greater than... Figure 2 Comparative examples. For example, in Figure 1 In this process, by making the second conductive path PT2 become connected with... Figure 2 Compared to the circuitous conductive path, the resistance value R2 is increased in the comparative example. Therefore, the resistance value R2 in the second conductive path PT2 is greater than the resistance value R1 in the first conductive path PT1 that connects the well NWL to the pad PD.

[0050] In this way, the charge on the substrate PSB does not travel through the second conductive path PT2 via the MIM capacitor CM, but rather... Figure 4 As shown in B1, discharge occurs through the first conductive path PT1. That is, the resistance R2 of the second conductive path PT2 is greater than the resistance R1 of the first conductive path PT1. Therefore, the charge on the substrate PSB discharges from the pad PD to GND through the first conductive path PT1, which has a smaller resistance R1, instead of through the second conductive path PT2 with its larger resistance R2. This suppresses discharge. Figure 3 The discharge of charge through the MIM capacitor CM, as in A1, can prevent electrostatic damage to the MIM capacitor CM.

[0051] For example, in the above Figure 2 In the comparative example, when the pad PD is set to GND potential, the potential of electrode ELA of capacitor CM decreases, and insulation failure occurs when the potential difference between electrode ELA and electrode ELB exceeds the withstand voltage of the insulation layer of capacitor CM. On the other hand, in this embodiment, since the resistance value R2 of the second conductive path PT2 is large, the potential of electrode ELA is less likely to decrease compared to the comparative example when the pad PD is set to GND potential, and before the potential of electrode ELA decreases, such as Figure 4 As shown in B1, the charge on the substrate PSB discharges to the GND side in the first conductive path PT1, where the resistance value R1 is lower. Therefore, the potential difference between electrodes ELA and ELB of the capacitor CM becomes less than the withstand voltage of the insulating film, thereby preventing insulation failure.

[0052] Furthermore, when the substrate PSB has accumulated positive charge, the discharge path at the PN junction between the substrate PSB and the well NWL in the first conductive path PT1 becomes the forward path of the PN junction. On the other hand, when the substrate PSB has accumulated negative charge, the charge discharge path becomes the reverse path of the PN junction, but by applying a high voltage during electrostatic discharge, the charge is discharged through avalanche breakdown or the like in the reverse direction.

[0053] Figure 5This is a cross-sectional view showing another configuration example of the MIM capacitor CM in the circuit device 10 of this embodiment. Figure 1 In the MIM capacitor CM, the capacitor CM is disposed between the metal layer ALE and the metal layer ALD, but... Figure 5 In this MIM capacitor CM, the capacitor CM is disposed between the metal layer ALD and the metal layer ALC. That is, the electrode ELA of the capacitor CM is composed of the metal layer ALC, and the electrode ELB is composed of the metal layer used for MIM between the metal layers ALD and ALC.

[0054] Specifically, in Figure 5 In, with Figure 1 Similarly, the well NWL and the pad PD are electrically connected through the first conductive path PT1. The first conductive path PT1 includes vias VA0, VA1, VA2, VA3, and VA4, through which the pad PD and the well NWL are electrically connected via the diffusion layer N+.

[0055] Additionally, in this embodiment, one of the electrodes ELA and ELB of the MIM capacitor CM is electrically connected to the pad PD via a second conductive path PT2. Figure 5 In this circuit, one electrode is electrode ELB, and the electrode ELB of capacitor CM is electrically connected to pad PD via a second conductive path PT2. Figure 5 In the diagram, the second conductive path PT2 includes via VC3, wiring WL1, vias VB3, VB2, VB1, wiring WL2, and vias VA1, VA2, VA3, and VA4. Wiring WL1 is the first wiring and is the wiring of the upper metal layer ALD of the metal layer ALC of electrode ELA. Wiring WL2 is the second wiring and is the wiring of the lower metal layer ALA of the metal layer ALC of electrode ELA. Vias VB3, VB2, and VB1 are the vias connecting metal layers ALD and ALC, ALC and ALB, and ALB and ALA, respectively. Via VC3 is the via connecting wiring WL1 of electrode ELB and metal layer ALD.

[0056] Furthermore, in this embodiment, another electrode of the MIM capacitor CM, either electrode ELA or electrode ELB, is electrically connected to the trap PWL via a third conductive path PT3. Figure 5 In the middle, the other electrode is electrode ELA, and electrode ELA of capacitor CM is electrically connected to trap NWL through a third conductive path PT3. Figure 5 In the circuit, the third conductive path PT3 includes vias VC2, VC1, and VC0. VC2 and VC1 are vias connecting ALC to ALB and ALB to ALA, respectively, while VC0 is a contact hole connecting the metal layer ALA to the diffusion layer P+. The electrode ELA of capacitor CM is electrically connected to the well PWL via vias VC2, VC1, and VC0, as well as the diffusion layer P+.

[0057] Moreover, in Figure 5 In the diagram, the resistance R2 of the second conductive path PT2 is also greater than the resistance R1 of the first conductive path PT1, thus the relationship R2>R1 holds true. The resistance R1 is, for example, generated by the parasitic resistance of vias VA4, VA3, VA2, VA1, and VA0. The resistance R2 is, for example, generated by the parasitic resistance of wirings WL1, WL2, vias VC3, VB3, VB2, VB1, VA1, VA2, VA3, and VA4.

[0058] Furthermore, various modifications can be implemented in this embodiment. For example, in Figure 1 , Figure 5 In this context, routing WL1 becomes the routing of the metal layer ALD, but routing WL1 can also be the routing of the metal layer above or below the metal layer ALD. Additionally, in... Figure 1 , Figure 5 In this embodiment, wiring WL2 is the wiring of the bottommost metal layer ALA, but wiring WL2 can also be the wiring of the metal layer above metal layer ALA. Furthermore, in this embodiment, by making the second conductive path PT2 a more circuitous path compared to the comparative example, the relationship R2>R1 is established, but the circuitous path of the second conductive path PT2 is not limited to... Figure 1 , Figure 5 A circuitous path as shown. For example, it is possible to implement a second conductive path PT2 as... Figure 1 , Figure 5 The paths of through-holes VB3, VB2, and VB1 detour from the top layer to the bottom layer, then from the bottom layer to the top layer, and then from the top layer to the bottom layer to connect with the first conductive path PT1, among other variations. Additionally, in Figure 1 , Figure 5 In this process, the resistance value R2 of the second conductive path PT2 is increased by meandering the path. However, the resistance value R2 can also be increased by inserting a resistive element into the second conductive path PT2. For example, a resistive element made of polysilicon or the like can be placed in the second conductive path PT2 to make the relationship R2 > R1 hold true.

[0059] Figures 6-12 This is a plan view showing the metal wiring and MIM arrangement in the circuit device 10 of this embodiment. The circuit device 10 has edges SD1, SD2, SD3, and SD4, where edge SD2 is the opposite edge of edge SD1, and edge SD4 is the opposite edge of edge SD3. Furthermore, direction DR1 is the direction from edge SD1 towards edge SD2, and direction DR2 is the direction from edge SD3 towards edge SD4. Figures 6-12 It is a plan view taken from above along direction DR3, which is orthogonal to directions DR1 and DR2.

[0060] Figure 6This is a plan view showing the layout and routing of the ALE metal layer. Figure 6 In this circuit, a metal layer ALE for a VDD pad PD is disposed at the first corner where edges SD1 and SD3 intersect, and a metal layer ALE for a GND pad PD2 is disposed at the second corner where edges SD2 and SD4 intersect. Furthermore, the routing LEGND1 from the GND of pad PD2 is routed along edges SD4 and SD1, and the routing LEGND2 from the GND of pad PD2 is routed along edges SD2 and SD3. That is, the routing LEGND1 and LEGND2 based on the GND of metal layer ALE is approximately loop-shaped along the inner periphery of the circuit device 10.

[0061] Figure 7 It is shown in Figure 1 A plan view illustrating an example configuration of a MIM capacitor CM placed between metal layers ALE and ALD, as described in the diagram. Figure 7 In the middle, the MIM capacitor CM is along Figure 6 The wiring of GND is as follows: LEGND1, LEGND2 and Figure 8 The VDD wiring LDVDD1 and LDVDD2 are configured to overlap with these wirings when viewed from above. Alternatively, the MIM capacitor CM can be positioned inside these wirings.

[0062] Figure 8 This is a plan view showing the layout and routing of the ALD metal layer. Figure 8 In this circuit, the VDD wiring LDVDD1 is routed along edges SD4 and SD1, and the VDD wiring LDVDD2 is routed along edges SD2 and SD3. That is, the VDD wiring LDVDD1 and LDVDD2 based on the metal layer ALD are routed in a roughly loop shape along the inner periphery of the circuit device 10.

[0063] In addition, Figure 8 It also shows Figure 1 , Figure 5 Examples of via configurations for VB3, VA4, and VA3. For instance, in the configuration area of ​​the MIM, the routing of the VDD of the ALD metal layer, i.e., routing WL1, is connected to the underlying ALC metal layer via via VB3. Similarly, in the configuration area of ​​the PD pad, the ALE metal layer of the PD pad is connected to the underlying ALD metal layer via via VA4, and the ALD metal layer is connected to the underlying ALC metal layer via via VA3. Furthermore, in practice, for example, in the configuration area of ​​the PD pad with a rectangular ALE metal layer, multiple vias VA4 and VA3 may be configured in a matrix.

[0064] Figure 9 It is shown in Figure 5A plan view illustrating an example configuration of a MIM capacitor CM placed between metal layers ALD and ALC, as described in the diagram. Figure 9 In the middle, the MIM capacitor CM is along Figure 6 The wiring of GND is as follows: LEGND1, LEGND2 and Figure 8 The VDD wiring LDVDD1 and LDVDD2 are configured to overlap with these wirings when viewed from above. Alternatively, the MIM capacitor CM can be positioned inside these wirings.

[0065] Figure 10 This is a plan view showing the layout and routing of the ALC metal layer. Figure 10 In the circuit, the GND wiring LCGND is routed along edges SD1, SD4, SD2, and SD3. That is, the GND wiring LCGND based on the metal layer ALC is routed in a generally loop shape along the inner periphery of the circuit device 10.

[0066] In addition, Figure 10 It also shows Figure 1 , Figure 5 Examples of via configurations for VB3, VB2, VA3, and VA2. For instance, in the MIM configuration area, metal layer ALD is connected to the underlying metal layer ALC via via VB3, and metal layer ALC is connected to the underlying metal layer ALB via via VB2. Similarly, in the PD configuration area, metal layer ALD is connected to the underlying metal layer ALC via via VA3, and metal layer ALC is connected to the underlying metal layer ALB via via VA2.

[0067] Figure 11 This is a plan view showing the layout and routing of the ALB metal layer. Figure 11 In this circuit, the VDD wiring LBVDD1 is routed along edges SD1 and SD4, and the VDD wiring LBVDD2 is routed along SD2 and SD3. That is, the VDD wiring LBVDD1 and LBVDD2 based on the metal layer ALB are routed in a roughly loop shape along the inner periphery of the circuit device 10.

[0068] In addition, Figure 11 It also shows Figure 1 , Figure 5 Examples of via configurations for VB2, VB1, VA2, and VA1. For instance, in the MIM configuration area, metal layer ALC is connected to the underlying metal layer ALB via via VB2, and metal layer ALB is connected to the underlying metal layer ALA via via VB1. Similarly, in the PD configuration area, metal layer ALC is connected to the underlying metal layer ALB via via VA2, and metal layer ALB is connected to the underlying metal layer ALA via via VA1.

[0069] Figure 12 This is a plan view showing the layout and routing of the ALA metal layer. The VDD and GND routing based on the ALA metal layer are configured in the MIM configuration area. Additionally, in the MIM configuration area, the ALB metal layer is connected to the underlying ALA metal layer via via VB1, and in the PD configuration area, the ALB metal layer is connected to the underlying ALA metal layer via via VA1.

[0070] As described above, the circuit device 10 of this embodiment includes a substrate PSB of a first conductivity type, a well PWL of a first conductivity type disposed on the substrate PSB, a well NWL of a second conductivity type disposed on the substrate PSB, a pad PD, and a MIM capacitor CM. The MIM capacitor CM includes electrodes ELA, ELB, and a dielectric layer IS disposed between electrodes ELA and ELB. Figure 1 , Figure 5 In this configuration, the first conductivity type is P-type, and the second conductivity type is N-type. Alternatively, a variation can be implemented where the first conductivity type is N-type and the second conductivity type is P-type. Furthermore, the well PWL is the first well, the well NWL is the second well, electrode ELA is the first electrode, and electrode ELB is the second electrode.

[0071] Furthermore, in this embodiment, the well NWL is electrically connected to the pad PD via a first conductive path PT1. Additionally, one electrode of the MIM capacitor CM, either electrode ELA or electrode ELB, is electrically connected to the pad PD via a second conductive path PT2, and the other electrode of ELA or ELB is electrically connected to the well PWL via a third conductive path PT3. Figure 1 In the circuit, one electrode connected to the pad PD is electrode ELA, and the other electrode connected to the sink PWL is electrode ELB. Figure 5 In the circuit, one electrode connected to the pad PD is electrode ELB, and the other electrode connected to the sink PWL is electrode ELA.

[0072] Moreover, in this embodiment, such as Figure 1 , Figure 5 As explained, the resistance R2 of the second conductive path PT2 is greater than the resistance R1 of the first conductive path PT1. In cases where static charge accumulates in the substrate PSB, the larger resistance R2 of the second conductive path PT2 helps to suppress the discharge of charge from the substrate PSB to the pad PD side via the MIM capacitor CM located in the second conductive path PT2. That is, the charge from the substrate PSB flows to the pad PD side via, for example, the first conductive path PT1 with a smaller resistance R1, instead of the second conductive path PT2 with its larger resistance R2. This prevents the dielectric layer IS of the MIM capacitor CM from being damaged by static electricity.

[0073] That is, the static charge accumulated on the substrate PSB of the circuit device 10 is discharged through various wirings. Furthermore, when the GND pad, which is at the same potential as the substrate PSB, is grounded, there is no problem even if the charge is discharged through that pad. However, when the PD pad, which supplies a different potential than the substrate PSB, is grounded, the charge is released from the substrate PSB through the PD pad. In this case, if conventional wiring methods are used, the charge may sometimes be discharged through the dielectric layer IS, i.e., the insulating film, of the MIM capacitor CM. If the charge is discharged in this path, then... Figure 3 As explained, the insulating film of the MIM capacitor CM can be damaged by electrostatic discharge. In this regard, according to this embodiment, the charge of the substrate PSB does not discharge from the pad PD via the second conductive path PT2 where the MIM capacitor CM is located, thus preventing the insulation of the MIM capacitor CM from being damaged.

[0074] Furthermore, in this embodiment, the second conductive path PT2 includes wiring WL1 of the same or upper metal layer as the metal layer of the electrode ELA. Wiring WL1 is the first wiring. For example, in Figure 1 In the second conductive path PT2, wiring WL1 of the metal layer ALD, which is on the same metal layer as the electrode ELA, is also present. Furthermore, in Figure 5 In the second conductive path PT2, wiring WL1 is provided on the metal layer ALD above the metal layer ALC of electrode ELA.

[0075] In this manner, one electrode of capacitor CM is electrically connected to pad PD via a second conductive path PT2. This second conductive path PT2 detours through wiring WL1 in a metal layer on the same or higher layer as electrode ELA of capacitor CM. By utilizing wiring WL1 to detour the path, parasitic resistance of wiring WL1 and the like is increased, thereby increasing the resistance value R2 of the second conductive path PT2. Furthermore, by increasing the resistance value R2, the discharge of charge in the second conductive path PT2 can be suppressed, preventing insulation damage to the MIM capacitor CM.

[0076] Additionally, one end of wiring WL1 is electrically connected to one electrode of the MIM capacitor CM, and the other end is electrically connected to the first conductive path PT1. For example, in Figure 1 In this configuration, one end of wiring WL1 is connected to electrode ELA, which serves as one electrode of the MIM capacitor CM, and the other end is connected to the first conductive path PT1. Additionally, in... Figure 5 In the circuit, one end of wiring WL1 is connected to one electrode of MIM capacitor CM, namely electrode ELB, and the other end is connected to the first conductive path PT1.

[0077] Thus, through a second conductive path PT2 that detours via the path of wiring WL1 and at least a portion of the first conductive path PT1, one electrode of capacitor CM is electrically connected to pad PD. This detour through wiring WL1 and at least a portion of the first conductive path PT1 increases the parasitic resistance of wiring WL1 and the parasitic resistance in the first conductive path PT1, thereby increasing the resistance value R2 of the second conductive path PT2 and preventing insulation failure of the MIM capacitor CM.

[0078] Furthermore, the second conductive path PT2 includes wiring WL2 on the lower metal layer of the electrode ELA of capacitor CM. Wiring WL2 is the second wiring. For example, in Figure 1 and Figure 5 In this circuit, the second conductive path PT2 includes wiring WL2 of the metal layer ALD of electrode ELA and the metal layer ALA below ALC. Furthermore, the metal layer of wiring WL2 can be the layer below the metal layer of electrode ELA, or it can be, for example, metal layers ALB, ALC, etc.

[0079] Therefore, one electrode of capacitor CM is electrically connected to pad PD via a second conductive path PT2. This second conductive path PT2 detours through the wiring WL2 of the metal layer beneath electrode ELA of capacitor CM. By using wiring WL2 to detour the path, the parasitic resistance of wiring WL2 and the like can be increased, thereby increasing the resistance value R2 of the second conductive path PT2 and preventing insulation failure of MIM capacitor CM.

[0080] Additionally, the metal layer of wiring WL2, for example, Figure 1 , Figure 5 The diagram shows the bottommost metal layer, ALA. That is, the routing WL2 of the bottommost metal layer ALA (among multiple metal layers ALE~ALA) is used to detour the path in the second conductive path PT2.

[0081] In this way, by using a second conductive path PT2 that detours from the metal layer of one electrode of the MIM capacitor CM to the wiring WL2 of the bottommost metal layer ALA, one electrode of the capacitor CM can be electrically connected to the pad PD. Furthermore, by making the path detour to the wiring WL2 of the bottommost metal layer ALA, the resistance value R2 of the second conductive path PT2 can be further increased, thus preventing insulation failure of the MIM capacitor CM.

[0082] Furthermore, the second conductive path PT2 includes wiring WL1 of the same or upper metal layer as the metal layer of the electrode ELA and wiring WL2 of the lower metal layer of the metal layer of the electrode ELA. For example, in Figure 1In the second conductive path PT2, wiring WL1 of the metal layer ALD (co-layer with electrode ELA) and wiring WL2 of the metal layer ALA (below electrode ELA) are also included. Figure 5 In the second conductive path PT2, wiring WL1 is located on the upper metal layer ALD of the metal layer ALC of electrode ELA, and wiring WL2 is located on the lower metal layer ALA of the metal layer ALC of electrode ELA. Furthermore, wiring WL1 and wiring WL2 are electrically connected via vias that connect the metal layers. For example, in... Figure 1 , Figure 5 In the process, wiring WL1 and wiring WL2 are electrically connected via through holes VB3, VB2, and VB1.

[0083] In this way, by using wiring WL1, wiring WL2, and the second conductive path PT2, which detours the path through vias VB3, VB2, and VB1 connecting wiring WL1 and wiring WL2, one electrode of capacitor CM can be electrically connected to pad PD. By using wiring WL1, vias VB1, VB2, and VB3, and wiring WL2 to detour the path, the parasitic resistance of wiring WL1, WL2, and vias VB1, VB2, and VB3 is increased, thereby increasing the resistance value R2 of the second conductive path PT2.

[0084] Furthermore, the substrate PSB and well PWL are set to the potential of the first power supply, and the pad PD is a pad supplied with a potential different from the potential of the first power supply. For example, when the conductivity type of the substrate PSB and well PWL is P-type, the substrate PSB and well PWL are set to the low-potential side of the first power supply, such as GND. And, the pad PD is a pad supplied with a potential different from the first power supply, such as VDD, when the circuit device 10 is operating. Alternatively, the conductivity type of the substrate and well may be N-type, in which case the first power supply becomes the high-potential side power supply.

[0085] In this way, the MIM capacitor CM can be used as a capacitor for stabilizing the potential between the well PWL and the pad PD. Moreover, when the substrate PSB has accumulated charge, if the pad PD is set to the potential of the first power supply, for example, the accumulated charge can be discharged using the first conductive path PT1 instead of the second conductive path PT2 through the capacitor CM.

[0086] Additionally, the first conductive path PT1 includes multiple vias connecting the metal layers. For example, in Figure 1 , Figure 5 In the first conductive path PT1, there are multiple through holes VA1, VA2, VA3, and VA4 that connect the metal layers ALA and ALB, ALB and ALC, ALC and ALD, and ALD and ALE.

[0087] In this way, when the substrate PSB has accumulated charge, the accumulated charge can be discharged from the pad PD through the vias VA1, VA2, VA3, and VA4 of the first conductive path PT1.

[0088] In addition, such as Figure 1 , Figure 5 As shown, the circuit device 10 of this embodiment includes a substrate PSB, a well PWL, a well NWL, a pad PD, and a MIM capacitor CM. Furthermore, the well NWL is electrically connected to the pad PD via a first conductive path PT1, one of the electrodes ELA and ELB is electrically connected to the pad PD via a second conductive path PT2, and the other electrode of ELA and ELB is electrically connected to the well PWL via a third conductive path PT3. The second conductive path PT2 includes wiring WL1 of the same or upper metal layer of the metal layer of electrode ELA and wiring WL2 of the lower metal layer of the metal layer of electrode ELA.

[0089] Therefore, one electrode of capacitor CM is electrically connected to pad PD via a second conductive path PT2. This second conductive path PT2 is circuitous, passing through wiring WL1 on the same or upper metal layer as electrode ELA of capacitor CM and wiring WL2 on the lower metal layer of electrode ELA. This circuitous path via wiring WL1 and WL2 adds parasitic resistance to wiring WL1, WL2, etc., which suppresses charge discharge in the second conductive path PT2 and prevents insulation damage to the MIM capacitor CM.

[0090] Furthermore, the circuit device 10 of this embodiment has multiple wiring layers formed of metal layers, and these multiple wiring layers are four or more, typically four or five layers. For example, in Figure 1 , Figure 5In this configuration, there are five metal layers, ALA to ALE, serving as multiple wiring layers. These wiring layers are used for signal transmission and power supply; to achieve miniaturization of the wiring-based three-dimensional crossover, four or more layers are preferred. Upper wiring layers are used for long-distance signal transmission and power supply, while lower wiring layers are used for short-distance signal transmission and power supply. For example, the wiring layer on the transistor side of the multiple wiring layers is used as local wiring, connecting the source, drain, and gate of the transistor. The conductive layer above it serves as intermediate wiring, connecting the local wiring to the global wiring for medium-distance signal transmission and power supply. Intermediate wiring may also include wiring layers primarily containing wiring extending along a first direction and wiring layers primarily containing wiring extending along a second direction intersecting the first direction. The upper layer serves as global wiring for long-distance signal transmission. For example, intermediate wiring can be wiring within a circuit block, and global wiring can be wiring between circuit blocks. Alternatively, GND wiring can be formed in two adjacent layers of the four layers, and VDD wiring can be formed in two other different layers. By forming power wiring in multiple layers, power supply stabilization can be achieved. Inductors can also be formed on the topmost wiring layer, and the topmost wiring layer can be thicker than other wiring layers.

[0091] 2. Detailed examples of circuit devices

[0092] Figure 13 A detailed structural example of the circuit device 10 of this embodiment is shown. The circuit device 10 includes an oscillation circuit 11 and an output circuit 12. Additionally, the circuit device 10 may include a control circuit 13, a power supply circuit 14, a temperature compensation circuit 15, a temperature sensor circuit 16, and a memory 17. Furthermore, the vibration device 1 of this embodiment includes a vibration element 5 and the circuit device 10, with the vibration element 5 electrically connected to the circuit device 10. Furthermore, the structures of the circuit device 10 and the vibration device 1 are not limited to... Figure 13 The structure allows for various transformations, such as omitting some structural elements, adding other structural elements, or replacing some structural elements with other structural elements. For example, in Figure 13 In this circuit, a clock signal generation circuit, such as a PLL circuit that doubles the clock frequency, can be installed between the oscillation circuit 11 and the output circuit 12. Furthermore, Figure 13 The diagram shows a structural example where the vibration device 1 is an oscillator that generates a clock signal CK, but the vibration device 1 can also be a device such as a gyroscope sensor or an accelerometer sensor.

[0093] like Figure 13As shown, the vibrating device 1 includes terminals TCK, TOE, TVDD, and TGND. Terminal TCK is used to output the clock signal CK, and terminal TOE is used to input / output the enable signal OE. TVDD is the terminal supplied with the power supply voltage VDD, and TGND is the terminal supplied with the ground voltage GND. GND can also be called VSS. For example, VDD corresponds to the high-potential side power supply voltage, and GND corresponds to the low-potential side power supply voltage. These terminals TCK, TOE, TVDD, and TGND are described later. Figure 14 The external connection terminals 91 and 92 correspond to each other. For example, if it is a 4-terminal vibrating device 1, then 4 terminals are provided as external connection terminals 91 and 92. In addition, the number of terminals of the vibrating device 1 is not limited to this, and can be more or less. Furthermore, the circuit device 10 includes pads PCK, POE, PVDD, PGND, PX1, and PX2. The pads are the terminals of the circuit device 10. These pads PCK, POE, PVDD, and PGND are electrically connected to the terminals TCK, TOE, TVDD, and TGND of the vibrating device 1.

[0094] The oscillation circuit 11 is a circuit that causes the vibrating element 5 to oscillate. For example, the oscillation circuit 11 is electrically connected to the vibrating element 5 via pads PX1 and PX2, and generates an oscillation signal by causing the vibrating element 5 to oscillate. For example, the oscillation circuit 11 can be implemented using an oscillation drive circuit and passive components such as capacitors and resistors provided between pads PX1 and PX2. The drive circuit can be implemented, for example, using a CMOS inverter circuit or a bipolar transistor. The drive circuit is the core circuit of the oscillation circuit 11, and it drives the vibrating element 5 with voltage or current, thereby causing the vibrating element 5 to oscillate. As the oscillation circuit 11, various types of oscillation circuits such as inverter type, Pierce type, Colpitts type, or Hartley type can be used, for example. In addition, the oscillation circuit 11 is provided with a variable capacitor circuit 86, and the oscillation frequency can be adjusted by adjusting the capacitance of the variable capacitor circuit 86. The variable capacitor circuit 86 can be implemented, for example, using a variable capacitor element such as a varactor diode. Alternatively, the variable capacitor circuit 86 can also be implemented using a capacitor array and a switch array connected to the capacitor array. For example, the variable capacitor circuit 86 can also be composed of a capacitor array and a switch array, wherein the capacitor array has multiple capacitors whose capacitance values ​​are binary weighted, and the switch array has multiple switches that enable or disable the connection between each capacitor in the capacitor array and pad PX1 or pad PX2.

[0095] Output circuit 12 outputs a clock signal CK based on an oscillation signal. For example, output circuit 12 buffers an oscillation clock signal based on an oscillation signal and outputs it as clock signal CK to pad PCK. This clock signal CK is then output to the outside via terminal TCK of the oscillating device 1. For example, output circuit 12 outputs the clock signal CK in the form of a single-ended CMOS signal. For example, when the output enable signal OE, input from terminal TOE via pad POE, is active, output circuit 12 outputs the clock signal CK under the control of control circuit 13. On the other hand, when the output enable signal OE is inactive, output circuit 12 sets the clock signal CK to a fixed voltage level, such as a low level. Furthermore, output circuit 12 can output a differential clock signal in the form of signals such as LVDS (Low Voltage Differential Signaling), PECL (Positive Emitter Coupled Logic), HCSL (High Speed ​​Current Steering Logic), or differential CMOS (Complementary MOS). In this case, two clock terminals and pads for the positive and negative polarities of the differential clock signal can be set, and the oscillating device 1 is, for example, a 6-terminal oscillator.

[0096] The control circuit 13 is a logic circuit that performs various control processes. For example, the control circuit 13 controls the circuit device 10 as a whole, or controls the sequence of actions of the circuit device 10. Furthermore, the control circuit 13 can also control the oscillation circuit 11, the power supply circuit 14, the temperature compensation circuit 15, or the memory 17, etc. The control circuit 13 can be implemented, for example, using an ASIC (Application Specific Integrated Circuit) circuit based on automatic configuration routing such as a gate array.

[0097] The power supply circuit 14 is supplied with VDD, the power supply voltage, from the terminal TVDD via the pad PVDD, and with GND, the ground voltage, from the terminal TGND via the pad PGND. Furthermore, the power supply circuit 14 provides power supply voltages for each internal circuit of the circuit device 10.

[0098] The power supply circuit 14 includes a reference voltage generation circuit 80, which generates a reference voltage used in the circuit device 10. Additionally, the power supply circuit 14 includes a voltage regulator circuit 81, which generates a regulated output voltage used in the circuit device 10. This regulated output voltage is supplied to various circuits in the circuit device 10, including the oscillation circuit 11, the output circuit 12, and the control circuit 13.

[0099] The temperature compensation circuit 15 performs temperature compensation for the oscillation frequency of the oscillation circuit 11. Furthermore, the output circuit 12 outputs a clock signal CK based on the temperature-compensated oscillation signal. Specifically, the temperature compensation circuit 15 performs temperature compensation based on the temperature detection signal from the temperature sensor circuit 16. For example, the temperature compensation circuit 15 generates a temperature compensation voltage based on the temperature detection voltage from the temperature sensor circuit 16 and outputs the generated temperature compensation voltage to the oscillation circuit 11, thereby performing temperature compensation for the oscillation frequency of the oscillation circuit 11. For example, the temperature compensation circuit 15 performs temperature compensation by outputting a temperature compensation voltage as the capacitor control voltage of the variable capacitor circuit 86 included in the oscillation circuit 11. In this case, the variable capacitor circuit 86 of the oscillation circuit 11 is implemented by a variable capacitor element such as a varactor diode. Temperature compensation is, for example, a process that compensates for changes in the oscillation frequency caused by temperature variations. For example, the temperature compensation circuit 15 performs temperature compensation based on a polynomial approximation analog method. For example, when the temperature compensation voltage is used to approximate the frequency-temperature characteristics of the vibrating element 5 using a polynomial, the temperature compensation circuit 15 performs analog-based temperature compensation based on the coefficient information of the polynomial.

[0100] Alternatively, the temperature compensation circuit 15 can also perform temperature compensation digitally. In this case, the temperature compensation circuit 15 is implemented, for example, through logic circuits. Specifically, the temperature compensation circuit 15 performs digital temperature compensation processing based on the temperature detection signal, i.e., the temperature detection data, from the temperature sensor circuit 16. For example, the temperature compensation circuit 15 calculates frequency adjustment data based on the temperature detection data. Furthermore, by adjusting the capacitance value of the variable capacitor circuit 86 of the oscillation circuit 11 based on the calculated frequency adjustment data, temperature compensation processing of the oscillation frequency of the oscillation circuit 11 is achieved. In this case, the variable capacitor circuit 86 of the oscillation circuit 11 is implemented using a capacitor array and a switch array having multiple capacitors with binary weighting. In addition, the memory 17 stores a lookup table representing the correspondence between the temperature detection data and the frequency adjustment data. The temperature compensation circuit 15 uses the lookup table read from the memory 17 by the control circuit 13 to perform temperature compensation processing to calculate the frequency adjustment data based on the temperature data.

[0101] Temperature sensor circuit 16 is a sensor circuit for detecting temperature. Temperature sensor circuit 16 outputs a temperature-dependent voltage that varies according to the ambient temperature as a temperature detection voltage. For example, temperature sensor circuit 16 generates the temperature detection voltage using circuit elements with temperature dependence. Specifically, temperature sensor circuit 16 outputs a temperature detection voltage whose voltage value varies with temperature by utilizing the temperature dependence of the forward voltage of a PN junction. The forward voltage of the PN junction can be, for example, the base-emitter voltage of a bipolar transistor.

[0102] Furthermore, when performing digital temperature compensation processing, the temperature sensor circuit 16 measures the ambient temperature and other temperatures, and outputs the results as temperature detection data. The temperature detection data is data that increases or decreases monotonically relative to the temperature, for example. In this case, the temperature sensor circuit 16 can utilize a temperature sensor circuit whose oscillation frequency is temperature-dependent.

[0103] The memory 17 stores various information used in the circuit device 10. The memory 17 is, for example, a non-volatile memory. The non-volatile memory is an EEPROM such as a FAMOS (Floating Gate Avalanche Injection MOS) memory or a MONOS (Metal-Oxide-Nitride-Oxide-Silicon) memory, but is not limited to these; it can also be an OTP (One-Time Programmable) memory or a fuse-type ROM. Alternatively, the memory 17 can also be implemented using a volatile memory such as RAM.

[0104] Furthermore, in this embodiment, as Figure 13 As shown, a capacitor CA is placed between the VDD pad PVDD and the GND pad PGND. Pad PVDD corresponds to... Figure 1 , Figure 5 , Figure 6 The pads PD and PGND correspond to Figure 6 The pad PD2. Furthermore, capacitor CA is a bypass capacitor used for power supply stabilization. As the power supply stabilization capacitor CA, a MIM capacitor CM is used.

[0105] When the circuit device 10 operates, it supplies VDD to the PVDD pad and GND to the PGND pad. However, during the manufacturing of the vibrating device 1, static electricity can sometimes cause charge to accumulate on the PSB substrate of the circuit device 10. Furthermore, when this charge is accumulated on the PSB substrate, for example, if the terminal TVDD of the vibrating device 1 comes into contact with an object at the GND potential, the accumulated charge can discharge to GND via the PVDD pad and the TVDD terminal. In this case, in this embodiment, the circuit device 10 also operates as described above. Figure 1 , Figure 4 , Figure 5 As explained, the charge is discharged via the first conductive path PT1 instead of the second conductive path PT2, thus preventing the capacitor CA, which is composed of MIM capacitor CM, from being damaged by electrostatic discharge.

[0106] 3. Vibrating devices

[0107] Figure 14 This is a cross-sectional view showing a structural example of the vibration device 1 according to this embodiment. Figure 14 As shown, the vibration device 1 of this embodiment includes a base 2, a cover 3, and a vibration element 5. Furthermore, the vibration device 1 may include a reconfigurable wiring layer 8 and external connection terminals 91 and 92. In the figures described in this embodiment, the X-axis, Y-axis, and Z-axis are illustrated as three mutually orthogonal axes. The direction along the X-axis is referred to as the X-axis direction or direction DR1, the direction along the Y-axis is referred to as the Y-axis direction or direction DR2, and the direction along the Z-axis is referred to as the Z-axis direction or direction DR3. Additionally, the front end of the arrow in each axis direction is referred to as the "positive side," the base end side as the "negative side," the positive side of the Z-axis direction as "up," and the negative side of the Z-axis direction as "down." For example, the Z-axis direction is along the vertical direction, and the XY plane is along the horizontal plane. Figure 14 This is a cross-sectional view of the vibrating device 1 taken from the direction DR2, which is the Y-axis.

[0108] Vibrating device 1 is, for example, an oscillator. Specifically, vibrating device 1 can be, for example, a temperature-compensated quartz oscillator (TCXO), a quartz oscillator with a thermostatic bath (OCXO), a voltage-controlled quartz oscillator (VCXO), a quartz oscillator without temperature compensation (SPXO), a SAW (Surface Acoustic Wave) oscillator, a voltage-controlled SAW oscillator, a MEMS (Micro Electro Mechanical Systems) oscillator, etc. A MEMS oscillator can be implemented using a MEMS vibrating element with a piezoelectric film and electrodes disposed on a substrate such as a silicon substrate. However, vibrating device 1 can also be an inertial sensor such as an accelerometer or angular velocity sensor, a force sensor such as a tilt sensor, etc.

[0109] The base 2 includes a substrate 20. The substrate 20 is a semiconductor substrate, such as a silicon substrate. The substrate 20 has a first surface 21 and a second surface 22 opposite to the first surface 21. The first surface 21 is, for example, the upper surface of the substrate 20, and the second surface 22 is, for example, the lower surface of the substrate 20. The first surface 21 and the second surface 22 of the substrate 20 are also the first surface and the second surface of the base 2. The first surface 21 and the second surface 22 of the substrate 20 are surfaces along the XY plane and are orthogonal to the Z-axis. That is, the first surface 21 and the second surface 22 are surfaces along directions DR1 and DR2, and are orthogonal to direction DR3. In addition, "orthogonal" includes not only the case of intersecting at 90°, but also the case of intersecting at an angle slightly inclined from 90°.

[0110] Furthermore, an integrated circuit 19 is disposed on the substrate 20 of the base 2. The integrated circuit 19, as a semiconductor circuit, is formed on the second surface 22 of the substrate 20. It is also possible to disposed of the integrated circuit 19 on the first surface 21 of the substrate 20. The integrated circuit 19 is composed of multiple circuit elements. The circuit elements are, for example, active elements such as transistors or diodes, or passive elements such as capacitors, resistors, or inductors. The transistors are CMOS transistors or bipolar transistors, etc. Specifically, each circuit block of the integrated circuit 19 is composed of multiple circuit blocks containing multiple circuit elements. In addition, the integrated circuit 19 is formed by a diffusion region, which is a region of impurities formed by doping the substrate 20 with impurities, and a wiring layer formed by stacking a metal layer and an insulating layer. The source region and drain region of the transistor, which is a circuit element of the integrated circuit 19, are formed through the diffusion region, and wiring connecting the circuit elements is formed through the wiring region.

[0111] and, Figure 14 The substrate 20 corresponds to Figure 1 , Figure 5 The substrate PSB. Furthermore, by providing integrated circuit 19 on substrate 20, [the following is achieved]... Figure 1 , Figure 5 Circuit device 10.

[0112] Furthermore, a through electrode 40 is provided on the substrate 20 of the base 2. The through electrode 40 is made of a conductive material that penetrates the first surface 21 and the second surface 22 of the substrate 20. For example, a through hole is formed in the substrate 20, and the through hole is filled with a conductive material to form the through electrode 40. The conductive material can be a metal such as copper, or a conductive polysilicon such as polysilicon. Conductive polysilicon refers to polysilicon that has been doped with impurities such as phosphorus (P), boron (B), or arsenic (As) to acquire conductivity. If polysilicon is used as the conductive material, the through electrode 40 can be made to have sufficient resistance to the heat applied during the formation process of the integrated circuit 19.

[0113] One end of the through electrode 40 is electrically connected to the vibrating element 5 via a conductive joint 60. Figure 14 In this design, the conductive bonding portion 60 is achieved by a bump or similar component that is electrically connected at one end to the vibrating element 5 and at the other end to the through electrode 40. The bump is a conductive bonding component, specifically a gold bump, silver bump, copper bump, solder bump, or resin core bump. Alternatively, the conductive bonding portion 60 can also be a conductive adhesive containing conductive fillers such as silver filler dispersed in various polyimide-based, epoxy-based, silicone-based, or acrylic-based adhesives. The other end of the through electrode 40 is electrically connected to the integrated circuit 19. Specifically, the other end of the through electrode 40 is connected to the circuit elements of the integrated circuit 19 via a contact pad formed on the integrated circuit 19. Thus, the vibrating element 5 and the integrated circuit 19 can be electrically connected via the through electrode 40.

[0114] The cover 3 is joined to the base 2 at joints 36 and 37. The base 2 is, for example, made of a semiconductor substrate such as a silicon substrate. Specifically, the cover 3 is provided with a recess 30 for accommodating the vibrating element 5, and has sidewalls 32 and 33 surrounding the recess 30. The sidewalls 32 and 33 are, for example, walls surrounding the recess 30 when viewed from above in the direction DR3, which is the Z-axis direction. Furthermore, the end faces 34 and 35 of the sidewalls 32 and 33 are joined to the first surface 21 of the base 2 at joints 36 and 37. The joints 36 and 37 are, for example, made of a metal film such as gold or copper. Furthermore, the base 2 and the cover 3 are joined by applying a weight-based pressure, as described later, to the joints 36 and 37 of the metal film such as gold. In addition, the method of joining the base 2 and the cover 3 at the joints 36 and 37 is not limited to this, and various joining methods such as direct joining can be considered. Furthermore, the base 2 and the cover 3 form an airtight storage space SP, within which the vibrating element 5 is housed. This storage space SP corresponds to the recess 30 of the cover 3. The storage space SP is airtightly sealed, and for example, it is in a depressurized state. Therefore, the vibrating element 5 can be stably driven. However, the state within the storage space SP is not limited to a depressurized state; for example, the storage space SP can also be in an inert gas atmosphere.

[0115] In this embodiment, both the base 2 and the cover 3 are made of a semiconductor substrate, such as a silicon substrate. This allows the base 2 and the cover 3 to have equal coefficients of thermal expansion, suppressing the generation of thermal stress caused by thermal expansion and enabling the realization of a vibration device 1 with excellent characteristics. Furthermore, since the vibration device 1 can be formed using semiconductor processes, it can be manufactured with high precision and efficiency, and its miniaturization can be achieved. Additionally, the semiconductor substrate constituting the base 2 and the cover 3 is not limited to a silicon substrate, but can also be a semiconductor substrate such as Ge, GaP, GaAs, or InP.

[0116] Vibration element 5 is a component that generates mechanical vibration through an electrical signal. Vibration element 5 is electrically connected to integrated circuit 19 (circuit device 10). For example, vibration element 5 is disposed on the first surface 21 side of substrate 20. Specifically, vibration element 5 is disposed at a position away from the first surface 21 of substrate 20 at a given separation distance. More specifically, vibration element 5 is fixed to the first surface 21 of substrate 20, for example, via a conductive bonding portion 60.

[0117] For example, the vibrating element 5 has a vibrating substrate and electrodes disposed on the surface of the vibrating substrate. The vibrating substrate has a thickness shear vibration mode and is formed, for example, from an AT-cut quartz substrate. Since the AT-cut quartz substrate has a third-order temperature characteristic, it becomes a vibrating element 5 with excellent temperature characteristics. Furthermore, the electrodes include an excitation electrode disposed on the upper surface of the vibrating substrate and an excitation electrode disposed opposite to the excitation electrode on the lower surface.

[0118] Furthermore, the structure of the vibration element 5 is not limited to the structure described above. For example, the vibration element 5 can be a mesa type where the vibration region, sandwiched between two excitation electrodes, protrudes from its periphery; conversely, it can be an inverted mesa type where the vibration region is recessed from its periphery. Additionally, it can be machined with a beveled surface by grinding around the vibrating substrate, or with a convex surface by making the upper and lower surfaces convex curved surfaces. Moreover, the vibration element 5 is not limited to vibrating in a thickness shear vibration mode. For example, the vibration element 5 can be a tuning fork type vibration element with multiple vibrating arms bending in the in-plane direction, a tuning fork type vibration element with multiple vibrating arms bending in the out-of-plane direction, a gyroscope sensor element having a drive arm for driving vibration and a detection arm for detecting vibration to detect angular velocity, or an acceleration sensor element having a detection section for detecting acceleration. Furthermore, the vibrating substrate is not limited to being formed from an AT-cut quartz substrate; it can also be formed from quartz substrates other than AT-cut quartz substrates, such as X-cut, Y-cut, Z-cut, BT-cut, SC-cut, or ST-cut quartz substrates. In this embodiment, the vibrating substrate is made of quartz, but it is not limited to this; for example, it can be made of piezoelectric single crystals such as lithium niobate, lithium tantalate, lithium tetraborate, potassium niobate, or gallium phosphate, or other piezoelectric single crystals. Additionally, the vibrating element 5 is not limited to a piezoelectrically driven vibrating element; it can also be an electrostatically driven vibrating element using electrostatic force.

[0119] External connection terminals 91 and 92 are disposed on the second surface 22 side of the substrate 20 via an insulating layer or the like. The insulating layer is, for example, the insulating layer constituting the redistribution wiring layer 8.

[0120] A reconfigurable wiring layer 8 is disposed on the second surface 22 side of the substrate 20, and includes an insulating layer and wiring for reconfiguration wiring. The insulating layer is, for example, made of a resin layer such as polyimide, and the wiring is, for example, made of a metal wiring such as copper foil. The insulating layer needs to have heat resistance to withstand the soldering during the mounting of the vibration device 1, and polyimide is preferred. In addition, the wiring material can also be a metal material such as silver, besides copper. By providing the reconfigurable wiring layer 8, the pads for contacts formed on the integrated circuit 19 can be electrically connected to the external connection terminals 91, 92. Furthermore, by connecting the external connection terminals 91, 92 of the vibration device 1 to the terminals and wiring of the circuit board on which the vibration device 1 is mounted, the vibration device 1 can be assembled into an electronic device. In addition, by providing such a reconfigurable wiring layer 8, local mechanical protection and thermal protection of the integrated circuit 19 can be provided to protect the integrated circuit 19 from the heat of the soldering process during the mounting of the vibration device 1.

[0121] Next, use Figures 15-21 An example of the manufacturing process for vibrating device 1 will be described. First, as follows... Figure 15 As shown, an integrated circuit 19 is formed on the first semiconductor wafer 120, and a wiring layer 8 and external connection terminals 91 and 92 are then configured. Then, as... Figure 16 As shown, the first surface 21 of the first semiconductor wafer 120 is ground and polished to a thickness of, for example, approximately 60 μm to 80 μm. Then, as... Figure 17 As shown, a through-silicon via (TSV) 41 is formed on the first semiconductor wafer 120, and an insulating film 42, such as silicon oxide (SiO2), is formed on the inner surface of the TSV 41. Then, as... Figure 18 As shown, a through electrode 40 is formed in the through hole 41.

[0122] Next, as Figure 19 As shown, the vibrating element 5 is connected to the junction 60. Thus, the vibrating element 5 is electrically connected to the integrated circuit 19. Additionally, a second semiconductor wafer 130 for forming the cover 3 is prepared, and a metal film 132, made of a bonding film such as gold, is formed on the recessed side of the second semiconductor wafer 130.

[0123] Next, as Figure 20 As shown, the second semiconductor wafer 130 forming the cover 3 is bonded to the first semiconductor wafer 120 forming the base 2 by applying stress via bonding portions 36 and 37. This bonding is performed, for example, under a vacuum atmosphere. Bonding portions 36 and 37 are formed by... Figure 19 The bonding portion is formed by a metal film 132 such as gold. When bonding the second semiconductor wafer 130 to the first semiconductor wafer 120, the force applied by the load is, for example, 10 tons or more, and for example, about 20 tons.

[0124] Next, as Figure 21 As shown, after grinding, the vibrating device 1 is cut into single pieces using a cutting saw or the like. Through this process, multiple vibrating devices 1 can be monolithically produced from the first semiconductor wafer 120 and the second semiconductor wafer 130. The length of the long side of the vibrating device 1 when viewed from above is, for example, approximately 1.2 mm to 1.0 mm, and the length of the short side is, for example, approximately 1.0 mm to 0.8 mm. The width of the cutting edge is, for example, approximately 20 μm, and the width of the joints 36 and 37 of the vibrating device 1 is, for example, approximately 30 μm to 100 μm, and for example, approximately 60 μm.

[0125] As described above, the circuit device 10 of this embodiment is implemented by providing an integrated circuit 19 on a substrate 20. Furthermore, the vibration device 1 of this embodiment includes: a circuit device 10 (integrated circuit 19, substrate 20); a through electrode 40 disposed on the substrate 20 of the circuit device 10; a vibration element 5 electrically connected to the through electrode 40; and a cover 3 that houses the vibration element 5 together with the substrate 20. Specifically, the vibration device 1 of this embodiment has a first surface 21 and a second surface 22, and for example includes: a base 2, which includes the substrate 20 on the second surface 22 where the integrated circuit 19 is disposed; and a vibration element 5 electrically connected to the integrated circuit 19. In addition, the vibration device 1 includes a cover 3, which has sidewall portions 32 and 33 surrounding a recess 30 for housing the vibration element 5, and the end faces 34 and 35 of the sidewall portions 32 and 33 are engaged with the first surface 21 at joint portions 36 and 37.

[0126] For example, in conventional vibration devices, the IC chip and the quartz vibration element are integrated into a ceramic package. In contrast, in... Figures 14-21 The WLP (Wafer Level Packaging) vibration device 1 described herein encapsulates the IC itself, thus maximizing the area of ​​the integrated circuit 19, which is the IC, and enabling the realization of a small and high-performance oscillator. For example, in ceramic-packaged vibration devices, the area of ​​the IC when viewed from above is, for example, less than 50% to 60% of the package area of ​​the vibration device. In contrast, according to the WLP vibration device 1, the area of ​​the integrated circuit 19 can be, for example, 50% to 60% larger than the area of ​​the base 2. Therefore, circuitry for enabling higher functionality of the vibration device 1 can be provided in the integrated circuit 19.

[0127] Furthermore, in Figure 14 In such a WLP vibrating device 1, charge may sometimes be accumulated in the substrate 20 via the cover 3 or the like during its manufacturing process. Moreover, when an external connection terminal of the external connection terminals 91 and 92, for example, connected to the pad of VDD, comes into contact with an object with the potential of GND, charge discharge may occur in the substrate 20.

[0128] Regarding this point, in this embodiment, as Figure 1 , Figure 5 As explained, the resistance value in the second conductive path PT2, which connects the electrodes of the MIM capacitor CM to the pads, increases. Thus, the charge on the substrate 20 is discharged via the first conductive path PT1 instead of through the second conductive path PT2 of the MIM capacitor CM, thereby preventing electrostatic damage to the MIM capacitor CM.

[0129] As described above, the circuit device 10 of this embodiment includes: a substrate of a first conductivity type; a first well of the first conductivity type disposed on the substrate; a second well of the second conductivity type disposed on the substrate; a pad; and a MIM capacitor having a first electrode, a second electrode, and a dielectric layer disposed between the first electrode and the second electrode. Furthermore, the second well and the pad are electrically connected via a first conductive path, one electrode of the first electrode and one electrode of the second electrode are electrically connected to the pad via a second conductive path, and the other electrode of the first electrode and the second electrode are electrically connected to the first well via a third conductive path. Moreover, the resistance value of the second conductive path is greater than the resistance value of the first conductive path.

[0130] According to this embodiment, the second well is connected to the pad via a first conductive path, and one electrode of the MIM capacitor is connected to the pad via a second conductive path PT2. Furthermore, the resistance of the second conductive path is greater than the resistance of the first conductive path. Thus, the charge accumulated on the substrate flows to the pad side via the first conductive path with lower resistance, rather than through the second conductive path with higher resistance. This prevents the MIM capacitor from being damaged by electrostatic discharge.

[0131] In addition, in this embodiment, the second conductive path may also include the first wiring of the same layer or the upper layer of the metal layer of the first electrode.

[0132] In this way, by means of the first wiring of the metal layer in the same or upper layer of the capacitor, the second conductive path is made to meander, and one electrode of the capacitor is electrically connected to the pad, which can increase the resistance value of the second conductive path.

[0133] Alternatively, in this embodiment, one end of the first wiring may be electrically connected to an electrode, and the other end of the first wiring may be electrically connected to a first conductive path.

[0134] In this way, by means of a second conductive path that detours through the path of the first wiring and at least a portion of the first conductive path, one electrode of the capacitor is electrically connected to the pad, thereby increasing the resistance value of the second conductive path.

[0135] In addition, in this embodiment, the second conductive path may also include a second wiring of the metal layer below the metal layer of the first electrode.

[0136] In this way, by using the second wiring of the metal layer below the first electrode of the capacitor to make the path detour to the second conductive path, one electrode of the capacitor is electrically connected to the pad, which can increase the resistance value of the second conductive path.

[0137] In addition, in this embodiment, the metal layer of the second wiring can also be the bottommost metal layer.

[0138] In this way, by using a second conductive path that detours from the metal layer of one electrode of the capacitor to the second wiring of the bottommost metal layer, one electrode of the capacitor can be electrically connected to the pad.

[0139] In addition, in this embodiment, the second conductive path may include: a first wiring of a metal layer in the same or upper layer of the metal layer of the first electrode; and a second wiring of a metal layer below the metal layer of the first electrode, wherein the first wiring and the second wiring are electrically connected via a via that connects the metal layers.

[0140] In this way, by means of a first wiring, a second wiring, and a second conductive path that makes the path meander by connecting the first wiring and the second wiring, one electrode of the capacitor can be electrically connected to the pad.

[0141] Alternatively, in this embodiment, the substrate and the first well may be set to the potential of the first power supply, and the pads may be pads supplied with a potential different from that of the first power supply.

[0142] In this way, when a charge is accumulated on the substrate, and the pad is set to a potential of, for example, a first power supply, the accumulated charge can be discharged via a first conductive path instead of via a second conductive path through a capacitor.

[0143] In addition, in this embodiment, the first conductive path may also include multiple vias connecting the metal layers.

[0144] In this way, when the substrate has accumulated charge, the accumulated charge can be discharged from the pad through the via of the first conductive path.

[0145] Furthermore, the circuit arrangement of this embodiment includes: a substrate of a first conductivity type; a first well of the first conductivity type disposed on the substrate; a second well of the second conductivity type disposed on the substrate; a pad; and a MIM capacitor having a first electrode, a second electrode, and a dielectric layer disposed between the first electrode and the second electrode. Additionally, the second well and the pad are electrically connected via a first conductive path, one electrode of the first electrode and one electrode of the second electrode are electrically connected to the pad via a second conductive path, and the other electrode of the first electrode and the second electrode are electrically connected to the first well via a third conductive path. Furthermore, the second conductive path includes: a first wiring of a metal layer on the same or upper layer as the metal layer of the first electrode; and a second wiring of a metal layer below the metal layer of the first electrode.

[0146] According to this embodiment, by utilizing a first wiring in a metal layer of the same or upper layer as the first electrode of the capacitor and a second wiring in a metal layer below the first electrode to create a circuitous second conductive path, one electrode of the capacitor is electrically connected to a pad. By utilizing the first and second wirings to create a circuitous path, charge discharge in the second conductive path can be suppressed, preventing electrostatic damage to the MIM capacitor.

[0147] Furthermore, the vibration device of this embodiment includes: the circuit device described above; a through electrode disposed on the substrate of the circuit device; a vibration element electrically connected to the through electrode; and a cover that houses the vibration element together with the substrate.

[0148] This enables the realization of small-sized vibration devices and maximizes the area of ​​integrated circuits for the circuitry of vibration devices.

[0149] Furthermore, while this embodiment has been described in detail above, those skilled in the art will readily understand that various modifications can be made without substantially departing from the new aspects and effects of this disclosure. Therefore, all such modifications are included within the scope of this disclosure. For example, a term described at least once in the specification or drawings along with a different, broader, or synonymous term can be replaced with that different term anywhere in the specification or drawings. Moreover, all combinations of this embodiment and its modifications are also included within the scope of this disclosure. Furthermore, the structure, operation, etc., of the circuit device, vibrating device, etc., are not limited to those described in this embodiment, and various modifications can be implemented.

Claims

1. A circuit device, characterized in that, Include: First type of conductive substrate; The first well of the first conductivity type is disposed on the substrate; A second well of a second conductivity type is disposed on the substrate; solder pads; and A MIM capacitor has a first electrode, a second electrode, and a dielectric layer disposed between the first electrode and the second electrode. The second well is electrically connected to the pad via a first conductive path. One of the first electrode and the second electrode is electrically connected to the pad via a second conductive path. The first electrode and another electrode of the second electrode are electrically connected to the first well via a third conductive path. The resistance value of the second conductive path is greater than the resistance value of the first conductive path.

2. The circuit device according to claim 1, characterized in that, The second conductive path includes a first wiring of a metal layer in the same or upper layer as the metal layer of the first electrode.

3. The circuit device according to claim 2, characterized in that, One end of the first wiring is electrically connected to the electrode, and the other end of the first wiring is electrically connected to the first conductive path.

4. The circuit device according to claim 1, characterized in that, The second conductive path includes a second wiring of a metal layer below the metal layer of the first electrode.

5. The circuit device according to claim 4, characterized in that, The metal layer of the second wiring is the bottommost metal layer.

6. The circuit device according to claim 1, characterized in that, The second conductive path includes: The first wiring of the metal layer in the same or upper layer as the first electrode; and The second wiring of the metal layer below the metal layer of the first electrode. The first wiring and the second wiring are electrically connected via through-holes that connect the metal layers.

7. The circuit device according to claim 1, characterized in that, The substrate and the first well are set to the potential of a first power source. The pads are pads supplied with a potential different from that of the first power source.

8. The circuit device according to claim 1, characterized in that, The first conductive path includes a plurality of vias that connect the metal layers.

9. A circuit device, characterized in that, Include: First type of conductive substrate; The first well of the first conductivity type is disposed on the substrate; A second well of a second conductivity type is disposed on the substrate; solder pads; and A MIM capacitor has a first electrode, a second electrode, and a dielectric layer disposed between the first electrode and the second electrode. The second well is electrically connected to the pad via a first conductive path. One of the first electrode and the second electrode is electrically connected to the pad via a second conductive path. The first electrode and another electrode of the second electrode are electrically connected to the first well via a third conductive path. The second conductive path includes: The first wiring of the metal layer in the same or upper layer as the first electrode; and The second wiring of the metal layer below the metal layer of the first electrode.

10. A vibration device, characterized in that, Include: The circuit device according to any one of claims 1-9; A through electrode is disposed on the substrate of the circuit device; Vibrating element, which is electrically connected to the through electrode; and The cover, together with the substrate, houses the vibrating element.

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