Crystal oscillator circuit and chip with low phase noise

Abstract

The application provides a crystal oscillator circuit and a chip with low phase noise, comprising: a signal generation module for generating a first periodic signal; an output buffer module for enhancing the driving capability of the first periodic signal and outputting the first periodic signal as a second square wave signal; the output buffer module comprises multiple inverters, and the first driving voltage of the output buffer module is Vdd1; wherein the first periodic signal comprises a sine signal or a first square wave signal, and the amplitude of the first periodic signal is greater than or equal to 2Vdd1. The embodiment solves the technical problem that the phase noise of the crystal oscillator circuit is large and cannot meet the requirements in an application scenario sensitive to phase noise, and achieves the technical effect of effectively reducing the phase noise.

Description

Technical Field

[0001] This application relates to the field of crystal oscillator technology, and more particularly to crystal oscillator circuits and chips with low phase noise. Background Technology

[0002] A crystal oscillator (XO), also known as a crystal oscillator, is an electronic component that uses the piezoelectric effect of quartz crystals to generate a stable frequency. In radio frequency transceiver chip systems, the crystal oscillator is responsible for generating a square wave signal of a certain frequency as a clock.

[0003] like Figure 1A As shown, existing crystal oscillator circuits typically consist of three parts: an existing oscillator unit 13, an existing self-biasing unit 14, and an existing output buffer module 25. These crystal oscillator circuits rely on a single driving voltage to achieve a relatively stable square wave signal output under PVT (Process Voltage Temperature), providing a clock signal for relevant electronic devices. However, in applications sensitive to phase noise, such as high-precision communication and high-end measuring instruments, the phase noise of existing crystal oscillator circuits is relatively high, failing to meet the requirements for low phase noise. Summary of the Invention

[0004] The purpose of this application is to provide a low-phase-noise crystal oscillator circuit, a stand-alone chip, and a square-wave output device to solve the technical problem of high phase noise in existing crystal oscillator circuits in applications sensitive to phase noise.

[0005] For the purposes mentioned above, this application provides the following technical solution: The first aspect of this application provides a low-phase-noise crystal oscillator circuit, comprising: The signal generation module is used to generate the first cycle signal; An output buffer module is used to enhance the driving capability of the first periodic signal and output the first periodic signal as a second square wave signal; the output buffer module includes a multi-stage inverter, and the first driving voltage of the output buffer module is Vdd1; The first periodic signal includes a sine wave signal or a first square wave signal, and the amplitude of the first periodic signal is greater than or equal to... .

[0006] Furthermore, the signal generation module includes: An oscillator unit for generating a sinusoidal signal includes a crystal subunit and a matching subunit. The crystal subunit includes a passive crystal, a first capacitor, and a second capacitor. The matching subunit includes a first feedback resistor, a bias current transistor, and a first inverter. A self-biasing unit is used to convert the sinusoidal signal into a first square wave signal; the self-biasing unit includes a DC blocking capacitor, a second feedback resistor, and a second inverter; The output buffer module also includes a level conversion unit for converting a high level to a low level; The driving voltage of both the oscillator unit and the self-biasing unit is the second driving voltage Vdd2, which is greater than the first driving voltage Vdd1.

[0007] Furthermore, the signal generation module includes: An oscillator unit for generating a sinusoidal signal includes a crystal subunit and a matching subunit. The crystal subunit includes a passive crystal, a first capacitor, and a second capacitor. The matching subunit includes a first feedback resistor, a bias current transistor group, a switching group, and a first inverter. A self-biasing unit is used to convert the sinusoidal signal into a first square wave signal; the self-biasing unit includes a DC blocking capacitor, a second feedback resistor, and a second inverter; The bias voltage of both the oscillator unit and the self-biasing unit is the first driving voltage Vdd1. The number of switches in the switch group is equal to the number of bias current transistors in the bias current transistor group. The switches are connected in series between the bias current transistors and the bias voltage.

[0008] Furthermore, the number of switches in the switch group and the number of bias current transistors in the bias current transistor group are both 3.

[0009] Furthermore, the signal generation module includes: An oscillator unit for generating a sinusoidal signal includes a crystal subunit and a matching subunit. The crystal subunit includes a passive crystal, a first capacitor, and a second capacitor. The matching subunit includes a second feedback resistor and a CMOS inverter. The bias voltage of the oscillator unit is the first driving voltage Vdd1.

[0010] Furthermore, the passive crystal, the first capacitor, and the second capacitor in the oscillator unit are separated from other components in the low-phase-noise crystal oscillator circuit.

[0011] Furthermore, the second driving voltage is greater than or equal to 1.4 times the first driving voltage and less than or equal to 1.6 times the first driving voltage.

[0012] Furthermore, it includes a second independent chip, the second independent chip comprising: The matching subunit, the self-biasing unit, and the output buffer module.

[0013] Furthermore, it includes a third independent chip, said third independent chip comprising: The matching subunit and the output buffer module.

[0014] A second aspect of this application provides a chip including the low-phase-noise crystal oscillator circuit described in the first aspect.

[0015] This application has at least the following advantages or beneficial effects: By designing a low-phase-noise crystal oscillator circuit, this application improves the amplitude of the sinusoidal signal output by the oscillator unit. The higher amplitude sinusoidal signal has a steeper slope when passing through the inverter flip-point such as the self-bias unit, and thus the edge is also steeper when it is flipped into a square wave signal, which can significantly improve the phase noise. It solves the technical problem that the phase noise of the crystal oscillator circuit is too large in application scenarios that are sensitive to phase noise, and cannot meet the requirements, thus achieving the technical effect of effectively reducing phase noise. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the specific embodiments of this application or the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0017] Figure 1A This is a schematic diagram of the structure of a crystal oscillator circuit in the prior art; Figure 1B This is a structural diagram of a crystal oscillator circuit in the prior art; Figure 2A for Figure 1B The simulation results of the self-biasing unit and output buffer module of the crystal oscillator circuit shown are illustrated. Figure 2B A schematic diagram of an ideal sinusoidal signal and a phase-distorted signal; Figure 3A This is a schematic diagram of the low phase noise crystal oscillator circuit described in Embodiment 1 of this application; Figure 3B for Figure 3A The simulation results of the low phase noise crystal oscillator circuit are shown in the figure. Figure 3C for Figure 1B The simulation results of the crystal oscillator circuit in the prior art are shown in the figure. Figure 4A This is a schematic diagram of the low phase noise crystal oscillator circuit described in Embodiment 2 of this application; Figure 4Bfor Figure 4A The simulation results of the low phase noise crystal oscillator circuit are shown in the figure. Figure 5A This is a schematic diagram of the low phase noise crystal oscillator circuit described in Embodiment 3 of this application; Figure 5B for Figure 5A The simulation results of the low phase noise crystal oscillator circuit are shown in the figure.

[0018] Figure reference numerals: 10-Signal generation module; 11-Oscillator unit; 12-Self-biasing unit; 20-Output buffer module; 111-Crystal sub-unit; 112-Matching sub-unit; 113-Bias current transistor group; 114-Switch group; 21-Level conversion unit; 13-Existing oscillator unit; 14-Existing self-biasing unit; 25-Existing output buffer module. Detailed Implementation

[0019] The technical solutions of this application will be clearly and completely described below with reference to the embodiments. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0020] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.

[0021] Figure 1B This is a structural diagram of a crystal oscillator circuit in the prior art. (Example:) Figure 1B As shown, the existing oscillator unit 13, the existing self-biasing unit 14, and the existing output buffer module 25 operate under the same driving voltage Vdd1, and the existing oscillator unit 13 uses a P-type metal-oxide-semiconductor (PMOS) field-effect transistor to provide bias. In the prior art, the square wave clock signal CKO generated by the crystal oscillator circuit has poor phase noise performance, and the square wave clock signal CKO is not accurate enough, which makes it difficult to synchronize the clocks of other components in electronic products, and cannot meet the needs of applications with high phase noise requirements, such as high-precision communication and high-end measurement instruments.

[0022] Phase noise is a crucial parameter for active crystal oscillator circuits. Traditional phase noise optimization involves using simulation software to examine the phase noise contribution of each component and then adjusting the design parameters of those components to reduce their impact on the overall phase noise. The phase noise of the square wave clock signal CKO generated by the crystal oscillator circuit is related to... Figure 1B The amplitude of the XOOUT signal is related to the phase noise of the CKO signal. The larger the amplitude of the XOOUT signal, the smaller the phase noise of the CKO signal. Figure 2A for Figure 1B The simulation results of the existing self-biasing unit 14 and the existing output buffer module 25 of the crystal oscillator circuit are shown. Figure 1B As shown, by inputting three sine wave signals with amplitudes of 400mV, 600mV, and 800mV, and one square wave signal at XOOUT, the following result is obtained: Figure 2A The simulation results are shown below. Figure 2A As shown in the simulation results, the square wave signal exhibits the best phase noise, which is due to its near-infinite slew rate at the rising edge. The second best result is a sine wave with an amplitude of 800mV. For the sine wave signal, the phase noise gradually decreases as the amplitude of the input signal increases. The theoretical analysis of the above experimental results is as follows: when signal When amplitude noise and phase noise are present, the output signal can be expressed as ,in It is the random fluctuation of amplitude over time, and is called amplitude noise; It is the random fluctuation of the phase over time, and is called phase noise. Figure 2B This is a schematic diagram of an ideal sinusoidal signal and a phase-distorted signal. (Example:) Figure 2B As shown, an ideal sinusoidal signal is a signal without phase noise. A phase-distorted signal is a signal that contains phase noise. Assume the time it takes for the phase-distorted signal to deviate from the ideal sinusoidal signal is... t, then phase noise = , swing rate , If it is voltage noise, then = Where voltage noise is the sum of phase noise and amplitude noise. That is, the conversion gain from voltage noise to phase noise is... Therefore, the larger the slew rate SR, the smaller the phase noise converted from the same voltage noise, and the better the phase noise performance. With constant frequency and voltage noise, a larger slew rate indicates a sinusoidal signal... The higher the slew rate, the more likely it is that the voltage noise contributed by the device itself cannot be reduced. Figure 1B The larger the amplitude of the XOOUT signal, the smaller the phase noise of CKO.

[0023] Example 1 The low phase noise crystal oscillator circuit provided in this application can increase the amplitude of the output signal of the signal generation module 10, thereby achieving the purpose of optimizing the phase noise of the crystal oscillator circuit. Figure 3A This is a schematic diagram of the low phase noise crystal oscillator circuit described in Embodiment 1 of this application. Figure 3A As shown, the low phase noise crystal oscillator circuit includes a signal generation module 10 and an output buffer module 20.

[0024] The signal generation module 10 is used to generate a first periodic signal, which, according to Embodiment 1, is a first square wave signal. Figure 3A As shown, the signal generation module 10 described in Embodiment 1 includes an oscillator unit 11 and a self-biasing unit 12. The oscillator unit 11 is used to generate a sinusoidal signal, and the oscillator unit 11 includes a crystal subunit 111 and a matching subunit 112. For the sake of simplicity in the illustration, Figure 3A Only the matching subunit 112 is shown; the crystal subunit 111 is not shown. The structure of the crystal subunit 111 is as follows: Figure 1B As shown, Figure 3A Medium crystal subunit 111 and Figure 1B They have the same location, that is, they are set between XOIN and XOOUT.

[0025] The crystal subunit 111 includes a passive crystal Xtal, a first capacitor C1, and a second capacitor C2. The matching subunit 112 includes a first feedback resistor RF, a bias current transistor P1, and a first inverter N1. The oscillator unit 11 mainly includes a first inverter N1, a first feedback resistor RF, a passive crystal Xtal, a first capacitor C1, and a second capacitor C2, and is capable of generating a sinusoidal signal of a fixed frequency. The first feedback resistor RF provides a DC bias point for the first inverter N1, thereby enabling the first inverter N1 to operate in the linear amplification region under small signal conditions, achieving amplification of weak signals and generating a sinusoidal signal of a fixed frequency. The XOIN and XOOUT ports are used to connect to the crystal subunit 111. The first capacitor C1 and the second capacitor C2 are selected with appropriate capacitance values ​​according to the crystal datasheet requirements. P1, as a bias current transistor, helps to achieve a stable current injection from the drive voltage of the oscillator unit 11 to the XOOUT port, thereby generating reliable sinusoidal oscillations under PVT conditions.

[0026] The self-biasing unit 12 is used to convert the sinusoidal signal into a first square wave signal; the self-biasing unit 12 includes a DC blocking capacitor C0, a second feedback resistor RF0, and a second inverter. Figure 3AAs shown, the second inverter is a complementary metal-oxide-semiconductor (CMOS) inverter, comprising a PMOS field-effect transistor P2 and an N-type metal-oxide-semiconductor (NMOS) field-effect transistor N2. A second feedback resistor RF0 is connected to the common gate and common drain terminals of P2 and N2 to fix the gate and drain voltages of P2 and N2, achieving voltage bias. A DC blocking capacitor C0 blocks DC from the sinusoidal signal generated by the oscillator unit 11. The self-biasing unit 12 stabilizes the DC operating point, fixing the operating point of the sinusoidal signal generated by the preceding oscillator unit 11 at the operating point of the self-biasing unit 12, thereby generating a first square wave signal with a duty cycle close to 50% under process voltage temperature (PVT) fluctuations.

[0027] The output buffer module 20 is used to enhance the driving capability of the first periodic signal and output the first periodic signal as a second square wave signal. The output buffer module 20 includes multiple stages of inverters, and the first driving voltage of the output buffer module 20 is Vdd1. The output buffer module 20 mainly includes multiple stages of CMOS inverters. The larger the width-to-length ratio of the inverter transistors, the stronger the driving capability, but the current and area will also be larger, so a trade-off needs to be made.

[0028] like Figure 3A As shown, the driving voltage of both the oscillator unit 11 and the self-biasing unit 12 is the second driving voltage Vdd2, which is greater than the first driving voltage Vdd1. Meanwhile, to ensure that the voltages connected to the signal generation module 10 and the output buffer module 20 are compatible, the output buffer module 20 further includes a level conversion unit (High to Low, H2L) 21 for converting high levels to low levels.

[0029] like Figure 1B As shown, the existing oscillator unit 13, the existing self-biasing unit 14, and the existing output buffer module 25 of the traditional crystal oscillator circuit are all powered by a single driving voltage Vdd1. Because the bias current transistor P1 consumes a certain voltage margin, the amplitude of the XOOUT output signal is reduced. Normally, the sine signal V... XOOUT < The technical solution described in Embodiment 1 of this application sets the driving voltage of the oscillator unit 11 and the self-biasing unit 12 to the second driving voltage Vdd2, so that the amplitude of the first period signal is greater than or equal to... For example, with the first driving voltage Vdd1 at 1V, setting the second driving voltage Vdd2 to 1.5V provided by a low dropout regulator (LDO) achieves the effect of increasing the amplitude of the sine wave signal and the first square wave signal, where the amplitude of the first square wave signal is 1.5V and the amplitude of the sine wave signal Vdd2 is 1.5V. XOOUT The amplitude of the first square wave signal is slightly lower than that of the first square wave signal. The level conversion unit 21 (H2L) converts the first square wave signal with an amplitude of Vdd2 into a square wave signal with an amplitude of Vdd1 to meet the requirements of the output buffer module 20. It should be noted that the first square wave signal is not a square wave signal in the strict sense and requires further processing to make its rising and falling edges steeper.

[0030] Optionally, the relationship between the first driving voltage Vdd1 and the second driving voltage Vdd2 can be set as follows: When the value of Vdd2 is slightly greater than Vdd1, it may be due to the larger loss of the bias current transistor P1, causing the sinusoidal signal V... XOOUT The increase is not significant, and the improvement in phase noise of the crystal oscillator circuit is not substantial. When the value of Vdd2 is much greater than Vdd1, the level conversion unit 21 will generate significant energy loss, reducing the overall efficiency of the circuit.

[0031] Figure 3B for Figure 3A The simulation results of the low phase noise crystal oscillator circuit are shown in the figure. Figure 3B The edge phase noise of the square wave clock signal CKO at offset frequencies near the oscillation frequency is shown. The edge phase noise at 10kHz, 100kHz, 1MHz and 10MHz are -149.6dBc / Hz, -156.6dBc / Hz, -158.4dBc / Hz and -158.5dBc / Hz, respectively. Figure 3C for Figure 1B The diagram shows the simulation results of a crystal oscillator circuit in the prior art, where Vdd1 is 1V. (See diagram for example.) Figure 3C As shown, the edge phase noise at 10kHz, 100kHz, 1MHz, and 10MHz are -141.3dBc / Hz, -143.5dBc / Hz, -144.0dBc / Hz, and -144.5dBc / Hz, respectively. Compared to... Figure 3C The prior art shown in Example 1 demonstrates superior phase noise performance, as illustrated in the experimental results.

[0032] This embodiment designs a low-phase-noise crystal oscillator circuit, which increases the amplitude of the sinusoidal signal output by the oscillator unit. The higher amplitude sinusoidal signal has a steeper slope when passing through the inverter flip-point such as the self-bias unit, and thus the edge is also steeper when it is flipped into a square wave signal, which can significantly improve the phase noise. It solves the technical problem that the phase noise of the crystal oscillator circuit is too large to meet the requirements in application scenarios that are sensitive to phase noise, and achieves the technical effect of effectively reducing phase noise.

[0033] Example 2 Figure 4A This is a schematic diagram of the low-phase-noise crystal oscillator circuit described in Embodiment 2 of this application. Figure 4A As shown, the signal generation module 10 described in Embodiment 2 includes an oscillator unit 11 and a self-biasing unit 12. The oscillator unit 11 is used to generate a sinusoidal signal, and the oscillator unit 11 includes a crystal subunit 111 and a matching subunit 112. For the sake of simplicity in the illustration, Figure 4A Only the matching subunit 112 is shown; the crystal subunit 111 is not shown. The structure of the crystal subunit 111 is as follows: Figure 1B As shown, Figure 4A Medium crystal subunit 111 and Figure 1B They have the same location, that is, they are set between XOIN and XOOUT.

[0034] The crystal subunit 111 includes a passive crystal Xtal, a first capacitor C1, and a second capacitor C2. The matching subunit 112 includes a first feedback resistor RF, a bias current transistor group 113, a switch group 114, and a first inverter N1. The oscillator unit 11 mainly includes a first inverter N1, a first feedback resistor RF, a passive crystal Xtal, a first capacitor C1, and a second capacitor C2, and is capable of generating a sinusoidal signal of a fixed frequency. The first feedback resistor RF provides a DC bias point for the first inverter N1, thereby enabling the first inverter N1 to operate in the linear amplification region under small signal conditions, achieving amplification of weak signals and generating a sinusoidal signal of a fixed frequency. The XOIN and XOOUT ports are used to connect to the crystal subunit 111. The first capacitor C1 and the second capacitor C2 are selected with appropriate capacitance values ​​according to the crystal datasheet requirements. The bias current transistor group 113 and the switch group 114 help to achieve a stable current injection from the drive voltage of the oscillator unit 11 to the XOOUT port, thereby generating reliable sinusoidal oscillations under PVT. The self-biasing unit 12 is used to convert a sine wave signal into a first square wave signal; the self-biasing unit 12 includes a DC blocking capacitor C0, a second feedback resistor RF0, and a second inverter.

[0035] like Figure 4AAs shown, the number of switches in the switch group 114 is equal to the number of bias current transistors in the bias current transistor group 113. The switches are connected in series between the bias current transistors and the bias voltage Vdd1. That is, each switch controls its corresponding bias current transistor, selectively connecting the bias voltage, thereby changing the current magnitude and voltage amplitude at the XOOUT port.

[0036] Optionally, the number of switches in the switch group 114 and the number of bias current transistors in the bias current transistor group 113 are both 3. For example... Figure 4A As shown, by setting three switches and three bias current transistors, the bias current is configured with three levels: switch 1 closed, switch 2 closed, and switch 3 closed. This enables adjustable current at the XOOUT port. Increasing the current can improve the amplitude of the sinusoidal signal output at XOOUT, thereby improving phase noise. To facilitate voltage supply, the bias voltage of both the oscillator unit 11 and the self-biasing unit 12 is the first driving voltage Vdd1, i.e., they use the same voltage source. Figure 4B for Figure 4A The simulation results of the low phase noise crystal oscillator circuit are shown in the figure. Figure 4B The edge phase noise of the square wave clock signal CKO at offset frequencies near the oscillation frequency is shown. The edge phase noise at 10kHz, 100kHz, 1MHz, and 10MHz are -144.1dBc / Hz, -147.3dBc / Hz, -148.0dBc / Hz, and -149.4dBc / Hz, respectively. With Vdd1 at 1V, Figure 1B In the prior art shown, the voltage at the XOOUT port of the crystal oscillator circuit is 760mV. With all three switches closed... Figure 4A As shown in this embodiment, the voltage at the XOOUT port is 948mV, which means that the amplitude of the sinusoidal signal output at XOOUT is significantly improved, and the edge phase noise of the square wave clock signal CKO at the offset frequency near the oscillation frequency is significantly improved.

[0037] This embodiment designs a low-phase-noise crystal oscillator circuit. By setting up a bias current transistor group and a switching group, the magnitude of the bias current and the amplitude of the sinusoidal signal output by the oscillator unit are increased. The higher amplitude sinusoidal signal has a steeper slope when passing through the inverter flip-point such as the self-bias unit. As a result, when it is flipped into a square wave signal, the edge is also steeper, which can significantly improve the phase noise. This solves the technical problem that the phase noise of the crystal oscillator circuit is too large in application scenarios that are sensitive to phase noise, and cannot meet the requirements. It achieves the technical effect of effectively reducing phase noise.

[0038] Optionally, the low-phase-noise crystal oscillator circuit includes a second independent chip, which comprises the matching subunit 112, the self-biasing unit 12, and the output buffer module 20. By setting an integrated circuit, the matching subunit 112, the self-biasing unit 12, and the output buffer module 20 are designed as independent chips and connected to the passive crystal Xtal, the first capacitor C1, and the second capacitor C2 in the oscillator unit 11, thereby reducing the overall size of the low-phase-noise crystal oscillator circuit and improving the convenience of circuit connection.

[0039] Optionally, the passive crystal Xtal, the first capacitor C1, and the second capacitor C2 in the oscillator unit 11 are separated from other components in the low-phase-noise crystal oscillator circuit. Separating the passive crystal Xtal, the first capacitor C1, and the second capacitor C2 improves the flexibility and practicality of the low-phase-noise crystal oscillator circuit, allowing for easy adjustment of the capacitors as needed during use to ensure proper oscillation.

[0040] Example 3 Figure 5A This is a schematic diagram of the low phase noise crystal oscillator circuit described in Embodiment 3 of this application. Figure 5A As shown, the signal generation module 10 described in Embodiment 3 includes an oscillator unit 11. The oscillator unit 11 is used to generate a sinusoidal signal, and the oscillator unit 11 includes a crystal subunit 111 and a matching subunit 112. For the sake of simplicity in the illustration, Figure 5A Only the matching subunit 112 is shown; the crystal subunit 111 is not shown. The structure of the crystal subunit 111 is as follows: Figure 1B As shown, Figure 5A Medium crystal subunit 111 and Figure 1B They have the same location, that is, they are set between XOIN and XOOUT.

[0041] The crystal subunit 111 includes a passive crystal Xtal, a first capacitor C1, and a second capacitor C2. The matching subunit 112 includes a second feedback resistor RF0 and a CMOS inverter. The second feedback resistor RF0 provides a DC bias point for the CMOS inverter, enabling it to operate in the linear amplification region under small-signal conditions, thus amplifying weak signals and generating a fixed-frequency sinusoidal signal. The XOIN and XOOUT ports are used to connect to the crystal subunit 111. The first capacitor C1 and the second capacitor C2 are selected with appropriate capacitance values ​​according to the crystal datasheet. The bias voltage of the oscillator unit 11 is the first driving voltage Vdd1.

[0042] Figure 1BThe existing crystal oscillator circuit shown uses a bias current transistor P1 to achieve reliable sinusoidal oscillation under PVT. However, using a PMOS field-effect transistor as the bias current transistor will consume a certain voltage margin, causing the amplitude of the sinusoidal oscillation at the XOOUT port to be unable to reach the vicinity of the first driving voltage Vdd1, resulting in a small amplitude and adversely affecting the phase noise. Figure 5A The inverter in the oscillator unit 11 of Embodiment 3 includes a PMOS field-effect transistor and an NMOS field-effect transistor, and is directly connected to the bias voltage Vdd1. The oscillator unit 11 is then directly cascaded with the output buffer module 20. This is because the oscillator unit 11 and the output buffer module 20 have symmetrical structures and the same DC point, so there is no need to set up a self-biasing unit 12 to bias the potential. The technical solution of Embodiment 3 simplifies the circuit structure on the one hand, and avoids the bias current transistor consuming voltage margin on the other hand, increasing the amplitude of the sinusoidal oscillation at the XOOUT port and improving phase noise performance.

[0043] Figure 5B for Figure 5A The simulation results of the low phase noise crystal oscillator circuit are shown in the figure. Figure 5B The edge phase noise of the square wave clock signal CKO at offset frequencies near the oscillation frequency is shown. The edge phase noise at 10kHz, 100kHz, 1MHz, and 10MHz are -142.4dBc / Hz, -144.8dBc / Hz, -145.3dBc / Hz, and -146.0dBc / Hz, respectively. With Vdd1 at 1V, Figure 1B In the prior art shown, the voltage at the XOOUT port of the crystal oscillator circuit is 760mV. Figure 5A As shown in this embodiment, the voltage at the XOOUT port is 902mV, which means that the amplitude of the sinusoidal signal output at XOOUT is significantly improved, and the edge phase noise of the square wave clock signal CKO at the offset frequency near the oscillation frequency is significantly improved.

[0044] This embodiment designs a low-phase-noise crystal oscillator circuit. By omitting the bias current transistor in the oscillator unit and using a PN dual transistor as an inverter, the amplitude of the sinusoidal signal output by the oscillator unit is increased. The higher amplitude sinusoidal signal has a steeper slope when passing through the inverter flip-point such as the output buffer module 20. As a result, when it is flipped into a square wave signal, the edge is also steeper, which can significantly improve the phase noise. This solves the technical problem that the phase noise of the crystal oscillator circuit is too large to meet the requirements in application scenarios that are sensitive to phase noise, and achieves the technical effect of effectively reducing phase noise.

[0045] Optionally, the low-phase-noise crystal oscillator circuit includes a third independent chip, which comprises the matching subunit 112 and the output buffer module 20. By setting an integrated circuit, the matching subunit 112 and the output buffer module 20 are designed as independent chips and connected to the passive crystal Xtal, the first capacitor C1 and the second capacitor C2 in the oscillator unit 11, reducing the overall size of the low-phase-noise crystal oscillator circuit and improving the convenience of circuit connection.

[0046] Optionally, the range of values ​​for the first driving voltage Vdd1 in the technical solutions described in the various embodiments of this application can be: The low-phase-noise crystal oscillator circuit described in this application is mainly used in products such as dual-mode Bluetooth, Bluetooth Low Energy, and Wireless Fidelity WiFi. Excessive voltage can lead to increased power consumption, potentially causing problems such as reduced crystal sub-cell lifetime and frequency drift; while If the voltage value is too low, it may lead to problems such as small amplitude and poor stability.

[0047] Example 4 This embodiment discloses a chip, including any of the low phase noise crystal oscillator circuits described in embodiments 1 to 3. The chip integrates the low phase noise crystal oscillator circuits described in embodiments 1 to 3 into a unified chip to realize the function of square wave output.

[0048] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A low-phase-noise crystal oscillator circuit, characterized in that, include: The signal generation module is used to generate the first cycle signal; An output buffer module is used to enhance the driving capability of the first periodic signal and output the first periodic signal as a second square wave signal; the output buffer module includes a multi-stage inverter, and the first driving voltage of the output buffer module is Vdd1; The first periodic signal includes a sine wave signal or a first square wave signal, and the amplitude of the first periodic signal is greater than or equal to... .

2. The low phase noise crystal oscillator circuit according to claim 1, characterized in that, The signal generation module includes: An oscillator unit for generating a sinusoidal signal includes a crystal subunit and a matching subunit. The crystal subunit includes a passive crystal, a first capacitor, and a second capacitor. The matching subunit includes a first feedback resistor, a bias current transistor, and a first inverter. A self-biasing unit is used to convert the sinusoidal signal into a first square wave signal; the self-biasing unit includes a DC blocking capacitor, a second feedback resistor, and a second inverter; The output buffer module also includes a level conversion unit for converting a high level to a low level; The driving voltage of both the oscillator unit and the self-biasing unit is the second driving voltage Vdd2, which is greater than the first driving voltage Vdd1.

3. The low phase noise crystal oscillator circuit according to claim 1, characterized in that, The signal generation module includes: An oscillator unit for generating a sinusoidal signal includes a crystal subunit and a matching subunit. The crystal subunit includes a passive crystal, a first capacitor, and a second capacitor. The matching subunit includes a first feedback resistor, a bias current transistor group, a switching group, and a first inverter. A self-biasing unit is used to convert the sinusoidal signal into a first square wave signal; the self-biasing unit includes a DC blocking capacitor, a second feedback resistor, and a second inverter; The bias voltage of both the oscillator unit and the self-biasing unit is the first driving voltage Vdd1. The number of switches in the switch group is equal to the number of bias current transistors in the bias current transistor group. The switches are connected in series between the bias current transistors and the bias voltage.

4. The low phase noise crystal oscillator circuit according to claim 3, characterized in that, The number of switches in the switch group and the number of bias current transistors in the bias current transistor group are both 3.

5. The low phase noise crystal oscillator circuit according to claim 1, characterized in that, The signal generation module includes: An oscillator unit for generating a sinusoidal signal, the oscillator unit comprising a crystal subunit and a matching subunit, the crystal subunit comprising a passive crystal, a first capacitor and a second capacitor, and the matching subunit comprising a second feedback resistor and a complementary metal-oxide-semiconductor (CMOS) inverter; The bias voltage of the oscillator unit is the first driving voltage Vdd1.

6. The low phase noise crystal oscillator circuit according to any one of claims 2-4, characterized in that, The passive crystal, first capacitor, and second capacitor in the oscillator unit are separated from other components in the low-phase-noise crystal oscillator circuit.

7. The low phase noise crystal oscillator circuit according to claim 2, characterized in that, The second driving voltage is greater than or equal to 1.4 times the first driving voltage and less than or equal to 1.6 times the first driving voltage.

8. The low phase noise crystal oscillator circuit according to any one of claims 2-4, characterized in that, Includes a second independent chip, the second independent chip comprising: The matching subunit, the self-biasing unit, and the output buffer module.

9. The low phase noise crystal oscillator circuit according to claim 5, characterized in that, Includes a third independent chip, said third independent chip comprising: The matching subunit and the output buffer module.

10. A chip, characterized in that, Includes a low-phase-noise crystal oscillator circuit as described in any one of claims 1-9.

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