W-band frequency synthesizer and applications thereof

Abstract

The application relates to the field of integrated circuits, in particular to a W-band frequency synthesizer and application thereof. The W-band frequency synthesizer comprises a multi-phase signal generator, an overlap-enhanced frequency multiplier, a current synthesizer and a matching network. The overlap-enhanced frequency multiplier comprises a plurality of frequency multiplication units; each frequency multiplication unit comprises two digital delay lines, two low-pass filters, one analog AND gate and one duty cycle adjuster. The core design idea of the circuit is not to directly construct and lock an oscillator in the W band; instead, a low-jitter, multi-phase, uniformly-interval-phase sinusoidal signal is generated near a frequency lower than the target frequency point, then the multi-phase input is processed through a plurality of frequency multiplication links in the overlap-enhanced frequency multiplier, and finally the multi-way output is subjected to current synthesis, impedance matching and harmonic filtering to obtain an oscillation signal in the W band. The scheme solves the problems of the existing W-band frequency signal generation circuit in terms of phase noise, power consumption and tuning range.

Description

Technical Field

[0001] This invention relates to the field of integrated circuits, and in particular to a W-band frequency synthesizer and its applications. Background Technology

[0002] Communication systems have a wider demand for ultra-high frequency signals; however, with current technology, designing a low-noise, wide-tuning-range, digitally controllable oscillator and phase-locked loop (PLL) feedback link directly in the W-band remains extremely difficult. The W-band corresponds to approximately 75 GHz to 110 GHz, where losses from inductors, transformers, tuning capacitor arrays, and parasitic traces increase significantly. A decrease in the quality factor (Q factor) of passive components directly raises the oscillator's phase noise (PN). If a direct W-band fully digital PLL is used, the feedback divider chain also needs to operate around 100 GHz; multi-stage high-speed dividers lead to a narrower locking range, additional noise accumulation, and increased power consumption. For communication and radar systems requiring multi-frequency coverage, simply increasing the frequency of traditional PLLs often sacrifices phase noise, power consumption, and feasibility.

[0003] Traditional multi-phase frequency multiplication schemes can rely on near-rail-to-rail square wave edges for synthesis in the lower millimeter-wave band. However, in the W-band, the driving capability and edge speed of CMOS transistors are insufficient to support an ideal square wave. If the traditional large-phase-space edge synthesis method is continued, the time window for the two inputs to be truly effective simultaneously is very short, resulting in a reduced pulse swing, insufficient fourth harmonic components, and consequently, deterioration in output power and efficiency. While using cascaded frequency multipliers offers an intuitive implementation path, it introduces more stages of active circuitry, more matching networks, a larger chip area, and more unwanted harmonic components, making it difficult to achieve a compact and efficient 100 GHz output.

[0004] W-band local oscillators (LOs) require high spectral purity, but reference spurs, non-target harmonics, and phase jitter can easily occur simultaneously. In communication systems, LO phase noise can increase the error vector amplitude and disrupt higher-order modulation; in radar systems, LO noise can worsen the detection capability of weak targets near strong reflective targets at close range; residual fundamental, second, and third harmonics in the frequency multiplication link can also enter the transceiver channel through mixing, leakage, or on-chip coupling, causing out-of-band spurs and false spectral lines. Therefore, W-band frequency synthesizers cannot simply aim for "oscillation up to 100 GHz"; a balance must be struck between low jitter, low reference spurs, and high harmonic suppression.

[0005] W-band local oscillators (LOs) for 6G communications, Multiple-Input Multiple-Output (MIMO) radar, and on-chip sensing typically need to be integrated within a small chip area and may need to serve multiple transceiver channels simultaneously. If the LO source area is large, has high power consumption, or insufficient output power, the system-level implementation will be forced to add external frequency multipliers, amplifiers, or complex LO distribution networks, leading to increased cost, packaging complexity, and channel consistency issues. Especially in phased array, automotive radar, and UAV radar, the LO link is not just a single circuit module, but a system bottleneck affecting array size, heat dissipation, synchronization, mass production consistency, and terminal battery life. Summary of the Invention

[0006] To address the shortcomings of existing W-band frequency signal generation circuits in terms of phase noise, power consumption, and tuning range, this invention provides a W-band frequency synthesizer and its applications.

[0007] The technical solution provided by this invention is as follows: A W-band frequency synthesizer includes: a multi-phase signal generator, an overlapping enhancement-type frequency multiplier, a current synthesizer, and a matching network. The multi-phase signal generator generates 2M sinusoidal signals with phases successively differing by 360° / 2M (M>1) and frequencies all 1 / M of the target frequency. The overlapping enhancement-type frequency multiplier includes M frequency multiplication units; each multiplication unit includes two digitally controlled delay lines, two low-pass filters, one analog AND gate, and one duty cycle adjuster. The sinusoidal signals from every two adjacent phases output by the multi-phase signal generator are input to one of the frequency multiplication units. Each sinusoidal signal undergoes phase compensation and low-pass filtering processing within the frequency multiplication unit via a digitally controlled delay line and a low-pass filter, before being input to the two inputs of the analog AND gate. The synthesized signal output from the analog AND gate is input to the duty cycle adjuster for pulse width adjustment, resulting in a narrow pulse signal. The current synthesizer is used to synthesize multiple narrow pulse signals with phase differences of 360° / M from the output of each frequency multiplier unit to obtain a fused signal I with the target frequency. comb The matching network is used to perform impedance matching and harmonic filtering on the fused signal, thereby generating the desired W-band oscillation signal.

[0008] As a further improvement of this invention, the numerically controlled delay line includes six inverters INV1~INV6 and a numerically controlled capacitor array. INV1~INV6 are cascaded sequentially to form an inverter chain; the input terminal of INV1 serves as the input terminal of the numerically controlled delay line, and the output terminal of INV6 serves as the output terminal of the numerically controlled delay line. The component size ratio from INV1 to INV3 is 1:2:4; the component size ratio from INV4 to INV6 is also 1:2:4.

[0009] The numerically controlled capacitor array comprises multiple capacitor cells arranged in a proportional ratio of 2 and transmission gates. One end of each capacitor cell is grounded, and the other end is electrically connected to the output of INV3 through an independent transmission gate. The conduction state of each transmission gate is controlled by the code values ​​of each bit of the numerically controlled signal CTRL, thereby adjusting the total capacitance value of the capacitor cells connected to the inverter chain; thus changing the delay length between the input and output signals on the inverter chain.

[0010] As a further improvement of the present invention, the code values ​​of the numerical control signals of the two numerical control delay lines in each frequency multiplier unit are optimized and adjusted so that the two input signals input to the analog AND gate satisfy the preset phase relationship.

[0011] As a further improvement of the present invention, the low-pass filter includes an inverter INV7, a resistor R1, and three capacitors C1 to C3. One end of C1 serves as the input terminal of the low-pass filter, and the other end of C1 is electrically connected to one end of R1 and the input terminal of INV7. The output terminal of INV7 is electrically connected to the other end of R1 and one end of C2; the other end of C2 is connected to one end of C3 and serves as the output terminal of the low-pass filter; the other end of C3 is grounded.

[0012] As a further improvement of this invention, the analog AND gate includes two resistors R1 and R2, three PMOS transistors P1~P3, and three NMOS transistors N1~N3. The circuit connection is as follows: the sources of P1~P3 are connected to VDD; one end of R1 is connected to the gates of P2 and N1 and serves as one of the input terminals IN of the analog AND gate. A One end of R2 is connected to the gates of P1 and N2 and serves as the other input IN of the analog AND gate. B The other input terminal of R1 and R2 is connected to the bias voltage V. B The drains of P1, P2, and N1 are connected to the gates of P3 and N3; the source of N1 is connected to the drain of N2; the sources of N2 and N3 are connected to VSS; the drains of P3 and N3 are connected and used as the output terminal OUT of the analog AND gate. As a further improvement of the present invention, the duty cycle regulator is an inverter composed of a PMOS transistor P4 and an NMOS transistor N4 with a size ratio of N:1 (N>1); the source of P4 is connected to VDD; the source of N4 is connected to VSS; the gates of P4 and N4 are connected and serve as the input terminal of the duty cycle regulator; the drains of P4 and N4 are connected and serve as the output terminal of the duty cycle regulator.

[0013] As a further improvement of the present invention, the size ratio of the PMOS transistor and the NMOS transistor in the duty cycle regulator is used as the first control parameter; the voltage value of the bias voltage connected to the analog AND gate is used as the second control parameter. The first control parameter and the second control parameter are adjusted together so that the pulse width of the narrow pulse signal output by the arbitrary frequency multiplier unit meets the preset value.

[0014] As a further improvement of the present invention, the current synthesizer includes M+1 NMOS transistors. The M narrow pulse signals output by each frequency multiplier unit, with a phase difference of 360° / M, are respectively connected to the gates of the 1st to Mth NMOS transistors; the sources of the 1st to Mth NMOS transistors are connected to VSS; the drains of the 1st to Mth NMOS transistors are connected to the source of the (M+1)th NMOS transistor; the gate of the (M+1)th NMOS transistor is connected to VDD, and the drain of the (M+1)th NMOS transistor serves as I... comb The output port.

[0015] As a further improvement of the present invention, the current synthesizer includes five NMOS transistors N51~N54 and N6; the circuit connection is as follows: the four narrow pulse signals output by the four frequency multiplier units, with a phase difference of 90°, are respectively connected to the gates of N51~N54; the sources of N51~N54 are connected to VSS; the drains of N51~N54 are vectored to the source of N6; the gate of N6 is connected to VDD; the drain of N6 serves as I... comb The output port.

[0016] As a further improvement of the present invention, the matching network includes four inductors L4~L7 and four capacitors C4~C7; one end of L4 and C4 is electrically connected to the output terminal of the current synthesizer; the other end of L4 and C4 is connected to VDD; L4 and L5 constitute a first mutual inductance circuit. One end of L5, C5, C6, and L6 is electrically connected; the other end of L5, C5, C6, and L6 is electrically connected; L6 and L7 constitute a second mutual inductance circuit. One end of L7 and C7 is connected and serves as the output terminal Vout of the matching network; the other end of L7 and C7 is connected to VSS.

[0017] By optimizing the capacitance values ​​of each capacitor and the inductance values ​​of each inductor in the matching network, as well as the coupling rates K1 and K2 of the two mutual inductance circuits, the input impedance and output impedance can be matched.

[0018] As a further improvement of the present invention, the matching network also includes a second harmonic notch filter composed of inductors L8 and L9 and capacitors C8 and C9. The circuit connection relationship of the second harmonic notch filter is as follows: one end of L8 is electrically connected to one end of C8; the other end of L8 is electrically connected to one end of C5, and the other end of C8 is grounded; one end of L9 is electrically connected to one end of C9; the other end of L9 is electrically connected to the other end of C5, and the other end of C9 is grounded.

[0019] By optimizing the capacitance values ​​of each capacitor and the inductance values ​​of each inductor in the second harmonic notch filter, the harmonic interference of the output signal can be made to meet the preset value.

[0020] As a further improvement of the present invention, the sinusoidal signals generated by the multi-phase signal generator are transmitted to the superimposed enhancement multiplier through differential transmission lines with overlapping wiring on the layout, thereby making the load capacitance of each phase output terminal consistent.

[0021] As a further improvement of the present invention, the multi-phase signal generator includes a multi-output ring traveling wave oscillator and a charge-rudder fully digital phase-locked loop; the charge-rudder fully digital phase-locked loop is used to acquire the output signal of the reference node in the ring traveling wave oscillator, and generate control signals for adjusting the access state of each capacitor array in the ring traveling wave oscillator according to the frequency and phase of the output signal of the reference node, thereby locking the output signal of each phase node of the ring traveling wave oscillator at a preset frequency.

[0022] As a further improvement of the present invention, the multi-phase signal generator is used to generate eight sinusoidal signals with phases successively differing by 45° and frequencies all of 1 / 4 of the target frequency.

[0023] The multi-output ring traveling wave oscillator consists of two cascaded ring traveling wave oscillators. The ring traveling wave oscillator contains eight transconductance elements Gm and provides 16 phase nodes with a phase difference of 22.5°.

[0024] Select at least two phase nodes from the preceding ring traveling wave oscillator as cascade ports and connect them to two phase nodes of the following ring traveling wave oscillator via capacitors; thereby causing the corresponding phase node in the following ring traveling wave oscillator to be delayed by 22.5° compared to the following ring traveling wave oscillator.

[0025] The 0°, 90°, 180°, and 270° phase nodes in the pre-stage ring traveling wave oscillator are used as output nodes for outputting sinusoidal signals with phases of 0°, 90°, 180°, and 270°; the 22.5°, 122.5°, 202.5°, and 292.5° phase nodes in the post-stage ring traveling wave oscillator are used as output nodes for outputting sinusoidal signals with phases of 45°, 135°, 225°, and 315°.

[0026] By cascading two ring traveling wave oscillators, the signal transmission paths between the eight output nodes and the overlapped enhancement multiplier are symmetrical and of the same length in the spatial portion of the layout. This ensures that the eight sinusoidal signals with the same phase difference output by the ring traveling wave oscillators maintain a constant phase difference when input to the overlapped enhancement multiplier.

[0027] The present invention also includes the application of the aforementioned W-band frequency synthesizer in W-band sensing systems, MIMO radars, measurement platforms, 6G millimeter-wave and Asia-Pacific Hertz communication transceivers, in which the W-band frequency synthesizer is used to provide an oscillation signal at a specified frequency point within the W-band.

[0028] The present invention has the following beneficial effects: 1. This invention, through a system architecture of "approximately 25 GHz lock-in + quadruple frequency output," avoids the high-risk path of directly constructing and locking a W-band digitally controlled oscillator. The Rotary Traveling-Wave Oscillator (RTWO) operates at approximately one-quarter of the final output frequency. The losses of passive components in the oscillation loop, the equivalent series resistance of the tuning capacitor array, and the speed pressure of the feedback divider link are all lower than in a direct 100 GHz solution. The charge-controlled all-digital phase-locked loop only needs to be closed around the lower-frequency RTWO, eliminating the need for a long-link W-band high-speed divider at the feedback end. This reduces problems such as divider noise accumulation, limited lock-in range, and increased power consumption of high-frequency active circuits. Although the final output is in the W-band, the core phase comparison and frequency control actions of the phase-locked loop occur in a more easily implemented frequency band. This approach also allows frequency tuning, digital control, and loop stability design to leverage mature millimeter-wave circuit experience, reducing the amplifying effect of layout parasitics and device model errors on closed-loop behavior. In other words, this solution breaks down the challenge into two separately optimizable stages: "low-noise multi-phase generation" and "high-efficiency fourth harmonic synthesis," enabling a more robust trade-off between phase noise, tuning range, power consumption, and circuit complexity in frequency synthesis around 100 GHz.

[0029] 2. The overlapping enhancement multi-frequency multiplier in this invention employs an overlapping enhancement pulse synthesis method with adjacent 45-degree phase overlaps, improving the effective pulse swing of the W-band fourth harmonic link. Traditional 135-degree interval edge synthesis relies on the rapid flipping of a near-ideal square wave, which is limited by transistor swing and slew rate in the W-band, resulting in narrower pulses or even difficulty in forming them. This invention first uses RTWO to provide an eight-phase sinusoidal signal, and then allows adjacent 45-degree signals to enter an analog AND gate, allowing the two inputs to simultaneously meet the conduction conditions for a longer period, thus increasing the pulse amplitude from the source. Subsequently, a low-pass filter weakens the edge distortion caused by higher-order harmonics, and a duty cycle adjuster compresses the wider pulse output of the analog AND gate into a narrower pulse more suitable for fourth harmonics, enhancing the target fourth harmonic component. Since the fourth harmonic output is not boosted step by step by multiple second harmonic multipliers, but is obtained by direct current synthesis of four shaped pulses, inter-stage losses, inter-stage matching, and additional bias current are all reduced, and the output is easier to design for matching around the target frequency. The four narrow pulses are current-synthesized to output a W-band signal, which is further suppressed by a matching network and a second harmonic notch filter. This approach avoids the area and power consumption overhead of cascaded frequency multipliers and is more suitable for the real CMOS conditions with limited driving capability of the W-band than ordinary multi-phase synthesis.

[0030] 3. The technical solution of this invention can simultaneously improve phase noise, reference spurious signals, and harmonic suppression, rather than optimizing only one of these indicators. Specifically, the eight-phase uniform signal generated by RTWO achieves a more consistent load environment through overlapping transmission line routing, reducing path differences between phases before entering the analog AND gate; the numerically controlled delay line provides fine timing adjustments to compensate for phase path deviations caused by actual manufacturing and layout; the low-pass filter allows the analog AND gate to process sinusoidal signals closer to the fundamental frequency, reducing the impact of higher-order harmonics on the threshold conduction time; and the duty cycle adjuster enhances the fourth harmonic from a duty cycle perspective while suppressing unwanted frequency components. Because these measures act on phase path consistency, input waveform purity, pulse width, and output frequency selection respectively, non-target harmonics are not passively attenuated at a single stage, but are continuously suppressed in the generation, shaping, and output stages.

[0031] 4. The technical solution of this invention achieves a good system trade-off between on-chip integration, output power, and energy efficiency. For system design, this means that the entire link from low-frequency multi-phase oscillation, phase-locked loop control, fourth harmonic synthesis, harmonic suppression to W-band output can be completed within a single chip, without relying on a larger and more power-consuming external frequency multiplication link. Since the output already includes a matching network and a second harmonic notch filter, the subsequent transceiver channels face a more concentrated local oscillator signal. The system does not need to add a large number of off-chip filters or buffer stages to compensate for the local oscillator quality, and it also reduces the additional losses and uncertainties caused by packaging traces. Attached Figure Description

[0032] Figure 1 This is a circuit diagram of the W-band frequency synthesizer provided in Embodiment 1 of the present invention.

[0033] Figure 2 This is a circuit diagram of the frequency multiplier unit in the W-band frequency synthesizer of Embodiment 1 of the present invention.

[0034] Figure 3 This is a circuit diagram of the numerically controlled delay line and low-pass filter used in Embodiment 1 of the present invention.

[0035] Figure 4 This is a circuit diagram of the analog AND gate used in Embodiment 1 of the present invention.

[0036] Figure 5 This is a circuit diagram of the duty cycle regulator used in Embodiment 1 of the present invention.

[0037] Figure 6 This is a circuit diagram of the current synthesizer used in Embodiment 1 of the present invention.

[0038] Figure 7 This is a circuit diagram of the matching network used in Embodiment 1 of the present invention.

[0039] Figure 8 This is a circuit diagram of the matching network with a second harmonic notch filter used in Embodiment 1 of the present invention.

[0040] Figure 9 This is a schematic diagram of the multi-phase signal generator composed of cascaded ring traveling wave oscillators used in Embodiment 1 of the present invention.

[0041] Figure 10 The circuit diagram is for the W-band frequency synthesizer used in the test experiment.

[0042] Figure 11 The test results are to measure the phase noise curve and integral root mean square jitter of the chip at 100 GHz output in the test experiment.

[0043] Figure 12 This is the reference spurious test result of the chip at 100 GHz output in the test experiment.

[0044] Figure 13 The results show the harmonic suppression performance of the chip under a 101.7 GHz output condition during the test experiment.

[0045] Figure 14 The test results were used to evaluate the chip's jitter, reference spurious emissions, and HRR in the range of 92.7 GHz to 101.7 GHz during the test experiment.

[0046] Figure 15 This is to obtain microscopic images of the chip and power consumption statistics for each part during the test experiment.

[0047] Figure 16 The test results are for the chip's output power and efficiency in the range of 92.7 GHz to 101.7 GHz during the test experiment. Detailed Implementation

[0048] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0049] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein in the specification of this invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "or / and" as used herein includes any and all combinations of one or more of the associated listed items.

[0050] Example 1 This embodiment provides a W-band frequency synthesizer designed for local oscillator outputs from approximately 92.7 GHz to 101.7 GHz. For example... Figure 1 As shown, the W-band frequency synthesizer includes a multi-phase signal generator, an overlapped enhancement multi-frequency multiplier, a current synthesizer, and a matching network. The core design concept of this circuit is not to directly construct and lock an oscillator in the W-band; instead, it generates a low-jitter, multi-phase, uniformly phase-spaced sinusoidal signal near a frequency lower than the target frequency, and then processes it through a multi-frequency multiplier link to obtain the W-band output. Therefore, the most sensitive and difficult-to-implement oscillation and phase-locked loop feedback operations can be performed at a lower frequency, while the high-frequency output is handled by a specially optimized frequency multiplier and synthesizer network.

[0051] In this embodiment, the multi-phase signal generator is used to generate 2M sinusoidal signals with phases successively differing by 360° / 2M (M>1) and frequencies all 1 / M of the target frequency. In practical applications, the multi-phase signal generator can be constructed using a charge-controlled fully digital phase-locked loop and a ring traveling-wave oscillator to achieve multi-phase signal output at a specified frequency within the low-frequency band. Of course, the multi-phase signal generator can also employ various oscillation circuits capable of achieving fixed multi-phase output.

[0052] The overlap-enhanced multiplier is used to generate M narrow pulse signals with a phase difference of 360° / M based on 2M sinusoidal signals with a phase difference of 360° / 2M and a frequency of 1 / M of the target frequency. In this embodiment, as... Figure 2 As shown, the overlapped enhancement multiplier includes M multiplier units; the multiphase signal generator generates two adjacent sinusoidal signals that form a group, and all 2M sinusoidal signals are divided into M groups, which are then input into the M multiplier units. Each multiplier unit is used to adjust the amplitude, phase step, and duty cycle of the two input sinusoidal signals with a phase difference of 360° / 2M, thereby obtaining a narrow pulse signal.

[0053] Specifically, in the overlapped enhancement multiplier designed in this embodiment, each multiplier unit includes two digitally controlled delay lines (DCDL), two low-pass filters (LPF), one analog AND gate (AAG), and one duty-cycle adjuster (DCA). The two adjacent sinusoidal signals output from the multi-phase signal generator to each multiplier unit should maintain a constant phase difference of 360° / 2MHz. However, due to differences in trace length, parasitic capacitance, and input load between different phase paths, the phase of the two sinusoidal signals may shift when they enter the multiplier unit. To address this issue, this embodiment first performs subtle timing adjustments on the two sinusoidal signals using two digitally controlled delay lines; then, it achieves differentiated phase compensation, restoring them to their initial phase and maintaining a constant phase difference of 360° / 2MHz. The outputs of the two numerically controlled delay lines are connected to two low-pass filters, respectively. The low-pass filters are used to retain the fundamental frequency component, which is approximately 1 / M of the target frequency, and to reduce edge distortion caused by higher-order harmonics. The two signals, after being processed by the low-pass filters, are then input into an analog AND gate.

[0054] In the frequency multiplier unit of this embodiment, the analog AND gate processes a biased analog sine wave, rather than an ideal digital square wave. This generates a response pulse when both inputs are simultaneously within their effective level range. Since the two input signals of the analog AND gate differ by only 360° / 2M degrees, and the effective time interval is longer than that of traditional large-interval combinations, a pulse with sufficient swing amplitude can still be formed even with the limited driving capability of W-band transistors. The pulse output of the analog AND gate has a wide duty cycle. To make the target harmonic stronger after frequency multiplication, this embodiment inputs the synthesized signal from the analog AND gate output to a duty cycle regulator for pulse width adjustment. In practical applications, the duty cycle regulator can use an inverter composed of a larger PMOS and a smaller NMOS. This asymmetrical inverter can compress a wider pulse into a narrower pulse signal with a stronger fourth harmonic component.

[0055] The current synthesizer is used to synthesize the M narrow pulse signals with phase differences of 360° / M from the output of the overlapped enhancement multiplier, thereby obtaining a fused signal I whose frequency is multiplied to the target frequency. comb Following this, a matching network is used to fuse the signal I. combImpedance matching and harmonic filtering are performed to generate the desired high-quality oscillation signal in the W-band. The circuit provided in this embodiment can sequentially achieve "low-frequency locking and multi-phase generation, adjacent phase overlapping pulses, duty cycle adjustment, current synthesis, and harmonic notch filtering," thereby solving the problem of simultaneously optimizing phase noise, reference spurious signals, output power, harmonic suppression, and power consumption area in W-band frequency synthesis through such a complete path.

[0056] To make the circuit principle and performance advantages of the novel W-band frequency synthesizer architecture provided in this embodiment clearer, the following example uses a W-band frequency synthesizer with a target frequency of 100GHz, consisting of a multi-phase signal generator capable of outputting eight 25GHz multi-phase sinusoidal signals with sequentially 45° phase intervals, an overlapping enhancement multi-frequency multiplier composed of four frequency multiplier units, a buffer-structured current synthesizer, and a matching network of a second harmonic notch filter. Each circuit part will be described in detail below: First, such as Figure 3 As shown, in this embodiment, the digitally controlled delay line (DCDL) includes six inverters INV1~INV6 and a digitally controlled capacitor array. INV1~INV6 are cascaded to form an inverter chain; the input terminal of INV1 serves as the input terminal of the digitally controlled delay line, and the output terminal of INV6 serves as the output terminal of the digitally controlled delay line. The component size ratio from INV1 to INV3 is 1:2:4; the component size ratio from INV4 to INV6 is also 1:2:4. The digitally controlled capacitor array includes multiple capacitor units with capacitance values ​​arranged in an equal ratio of 2 and transmission gates. One end of each capacitor unit is grounded, and the other end is electrically connected to the output terminal of INV3 through an independent transmission gate. The conduction state of each transmission gate is controlled by the code value of each bit of the digitally controlled signal CTRL to adjust the total capacitance value of the capacitor units connected to the inverter chain; thereby changing the delay length between the input and output signals on the inverter chain.

[0057] Specifically, in Figure 3 In the typical scheme of this embodiment, the number of capacitor units in the numerically controlled capacitor array is 5; the ratio of the capacitance values ​​is 16:8:4:2:1; the transmission gates connected to each capacitor unit are switched on and off using a 5-bit binary code CTRL<4:0>; thus, the delay of the input sine signal can be adjusted in steps as low as 5 fs in the numerically controlled delay line. This embodiment optimizes the code value of the numerically controlled signal CTRL in the two numerically controlled delay lines of each frequency multiplier unit, ultimately ensuring that the two input signals of the analog AND gate transmitted to the back end satisfy a preset phase relationship.

[0058] After the CNC delay line, such as Figure 3As shown, the low-pass filter (LPF) used in this embodiment consists of one inverter INV7, one resistor R1, and three capacitors C1-C3. One end of C1 serves as the input terminal of the low-pass filter, and the other end of C1 is electrically connected to one end of R1 and the input terminal of INV7. The output terminal of INV7 is electrically connected to the other end of R1 and one end of C2; the other end of C2 is connected to one end of C3 and serves as the output terminal of the low-pass filter; the other end of C3 is grounded. In this embodiment, the specifications of the components in the low-pass filter can be optimized and adjusted according to the frequency range of the signal to be filtered. Furthermore, Figure 3 The circuit shown is only a typical circuit of the low-pass filter provided in this embodiment. In other embodiments, it can be replaced with other low-pass filters with the same filtering function.

[0059] like Figure 4 As shown, the analog AND gate AAG used in this embodiment includes two resistors R1 and R2, three PMOS transistors P1~P3, and three NMOS transistors N1~N3. The circuit connection is as follows: the source terminals of P1~P3 are connected to VDD; one end of R1 is connected to the gates of P2 and N1 and serves as one of the input terminals IN of the analog AND gate. A One end of R2 is connected to the gates of P1 and N2 and serves as the other input IN of the analog AND gate. B The other input terminal of R1 and R2 is connected to the bias voltage V. B The drains of P1, P2, and N1 are connected to the gates of P3 and N3; the source of N1 is connected to the drain of N2; the sources of N2 and N3 are connected to VSS; the drains of P3 and N3 are connected and serve as the output terminal OUT of an analog AND gate. Figure 4 In the analog AND gate shown, R1 and R2 are large resistors on the order of kΩ used to provide bias; in this embodiment, 8kΩ resistors can be used. Bias voltage V B This constitutes the key parameter that ultimately affects the output signal, V. B The voltage value can be flexibly adjusted as needed during circuit application. In this embodiment, for the four frequency multiplier units in the overlapping enhancement type frequency multiplier, the V of each analog AND gate is... B The values ​​can be adjusted synchronously to ensure that the pulse width of the narrow pulse signal output by each frequency multiplier unit and the intensity of the fourth harmonic classification remain consistent.

[0060] like Figure 5As shown, the duty cycle regulator in this embodiment uses an inverter composed of a PMOS transistor P4 and an NMOS transistor N4 with a size ratio of N:1 (N>1). The source of P4 is connected to VDD; the source of N4 is connected to VSS; the gates of P4 and N4 are connected and serve as the input of the duty cycle regulator; the drains of P4 and N4 are connected and serve as the output of the duty cycle regulator. Specifically, for the overlapping enhancement-type frequency multiplier used in this embodiment for a 25GHz fourth harmonic, the pulse duty cycle of the synthesized signal output from the front-stage analog AND gate AAG is wide, approximately 37.5%. To make the target harmonic stronger after the fourth harmonic, the size ratio of the PMOS to NMOS in the duty cycle regulator of this embodiment is approximately 5.6:1. The component parameters in the duty cycle regulators of multiple different frequency multiplication units in the overlapping enhancement-type frequency multiplier remain consistent.

[0061] Finally, it should be emphasized that for each frequency multiplier unit, the size ratio of the PMOS and NMOS transistors in the duty cycle regulator is used as the first control parameter; the voltage value of the bias voltage connected to the analog AND gate is used as the second control parameter. The first and second control parameters are adjusted together so that the pulse width of the narrow pulse signal output by any frequency multiplier unit meets the preset value.

[0062] For the M-channel outputs of the pre-amplifier frequency multiplier, the current synthesizer in this embodiment includes M+1 NMOS transistors. The first to M NMOS transistors act as receivers, and the M narrow pulse signals output by each frequency multiplier, with a phase difference of 360° / M, are respectively connected to the gates of the M receivers; the source of each receiver is connected to VSS. The last NMOS transistor acts as a bus, and the drain of each receiver is connected to the source of the return current transistor; the gate of the bus is connected to VDD, and the drain of the bus acts as I... comb The output port.

[0063] Taking the circuit with a frequency multiplier of four as an example, such as Figure 6 As shown, the current synthesizer consists of five NMOS transistors N51~N54 and N6. The circuit connections are as follows: the four narrow pulse signals output from the four frequency multiplier units, each 90° out of phase, are connected to the gates of N51~N54 respectively; the sources of N51~N54 are connected to VSS; the drains of N51~N54 are connected to the source of N6; the gate of N6 is connected to VDD; and the drain of N6 serves as I0. comb The output port.

[0064] In practical applications, such as Figure 7As shown, the matching network provided in this embodiment includes four inductors L4~L7 and four capacitors C4~C7. One end of L4 and C4 is electrically connected to the output terminal of the current synthesizer; the other end of L4 and C4 is connected to VDD; L4 and L5 form the first mutual inductance circuit. One end of L5, C5, C6, and L6 is electrically connected; the other end of L5, C5, C6, and L6 is electrically connected; L6 and L7 form the second mutual inductance circuit. One end of L7 and C7 is connected and serves as the output terminal Vout of the matching network; the other end of L7 and C7 is connected to VSS. In practical applications, by optimizing the capacitance values ​​of each capacitor and the inductance values ​​of each inductor in the matching network, as well as the coupling rates K1 and K2 of the two mutual inductance circuits, the input impedance and output impedance can be matched.

[0065] The circuit further optimized in this embodiment, such as Figure 8 As shown, the matching network can also include a second harmonic notch filter composed of inductors L8 and L9 and capacitors C8 and C9. The circuit connection of the second harmonic notch filter is as follows: one end of L8 is electrically connected to one end of C8; the other end of L8 is electrically connected to one end of C5, and the other end of C8 is grounded; one end of L9 is electrically connected to one end of C9; the other end of L9 is electrically connected to the other end of C5, and the other end of C9 is grounded. By optimizing the capacitance values ​​of each capacitor and the inductance values ​​of each inductor in the second harmonic notch filter, the harmonic interference of the output signal can be made to meet the preset value.

[0066] As previously mentioned, for the multi-phase signal generation circuit of the front-end, there are multiple sinusoidal signals with fixed phase differences, such as the eight sinusoidal signals from 0 degrees, 45 degrees, 90 degrees to 315 degrees in the quadruple circuit. In order to ensure accurate phase matching in the subsequent frequency multiplication operation in the overlapping enhancement multiplier, it is necessary to avoid introducing unnecessary phase deviations during the signal transmission stage between the two. To address this issue, this embodiment also uses differential transmission lines (Diff.TL) with overlapping routing on the layout to transmit the sinusoidal signals generated by the multi-phase signal generator. This makes the load capacitance seen at each phase output end as consistent as possible, reducing the differences between different phase paths caused by different trace lengths, parasitic capacitances, and input loads. For multi-phase frequency multiplication, the consistency of the phase path directly affects the residual of the output fundamental, second harmonic, and third harmonic. Therefore, this layout connection method is an important prerequisite for the system to achieve a high harmonic rejection ratio.

[0067] Furthermore, in practical applications, the multi-phase signal generator in this embodiment is typically implemented using a ring traveling wave oscillator and a charge-steering-sampling all-digital phase-locked loop (CSS-ADPLL). The charge-steering-sampling all-digital phase-locked loop is used to acquire the output signal of the reference node in the ring traveling wave oscillator, and generates control signals based on the frequency and phase of the output signal of the reference node to adjust the connection state of each capacitor array in the ring traveling wave oscillator, thereby locking the output signal of each phase node of the ring traveling wave oscillator at a preset frequency.

[0068] Considering that the multi-phase output nodes of a traditional RTWO are typically positioned at different locations around the loop, maintaining consistent path lengths from each output node to subsequent circuitry (including overlay enhancement multipliers, current synthesizers, and matching networks) on the layout necessitates placing the subsequent circuitry at the center of the RTWO. This is virtually impossible in circuit layout. The subsequent circuitry usually needs to be shrunk to a very small size to fit within the RTWO center, and only a few circuits can be made this small. Furthermore, increasing the RTWO's inner diameter generally cannot increase the area available for the circuitry within the center, as this would directly alter the RTWO's oscillation frequency. Therefore, in practical applications, the subsequent circuitry is typically placed on one side of the RTWO.

[0069] To address this issue, this embodiment employs a novel multi-phase signal generator composed of two cascaded ring traveling-wave oscillators. This generator can provide multi-phase output nodes to parallel-arranged subsequent circuits, and the path lengths of the output multi-phase signals on the layout remain approximately consistent. Specifically, taking a multi-phase signal generator capable of generating eight sinusoidal signals with phases successively differing by 45° and frequencies all at 1 / 4 of the target frequency as an example... Figure 9 As shown, the multi-phase signal generator comprises two cascaded traveling-wave ring oscillators and a charge-controlled fully digital phase-locked loop. As can be seen in the figure, each traveling-wave ring oscillator contains eight transconductance elements Gm and provides 16 phase nodes with a sequential phase difference of 22.5°.

[0070] In this embodiment, at least two phase nodes are selected from the preceding ring traveling wave oscillator (TRO) as cascade ports, and these ports are connected to two phase nodes of the following TRO via capacitors. This results in the corresponding phase nodes in the following TRO being delayed by 22.5° compared to the preceding TRO. Based on this, this embodiment uses the 0°, 90°, 180°, and 270° phase nodes of the preceding TRO as output nodes for sinusoidal signals with phases of 0°, 90°, 180°, and 270°. Similarly, the 22.5°, 122.5°, 202.5°, and 292.5° phase nodes of the following TRO are used as output nodes for sinusoidal signals with phases of 45°, 135°, 225°, and 315°.

[0071] At this time, Figure 9 In the layout shown, the two output nodes at 0° and 180° are located exactly at the upper left corner of the preceding ring traveling wave oscillator; the two output nodes at 90° and 270° are located exactly at the lower right corner of the preceding ring traveling wave oscillator; the two output nodes at 45° and 225° are located exactly at the upper right corner of the following ring traveling wave oscillator; and the two output nodes at 135° and 315° are located exactly at the lower left corner of the following ring traveling wave oscillator.

[0072] This embodiment cascades two ring traveling wave oscillators, changing the positional distribution of each phase node on the layout. This results in the signal transmission paths between the eight output nodes and the overlapping enhancement multiplier having symmetry and the same length in the spatial portion of the layout. Consequently, the eight sinusoidal signals with the same phase difference output by the ring traveling wave oscillator maintain a relatively constant phase difference when input to the overlapping enhancement multiplier.

[0073] Based on the circuit design principles and layout described above, the W-band frequency synthesizer provided in this embodiment has the following advantages: (1) It is very difficult to directly implement a low-noise, wide-tuning-range, digitally controllable oscillator and phase-locked loop feedback link in the W-band. The W-band corresponds to about 75 GHz to 110 GHz, where the losses of inductors, transformers, tuning capacitor arrays and traces increase significantly, and the decrease in the quality factor (Q factor) of passive components will directly increase the phase noise (PN) of the oscillator. If a direct W-band fully digital phase-locked loop is used, the feedback frequency divider chain also needs to operate around 100 GHz. Multi-stage high-speed frequency dividers will lead to a narrower locking range, additional noise accumulation and increased power consumption. For communication and radar systems that require multi-frequency coverage, simply pushing up the frequency of traditional phase-locked loops often sacrifices phase noise, power consumption and feasibility at the same time.

[0074] In this implementation, the system architecture of "approximately 25 GHz lock-in + quadruple frequency output" avoids the high-risk path of directly constructing and locking a W-band digitally controlled oscillator (DCO). The RTWO operates near a quarter of the final output frequency, resulting in lower losses in passive components, reduced equivalent series resistance of the tuning capacitor array, and lower speed constraints in the feedback divider link compared to a direct 100 GHz solution. The CSS-ADPLL only needs to close the loop around the lower-frequency RTWO, eliminating the need for a long-link W-band high-speed divider at the feedback end. This reduces issues such as divider noise accumulation, limited lock-in range, and increased power consumption of high-frequency active circuits. Although the final output is in the W-band, the core phase comparison and frequency control actions of the PLL occur in a more easily implemented frequency band. This approach also allows for the use of mature millimeter-wave circuit experience in frequency tuning, digital control, and loop stability design, reducing the amplifying effect of layout parasitics and device model errors on closed-loop behavior. In other words, this solution breaks down the challenge into two separately optimizable stages: "low-noise multi-phase generation" and "high-efficiency fourth harmonic synthesis," enabling a more robust trade-off between phase noise, tuning range, power consumption, and circuit complexity in frequency synthesis around 100 GHz.

[0075] (2) Traditional multi-phase quadruple frequency multiplication schemes can rely on near-rail-to-rail square wave edges for synthesis in the lower millimeter-wave band, but in the W-band, the driving capability and edge speed of CMOS transistors are insufficient to support an ideal square wave. If the traditional large-phase-interval edge synthesis method is continued, the time window for the two inputs to be truly effective simultaneously is very short, the generated pulse swing is reduced, the fourth harmonic component is insufficient, and the output power and efficiency deteriorate accordingly. If a cascaded frequency multiplier is used instead, although the implementation path is intuitive, it will bring more active circuits, more matching networks, larger chip area, and more unwanted harmonic components, making it difficult to obtain a compact and efficient 100 GHz output.

[0076] In this embodiment, the OEPC-FQ overlay-enhanced frequency multiplier employs an overlay-enhanced pulse synthesis method with adjacent 45-degree phase overlaps, improving the effective pulse swing of the W-band fourth harmonic link. Traditional 135-degree interval edge synthesis relies on the rapid flipping of a near-ideal square wave, which is limited by transistor swing and slew rate in the W-band, resulting in narrower pulses or even difficulty in forming them. This solution first uses RTWO to provide an eight-phase sinusoidal signal, then allows adjacent 45-degree signals to enter the AAG, extending the time for both inputs to simultaneously meet the conduction conditions, thus increasing the pulse amplitude from the source. Subsequently, the LPF weakens the edge distortion caused by higher-order harmonics, and the DCA compresses the wider pulse output from the AAG into a narrower pulse more suitable for fourth harmonics, enhancing the target fourth harmonic component. Since the fourth harmonic output is not progressively increased by multiple stages of second harmonics, but rather obtained by direct current synthesis of four shaped pulses, interstage losses, interstage matching, and additional bias current are reduced, and the output is easier to design for matching around the target frequency. The four narrow pulses are current-synthesized to output a W-band signal, which is further suppressed by a matching network and a second harmonic notch filter. This approach avoids the area and power consumption overhead of cascaded frequency multipliers and is more suitable for the real CMOS conditions with limited driving capability of the W-band than ordinary multi-phase synthesis.

[0077] (3) The W-band local oscillator has high requirements for spectral purity, but reference spurs, non-target harmonics, and phase jitter can easily occur simultaneously. In communication systems, local oscillator phase noise can increase the error vector amplitude and disrupt higher-order modulation; in radar systems, local oscillator noise can degrade the detection capability of weak targets next to strong reflective targets at close range; the fundamental, second, and third harmonic remnants in the frequency multiplication link may also enter the transceiver channel through mixing, leakage, or on-chip coupling, causing out-of-band spurs and false spectral lines. Therefore, W-band frequency synthesizers cannot only pursue "oscillation up to 100 GHz", but must also achieve a balance between low jitter, low reference spurs, and high harmonic suppression.

[0078] The technical solution provided in this embodiment can simultaneously improve phase noise, reference spurious signals, and harmonic suppression, rather than optimizing only one of these indicators. The eight-phase uniform signal generated by RTWO obtains a more consistent load environment through overlapping transmission line routing, reducing path differences between each phase before entering AAG; DCDL provides fine timing adjustments to compensate for phase path deviations caused by actual manufacturing and layout; LPF allows AAG to process sinusoidal signals closer to the fundamental frequency, reducing the impact of higher-order harmonics on threshold conduction time; DCA enhances the fourth harmonic from the duty cycle perspective and suppresses unwanted frequency components. Since these measures act on phase path consistency, input waveform purity, pulse width, and output frequency selection respectively, non-target harmonics are not passively attenuated at a single stage, but are continuously suppressed in the generation, shaping, and output stages.

[0079] (4) Typical application scenarios usually require the W-band frequency synthesizer to be integrated into a small chip area and may serve multiple transceiver channels simultaneously. If the local oscillator source area is large, power consumption is high, or output power is insufficient, the system-level implementation will be forced to add external frequency multipliers, amplifiers, or complex local oscillator distribution networks, leading to increased cost, packaging difficulty, and channel consistency issues. Especially in phased array, vehicle radar, and UAV radar, the local oscillator link is not just a single circuit module, but a system bottleneck affecting array size, heat dissipation, synchronization, mass production consistency, and terminal battery life.

[0080] To address the requirements of this scenario, the technical solution provided in this embodiment achieves a good system trade-off between on-chip integration, output power, and energy efficiency. For system design, this means that the entire chain, from low-frequency multi-phase oscillation, phase-locked loop control, fourth harmonic synthesis, harmonic suppression to W-band output, can be completed within a single chip, eliminating the need for a larger and more power-intensive external frequency multiplication chain. Since the output already includes a matching network and a second harmonic notch filter, the subsequent transceiver channels deal with a more concentrated local oscillator signal. The system does not need to add a large number of off-chip filters or buffer stages to compensate for the local oscillator quality, and it also reduces the additional losses and uncertainties caused by packaging traces.

[0081] Example 2 The W-band frequency synthesizer provided in Example 1 has several advantages, including lower phase noise, wider tuning range, better circuit integration, and lower area and power consumption. In practical applications, it can be packaged as a high-frequency oscillator chip and widely used in various scenarios requiring high-frequency W-band oscillation signals. Typical application scenarios include: (I) For 6G millimeter-wave and Asia-Pacific Hertz communication transceivers. This invention can provide a low-jitter local oscillator for up-conversion and down-conversion links around 100 GHz. Addressing the difficulty in implementing direct W-band DCO and long high-speed frequency division links in Problem 1, this solution places the main loop of the phase-locked loop around 25 GHz, and then obtains the W-band output through on-chip quadruple frequency multiplication, enabling the transceiver to obtain a high-frequency local oscillator with lower power consumption. Regarding the problem of phase noise and reference spurs affecting high-order modulation, 79.9 fs-level jitter and approximately -52.8 dBc reference spurs help reduce modulation errors and adjacent channel interference. For 6G front-ends requiring high throughput, wide bandwidth, and high spectral efficiency, this local oscillator solution can reduce the drag on the link budget from the high-frequency local oscillator source itself.

[0082] (II) Applications in vehicle-mounted, UAV, and industrial MIMO radars. The phase noise of the radar local oscillator directly affects the spectral floor in both the range and velocity directions. Weak targets near strong reflective targets are particularly susceptible to being masked by local oscillator noise and spurious signals. This invention provides a local oscillator signal with low jitter and high harmonic suppression around 100 GHz through RTWO low-frequency locking and OEPC-FQ frequency doubling output, reducing the probability of spurious spectral lines and non-target harmonics entering the receiving link. Addressing the limitations of multi-channel array area and power consumption, 0.23 mm... 2 Its active area and total power consumption of 81.1 mW make it more suitable for integration into multi-channel radar chips. With a more compact local oscillator, the array can allocate more area and power consumption to the power amplifier, low-noise amplifier, phase shifter, and data conversion link.

[0083] (III) W-band sensing systems used for high-resolution imaging, close-range security inspection, and material detection. These systems require stable, repeatable, and spectrally clean excitation signals; otherwise, the reflected or transmitted spectrum of the object under test will be mixed with local oscillator harmonics and spurious responses caused by stray noise. This solution features a high harmonic suppression ratio. The OEPC-FQ enhances the fourth harmonic target component through adjacent phase overlap pulses, while using DCA and a second harmonic notch filter to reduce the residual fundamental, second, and third harmonic frequencies. This makes it easier for the system at the receiver to determine whether a spectral line originates from the object under test, rather than from the local oscillator itself. For imaging systems, lower jitter also improves coherent accumulation quality, which is beneficial for detail resolution and multi-frame fusion.

[0084] (iv) Used for on-chip test signal sources, millimeter-wave measurement platforms, and local oscillator distribution networks. Chip testing, package evaluation, and multi-channel verification often require a stable, on-chip integrated W-band signal source. Using external signal sources and frequency multiplier modules results in high testing costs, and connection losses and probe repeatability can also affect the results. This invention integrates the frequency synthesis link on-chip, with an output covering 92.7 GHz to 101.7 GHz, serving as a W-band excitation source for on-chip self-testing or experimental platforms. Addressing the pain points of complex external links and high area and power consumption in existing solutions, this invention reduces the number of external high-frequency modules. Regarding the problems of spurious and harmonic interference measurement in existing technologies, high HRR and low reference spurious emissions improve the reliability of the test signal, making the performance evaluation of subsequent circuits closer to the actual operating state.

[0085] Performance testing To verify the performance of the W-band frequency synthesizer provided by this invention, technicians used, for example... Figure 10 Taking the circuit shown as an example, the W-band frequency synthesizer was fabricated using 22nm CMOS technology, and the chip's performance, including frequency range, phase noise, reference spurious emissions, harmonic suppression, output power, chip area, and power consumption, was tested.

[0086] exist Figure 10 In the circuit shown, the charge-controlled sampling all-digital phase-locked loop (CSS-ADPLL) first locks the cascaded traveling-wave ring oscillator (RTWO), causing RTWO to oscillate around one-quarter of the target output frequency of 100 GHz. RTWO outputs eight multi-phase signals with a phase spacing of 45 degrees, i.e., 0 degrees, 45 degrees, 90 degrees, up to 315 degrees. These eight signals are sent to the overlapped enhancement multiple multiplier (OEPC-FQ) via differential transmission lines. After entering the OEPC-FQ, the two adjacent 45-degree sinusoidal signals first undergo fine timing adjustment via a digitally controlled delay line (DCDL), which adjusts in steps of approximately 50 fs to compensate for phase path differences introduced by manufacturing and layout. Subsequently, the signals pass through a low-pass filter, retaining approximately 25 GHz of fundamental frequency components and attenuating edge distortion caused by higher-order harmonics. The adjacent phase signals after low-pass filtering enter the analog AND gate (AAG). The AAG outputs a pulse with a wide duty cycle of approximately 37.5%. To make the target harmonic stronger after the fourth harmonic is harmonic, the pulse then enters the duty cycle regulator; this results in a narrower pulse signal that is compressed into a narrower pulse signal with a stronger fourth harmonic component. The four narrow pulse signals, which are 90 degrees out of phase, are combined into a current and then output as a W-band signal after passing through a buffer, a matching network, and a second harmonic notch filter.

[0087] 1. Phase noise In this experiment, the test results of the 100 GHz output phase noise curve and the root mean square jitter (RMS jitter) are as follows: Figure 11 As shown in the figure, the data indicates that the prototype chip of this W-band frequency synthesizer can output W-band signals in the range of 92.7 GHz to 101.7 GHz, corresponding to a fourfold frequency harmonic output of RTWO of approximately 23.2 GHz to 25.4 GHz.

[0088] At a 100 GHz carrier, with an integration range of 10 kHz to 40 MHz, the measured RMS jitter was approximately 79.9 fs. The approximately 6 GHz signal after frequency division showed similar jitter to the 100 GHz output, indicating that the quadruple frequency link did not introduce significant phase noise degradation.

[0089] In this experiment, the reference spurious test results at 100 GHz output are as follows: Figure 12 As shown, the harmonic suppression test results under the 101.7 GHz output condition are as follows: Figure 13 As shown, further statistical analysis yielded the test results for integral root mean square jitter, reference spurious emissions, and rejection ratio (HRR) in the range of 92.7 GHz to 101.7 GHz. Figure 14 As shown.

[0090] Analysis of the data in the above figures shows that, under the conditions of 100 GHz output and 250 MHz reference frequency, the measured reference spurious signal is approximately -52.8 dBc. The suppression ratios (HRR1, HRR2, and HRR3) of the fundamental, second harmonic, and third harmonic of the output signal relative to the target output are 55.4 dBc, 54 dBc, and 52.6 dBc, respectively; the overall HRR remains above approximately 51 dBc across the entire frequency band. Therefore, the technical solution provided by this invention can provide a cleaner W-band local oscillator for the system.

[0091] 2. Area and power consumption In this experiment, the complete prototype of the chip was produced using a 22 nm CMOS process, and the micrographs are shown below. Figure 15 As shown. Further statistical analysis yielded the test results for the circuit's output power and efficiency in the 92.7 GHz to 101.7 GHz range, as shown below. Figure 16 As shown. Based on the above data, the active area of ​​the chip is approximately 0.23 mm². 2 The total power consumption is approximately 81.1 mW. This includes approximately 26.6 mW for the RTWO, approximately 29.2 mW for the OEPC-FQ and related DCDL, and approximately 20.5 mW for the transmission line buffer. The output range covers 92.7 GHz to 101.7 GHz. Output power and system efficiency vary relatively gradually within this range. Output power peaks around 98 GHz, with a peak saturation output power of approximately -5.4 dBm.

[0092] Therefore, the chip solution provided by this invention can better balance on-chip integration, output power and energy efficiency, reduce the pressure of local oscillator module on chip area, power supply budget and packaging interconnection, and improve the consistency of on-chip local oscillator allocation; thus it is suitable for application in multi-channel arrays or compact sensing terminals.

[0093] The above-described embodiments are merely one implementation of the present invention, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of the invention. It should be noted that those skilled in the art can make various modifications and improvements without departing from the inventive concept, and these all fall within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the appended claims.

Claims

1. A W-band frequency synthesizer, comprising: A multi-phase signal generator is used to generate 2M sinusoidal signals with phases successively differing by 360° / 2M and frequencies all 1 / M of the target frequency, where M>1; An overlay-enhanced multiplier comprises M multiplier units. Each multiplier unit includes two digitally controlled delay lines, two low-pass filters, one analog AND gate, and one duty cycle adjuster. The sinusoidal signals from every two adjacent phases of the multi-phase signal generator are input into one of the multiplier units. Each sinusoidal signal undergoes phase compensation and low-pass filtering processing within the multiplier unit via a digitally controlled delay line and a low-pass filter, before being input to the two input terminals of the analog AND gate. The synthesized signal output from the analog AND gate is input to the duty cycle adjuster for pulse width adjustment, thereby obtaining a narrow pulse signal. A current synthesizer is used to synthesize multiple narrow pulse signals with phase differences of 360° / M from the output of each frequency multiplier unit to obtain a fused signal with the target frequency. A matching network is used to perform impedance matching and harmonic filtering on the fused signal, thereby generating the desired W-band oscillation signal.

2. The W-band frequency synthesizer according to claim 1, characterized in that: The numerically controlled delay line includes six inverters INV1 to INV6 and a numerically controlled capacitor array; INV1 to INV6 are cascaded to form an inverter chain; the input terminal of INV1 serves as the input terminal of the numerically controlled delay line, and the output terminal of INV6 serves as the output terminal of the numerically controlled delay line; wherein, the component size ratio from INV1 to INV3 is 1:2:4; the component size ratio from INV4 to INV6 is also 1:2:4; The numerically controlled capacitor array includes multiple capacitor units with capacitance values ​​arranged in a common ratio of 2 and transmission gates; one end of each capacitor unit is grounded, and the other end is electrically connected to the output terminal of INV3 through an independent transmission gate; the conduction state of each transmission gate is controlled by the code value of each bit of the numerically controlled signal CTRL to adjust the total capacitance value of the capacitor units connected to the inverter chain; thereby changing the delay length between the input signal and the output signal on the inverter chain.

3. The W-band frequency synthesizer according to claim 1, characterized in that: The low-pass filter includes an inverter INV7, a resistor R1, and three capacitors C1 to C3. One end of C1 serves as the input terminal of the low-pass filter, and the other end of C1 is electrically connected to one end of R1 and the input terminal of INV7. The output terminal of INV7 is electrically connected to the other end of R1 and one end of C2. The other end of C2 is connected to one end of C3 and serves as the output terminal of the low-pass filter. The other end of C3 is grounded.

4. The W-band frequency synthesizer according to claim 3, characterized in that: The analog AND gate includes two resistors R1 and R2, three PMOS transistors P1~P3 and three NMOS transistors N1~N3; The sources of P1~P3 are connected to VDD; one end of R1 is connected to the gates of P2 and N1 and serves as one of the inputs IN of an analog AND gate. A One end of R2 is connected to the gates of P1 and N2 and serves as the other input IN of the analog AND gate. B The other input terminal of R1 and R2 is connected to the bias voltage V. B The drains of P1, P2, and N1 are connected to the gates of P3 and N3; the source of N1 is connected to the drain of N2; the sources of N2 and N3 are connected to VSS; the drains of P3 and N3 are connected and used as the output terminal OUT of the analog AND gate. The duty cycle regulator is an inverter composed of a PMOS transistor P4 and an NMOS transistor N4 with a size ratio of N:1, where N > 1; the source of P4 is connected to VDD; the source of N4 is connected to VSS; the gates of P4 and N4 are connected and serve as the input terminal of the duty cycle regulator; the drains of P4 and N4 are connected and serve as the output terminal of the duty cycle regulator.

5. The W-band frequency synthesizer according to claim 1, characterized in that: The current synthesizer includes M+1 NMOS transistors; the M narrow pulse signals output by each frequency multiplier unit, with a phase difference of 360° / M, are respectively connected to the gates of the 1st to Mth NMOS transistors; the sources of the 1st to Mth NMOS transistors are connected to VSS; the drains of the 1st to Mth NMOS transistors are connected to the source of the M+1th NMOS transistor; the gate of the M+1th NMOS transistor is connected to VDD, and the drain of the M+1th NMOS transistor serves as I... comb The output port.

6. The W-band frequency synthesizer according to claim 5, characterized in that: The matching network includes four inductors L4~L7 and four capacitors C4~C7; one end of L4 and C4 is electrically connected to the output of the current synthesizer; the other end of L4 and C4 is connected to VDD; L4 and L5 form a first mutual inductance circuit; one end of L5, C5, C6, and L6 is electrically connected; the other end of L5, C5, C6, and L6 is electrically connected; L6 and L7 form a second mutual inductance circuit; one end of L7 and C7 is connected and serves as the output Vout of the matching network; the other end of L7 and C7 is connected to VSS.

7. The W-band frequency synthesizer according to claim 5, characterized in that: The sinusoidal signals output by the multi-phase signal generator are transmitted to the overlapping enhancement multiplier through differential transmission lines with overlapping wiring on the layout, thereby making the load capacitance of each phase output terminal consistent. The matching network further includes a second harmonic notch filter; the second harmonic notch filter includes inductors L8 and L9 and capacitors C8 and C9; one end of L8 is electrically connected to one end of C8; the other end of L8 is electrically connected to one end of C5, and the other end of C8 is grounded; one end of L9 is electrically connected to one end of C9; the other end of L9 is electrically connected to the other end of C5, and the other end of C9 is grounded.

8. The W-band frequency synthesizer according to claim 1, characterized in that: The multi-phase signal generator includes a multi-output ring traveling wave oscillator and a charge-rudder fully digital phase-locked loop; the charge-rudder fully digital phase-locked loop is used to acquire the output signal of the reference node in the ring traveling wave oscillator, and generate control signals for adjusting the access state of each capacitor array in the ring traveling wave oscillator according to the frequency and phase of the output signal of the reference node, thereby locking the output signal of each phase node of the ring traveling wave oscillator at a preset frequency.

9. The W-band frequency synthesizer according to claim 8, characterized in that: The multi-phase signal generator is used to generate eight sinusoidal signals with phases differing by 45° and frequencies that are all 1 / 4 of the target frequency. The multi-output ring traveling wave oscillator includes two cascaded ring traveling wave oscillators; the ring traveling wave oscillator contains 8 transconductance elements Gm and provides 16 phase nodes with a phase difference of 22.5° in sequence; Select at least two phase nodes from the preceding ring traveling wave oscillator as cascade ports and connect them to two phase nodes of the following ring traveling wave oscillator via capacitors; thereby causing the corresponding phase node in the following ring traveling wave oscillator to be delayed by 22.5° compared to the following ring traveling wave oscillator. The 0°, 90°, 180°, and 270° phase nodes in the pre-stage ring traveling wave oscillator are used as output nodes for outputting sinusoidal signals with phases of 0°, 90°, 180°, and 270°; the 22.5°, 122.5°, 202.5°, and 292.5° phase nodes in the post-stage ring traveling wave oscillator are used as output nodes for outputting sinusoidal signals with phases of 45°, 135°, 225°, and 315°. By cascading two ring traveling wave oscillators, the signal transmission paths between the eight output nodes and the overlapped enhancement multiplier are symmetrical and of the same length in the spatial portion of the layout. This ensures that the eight sinusoidal signals with the same phase difference output by the ring traveling wave oscillators maintain a constant phase difference when input to the overlapped enhancement multiplier.

10. An application of the W-band frequency synthesizer as described in any one of claims 1-7 in W-band sensing systems, MIMO radar, measurement platforms, 6G millimeter-wave and Asia-Pacific Hertz communication transceivers, characterized in that: The W-band frequency synthesizer is used to provide an oscillation signal at a specified frequency point within the W-band.

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