Offset calibration in a difference circuit

Abstract

The present disclosure relates to offset calibration in differential circuits. A circuit includes a differential circuit and a calibration circuit. The differential circuit includes an input control terminal to receive a differential input signal, a current supply terminal to receive a calibration current, and an output control terminal to generate a differential output signal based on the differential input signal and the calibration current. The calibration circuit is coupled to the differential circuit. The calibration circuit includes a calibration current source to generate the calibration current. Further, the calibration circuit includes a control input to receive a control signal to control activation of the calibration current source, and a control output to provide the calibration current at the current supply terminal to calibrate an offset between the differential output signal.

Description

Technical Field

[0001] This disclosure generally relates to differential circuits, and more specifically, to offset calibration in differential circuits. Background Technology

[0002] Differential signal processing circuits are crucial for providing noise immunity and signal integrity in high-speed communication systems. However, inherent offset errors arise in these circuits due to process variations, temperature fluctuations, and power supply instability, leading to a degrade in the overall performance of differential circuits. Conventional offset measurement and calibration techniques result in low residual common-mode after offset calibration, causing linearity issues and DC gain variations. Furthermore, for multi-stage differential circuits, this offset is amplified with each stage, further impacting system performance. Summary of the Invention

[0003] In embodiments of this disclosure, a circuit is disclosed. The circuit may include a differential circuit and a calibration circuit coupled to the differential circuit. The differential circuit may include a first node and a second node, a first input control terminal and a second input control terminal, and a first output control terminal and a second output control terminal. The first input control terminal and the second input control terminal may receive a first input signal and a second input signal, respectively. The first output control terminal and the second output control terminal may generate a first output signal and a second output signal at their respective locations based on the first input signal and the second input signal. The calibration circuit may include a first calibration current source and a second calibration current source, a first plurality of control inputs, and a first plurality of control outputs. The first calibration current source and the second calibration current source may generate a first calibration current and a second calibration current, respectively. The plurality of control inputs may receive a set of control signals to control the direction of the first calibration current and the second calibration current. The plurality of control outputs may perform one of the following: (i) providing the first calibration current and the second calibration current at the first node and the second node, respectively, and (ii) providing the second calibration current and the first calibration current at the first node and the second node, respectively, thereby calibrating the offset between the first output signal and the second output signal.

[0004] In some embodiments, the differential circuit may further include a first transistor and a second transistor. The first transistor may include a first input control terminal, a first current supply terminal coupled to the first node, and a first output control terminal. The second transistor may include a second input control terminal, a second current supply terminal coupled to the second node, and a second output control terminal.

[0005] In some embodiments, the differential circuit may further include a first bias current source and a second bias current source. The first bias current source may include a first terminal coupled to the first node and a second terminal coupled to a voltage supply source. The first bias current source may generate a first bias current at its first terminal. The second bias current source may include a first terminal coupled to the second node and a second terminal coupled to the voltage supply source. The second bias current source may generate a second bias current at its first terminal.

[0006] In some embodiments, the differential circuit may further include a first resistor to a third resistor. The first resistor may be coupled between the first node and the second node. The second resistor may be coupled between the first output control terminal and the voltage supply source. The third resistor may be coupled between the second output control terminal and the voltage supply source.

[0007] In some embodiments, the calibration circuit may further include a first switch and a second switch. The first switch may be coupled to the first calibration current source and the first node. The first switch may include a first terminal for receiving a first control signal from the set of control signals, and a second terminal for providing a first calibration current at the first node based on the first control signal to pull up the first output signal. The second switch may be coupled to the second calibration current source and the second node. The second switch may include a first terminal for receiving a second control signal from the set of control signals, and a second terminal for providing a second calibration current at the second node based on the second control signal to pull down the second output signal.

[0008] In some embodiments, the offset calibration circuit may further include a third switch and a fourth switch. The third switch may be coupled to the first calibration current source and the second node. The third switch may include a first terminal for receiving a third control signal from the set of control signals, and a second terminal for providing the first calibration current at the second node based on the third control signal to pull up the second output signal. The fourth switch may be coupled to the second calibration current source and the first node. The fourth switch may include a first terminal for receiving a fourth control signal from the set of control signals, and a second terminal for providing the second calibration current at the first node based on the fourth control signal to pull down the first output signal.

[0009] In some embodiments, the circuit may further include a control circuit. The control circuit may be coupled to the differential circuit and the offset calibration circuit. The control circuit may receive the first output signal and the second output signal from the differential circuit, and generate the set of control signals based on the first output signal and the second output signal.

[0010] In some embodiments, the set of control signals includes the first control signal to the fourth control signal. The control circuit can (i) assert the first control signal and the second control signal when the amplitude of the first output signal is less than the amplitude of the second output signal, and (ii) assert the third control signal and the fourth control signal when the amplitude of the first output signal is greater than the amplitude of the second output signal. When the first control signal and the second control signal are asserted, the first output signal and the second output signal are calibrated based on the first calibration current and the second calibration current, respectively; and when the third control signal and the fourth control signal are asserted, the first output signal and the second output signal are calibrated based on the second calibration current and the first calibration current, respectively.

[0011] In some embodiments, the circuit includes a control circuit coupled to the differential circuit and the calibration circuit. The control circuit can generate a first tuning signal and a second tuning signal based on the first output signal and the second output signal, provide the first tuning signal and the second tuning signal to the first calibration current source and the second calibration current source, respectively, and adjust the first tuning signal and the second tuning signal by predetermined values ​​to increase the amplitudes of the first calibration current and the second calibration current, thereby calibrating the offset between the first output signal and the second output signal.

[0012] In some embodiments, the circuit may further include a correction circuit coupled to the differential circuit. The correction circuit may receive an adjustment signal, generate a first correction signal and a second correction signal based on the adjustment signal, and provide the first correction signal and the second correction signal to the differential circuit to correct the amplitudes of the first output signal and the second output signal, respectively. The amplitudes of the first output signal and the second output signal can be corrected to obtain a common-mode signal greater than or equal to a predefined value.

[0013] In some embodiments, the common-mode signal corresponds to the average of the amplitudes of the first output signal and the second output signal. When the common-mode signal is greater than or equal to the predefined value, the first calibration current and the second calibration current are redirected.

[0014] In some embodiments, the correction circuit may include a first digital-to-analog converter (DAC) and a second DAC coupled to the differential circuit. The first DAC may receive the adjustment signal, generate the first correction signal based on the adjustment signal, and provide the first correction signal to the differential circuit. The second DAC is coupled to the differential circuit and may receive the adjustment signal, generate the second correction signal based on the adjustment signal, and provide the second correction signal to the differential circuit.

[0015] In some embodiments, the differential circuit may include a first transistor and a second transistor, a first resistor and a second resistor, and a fifth switch and a sixth switch. The first transistor may include a first input control terminal, a first current supply terminal coupled to the first node, and a first output control terminal. The second transistor may include a second input control terminal, a second current supply terminal coupled to the second node, and a second output control terminal. The first resistor may be coupled to the first output control terminal. The second resistor may be coupled to the second output control terminal. The fifth switch may include a first terminal coupled to the first resistor, a second terminal coupled to a power supply, and a control terminal coupled to the correction circuit. The fifth switch may receive the first correction signal at the control terminal to correct the amplitude of the first output signal. The sixth switch may include a first terminal coupled to the second resistor, a second terminal coupled to the power supply, and a control terminal coupled to the correction circuit. The sixth switch may receive the second correction signal at the control terminal to correct the amplitude of the second output signal.

[0016] In some embodiments, the differential circuit may further include a first bias current source, a second bias current source, and a third resistor. The first bias current source may include a first terminal coupled to the first node and a second terminal coupled to a voltage supply source. The first bias current source may generate a first bias current at its first terminal. The second bias current source may include a first terminal coupled to the second node and a second terminal coupled to the voltage supply source. The second bias current source may generate a second bias current at its first terminal. The third resistor may be coupled between the first node and the second node.

[0017] In some embodiments, the circuit may further include a control circuit. The control circuit may generate the adjustment signal based on the common-mode signal and adjust the adjustment signal by a predetermined value until the common-mode signal is greater than or equal to the predefined value.

[0018] In some embodiments, the control circuit may include a first common-mode generator coupled to the differential circuit and a first comparator coupled to the first common-mode generator. The first common-mode generator may receive the first output signal and the second output signal, and generate the common-mode signal based on the first output signal and the second output signal. The first comparator may compare the common-mode signal with a predefined value. The adjustment signal is generated based on the comparison between the common-mode signal and the predefined value.

[0019] In some embodiments, the control circuit may further include a second comparator coupled to the differential circuit, a third DAC coupled to the calibration circuit, and logic circuitry coupled to the second comparator and the third DAC. The second comparator may receive the first output signal and the second output signal, and compare the first output signal and the second output signal. The set of control signals is generated based on the comparison of the first output signal and the second output signal. The third DAC may generate a first tuning signal and a second tuning signal based on the first output signal and the second output signal to control the generation of the first calibration current and the second calibration current. The logic circuitry may generate the set of control signals and control the scanning operation of the third DAC based on the first output signal and the second output signal.

[0020] In another embodiment of this disclosure, a circuit including a plurality of differential circuits is disclosed.

[0021] In some embodiments, the plurality of differential circuits may be coupled sequentially.

[0022] In another embodiment of this disclosure, a circuit is disclosed. The circuit may include a differential circuit and an offset calibration circuit coupled to the differential circuit. The differential circuit may include a first node and a second node, a first input control terminal and a second input control terminal, and a first output control terminal and a second output control terminal. The first input control terminal and the second input control terminal may receive a first input signal and a second input signal, respectively. The first output control terminal and the second output control terminal may generate a first output signal and a second output signal at their respective locations based on the first input signal and the second input signal. The offset calibration circuit may include a first calibration current source and a second calibration current source, a plurality of control inputs, and a plurality of control outputs. The first calibration current source and the second calibration current source may generate a first calibration current and a second calibration current. The plurality of control inputs may receive a set of control signals. The plurality of control outputs may, based on the set of control signals, perform one of the following: (i) providing the first calibration current and the second calibration current at the first node and the second node, respectively; and (ii) providing the second calibration current and the first calibration current at the first node and the second node, respectively. Attached Figure Description

[0023] The following detailed description of embodiments of the present disclosure will be better understood when read in conjunction with the accompanying drawings. This disclosure is illustrated by way of example and is not limited to the drawings, in which the same reference numerals denote similar elements.

[0024] Figure 1 A schematic block diagram of a circuit including a multi-stage differential circuit according to an embodiment of the present disclosure is shown;

[0025] Figure 2 An embodiment according to this disclosure is shown. Figure 1 A schematic circuit diagram of the first differential circuit in a multi-stage differential circuit;

[0026] Figure 3 Another embodiment according to this disclosure is shown. Figure 1 A schematic circuit diagram of the first differential circuit;

[0027] Figure 4 An embodiment according to this disclosure is shown. Figure 1 A schematic circuit diagram of the control circuit of the circuit; and

[0028] Figure 5A and 5B The flowcharts presented together illustrate a method for using an embodiment of the present disclosure to... Figure 1 The method of offset calibration performed by the circuit. Detailed Implementation

[0029] The detailed description of the accompanying drawings is intended as a description of embodiments of the present disclosure and is not intended to represent the only form in which the present disclosure may be practiced. It should be understood that the same or equivalent functionality may be achieved through different embodiments intended to be covered within the spirit and scope of the present disclosure.

[0030] Differential circuits are susceptible to offset errors caused by process variations, power supply fluctuations, temperature variations, and long-term component drift. Offset errors introduce imbalances into the differential output signal, affecting signal accuracy and overall system performance. Conventional offset correction techniques use a continuous feedback loop coupled at the output of the differential circuit to dynamically calibrate the offset. However, this conventional technique results in a complex circuit system that introduces additional parasitic capacitance at the differential circuit output, leading to a 3 dB bandwidth degradation and deterioration of output signal parameters.

[0031] Other known static calibration techniques utilize a predefined calibration current supplied at the output of the differential circuit to compensate for offset errors. However, this technique suffers from low residual common-mode after offset calibration, leading to linearity issues (1dB compression) and DC gain variations. As circuit design sizes and operational tolerances become increasingly stringent, maintaining consistent and accurate offset calibration becomes a significant challenge. In high-precision applications such as analog front-end circuits, high-speed communication interfaces, and sensor-based measurement systems, offset deviations can adversely affect the operational accuracy of the system. Furthermore, for multi-stage differential circuits, the offset is amplified with each differential stage, impacting the overall system performance.

[0032] Various embodiments of this disclosure disclose a circuit including a differential circuit and a calibration circuit. The differential circuit may include an input terminal for receiving a differential input signal, a power supply terminal (node) for receiving a calibration current, and an output terminal for generating a differential output signal based on the differential input signal and the calibration current. The calibration circuit may additionally receive a set of control signals to control the direction of the calibration current. Based on the direction of the calibration current, the calibration circuit may provide a calibration current at the power supply terminal of the differential circuit to calibrate the offset between the differential output signals.

[0033] Compared to conventional techniques, this disclosure allows for the selective redirection of the calibration current based on the aforementioned set of control signals, providing a calibration current at the power supply terminal relative to the output of the differential circuit. Therefore, the disclosed circuit facilitates real-time offset calibration, thereby enhancing the accuracy and reliability of the differential circuit under varying operating conditions.

[0034] Figure 1A schematic block diagram of a circuit 100 including multi-stage differential circuitry according to an embodiment of the present disclosure is shown. Circuit 100 may include multi-stage differential circuitry 102, control circuitry 104, and power supply 106, wherein multi-stage differential circuitry 102 includes first to Nth differential circuits 102a-102n. Circuit 100 may be implemented in communication applications such as serializer / deserializer (SerDes) interfaces or memory interfaces, such as Peripheral Component Interconnect High Speed ​​(PCIE) communication interfaces, Universal Serial Bus (USB) 3.1 interfaces, Double Data Rate (DDR) memory, etc., but may be used in other types of circuitry in other embodiments.

[0035] In one embodiment, each of the first to Nth differential circuits 102a-102n may correspond to an amplifier stage of a multi-stage amplifier circuit. Each amplifier stage may include a differential circuit and an offset calibration circuit (such as...). Figure 2 and 3 (As shown). The differential circuit can receive differential inputs and generate differential outputs. In some scenarios, the differential output may include an offset error. To calibrate the offset error, control circuit 104 can control an offset calibration circuit to provide a calibration current to the differential circuit. In one embodiment, the calibration current can be provided to the differential circuit at the source side. Figure 2 and 3 Offset calibration is explained in detail.

[0036] Each of the first to Nth differential circuits 102a-102n can be coupled to the control circuit 104 and the power supply 106. The first to Nth differential circuits 102a-102n can be coupled sequentially, such that subsequent differential circuits can receive the differential output generated by the previous differential circuit as differential inputs. In one embodiment, the first differential circuit 102a can receive a power supply voltage VDD, differential input signals (e.g., a first input signal IS1 and a second input signal IS2), a first set of control signals CS1-CS4, and a first set of tuning signals TS1-TS2. Based on the power supply voltage VDD, the first input signal IS1 and the second input signal IS2, the first set of control signals CS1-CS4, and the first set of tuning signals TS1-TS2, the first differential circuit 102a can generate differential outputs, such as a first output signal OS1 and a second output signal OS2. Similarly, the second differential circuit 102b can receive the power supply voltage VDD, the first output signal OS1 and the second output signal OS2 as differential input signals, the second set of control signals CS5-CS8 and the second set of tuning signals TS3-TS4, and generate differential outputs, such as the third output signal OS3 and the fourth output signal OS4. Furthermore, the Nth differential circuit 102n can receive the power supply voltage VDD, the output signals generated by the previous differential circuit as differential input signals, the Nth set of control signals CS(4N-3)-CS(4N) and the Nth set of tuning signals TS(2N-1)-TS(2N), and generate differential outputs, such as output signals OS(2N-1) and OS(2N).

[0037] The control circuit 104 can be coupled to the first to Nth differential circuits 102a-102n and the power supply 106. The control circuit 104 can receive the differential outputs generated by each differential circuit, for example, output signals OS1-OS(2N-1). Based on the output signals OS1-OS(2N-1), the control circuit 104 can generate the first to Nth sets of control signals CS1-CS(4N) and the first to Nth sets of tuning signals TS1-TS(2N).

[0038] Power supply 106 can correspond to a power supply source capable of generating power supply voltage VDD. Although Figure 1 All circuitry is shown to be implemented within circuit 100, but in various embodiments, some circuitry may be located outside of circuit 100. For example, in some embodiments, power supply 106 may be located outside of circuit 100.

[0039] Figure 2 An embodiment according to this disclosure is shown. Figure 1 A schematic circuit diagram of the first differential circuit 102a in the multi-stage differential circuit 102. The first differential circuit 102a may include differential circuit 202 and offset calibration circuit 204.

[0040] The differential circuit 202 can receive a first input signal IS1 and a second input signal IS2, as well as a first calibration current IC1 and a second calibration current IC2, and generate a first output signal OS1 and a second output signal OS2. In some embodiments, the first output signal OS1 and the second output signal OS2 may include offsets caused by process variations, temperature fluctuations, and power supply instability in the differential circuit 202. The offset calibration circuit 204 can calibrate the offset between the first output signal OS1 and the second output signal OS2 by providing the first calibration current IC1 and the second calibration current IC2 on the source side of the differential circuit 202, as described in this disclosure. The differential circuit 202 may include a first node N1 and a second node N2, a first transistor T1 and a second transistor T2, and a first bias current source 206a and a second bias current source 206b.

[0041] First bias current source 206a and second bias current source 206b:

[0042] The first bias current source 206a may include a first terminal coupled to the first node N1 and a second terminal coupled to a voltage supply source. 206a A first bias current IB1 can be generated at a first terminal of a first bias current source 206a. The first bias current source 206a can provide the first bias current IB1 to transistor T1 via a first node N1 to bias the first transistor T1 (e.g., to achieve desired amplification of the first input signal IS1). Similarly, a second bias current source 206b can include a first terminal coupled to a second node N2 and a second terminal coupled to a voltage supply source. The second bias current source 206b can generate a second bias current IB2 at its first terminal. The second bias current source 206b can provide the second bias current IB2 to transistor T2 via a second node N2 to bias the second transistor T2 (e.g., to achieve desired amplification of the second input signal IS2). In one embodiment, the voltage supply source can correspond to ground, a positive voltage signal, or a negative voltage signal.

[0043] First transistor T1 and second transistor T2:

[0044] The first transistor T1 may include a first input control terminal, a first output control terminal coupled to the control circuit 104, and a first current supply terminal coupled to the first node N1. The first transistor T1 may receive a first input signal IS1 at the first input control terminal and a first bias current IB1 at the first current supply terminal via the first node N1, and generate a first output signal OS1 at the first output control terminal. In one embodiment, the first transistor T1 may amplify and invert the first input signal IS1 based on the first bias current IB1 to generate the first output signal OS1. In one example, the first output signal OS1 may correspond to an amplified and inverted version of the first input signal IS1.

[0045] Similarly, the second transistor T2 may include a second input control terminal, a second output control terminal coupled to the control circuit 104, and a second current supply terminal coupled to the second node N2. Additionally, the second transistor T2 may receive the second input signal IS1 at the second input control terminal and the second bias current IB2 at the second current supply terminal via the second node N2, and generate a second output signal OS2 at the second output control terminal. In one embodiment, the second transistor T2 may amplify and invert the second input signal IS2 based on the second bias current IB2 to generate the second output signal OS2. In one example, the second output signal OS2 may correspond to an amplified and inverted version of the second input signal IS2. Therefore, the first transistor T1 and the second transistor T2 can amplify the voltage difference between the first input signal IS1 and the second input signal IS2. In an embodiment, the first transistor T1 and the second transistor T2 are n-channel metal-oxide-semiconductor (NMOS) transistors, and the current supply terminal, input control terminal, and output control terminal of the first transistor T1 and the second transistor T2 correspond to the source terminal, gate terminal, and drain terminal, respectively. However, in other embodiments, the first transistor T1 and the second transistor T2 can be other types of transistors, such as bipolar transistors or p-channel metal-oxide-semiconductor (PMOS) transistors.

[0046] In one embodiment, each differential circuit in the multi-stage differential circuit 102 may be implemented using an NMOS transistor. However, in other embodiments, each differential circuit in the multi-stage differential circuit 102 may be implemented using a PMOS transistor, such that a first bias current source 206a and a second bias current source 206b are coupled between a first transistor T1 and a second transistor T2, and the power supply voltage VDD and resistors R2 and R3 are coupled between the first transistor T1 and the second transistor T2 and ground.

[0047] Control circuit 104:

[0048] like Figure 1The control circuit 104 shown can receive a first output signal OS1 and a second output signal OS2 from the first transistor T1 and the second transistor T2 of the differential circuit 202. Based on the first output signal OS1 and the second output signal OS2, the control circuit 104 can generate a first set of control signals CS1-CS4 and a first set of tuning signals TS1 and TS2. The first set of control signals CS1-CS4 may include the first to fourth control signals CS1-CS4.

[0049] Offset calibration circuit 204:

[0050] Offset calibration circuit 204 can be coupled to differential circuit 202 and control circuit 104. Offset calibration circuit 204 can receive a first set of control signals CS1-CS4 and a first set of tuning signals TS1 and TS2 from control circuit 104. Based on the first set of control signals CS1-CS4 and the first set of tuning signals TS1 and TS2, offset calibration circuit 204 can generate a first calibration current IC1 and a second calibration current IC2 for calibrating the offset between the first output signal OS1 and the second output signal OS2.

[0051] The offset calibration circuit 204 may include a first calibration current source 208a and a second calibration current source 208b for generating a first calibration current IC1 and a second calibration current IC2, and a plurality of control inputs for receiving a first set of control signals CS1-CS4. The offset calibration circuit 204 may further include a plurality of control outputs to provide the first calibration current IC1 and the second calibration current IC2 at a first node N1 and a second node N2 of the differential circuit 202 based on the first set of control signals CS1-CS4. In one scenario, the offset calibration circuit 204 may provide the first calibration current IC1 and the second calibration current IC2 at the first node N1 and the second node N2, respectively. In another scenario, the offset calibration circuit 204 may provide the first calibration current IC1 and the second calibration current IC2 at the second node N2 and the first node N1, respectively. In one embodiment, the offset calibration circuit 204 may include first to fourth switches S1-S4, which may receive the first set of control signals CS1-CS4 to control the direction of the first calibration current IC1 and the second calibration current IC2.

[0052] Switches S1-S4 (first to fourth):

[0053] The first switch S1 may be coupled to the first calibration current source 208a, the first node N1, and the control circuit 104. The first switch S1 may include a first terminal for receiving the first control signal CS1 from a first set of control signals CS1-CS4, a second terminal for receiving the first calibration current IC1, and a third terminal for providing the first calibration current IC1 at the first node N1 to pull up the first output signal OS1 based on an assertion of the first control signal CS1. In one embodiment, to pull up the first output signal OS1, the first calibration current IC1 may be applied to a first bias current IB1, thereby pulling up (e.g., increasing) the voltage level of the first output signal OS1.

[0054] The second switch S2 can be coupled to the second calibration current source 208b, the second node N2, and the control circuit 104. The second switch S2 may include a first terminal for receiving the second control signal CS2 from the first set of control signals CS1-CS4, a second terminal for receiving the second calibration current IC2, and a third terminal for providing the second calibration current IC2 at the second node N2 to pull down the second output signal OS2 based on an assertion of the second control signal CS2. In one embodiment, to pull down the second output signal OS2, the second calibration current IC2 can be subtracted from the second bias current IB2, thereby pulling down (e.g., reducing) the voltage level of the second output signal OS2.

[0055] The third switch S3 can be coupled to the first calibration current source 208a, the second node N2, and the control circuit 104. The third switch S3 may include a first terminal for receiving the third control signal CS3 from the first set of control signals CS1-CS4, a second terminal for receiving the first calibration current IC1, and a third terminal for providing the first calibration current IC1 at the second node N2 to pull up the second output signal OS2 based on the assertion of the third control signal CS3. Furthermore, the fourth switch S4 can be coupled to the second calibration current source 208b, the first node N1, and the control circuit 104. The fourth switch S4 may include a first terminal for receiving the fourth control signal CS4 from the first set of control signals CS1-CS4, a second terminal for receiving the second calibration current IC2, and a third terminal for providing the second calibration current IC2 at the first node N1 to pull down the first output signal OS1 based on the assertion of the fourth control signal CS4.

[0056] In operation, when the amplitude of the first output signal OS1 is less than the amplitude of the second output signal OS2, the control circuit 104 can assert the first control signal CS1 and the second control signal CS2. When the first control signal CS1 and the second control signal CS2 can be asserted, the first switch S1 and the second switch S2 can be activated. Therefore, the first output signal OS1 and the second output signal OS2 can be calibrated based on the first calibration current IC1 and the second calibration current IC2, respectively. The first calibration current IC1 can pull up the amplitude of the first output signal OS1, and the second calibration current IC2 can pull down the amplitude of the second output signal OS2 to calibrate the offset between the first output signal OS1 and the second output signal OS2 (e.g., to bring the amplitudes of the first output signal OS1 and the second output signal OS2 to the same level).

[0057] Furthermore, when the amplitude of the first output signal OS1 is greater than the amplitude of the second output signal OS2, the control circuit 104 can assert the third control signal CS3 and the fourth control signal CS4. When the third control signal CS3 and the fourth control signal CS4 can be asserted, the third switch S3 and the fourth switch S4 are activated. Therefore, the first output signal OS1 and the second output signal OS2 can be calibrated based on the second calibration current IC2 and the first calibration current IC1, respectively. The second calibration current IC2 can pull down the amplitude of the first output signal OS1, and the first calibration current IC1 can pull up the amplitude of the second output signal OS2 to calibrate the offset between the first output signal OS1 and the second output signal OS2.

[0058] In one embodiment, the amount by which the amplitudes of the first output signal OS1 and the second output signal OS2 can be pulled up or down can be based on the amplitudes of the first calibration current IC1 and the second calibration current IC2. The control circuit 104 can provide the first tuning signal TS1 and the second tuning signal TS2 from the first set of tuning signals TS1-TS2 to the first calibration current source 208a and the second calibration current source 208b, respectively. The first tuning signal TS1 and the second tuning signal TS2 can control the amplitudes of the first calibration current IC1 and the second calibration current IC2, respectively. In one embodiment, the first calibration current IC1 and the second calibration current IC2 can be at a first amplitude and a second amplitude, respectively. The control circuit 104 can monitor the first output signal OS1 and the second output signal OS2 to determine whether the offset between the first output signal OS1 and the second output signal OS2 is calibrated or uncalibrated at the first amplitude and the second amplitude of the first calibration current IC1 and the second calibration current IC2. If the offset between the first output signal OS1 and the second output signal OS2 remains uncalibrated at a first amplitude and a second amplitude of the first calibration current IC1 and the second calibration current IC2, the control circuit 104 can adjust the first tuning signal TS1 and the second tuning signal TS2 to increase the amplitude of the first calibration current IC1 and the second calibration current IC2 to calibrate the offset between the first output signal OS1 and the second output signal OS2. In one example, the control circuit 104 can adjust the first tuning signal TS1 and the second tuning signal TS2 to a first value (e.g., a predetermined value). In one embodiment, the first value can be predetermined by the control circuit 104. Furthermore, the first tuning signal TS1 and the second tuning signal TS2 can be adjusted to the first value to increase the amplitude of the first calibration current IC1 and the second calibration current IC2, respectively, until the offset between the first output signal OS1 and the second output signal OS2 is calibrated. In one embodiment, the control circuit 104 can determine the first value. Further, the first tuning signal TS1 and the second tuning signal TS2 can be iteratively adjusted to calibrate the offset between the first output signal OS1 and the second output signal OS2. In one embodiment, the first tuning signal TS1 and the second tuning signal TS2 are adjusted simultaneously to calibrate the offset between the first output signal OS1 and the second output signal OS2.

[0059] First to third resistors R1-R3:

[0060] The differential circuit 202 may further include first to third resistors R1-R3. The first resistor R1 may be coupled between the first node N1 and the second node N2. The first resistor R1 may include a first end coupled to a first terminal of the first node N1 and the first bias current source 206a, and a second end coupled to a first terminal of the second node N2 and the second bias current source 206b. In one embodiment, the first resistor R1 may be an overdriven degenerate resistor implemented to control the first input signal IS1 and the second input signal IS2. The second resistor R2 may include a first end coupled to a first output control terminal and a second end coupled to a voltage supply source. In one embodiment, the second end of the second resistor R2 is coupled to power supply 106 to receive the power supply voltage VDD. Similarly, the third resistor R3 may include a first end coupled to a second output control terminal and a second end coupled to a voltage supply source. In one embodiment, the second end of the third resistor R3 is coupled to power supply 106 to receive the power supply voltage VDD. In one embodiment, the second resistor R2 and the third resistor R3 may correspond to a load resistor that can regulate the flow of the aforementioned current in the differential circuit 202.

[0061] It will be apparent to those skilled in the art that the remaining differential circuits 102b-102n can be structurally and functionally similar to... Figure 2 The first differential circuit 102a, and can be used with Figure 2 The offset between the differential outputs generated by the corresponding circuits is calibrated in a manner similar to that described in the diagram. Therefore, each of the first to Nth differential circuits 102b-102n can be offset calibrated, thereby calibrating the total offset of the multi-stage circuit.

[0062] Figure 3 Another embodiment according to this disclosure is shown. Figure 1 A schematic circuit diagram of the first differential circuit 102a in the multi-stage differential circuit 102. The first differential circuit 102a may include a differential circuit 202, an offset calibration circuit 204, and a correction circuit 302.

[0063] The differential circuit 202 can receive a first input signal IS1 and a second input signal IS2, a first calibration current IC1 and a second calibration current IC2, and a first correction signal CO1 and a second correction signal CO2, and generate a first output signal OS1 and a second output signal OS2. In some embodiments, the first output signal OS1 and the second output signal OS2 may have a value less than a predefined value relative to the first common-mode signal CMS1 (to be discussed later). Figure 4(As shown in the figure) the associated common-mode voltage. The correction circuit 302 can correct the common-mode voltage by providing a first correction signal CO1 and a second correction signal CO2 to the differential circuit 202, as described in this disclosure. Additionally, the first output signal OS1 and the second output signal OS2 can include offsets caused by process variations, temperature fluctuations, and power supply instability in the differential circuit 202. The offset calibration circuit 204 can calibrate the offset between the first output signal OS1 and the second output signal OS2 by providing a first calibration current IC1 and a second calibration current IC2 on the source side of the differential circuit 202, as described in this disclosure. The differential circuit 202 can include a first node N1 and a second node N2, a first transistor T1 and a second transistor T2, a first bias current source 206a and a second bias current source 206b, first to third resistors R1-R3, and a fifth switch S5 and a sixth switch S6.

[0064] First bias current source 206a and second bias current source 206b, and first transistor T1 and second transistor T2:

[0065] The first bias current source 206a can generate a first bias current IB1 at its first terminal, and the second bias current source 206b can generate a second bias current IB2 at its first terminal. The first transistor T1 can receive a first input signal IS1 at the first input control terminal via the first node N1 and receive the first bias current IB1 at the first current supply terminal, and generate a first output signal OS1 at the first output control terminal. Similarly, the second transistor T2 can receive a second input signal IS2 at the second input control terminal via the second node N2 and receive the second bias current IB2 at the second current supply terminal, and generate a second output signal OS2 at the second output control terminal. It will be apparent to those skilled in the art that the first transistor T1, the second transistor T2, and the first bias current source 206a and the second bias current source 206b are connected in conjunction with… Figure 2 It works in a similar way to the method described in [the text].

[0066] Control circuit 104:

[0067] Control circuit 104 can receive a first output signal OS1 and a second output signal OS2 from the first transistor T1 and the second transistor T2 of differential circuit 202, and generate a first set of control signals CS1-CS4, a first set of tuning signals TS1 and TS2, and a first set of adjustment signals RS1 and RS2 based on the first output signal OS1 and the second output signal OS2. In one embodiment, the common-mode voltage of the first output signal OS1 and the second output signal OS2 may be less than a predefined value (e.g., an expected value for the operation of differential circuit 202), and therefore may require correction. The common-mode voltage may correspond to the average of the amplitudes of the first output signal OS1 and the second output signal OS2. When the common-mode voltage may be less than the predefined value, control circuit 104 can correct the common-mode voltage. After correcting the common-mode voltage, the first calibration current IC1 and the second calibration current IC2 can be redirected to calibrate the offset between the first output signal OS1 and the second output signal OS2.

[0068] Fifth switch S5 and sixth switch S6:

[0069] The fifth switch S5 may include a first terminal coupled to the second resistor R2, a second terminal coupled to the power supply 106 to receive the power supply voltage VDD, and a control terminal coupled to the correction circuit 302. The fifth switch S5 may receive a first correction signal CO1 at the control terminal to correct the amplitude of the first output signal OS1. Similarly, the sixth switch S6 may include a first terminal coupled to the third resistor R3, a second terminal coupled to the power supply 106 to receive the power supply voltage VDD, and a control terminal coupled to the correction circuit 302. The sixth switch S6 may receive a second correction signal CO2 at the control terminal to correct the amplitude of the second output signal OS2.

[0070] Correction circuit 302:

[0071] The correction circuit 302 can be coupled to the differential circuit 202 and the control circuit 104. The correction circuit 302 can receive a first adjustment signal RS1 and generate a first correction signal CO1 and a second correction signal CO2 based on the first adjustment signal RS1. In one embodiment, the correction circuit 302 can provide the first correction signal CO1 and the second correction signal CO2 at the control terminals of the fifth switch S5 and the sixth switch S6 of the differential circuit 202 to correct the amplitudes of the first output signal OS1 and the second output signal OS2, respectively. The amplitudes of the first output signal OS1 and the second output signal OS2 can be corrected by pulling up the first output signal OS1 and the second output signal OS2 based on the first correction signal CO1 and the second correction signal CO2. In one example, the first output signal OS1 and the second output signal OS2 correspond to a first output voltage and a second output voltage, which can be pulled up to the desired amplitudes of the first output signal OS1 and the second output signal OS2. The amplitudes of the first output signal OS1 and the second output signal OS2 can be corrected to obtain a common-mode voltage greater than or equal to a predefined value. In one example, the predefined value could be 65% of VDD, such that the residual common-mode signal can be greater than 65% of the operating supply voltage (e.g., VDD), thereby placing the input differential pair (e.g., the first input signal IS1 and the second input signal IS2) in the saturation region of the first transistor and the second transistor (T1 and T2). In one embodiment, the correction circuit 302 may include a first digital-to-analog converter (DAC) 304 and a second DAC 306.

[0072] First DAC 304 and second DAC 306:

[0073] The first DAC 304 can be coupled to the fifth switch S5 of the differential circuit 202 and the control circuit 104. The first DAC 304 can receive the first adjustment signal RS1 and generate a first correction signal CO1 based on the first adjustment signal RS1. In addition, the first DAC 304 can provide the first correction signal CO1 to the fifth switch S5 to activate the fifth switch S5, and correct the first output signal OS1 by pulling up the first output signal OS1.

[0074] Similarly, the second DAC 306 can be coupled to the sixth switch S6 of the differential circuit 202 and the control circuit 104. The second DAC 306 can receive the first adjustment signal RS1 and generate a second correction signal CO2 based on the first adjustment signal RS1. Furthermore, the second DAC 306 can provide the second correction signal CO2 to the sixth switch S6 to activate the sixth switch S6, and correct the second output signal OS2 by pulling it up. When the first output signal OS1 and the second output signal OS2 can be corrected by pulling up the amplitude of the first output signal OS1 and the second output signal OS2, the common-mode voltage can be corrected to be equal to or greater than a predefined value.

[0075] In operation, the amount by which the amplitudes of the first output signal OS1 and the second output signal OS2 can be pulled up can be based on the amplitudes of the voltages of the first correction signal CO1 and the second correction signal CO2. Control circuit 104 can provide a first adjustment signal RS1 to the first DAC 304 and the second DAC 306. The first adjustment signal RS1 can control the amplitudes of the first correction signal CO1 and the second correction signal CO2. Control circuit 104 can monitor the first output signal OS1, the second output signal OS2, and the common-mode voltage to determine whether the common-mode voltage is equal to or less than a predefined value at the current amplitudes of the first correction signal CO1 and the second correction signal CO2. If the common-mode voltage is less than the predefined value at the current amplitudes of the first correction signal CO1 and the second correction signal CO2, control circuit 104 can adjust the amplitude of the first adjustment signal RS1 by a second value. In one embodiment, the first adjustment signal can be a multi-bit digital signal. The second value can be a predetermined value. Furthermore, the first adjustment signal RS1 can be adjusted to increase the amplitudes of the first correction signal CO1 and the second correction signal CO2 until the common-mode voltage is equal to or greater than the predefined value. In one embodiment, control circuit 104 can determine the second value. Therefore, the first adjustment signal RS1 can be iteratively adjusted to the second value, thereby pulling up the first output signal OS1 and the second output signal OS2 and correcting the common-mode voltage.

[0076] In one embodiment, switches S5 and S6 can be implemented using NMOS transistors or PMOS transistors, such that the first correction signal CO1 and the second correction signal CO2 can respectively control the resistance values ​​of the NMOS transistors or PMOS transistors corresponding to switches S5 and S6 to correct the common-mode voltage.

[0077] When correcting the common-mode voltage, for example, when the common-mode voltage is equal to or greater than a predefined value, the offset calibration circuit 204 can be activated to perform offset calibration of the differential circuit 202. It will be apparent to those skilled in the art that the offset calibration circuit 204 can be implemented to... Figure 2The offset between the first output signal OS1 and the second output signal OS2 is calibrated in a manner similar to that described in the text.

[0078] The second resistor R2 can be coupled between the first output control terminal and the fifth switch S5. Similarly, the third resistor R3 can be coupled between the second output control terminal and the sixth switch S6. In one embodiment, the second resistor R2 and the third resistor R3 can correspond to load resistors implemented to regulate the current in the differential circuit 202.

[0079] It will be apparent to those skilled in the art that the remaining differential circuits 102b-102n can be structurally and functionally similar to... Figure 3 The first differential circuit 102a, and can be used with Figure 2 and 3 The common-mode voltage of the corresponding differential output is corrected and the offset between the differential outputs generated by the corresponding circuits is calibrated in a manner similar to that described in the paper. Therefore, each of the first to Nth differential circuits 102b-102n can correct the corresponding common-mode voltage and calibrate the offset, thereby calibrating the total offset of the multi-stage differential circuit.

[0080] Figure 4 An embodiment according to this disclosure is shown. Figure 1 A schematic circuit diagram of the control circuit 104 of circuit 100. The control circuit 104 may include multiple common-mode generators 402a-402n, a first plurality of comparators 404a-404n, logic circuit 406, multiple switches S7-Sn, a second plurality of comparators 408a-408n, and multiple DACs 410a-410n.

[0081] Multiple common mode generators 402a-402n:

[0082] Multiple common-mode generators 402a-402n may include first to Nth generators 402a-402n. The first common-mode generator 402a may be coupled to the differential circuit 202 of the first differential circuit 102a to receive a first output signal OS1 and a second output signal OS2, and generate a first common-mode signal CMS1. Those skilled in the art will understand that the second to nth common-mode generators 402b-402n may be coupled to corresponding differential circuits to receive corresponding differential outputs, and generate second to nth common-mode signals CMS2-CMSN in a manner similar to that used to generate the first common-mode signal CMS1.

[0083] The first multiple comparators 404a-404n:

[0084] The first plurality of comparators 404a-404n may include first to Nth comparators 404a-404n. The first comparator 404a may be coupled to a first common-mode generator 402a and logic circuit 406. The first comparator 404a may compare a first common-mode signal CMS1 with a predefined value to generate a first comparison signal CP1. In one embodiment, the comparison of the first common-mode signal CMS1 with the predefined value may refer to a comparison of the voltage level of the first common-mode signal CMS1 with the predefined value. A first adjustment signal RS1 may be generated based on the first comparison signal CP1. Those skilled in the art will understand that the second to nth comparators 404b-404n may compare second to nth common-mode signals CMS2-CMSN with predefined values ​​to generate second to nth comparison signals CP2-CPN in a manner similar to comparing the first common-mode signal CMS1 with the predefined value.

[0085] Logic Circuit 406:

[0086] Logic circuit 406 can receive a first comparison signal CP1 and a predefined value, and increase the amplitude of the first adjustment signal RS1 until the common-mode voltage associated with the first common-mode signal CMS1 is greater than or equal to the predefined value. Those skilled in the art will understand that the second to nth comparators 404b-404n can compare their respective common-mode signals with the predefined values ​​and provide the second to Nth comparison signals CP2-CPN to logic circuit 406 for generating the second to Nth adjustment signals RS2-RSN in a manner similar to that used to generate the first adjustment signal RS1. Logic circuit 406 can provide the first to Nth adjustment signals RS1-RSN to the corresponding differential circuits in the first to Nth differential circuits 102a-102n.

[0087] Multiple switches S7-Sn:

[0088] Multiple switches S7-Sn can be coupled to first to Nth differential circuits 102a-102n, first multiple comparators 404a-404n, and second multiple comparators 408a-408n. Each of the multiple switches S7-Sn can receive a corresponding comparison signal from the first to Nth comparison signals CP1-CPN and a corresponding differential output, and can provide the differential output to the corresponding comparator in the second multiple comparators 408a-408n when the corresponding comparison signal indicates that the corresponding common-mode signal is greater than or equal to a predefined value. For example, the seventh switch S7 of the multiple switches S7-Sn can receive a first output signal OS1 and a second output signal OS2, as well as a first comparison signal CP1. When the first comparison signal CP1 indicates that the first common-mode signal CMS1 is greater than or equal to a predefined value, the seventh switch S7 can provide the first output signal OS1 and the second output signal OS2 to the first comparator 408a.

[0089] Second multiple comparators 408a-408n:

[0090] The second plurality of comparators 408a-408n may include first to Nth comparators 404a-404n. The first comparator 408n in the second plurality of comparators 408a-408n may be coupled to the differential circuit 202 via a seventh switch S7. The first comparator 408n in the second plurality of comparators 408a-408n may receive a first output signal OS1 and a second output signal OS2, and compare the first output signal OS1 and the second output signal OS2. The output of the comparison of the first output signal OS1 and the second output signal OS2 may be provided to logic circuit 406. Logic circuit 406 may generate a first set of control signals CS1-CS4 based on the output received from the first comparator 408a. In one embodiment, when the first output signal OS1 is less than the second output signal OS2, the first control signal CS1 and the second control signal CS2 may be asserted, and the assertions of the third control signal CS3 and the fourth control signal CS4 may be cancelled to calibrate the offset between the first output signal OS1 and the second output signal OS2. Furthermore, when the first output signal OS1 is greater than the second output signal OS2, the assertions of the first control signal CS1 and the second control signal CS2 can be cancelled, and the assertions of the third control signal CS3 and the fourth control signal CS4 can be made to calibrate the offset between the first output signal OS1 and the second output signal OS2.

[0091] Multiple DACs 410a-410n:

[0092] The plurality of DACs 410a-410n may include a third to an Nth DAC 410a-410n. The third DAC 410a may be coupled to a first comparator 408n and an offset calibration circuit 204 in the second plurality of comparators 408a-408n. The third DAC 410a may generate a first tuning signal TS1 and a second tuning signal TS2 based on a first output signal OS1 and a second output signal OS2 to control the generation of a first calibration current IC1 and a second calibration current IC2. Those skilled in the art will understand that the remaining DACs in the plurality of DACs 410a-410n may generate corresponding tuning signals TS3-TS(2N) in a manner similar to that used to generate the first tuning signal TS1 and the second tuning signal TS2.

[0093] Logic circuit 406 can control the scan operation of each of the plurality of DACs 410a-410n based on the corresponding differential output signals. For example, logic circuit 406 can control the scan operation of the third DAC 410a based on the first output signal OS1 and the second output signal OS2 to iteratively increase the amplitude of the first tuning signal TS1 and the second tuning signal TS2.

[0094] Figure 5A and 5B Together, flowchart 500 illustrates an embodiment of the present disclosure for use by... Figure 1 The method of offset calibration is performed by circuit 100. The method can be implemented by each of the first to Nth differential circuits 102a-102n to calibrate the offset in the corresponding differential output signal. In the current embodiment, the method is implemented by the first differential circuit 102a to calibrate the offset between the first output signal OS1 and the second output signal OS2.

[0095] At 502, the differential circuit 202 can receive a first input signal IS1 and a second input signal IS2. At 504, the differential circuit 202 can generate a first output signal OS1 and a second output signal OS2 based on the first input signal IS1 and the second input signal IS2.

[0096] At 506, the control circuit 104 can generate a first common-mode signal CMS1 based on the first output signal OS1 and the second output signal OS2. At 508, the control circuit 104 can compare the first common-mode signal CMS1 with a predefined value.

[0097] At step 510, control circuit 104 can determine whether the amplitude of the first common-mode signal CMS1 is greater than a predefined value. If at step 510, control circuit 104 determines that the amplitude of the first common-mode signal CMS1 is less than the predefined value, then step 512 is executed. At step 512, control circuit 104 can adjust the first adjustment signal RS1 to correct the amplitudes of the first output signal OS1 and the second output signal OS2. After step 512, step 510 is executed again. Therefore, step 510 is executed until the first common-mode signal CMS1 is greater than or equal to the predefined value. If at step 510, control circuit 104 determines that the amplitude of the first common-mode signal CMS1 is greater than or equal to the predefined value, then control circuit 104 can fix the amplitude of the first adjustment signal RS1, and step 516 can be executed.

[0098] At 516, control circuit 104 can compare the first output signal OS1 and the second output signal OS2, and determine whether the voltage amplitude of the first output signal OS1 is less than the voltage amplitude of the second output signal OS2. If at 516, control circuit 104 determines that the amplitude of the first output signal OS1 is less than the amplitude of the second output signal OS2, then proceed to 518. At 518, control circuit 104 can assert the first control signal CS1 and the second control signal CS2 to provide a first calibration current IC1 at the first node N1 to pull up the first output signal OS1, and to provide a second calibration current IC2 at the second node N2 to pull down the second output signal OS2.

[0099] If at step 516, control circuit 104 determines that the amplitude of the first output signal OS1 is greater than the amplitude of the second output signal OS2, then step 520 is executed. At step 520, control circuit 104 can assert a third control signal CS3 and a fourth control signal CS4 to provide a first calibration current IC1 at the second node N2 to pull up the second output signal OS2, and to provide a second calibration current IC2 at the first node N1 to pull down the first output signal OS1. After steps 518 and 520, step 522 can be executed.

[0100] At 522, control circuit 104 can determine whether the offset between the first output signal OS1 and the second output signal OS2 has been calibrated. If at 522, control circuit 104 determines that the offset between the first output signal OS1 and the second output signal OS2 has not been calibrated, then 524 is executed. At 524, control circuit 104 can adjust the first tuning signal TS1 and the second tuning signal TS2 to increase the amplitude of the first calibration current IC1 and the second calibration current IC2 to calibrate the offset. If at 522, control circuit 104 determines that the offset between the first output signal OS1 and the second output signal OS2 has been calibrated, then the amplitudes of the first tuning signal TS1 and the second tuning signal TS2 can be fixed by control circuit 104, and thus the offset between the first output signal OS1 and the second output signal OS2 can be calibrated.

[0101] Each of the first to Nth differential circuits 102a-102n can implement a method for calibrating the corresponding offset of the corresponding differential output signal, thereby calibrating the total offset of the multi-stage differential circuit.

[0102] Therefore, by selectively redirecting the calibration currents (e.g., calibration currents IC1 and IC2) based on the set of control signals (e.g., first to fourth control signals CS1-CS4), the offset calibration circuit 204 can provide calibration currents (e.g., first calibration current IC1 and second calibration current IC2) at the current supply terminal of the differential circuit 202 instead of at the output control terminal, overcoming the challenges of conventional techniques. In this way, a set of electrical parameters of the differential circuit 202 can be unaffected by the offset calibration circuit 204. This set of electrical parameters may include at least one of the following: 3 dB bandwidth, 1 dB compression (linearity) when the supply is high or low, and a continuous-time linear equalizer (CTLE) boost at the final output of the multi-stage differential circuit 102 at the Nyquist frequency. The set of electrical parameters may further include the DC gain variation after offset calibration at each differential stage of the multi-stage differential circuit 102. Therefore, the disclosed circuit 100 facilitates real-time offset calibration, thereby enhancing the accuracy and reliability of differential signal processing under varying operating conditions.

[0103] Furthermore, since the offset calibration circuit 204 is coupled to the source side of the differential circuit 202, for example, coupled to the source terminals of the first transistor T1 and the second transistor T2, and because the offset calibration circuit 204 is simpler and includes fewer components than a conventional offset calibration circuit, no additional parasitic capacitance is introduced at the differential output of the differential circuit 202. Thus, the bandwidth (e.g., 3 dB bandwidth) and the aforementioned set of electrical parameters of the output signal (e.g., CTLE boost and DC gain variations) remain unaffected.

[0104] While various embodiments of this disclosure have been shown and described, it will be clear that this disclosure is not limited to these embodiments. Many modifications, alterations, variations, substitutions, and equivalents will be apparent to those skilled in the art without departing from the spirit and scope of this disclosure as set forth in the claims. Furthermore, unless otherwise stated, terms such as 'first' and 'second' are used to arbitrarily distinguish the elements described by these terms. Therefore, these terms are not necessarily intended to indicate the time or other priority of these elements. The term "coupling" can refer to at least one of direct or indirect coupling, not necessarily by mechanical or any physical means. Furthermore, a system or method that "comprises," "has," or "includes" one or more elements has, but is not limited to, having only, these one or more elements.

Claims

1. A circuit, characterized in that, include: Differential circuit, the differential circuit comprising: First node and second node; A first input control terminal and a second input control terminal are used to receive a first input signal and a second input signal, respectively; and A first output control terminal and a second output control terminal are configured to generate a first output signal and a second output signal at the first output control terminal and the second output control terminal, respectively, based on the first input signal and the second input signal; and A calibration circuit, coupled to the differential circuit, wherein the calibration circuit includes: The first calibration current source and the second calibration current source are used to generate the first calibration current and the second calibration current, respectively. Multiple control inputs are used to receive a set of control signals to control the direction of the first calibration current and the second calibration current; and Multiple control outputs are provided for (i) providing a first calibration current and a second calibration current at the first node and the second node, respectively, and (ii) providing a second calibration current and a first calibration current at the first node and the second node, respectively, thereby calibrating the offset between the first output signal and the second output signal.

2. The circuit according to claim 1, characterized in that, The differential circuit includes: A first transistor, comprising a first input control terminal, a first current supply terminal coupled to the first node, and a first output control terminal; and The second transistor includes a second input control terminal, a second current supply terminal coupled to the second node, and a second output control terminal.

3. The circuit according to claim 1, characterized in that, The calibration circuit further includes: A first switch, coupled to the first calibration current source and the first node, wherein the first switch comprises: The first terminal is used to receive the first control signal from the set of control signals; and The second terminal is used to provide the first calibration current at the first node based on the first control signal to pull up the first output signal; and A second switch, coupled to the second calibration current source and the second node, wherein the second switch comprises: The first terminal is used to receive the second control signal from the set of control signals; and The second terminal is used to provide the second calibration current at the second node based on the second control signal to pull down the second output signal.

4. The circuit according to claim 1, characterized in that, In addition, including: A control circuit, coupled to the differential circuit and the calibration circuit, wherein the control circuit: A first tuning signal and a second tuning signal are generated based on the first output signal and the second output signal; The first tuning signal and the second tuning signal are respectively provided to the first calibration current source and the second calibration current source; as well as The first tuning signal and the second tuning signal are adjusted to increase the amplitude of the first calibration current and the second calibration current, respectively, thereby calibrating the offset between the first output signal and the second output signal.

5. The circuit according to claim 1, characterized in that, In addition, including: A correction circuit, coupled to the differential circuit, wherein the correction circuit: Receive adjustment signals; A first correction signal and a second correction signal are generated based on the adjustment signal; and The first correction signal and the second correction signal are provided to the differential circuit to correct the amplitudes of the first output signal and the second output signal, respectively, wherein the amplitudes of the first output signal and the second output signal are corrected to obtain a common-mode signal greater than or equal to a predefined value.

6. The circuit according to claim 5, characterized in that, The common-mode signal corresponds to the average of the amplitudes of the first output signal and the second output signal, and wherein the first calibration current and the second calibration current are redirected when the common-mode signal is greater than or equal to the predefined value.

7. The circuit according to claim 5, characterized in that, The correction circuit includes: A first digital-to-analog converter (DAC) is coupled to the differential circuit, wherein the first DAC: Receive the adjustment signal; The first correction signal is generated based on the adjustment signal; and The first correction signal is provided to the differential circuit; and A second DAC is coupled to the differential circuit, wherein the second DAC: Receive the adjustment signal; The second correction signal is generated based on the adjustment signal; and The second correction signal is provided to the differential circuit.

8. The circuit according to claim 5, characterized in that, In addition, including: Control circuit, used for: The adjustment signal is generated based on the common-mode signal; and The adjustment signal is adjusted to a predetermined value until the common-mode signal is greater than or equal to the predefined value.

9. A circuit, characterized in that, Includes a plurality of differential circuits, each according to claim 1.

10. A circuit, characterized in that, include: Differential circuit, the differential circuit comprising: First node and second node; A first input control terminal and a second input control terminal are used to receive a first input signal and a second input signal, respectively; and A first output control terminal and a second output control terminal are configured to generate a first output signal and a second output signal at the first output control terminal and the second output control terminal, respectively, based on the first input signal and the second input signal; and Offset calibration circuit, coupled to the differential circuit, wherein the offset calibration circuit includes: A first calibration current source and a second calibration current source are used to generate a first calibration current and a second calibration current. Multiple control inputs are used to receive a set of control signals; and Multiple control outputs are provided for performing one of the following based on the set of control signals: (i) providing the first calibration current and the second calibration current at the first node and the second node, respectively, and (ii) providing the second calibration current and the first calibration current at the first node and the second node, respectively.

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