A variable gain amplifier and AGC circuit conversion circuit

Abstract

The present application belongs to the field of integrated circuit, and particularly relates to a variable gain amplifier and AGC circuit conversion circuit, comprising a variable gain amplifier, a switching device and a detector circuit; the output end of the detector circuit is connected with the gain control end of the variable gain amplifier through the switching device; wherein, when the switching device is in the on state, the voltage V DETO output by the detector circuit is fed back to the gain control end, forming an AGC feedback loop; when the switching device is in the off state, the voltage V DETO output by the detector circuit is not fed back to the gain control end, and the variable gain amplifier is in the open loop working state; the present application effectively solves the problem that the parallel gating of the VGA and the AGC circuit in the signal conditioning complex system is difficult to realize.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuits, and specifically relates to a variable gain amplifier and AGC circuit conversion circuit. Background Technology

[0002] A linear variable gain amplifier (VGA) is an amplifier whose gain (dB) is linearly related to the gain control voltage (V). Its core function is to adjust the gain in real time by regulating the gain control voltage, thereby maintaining the stability of the signal amplitude under different operating conditions. It is widely used in automatic gain control (AGC) loops. An AGC loop typically consists of a variable gain amplifier (VGA), a detector, a low-pass filter, and an error comparator. Based on the loop structure, it can be divided into feedback AGC loops and feedforward AGC loops. Feedback AGC loops detect the circuit's output signal, while feedforward AGC loops detect the input signal, as shown below. Figure 1 and Figure 2 As shown. V in For the input signal, V out For the output signal, V REF This is the reference voltage. Figure 1 In the feedback AGC loop shown, the detector detects the amplitude of the output signal, and after filtering by a low-pass filter, the average value is obtained. This value is related to V. REF The comparison produces a gain control voltage V. C Used to adjust the gain of the VGA. When the two input signals of the error comparator are equal, the entire circuit reaches a steady state, and the output signal remains unchanged. Meanwhile... Figure 2 In the feedforward AGC loop shown, the detector detects the amplitude of the input signal and generates a gain control voltage V through an error comparator. C This allows for adjustment of the VGA gain to stabilize the output signal. Both types of AGC loops have their advantages and disadvantages. Feedback AGC loops, due to the introduction of a feedback mechanism, improve circuit linearity, but when the input signal changes significantly, deep negative feedback may affect the stability of the entire circuit. Feedforward AGC loops, on the other hand, have no feedback loop, eliminating the need to consider circuit stability issues. They can handle significantly changing signals without altering the circuit's settling time, but their requirements for high linearity and high dynamic range increase design complexity. Therefore, in practical applications, feedback AGC loops are more common.

[0003] Currently, most feedback-based AGC loops are implemented using discrete components, and can be considered as a type of circuit board with AGC functionality. These circuit boards are relatively large, temperature-sensitive, require high component matching, have low manufacturing yields, and relatively large errors. Only a few monolithic integrated circuits can implement AGC functionality, but these are mostly application-specific integrated circuits (ASICs), capable of performing only a single AGC function on the integrated circuit board. In systems with complex signal conditioning, the output signal may be an amplified value of the input signal at one stage, while needing to stabilize at a specific value in the next stage. In this case, VGA and AGC circuits usually need to be used in parallel, relying on precise digital signal control for their conduction. However, this implementation method may result in signal overlap during the switching between VGA and AGC circuits due to the time delay, requiring additional components for processing, making implementation difficult; furthermore, it requires a larger area on the integrated circuit board to solder the VGA and AGC components, further increasing the cost of the circuit board.

[0004] In summary, in complex signal conditioning systems, using parallel VGA and AGC circuits for gating is not only complex to implement, but also requires a large area of ​​integrated circuit board and has a high cost. Summary of the Invention

[0005] To address the aforementioned problems, this invention provides a variable gain amplifier to AGC circuit conversion circuit, comprising a variable gain amplifier, a switching device, and a detector circuit; the output terminal of the detector circuit is connected to the gain control terminal of the variable gain amplifier via the switching device; wherein, when the switching device is in the ON state, the voltage V output by the detector circuit is... DETO Feedback is sent to the gain control terminal, forming an AGC feedback loop; when the switching device is in the off state, the voltage V output by the detector circuit... DETO Without feedback to the gain control terminal, the variable gain amplifier operates in an open-loop state.

[0006] Furthermore, the variable gain amplifier, switching devices, and detector circuitry are integrated within the same chip.

[0007] Furthermore, the detector circuit includes resistors R1~R10, capacitors C1~C4, diodes D1~D2, PNP transistors Q1~Q14, NPN transistors Q15~Q17, PNP transistor Q18, NPN transistor Q19, PNP transistor Q20, and current sources A1~A6; the connections of each component are as follows:

[0008] The upper end of resistor R1 serves as the detector input terminal, used to receive the input signal V. IN +vin; The lower end of resistor R1 is connected to the upper end of resistor R2 and the upper end of capacitor C1. The voltage at this connection point is denoted as V. CM+2△vin; The lower end of resistor R2 is connected to the lower end of capacitor C1, the upper end of resistor R3, and the upper end of capacitor C2. The voltage at this connection point is denoted as V. CM +△vin; The lower end of resistor R3 is connected to the lower end of capacitor C2, the upper end of resistor R4, and the upper end of resistor R5. The voltage at this connection point is denoted as V. CM The lower end of resistor R5 is connected to the upper end of resistor R6, and the voltage at this connection point is denoted as V. CM -△V; The lower end of resistor R4 is connected to the lower end of resistor R6 and the input terminal of current source A1. The voltage at this connection point is denoted as V. CM -2ΔV; The output terminal of the current source is grounded;

[0009] The emitters of PNP transistors Q1-Q3 are connected to the output terminal of current source A3; the emitters of PNP transistors Q4-Q6 are connected to the output terminal of current source A4; the emitters of PNP transistors Q7-Q9 are connected to the output terminal of current source A5; and the emitters of PNP transistors Q10-Q12 are connected to the output terminal of current source A6. The collectors of PNP transistors Q1-Q2, Q6-Q7, and Q10-Q11 are connected to the upper end of resistor R9; the collectors of PNP transistors Q3-Q5, Q8-Q9, and Q12 are connected to the upper end of resistor R10; and the bases of PNP transistors Q1, Q5, Q9, and Q11 are connected to the voltage V. CM The base connection voltage V of PNP transistors Q2 and Q10 CM -2ΔV; Base connection voltage V of PNP transistors Q3 and Q12 CM -△V; Base connection voltage V of PNP transistors Q4 and Q8 CM +2△vin; Base connection voltage V of PNP transistors Q6 and Q7 CM +△vin; The lower end of resistor R9 is connected to the upper end of resistor R8, the base of PNP transistor Q13, the collector of NPN transistor Q17, the emitter of PNP transistor Q18, the positive terminal of diode D1, and the negative terminal of diode D2; The lower end of resistor R10 is connected to the collector of NPN transistor Q19, the emitter of PNP transistor Q20, the upper end of capacitor C4, the negative terminal of diode D1, and the positive terminal of diode D2. This connection point serves as the output terminal of the detector, with an output voltage V. DETO The emitter of PNP transistor Q13 is connected to the output terminal of current source A2 and the upper end of resistor R7. The collector of PNP transistor Q13 is connected to the collector of NPN transistor Q15, the base of NPN transistor Q15, and the base of NPN transistor Q16. The emitter of PNP transistor Q14 is connected to the lower end of resistor R7, and the base of PNP transistor Q14 is connected to voltage V. DETOThe collector of PNP transistor Q14 is connected to the collector of NPN transistor Q16, the lower end of capacitor C3, the base of NPN transistor Q17, and the base of NPN transistor Q19; the emitters of NPN transistors Q15~Q17 are grounded; the base of PNP transistor Q18 is connected to the base of PNP transistor Q20 and voltage V. BIAS The collector of PNP transistor Q18 is grounded; the emitter of NPN transistor Q19 is grounded; the collector of PNP transistor Q20 is grounded; the lower end of capacitor C4 is grounded; the input terminals of current sources A2~A6 are connected to power supply VCC; and the lower end of resistor R8 is connected to the upper end of capacitor C3.

[0010] Among them, V IN Input signal V IN +vin is the DC component, where vin is the input signal V. IN +vin's small-signal component of the AC signal, V CM Here, a fixed DC voltage is preset, ΔV is the voltage drop, and Δvin is the voltage change. Furthermore, resistors R2, R3, R5, and R6 have the same resistance value; ΔV is the current I output from current source A1. REF The current flows through resistors R4, R5, and R6, and their relationship satisfies:

[0011] .

[0012] Furthermore, the current outputs of current sources A3 and A4 are equal; the current outputs of current sources A2, A5~A6 are 4 times that of current source A3.

[0013] Furthermore, △vin satisfies △vin = [R3 / (R1+R2+R3)]·vin.

[0014] Furthermore, the output voltage of the variable gain amplifier has a negative slope relationship with the gain control voltage.

[0015] The beneficial effects of this invention are:

[0016] This invention integrates the detector circuit into the VGA, enabling switching between VGA and AGC functions. This effectively solves the problem of difficulty in parallel selection of VGA and AGC circuits in complex signal conditioning systems. This solution significantly saves integrated circuit board area, achieving two functions within the same area, thereby greatly reducing costs.

[0017] Furthermore, the detector circuit proposed in this invention is highly versatile and does not impose many restrictions on VGA circuit design. It can achieve AGC function by making only slight modifications to most existing VGA circuits.

[0018] This circuit is implemented using a bipolar process, which can effectively verify the feasibility of the design and provide guidance for further improvements in advanced processes. Attached Figure Description

[0019] Figure 1 This is a feedback-based AGC loop diagram;

[0020] Figure 2 This is a loop diagram for a feedforward AGC system.

[0021] Figure 3 This is a schematic diagram of a variable gain amplifier and AGC circuit conversion circuit according to the present invention. Detailed Implementation

[0022] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0023] To overcome the problems of complex implementation, large footprint, and high cost when parallel selection of VGA and AGC circuits is used in complex signal conditioning systems, this invention proposes a variable gain amplifier to AGC circuit conversion circuit. This circuit integrates the detector circuit and the variable gain amplifier into a single chip, and controls whether the detector output is fed back to the VGA gain control terminal through an internally integrated switch, thereby realizing the switching between VGA mode and AGC mode of the integrated chip. Using this solution, only a single integrated chip is needed to replace the traditional parallel selection scheme of VGA and AGC circuits, which is simpler to operate, requires less integration area, and is also less expensive.

[0024] Please see Figure 3 The detector circuit proposed in this embodiment of the invention includes resistors R1~R10, capacitors C1~C4, diodes D1~D2, PNP transistors Q1~Q14, NPN transistors Q15~Q17, PNP transistor Q18, NPN transistor Q19, PNP transistor Q20, and current sources A1~A6; the connections of each component are as follows:

[0025] The upper end of resistor R1 serves as the detector input terminal, used to receive the input signal V. IN +vin; The lower end of resistor R1 is connected to the upper end of resistor R2 and the upper end of capacitor C1. The voltage at this connection point is denoted as V. CM +2△vin; The lower end of resistor R2 is connected to the lower end of capacitor C1, the upper end of resistor R3, and the upper end of capacitor C2. The voltage at this connection point is denoted as V. CM +△vin; The lower end of resistor R3 is connected to the lower end of capacitor C2, the upper end of resistor R4, and the upper end of resistor R5. The voltage at this connection point is denoted as V. CMThe lower end of resistor R5 is connected to the upper end of resistor R6, and the voltage at this connection point is denoted as V. CM -△V; The lower end of resistor R4 is connected to the lower end of resistor R6 and the input terminal of current source A1. The voltage at this connection point is denoted as V. CM -2ΔV; The output terminal of the current source is grounded;

[0026] The emitters of PNP transistors Q1-Q3 are connected to the output terminal of current source A3; the emitters of PNP transistors Q4-Q6 are connected to the output terminal of current source A4; the emitters of PNP transistors Q7-Q9 are connected to the output terminal of current source A5; and the emitters of PNP transistors Q10-Q12 are connected to the output terminal of current source A6. The collectors of PNP transistors Q1-Q2, Q6-Q7, and Q10-Q11 are connected to the upper end of resistor R9; the collectors of PNP transistors Q3-Q5, Q8-Q9, and Q12 are connected to the upper end of resistor R10; and the bases of PNP transistors Q1, Q5, Q9, and Q11 are connected to the voltage V. CM The base connection voltage V of PNP transistors Q2 and Q10 CM -2ΔV; Base connection voltage V of PNP transistors Q3 and Q12 CM -△V; Base connection voltage V of PNP transistors Q4 and Q8 CM +2△vin; Base connection voltage V of PNP transistors Q6 and Q7 CM +△vin; The lower end of resistor R9 is connected to the upper end of resistor R8, the base of PNP transistor Q13, the collector of NPN transistor Q17, the emitter of PNP transistor Q18, the positive terminal of diode D1, and the negative terminal of diode D2; The lower end of resistor R10 is connected to the collector of NPN transistor Q19, the emitter of PNP transistor Q20, the upper end of capacitor C4, the negative terminal of diode D1, and the positive terminal of diode D2. This connection point serves as the output terminal of the detector, with an output voltage V. DETO The emitter of PNP transistor Q13 is connected to the output terminal of current source A2 and the upper end of resistor R7. The collector of PNP transistor Q13 is connected to the collector of NPN transistor Q15, the base of NPN transistor Q15, and the base of NPN transistor Q16. The emitter of PNP transistor Q14 is connected to the lower end of resistor R7, and the base of PNP transistor Q14 is connected to voltage V. DETO The collector of PNP transistor Q14 is connected to the collector of NPN transistor Q16, the lower end of capacitor C3, the base of NPN transistor Q17, and the base of NPN transistor Q19; the emitters of NPN transistors Q15~Q17 are grounded; the base of PNP transistor Q18 is connected to the base of PNP transistor Q20 and voltage V. BIAS The collector of PNP transistor Q18 is grounded; the emitter of NPN transistor Q19 is grounded; the collector of PNP transistor Q20 is grounded; the lower end of capacitor C4 is grounded; the input terminals of current sources A2~A6 are connected to power supply VCC; and the lower end of resistor R8 is connected to the upper end of capacitor C3.

[0027] Among them, V IN Input signal V IN +vin is the DC component, where vin is the input signal V. IN +vin's small-signal component of the AC signal, V CM Here, ΔV is the preset fixed DC voltage, ΔV is the voltage drop, and Δvin is the voltage change.

[0028] The working principle of the detector circuit proposed in this invention is as follows:

[0029] First, set the VGA output voltage and gain control voltage to have a negative slope relationship, meaning the output voltage decreases as the gain control voltage increases. Second, set R1~R... 10 These represent the resistance values ​​of resistors R1 through R10. The circuit parameters are set as follows: VCC = 5V, R2 = R3 = R5 = R6, A1 is a DC current source with an output current of I. REF The current output by current sources A3 and A4 is I, and the current output by current sources A2, A5~A6 is 4I. At this time, the voltage drop ΔV generated by resistors R4, R5, and R6 is:

[0030]

[0031] The differential current generated by ΔV is expressed as I. CQ1 +I CQ2 -I CQ3 Or I CQ10 +I CQ11 -I CQ12 ,but:

[0032]

[0033] Among them, I CQ1 I CQ2 I CQ3 I CQ10 I CQ11 I CQ12 V represents the collector current of Q1, Q2, Q3, Q10, Q11, and Q12, respectively. BEQ1 V BEQ2 V BEQ3 These represent the base-emitter voltages of Q1, Q2, and Q3, respectively.

[0034] Combine I CQ1 +I CQ2 +I CQ3 =I yields:

[0035]

[0036]

[0037] n is defined as the ratio of the emitter area of ​​Q3 to the emitter area of ​​Q1, where Q1 and Q2 have the same emitter area; m is defined as the ratio of the emitter area of ​​Q12 to the emitter area of ​​Q10, where Q10 and Q11 have the same emitter area. V T The thermal voltage, a physical constant, shows that the hyperbolic cosine function *cosh* increases monotonically in the first quadrant, indicating that the differential current in the detector increases accordingly. Similarly:

[0038]

[0039]

[0040] Among them, I CQ4 I CQ5 I CQ6 I CQ7 I CQ8 I CQ9 These represent the collector currents of Q4, Q5, Q6, Q7, Q8, and Q9, respectively.

[0041] If the differential current of the detector flows through R9 and R10, then:

[0042]

[0043] Among them, I R9 I R10 These represent the currents through resistors R9 and R10, respectively.

[0044] In the above circuit, V CM With an input DC voltage of 2.5V, R1 is chosen to have a relatively large value, resulting in a detector input signal V. IN After attenuation, the DC voltage across R2 approaches V. CM △vin satisfies △vin = [R3 / (R1+R2+R3)]·vin.

[0045] A simple switching device is placed between the detector and the variable gain amplifier. When the switch is on, the voltage V... DETO Feedback is sent to the gain control terminal.

[0046] When vin=0, meaning the detector has no AC small-signal input, the bias voltage V is set in DC mode. BIAS The voltage is 1.8V, which preferentially turns on Q18, thereby increasing the collector voltage V of Q17. CQ17 It is 2.5V. After being clamped by diode D1, V DETO The voltage is maintained at 1.8V, at which point Q20 is not conducting. Because V CQ17 With V DETO The inequality leads to ICQ14 Greater than I CQ13 Q15 and Q16 form an approximately 1:1 current mirror. At this point, the current flowing into the bases of Q17 and Q19 is relatively large. Furthermore, the upward impedance of Q17 and Q19 is very high, causing them to act as switches. Their collector voltages are only a few tens of millivolts, and the circuit eventually reaches a steady state (due to the presence of R7, V...). DETO Slightly lower than V CQ17 In a steady state, I R10 with I R9 They are basically equal (or I) R10 Slightly lower than I R9 ).

[0047] As vin gradually increases from zero, in the transient initial state, I R10 Significantly increased, I R9 Significantly reduced, resulting in V DETO Increase. Due to V DETO Connecting the gain control voltage to the variable gain amplifier will reduce the amplifier's gain, thus lowering its output and consequently reducing the detector's input signal vin. This change will then cause I... R10 Decrease, I R9 Increase, and repeat this iteratively until I... R10 with I R9 When the base currents of Q17 and Q19 are essentially equal, the circuit tends to stabilize. (When the circuit is stable, the base currents of Q17 and Q19 should be very small, which requires V...) CQ17 With V DETO Increases and increases, thus making I R10 Approximately equal to I R9 ).

[0048] Therefore, as long as ΔV, I, and 4I are fixed, regardless of how the input signal amplitude changes, the circuit will remain stable under steady-state conditions. R10 Approximately equal to I R9 The condition will force Δvin to remain essentially unchanged, thereby causing the input signal V to... IN +vin stabilizes at a fixed value, thus keeping the output of the variable gain amplifier constant. This is achieved by properly setting R1~R6 and I... REF This allows you to change the target value of the stable output of the variable gain amplifier.

[0049] It is worth mentioning that V DETO This should be the DC voltage value. By adjusting the value of capacitor C4, the upper cutoff frequency of the low-pass filter can be adjusted, thereby obtaining the desired DC component.

[0050] In summary, the detector output V is controlled by a switch. DETO Whether the gain control voltage V is fed back to the variable gain amplifierC This allows the device to operate in either VGA or AGC mode.

[0051] Therefore, the above design proves that the detector circuit proposed in this invention can realize the mutual conversion between the linear variable gain amplifier and the automatic gain control circuit, effectively solving the problem of difficulty in parallel selection of VGA and AGC circuits in complex signal conditioning systems, while saving the area of ​​the integrated circuit board, reducing the number of devices, and lowering the cost.

[0052] Although embodiments of the invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the appended claims and their equivalents.

Claims

1. A variable gain amplifier to AGC circuit conversion circuit, characterized in that, It includes a variable gain amplifier, a switching device, and a detector circuit; the output of the detector circuit is connected to the gain control terminal of the variable gain amplifier via the switching device; wherein, when the switching device is in the ON state, the voltage V output by the detector circuit is... DETO Feedback is sent to the gain control terminal, forming an AGC feedback loop; when the switching device is in the off state, the voltage V output by the detector circuit... DETO Without feedback to the gain control terminal, the variable gain amplifier operates in an open-loop state.

2. The variable gain amplifier and AGC circuit conversion circuit according to claim 1, characterized in that, The variable gain amplifier, switching devices, and detector circuitry are integrated into the same chip.

3. The variable gain amplifier and AGC circuit conversion circuit according to claim 1, characterized in that, The detector circuit includes resistors R1~R10, capacitors C1~C4, diodes D1~D2, PNP transistors Q1~Q14, NPN transistors Q15~Q17, PNP transistor Q18, NPN transistor Q19, PNP transistor Q20, and current sources A1~A6; the connections of each component are as follows: The upper end of resistor R1 serves as the detector input terminal, used to receive the input signal V. IN +vin; The lower end of resistor R1 is connected to the upper end of resistor R2 and the upper end of capacitor C1. The voltage at this connection point is denoted as V. CM +2△vin; The lower end of resistor R2 is connected to the lower end of capacitor C1, the upper end of resistor R3, and the upper end of capacitor C2. The voltage at this connection point is denoted as V. CM +△vin; The lower end of resistor R3 is connected to the lower end of capacitor C2, the upper end of resistor R4, and the upper end of resistor R5. The voltage at this connection point is denoted as V. CM The lower end of resistor R5 is connected to the upper end of resistor R6, and the voltage at this connection point is denoted as V. CM -△V; The lower end of resistor R4 is connected to the lower end of resistor R6 and the input terminal of current source A1. The voltage at this connection point is denoted as V. CM -2ΔV; The output terminal of the current source is grounded; The emitters of PNP transistors Q1-Q3 are connected to the output terminal of current source A3; the emitters of PNP transistors Q4-Q6 are connected to the output terminal of current source A4; the emitters of PNP transistors Q7-Q9 are connected to the output terminal of current source A5; and the emitters of PNP transistors Q10-Q12 are connected to the output terminal of current source A6. The collectors of PNP transistors Q1-Q2, Q6-Q7, and Q10-Q11 are connected to the upper end of resistor R9. The collectors of PNP transistors Q3-Q5, Q8-Q9, and Q12 are connected to the upper end of resistor R10. The bases of PNP transistors Q1, Q5, Q9, and Q11 are connected to the voltage V. CM The base connection voltage V of PNP transistors Q2 and Q10 CM -2ΔV; Base connection voltage V of PNP transistors Q3 and Q12 CM -△V; Base connection voltage V of PNP transistors Q4 and Q8 CM +2△vin; Base connection voltage V of PNP transistors Q6 and Q7 CM +△vin; The lower end of resistor R9 is connected to the upper end of resistor R8, the base of PNP transistor Q13, the collector of NPN transistor Q17, the emitter of PNP transistor Q18, the positive terminal of diode D1, and the negative terminal of diode D2; The lower end of resistor R10 is connected to the collector of NPN transistor Q19, the emitter of PNP transistor Q20, the upper end of capacitor C4, the negative terminal of diode D1, and the positive terminal of diode D2. This connection point serves as the output terminal of the detector, with an output voltage V. DETO The emitter of PNP transistor Q13 is connected to the output terminal of current source A2 and the upper end of resistor R7. The collector of PNP transistor Q13 is connected to the collector of NPN transistor Q15, the base of NPN transistor Q15, and the base of NPN transistor Q16. The emitter of PNP transistor Q14 is connected to the lower end of resistor R7, and the base of PNP transistor Q14 is connected to voltage V. DETO The collector of PNP transistor Q14 is connected to the collector of NPN transistor Q16, the lower end of capacitor C3, the base of NPN transistor Q17, and the base of NPN transistor Q19; the emitters of NPN transistors Q15~Q17 are grounded; the base of PNP transistor Q18 is connected to the base of PNP transistor Q20 and voltage V. BIAS The collector of PNP transistor Q18 is grounded; the emitter of NPN transistor Q19 is grounded; the collector of PNP transistor Q20 is grounded; the lower end of capacitor C4 is grounded; the input terminals of current sources A2~A6 are connected to power supply VCC; and the lower end of resistor R8 is connected to the upper end of capacitor C3. Among them, V IN Input signal V IN +vin is the DC component, where vin is the input signal V. IN +vin's small-signal component of the AC signal, V CM Here, ΔV is the preset fixed DC voltage, ΔV is the voltage drop, and Δvin is the voltage change.

4. The variable gain amplifier and AGC circuit conversion circuit according to claim 3, characterized in that, Resistors R2, R3, R5, and R6 have the same resistance value; ΔV is the current I output from current source A1. REF The current flows through resistors R4, R5, and R6, and their relationship satisfies: 。 5. The variable gain amplifier and AGC circuit conversion circuit according to claim 3, characterized in that, The current outputs of current sources A3 and A4 are equal; the current outputs of current sources A2, A5~A6 are 4 times that of current source A3.

6. The variable gain amplifier and AGC circuit conversion circuit according to claim 3, characterized in that, △vin satisfies △vin = [R3 / (R1+R2+R3)]·vin.

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