Low noise amplifier circuit, chip and communication device

Abstract

Embodiments of the present application provide a low noise amplification circuit, a chip and a communication device, which are used for improving the phenomenon that the module area is large and the overall cost increases. The low noise amplification circuit comprises a first amplification circuit, a second amplification circuit, a third amplification circuit and an inter-stage matching device. The first amplification circuit is used for receiving and processing a radio frequency signal of a first frequency band, the second amplification circuit is used for receiving and processing a radio frequency signal of a second frequency band, and the third amplification circuit is coupled with the first amplification circuit and the second amplification circuit in an on-off manner. The number of the inter-stage matching devices coupled between the first amplification circuit and the third amplification circuit is greater than the number of the inter-stage matching devices coupled between the second amplification circuit and the third amplification circuit. Embodiments of the present application can realize switching between different amplification circuits, which is conducive to saving the area of the low noise amplification circuit on the chip, and further conducive to reducing the cost.

Description

Technical Field

[0001] This application relates to the field of communication technology, specifically to a low-noise amplifier circuit, a chip, and a communication device. Background Technology

[0002] With the development of wireless communication technology, electronic devices with mobile communication or wireless communication functions have become increasingly common, providing wireless communication services to users. In these electronic devices, processing radio frequency (RF) signals is a frequent practice. For example, after receiving an RF signal, a low-noise amplifier (LNA) is needed to amplify the weak signal and minimize noise. However, related technologies using multi-frequency LNAs occupy a large area, increasing overall cost. Summary of the Invention

[0003] This application provides a low-noise amplifier circuit, chip, and communication device to improve the phenomenon of large module area and increased overall cost.

[0004] To achieve the above objectives, the embodiments of this application provide the following solutions:

[0005] On one hand, a low-noise amplifier circuit is provided, comprising a first amplifier circuit, a second amplifier circuit, a third amplifier circuit, and interstage matching devices. The first amplifier circuit receives and processes radio frequency signals in a first frequency band; the second amplifier circuit receives and processes radio frequency signals in a second frequency band; the third amplifier circuit is selectively coupled to both the first and second amplifier circuits; and the third amplifier circuit processes radio frequency signals from either the first or second amplifier circuit. The number of interstage matching devices coupled between the first and third amplifier circuits is greater than the number of interstage matching devices coupled between the second and third amplifier circuits.

[0006] With the above configuration, the interstage matching devices coupled to the first and third amplifier circuits constitute a first interstage matching circuit. This first interstage matching circuit is used to reduce the impedance mismatch of the radio frequency signal between the first and third amplifier circuits in a first frequency band. The interstage matching devices coupled to the second and third amplifier circuits constitute a second interstage matching circuit. This second interstage matching circuit is used to reduce the impedance mismatch of the radio frequency signal between the second and third amplifier circuits in a second frequency band.

[0007] Because the number of inter-stage matching devices in the first-stage inter-matching circuit is greater than that in the second-stage inter-matching circuit, the first-stage inter-matching circuit can perform impedance matching for RF signals with a relatively wide bandwidth. The circuit used to process RF signals in the first frequency band can be called a wideband LNA. The second-stage inter-matching circuit can perform impedance matching for RF signals with a relatively narrow bandwidth. The circuit used to process RF signals in the second frequency band can be called a narrowband LNA. In communication scenarios involving a wider frequency band, compared to switching between multiple narrowband LNAs, the embodiments of this application can achieve switching between wideband and narrowband LNAs, which helps save the area of ​​the low-noise amplifier circuit on the chip, thereby reducing costs.

[0008] In some embodiments, the relative bandwidth of the first frequency band can be greater than the relative bandwidth of the second frequency band. Here, "relative bandwidth" can be understood as the ratio of twice the difference between the upper and lower frequency limits to the sum of the upper and lower frequency limits. With the above settings, the low-noise amplifier circuit can switchably process RF signals with either a larger or smaller relative bandwidth.

[0009] In some embodiments, the relative bandwidth of the first frequency band is greater than 25%, and the relative bandwidth of the second frequency band is less than 25%. Here and in the embodiments below, a relative bandwidth greater than 25% (i.e., the first frequency band) can be referred to as broadband, and a relative bandwidth less than 25% (i.e., the second frequency band) can be referred to as narrowband.

[0010] In some embodiments, the first amplifier circuit includes a first transistor, the gate of which is used to receive a radio frequency (RF) signal, and the drain of which is used to output a processed RF signal. The second amplifier circuit includes a second transistor, the gate of which is used to receive the RF signal, and the drain of which is used to output the processed RF signal. A third amplifier circuit is coupled to the drains of the first and second transistors in a switchable manner. With this configuration, both the first and second transistors can be common-source transistors, and both have amplification capabilities.

[0011] In some embodiments, the third amplifier circuit includes a third transistor, the source of which is coupled to the drain of the first transistor and the drain of the second transistor in a switchable manner. With the above configuration, the third transistor is a common-gate transistor, and it can perform an amplification function.

[0012] In some embodiments, the interstage matching devices are all coupled between the drain of the first transistor and the source of the third transistor. With this configuration, the number of interstage matching devices coupled between the first and third amplifier circuits is greater than the number coupled between the second and third amplifier circuits. The first amplifier circuit and the interstage matching devices can process radio frequency signals with relatively wide bandwidths, while the second amplifier circuit can process radio frequency signals with relatively narrow bandwidths, enabling the low-noise amplifier circuit to switch between wideband and narrowband processing of radio frequency signals.

[0013] In some embodiments, the interstage matching device includes a first inductor and a first capacitor. One end of the first inductor is coupled to the drain of a first transistor, and the other end of the first inductor is coupled to the source of a third transistor in a switchable manner. One end of the first capacitor is coupled to the first inductor, and the other end of the first capacitor is grounded. With the above configuration, the interstage matching device can perform impedance matching for radio frequency signals.

[0014] In some embodiments, the third amplifier circuit includes a third transistor, the gate of which is electrically and non-disconnectably coupled to the drains of the first transistor and the second transistor. With this configuration, the third transistor is a common-source transistor and can perform amplification.

[0015] In some embodiments, some interstage matching devices constitute a first sub-circuit, and some interstage matching devices constitute a second sub-circuit. One end of the first sub-circuit is coupled to the gate of a third transistor, and the other end of the first sub-circuit is coupled to the second sub-circuit through an interstage capacitor. The second sub-circuit is coupled to the drain of the first transistor in a switchable manner. The other end of the first sub-circuit is also coupled to the drain of the second transistor in a switchable manner through an interstage capacitor. With the above configuration, the first sub-circuit, the interstage capacitor, and the second sub-circuit together constitute a first interstage matching circuit, and the first sub-circuit and the interstage capacitor together constitute a second interstage matching circuit, such that the number of devices in the first interstage matching circuit is greater than the number of devices in the second interstage matching circuit.

[0016] In some embodiments, the first sub-circuit includes a second inductor and a second capacitor. The second inductor is coupled between the gate of the third transistor and the interstage capacitor. One end of the second capacitor is coupled to the second inductor, and the other end of the second capacitor is grounded. The second sub-circuit also includes a third inductor. One end of the third inductor is coupled to the interstage capacitor, and the other end of the third inductor is coupled to the drain of the first transistor in a switchable manner. With the above configuration, the interstage matching device can perform impedance matching for radio frequency signals.

[0017] In some embodiments, the third amplifier circuit includes a third transistor, the gate of which is selectively coupled to the drain of the first transistor, and the source of which is selectively coupled to the drain of the second transistor. With this configuration, when the first and third transistors are turned on, the gate of the third transistor receives the first amplified radio frequency signal; the third transistor is a common-source transistor and thus functions as an amplifier. When the second and third transistors are turned on, the source of the third transistor receives the first amplified radio frequency signal; the third transistor is a common-gate transistor and thus functions as an amplifier.

[0018] In some embodiments, the inter-stage matching devices are all coupled between the drain of the first transistor and the gate of the third transistor. With the above configuration, the number of devices in the first inter-stage matching circuit is greater than the number of devices in the second inter-stage matching circuit.

[0019] In some embodiments, the low-noise amplifier circuit further includes an output matching circuit coupled to the drain of the third transistor. The output matching circuit is used to perform impedance matching on the radio frequency signal from the third amplifier circuit and output the impedance-matched radio frequency signal.

[0020] In some embodiments, the low-noise amplifier circuit includes a first power supply circuit with a plurality of first output terminals for outputting a plurality of different bias voltage signals. The gate of a third transistor is switchably coupled to one of the plurality of first output terminals, or an output matching circuit is switchably coupled to one of the plurality of first output terminals. Through this configuration, the power supply bias voltage of the third transistor and the output matching circuit can be adjusted, thereby enabling the low-noise amplifier circuit to achieve different linearities and noise performances, and allowing the low-noise amplifier circuit to switch between different standards.

[0021] In some embodiments, an input matching circuit is further included. The input matching circuit is coupled to both the first and second amplifier circuits. The input matching circuit receives radio frequency (RF) signals and performs impedance matching on the RF signals. With this configuration, both the first and second amplifier circuits are coupled to the same input matching circuit, which helps reduce the number of input matching circuits, thereby reducing the footprint of the low-noise amplifier circuit and facilitating cost reduction. Simultaneously, the first and second amplifier circuits share a single port (Pad) coupled to the input matching circuit, further reducing the number of ports and thus further reducing the footprint of the low-noise amplifier circuit.

[0022] In some embodiments, the low-noise amplifier circuit includes a second power supply circuit with multiple second output terminals for outputting multiple different bias voltage signals. The first amplifier circuit includes a first transistor, the gate of which is switchably coupled to one of the multiple second output terminals; or, the second amplifier circuit includes a second transistor, the gate of which is switchably coupled to one of the multiple second output terminals. This configuration allows the second power supply circuit to provide different bias voltage signals to the first and second transistors, enabling adjustable bias voltage designs for both transistors. This, in turn, allows the low-noise amplifier circuit to achieve different linearities and noise performances, and enables it to switch between different standards.

[0023] In some embodiments, the first amplifier circuit further includes a first tuning circuit coupled between the source and gate of the first transistor. The second amplifier circuit further includes a second tuning circuit coupled between the source and gate of the second transistor. By providing the first tuning circuit, impedance matching is further provided for the radio frequency signal in the first frequency band. By providing the second tuning circuit, impedance matching is further provided for the radio frequency signal in the second frequency band.

[0024] In some embodiments, the radio frequency receiving circuit further includes a third tuning circuit, one end of which is coupled to the source of the first transistor and the source of the second transistor, respectively, and the other end of which is grounded. By providing the third tuning circuit, impedance matching is further provided for the radio frequency signals in the first and second frequency bands.

[0025] On the other hand, a chip is provided that includes the low-noise amplifier circuit described in the above embodiments. The chip provided by the embodiments of this application includes the low-noise amplifier circuit as described above, and therefore has all the aforementioned beneficial effects, which will not be repeated here.

[0026] In some embodiments, the chip further includes a power amplifier circuit and an RF switch circuit; the RF switch circuit is used to switch coupling with the power amplifier circuit or the low-noise amplifier circuit.

[0027] On the other hand, a communication device is provided, further comprising at least one antenna and the chip described in the above embodiments, wherein the chip is coupled to the antenna. The chip provided in the embodiments of this application includes the chip described above, and therefore possesses all the aforementioned beneficial effects, which will not be repeated here.

[0028] On the other hand, a low-noise amplifier circuit is provided, including: an input matching circuit, a first amplifier circuit, a second amplifier circuit, a third amplifier circuit, and an output matching circuit.

[0029] The input matching circuit receives and impedance-matches the radio frequency (RF) signal. A first amplifier circuit, coupled to the input matching circuit, processes RF signals in a first frequency band. A second amplifier circuit, also coupled to the input matching circuit, processes RF signals in a second frequency band. A third amplifier circuit is selectively coupled to both the first and second amplifier circuits, and processes RF signals from either the first or second amplifier circuit. The output matching circuit, coupled to the third amplifier circuit, performs impedance matching on the RF signal from the third amplifier circuit and outputs the impedance-matched RF signal. The first and second amplifier circuits share a single port coupled to the input matching circuit, which helps reduce the number of ports and thus the footprint of the low-noise amplifier circuit. Attached Figure Description

[0030] Figure 1 A structural diagram of a communication device provided in an embodiment of this application;

[0031] Figure 2 A structural diagram of a low-noise amplifier circuit provided in an embodiment of this application;

[0032] Figure 3 A structural diagram of another low-noise amplifier circuit provided in the embodiments of this application;

[0033] Figure 4 A structural diagram of an output matching network provided in an embodiment of this application;

[0034] Figure 5 A structural diagram of another output matching network provided in an embodiment of this application;

[0035] Figure 6 A structural diagram of another output matching network provided in an embodiment of this application;

[0036] Figure 7 A structural diagram of an interstage matching device provided in an embodiment of this application;

[0037] Figure 8 A structural diagram of another interstage matching device provided in an embodiment of this application;

[0038] Figure 9 A structural diagram of another interstage matching device provided in an embodiment of this application;

[0039] Figure 10 A structural diagram of another interstage matching device provided in an embodiment of this application;

[0040] Figure 11 A structural diagram of a first tuning circuit provided in an embodiment of this application;

[0041] Figure 12 A structural diagram of a second tuning circuit provided in an embodiment of this application;

[0042] Figure 13 A structural diagram of a third tuning circuit provided in an embodiment of this application;

[0043] Figure 14 A structural diagram of another low-noise amplifier circuit provided in the embodiments of this application;

[0044] Figure 15 A structural diagram of a first sub-circuit provided in an embodiment of this application;

[0045] Figure 16 A structural diagram of another first sub-circuit provided in an embodiment of this application;

[0046] Figure 17 A structural diagram of another first sub-circuit provided in an embodiment of this application;

[0047] Figure 18 A structural diagram of another first sub-circuit provided in an embodiment of this application;

[0048] Figure 19 A structural diagram of a second sub-circuit provided in an embodiment of this application;

[0049] Figure 20 A structural diagram of another second sub-circuit provided in an embodiment of this application;

[0050] Figure 21 A structural diagram of another second sub-circuit provided in an embodiment of this application;

[0051] Figure 22 A structural diagram of another low-noise amplifier circuit provided in the embodiments of this application;

[0052] Figure 23 This is a structural diagram of another low-noise amplifier circuit provided in an embodiment of this application. Detailed Implementation

[0053] The technical solutions of the embodiments of this application will be described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments.

[0054] Hereinafter, the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined with "first," "second," etc., may explicitly or implicitly include one or more of that feature.

[0055] Furthermore, in the embodiments of this application, directional terms such as "up," "down," "left," "right," "horizontal," and "vertical" are defined relative to the orientation of the components shown in the accompanying drawings. It should be understood that these directional terms are relative concepts, used for relative description and clarification, and can change accordingly depending on the orientation of the components in the accompanying drawings.

[0056] In the embodiments of this application, unless otherwise explicitly specified and limited, the term "connection / linking" should be interpreted broadly, and may refer to a mechanical connection or a physical connection. That is, A and B being connected or linked may mean that there are fastening components (such as screws, bolts, rivets, etc.) between A and B, or that A and B are in contact with each other and are difficult to separate.

[0057] Coupling can be understood as direct coupling and / or indirect coupling. "Coupled connection" can be understood as a direct coupling connection and / or indirect coupling connection. Direct coupling can also be called "electrical connection," which can be understood as physical contact and electrical conduction between components; it can also be understood as the form of connection between different components in a circuit structure through physical lines that can transmit electrical signals, such as copper foil or wires on a printed circuit board (PCB). "Indirect coupling" can be understood as electrical conduction between two conductors through a gap / non-contact method. In one embodiment, indirect coupling can also be called capacitive coupling, for example, signal transmission is achieved by forming an equivalent capacitance through coupling between the gaps between two conductive parts.

[0058] Connection: The process of making two or more components conduct or connect through the above-mentioned "electrical connection" or "indirect coupling" to transmit signals / energy can be called connection.

[0059] End / Point: The term "end / point" in the context of the antenna radiator's first end / second end / feed end / ground end / feed point / ground point / connection point should not be narrowly interpreted as necessarily an endpoint or end physically disconnected from other radiators. It can also be considered a point or segment on a continuous radiator. In one embodiment, "end / point" can include a connection / coupling region on the antenna radiator that couples to other conductive structures. For example, a feed end / feed point can be a coupling region on the antenna radiator that couples to a feed structure or feed circuit (e.g., a region facing a part of the feed circuit). Similarly, a ground end / ground point can be a connection / coupling region on the antenna radiator that couples to a ground structure or ground circuit.

[0060] The terms collinearity, coaxiality, coplanarity, symmetry (e.g., axial symmetry, or central symmetry), parallelism, perpendicularity, and similarity (e.g., same length, same width, etc.) mentioned in the embodiments of this application are all relative to the current technological level, and not absolute and strict mathematical definitions. There may be a deviation of less than a predetermined threshold (e.g., 1 mm, 0.5 mm, or 0.1 mm) between the edges of two collinear radiating stubs or two antenna elements in the line width direction. There may be a deviation of less than a predetermined threshold between the edges of two coplanar radiating stubs or two antenna elements in the direction perpendicular to their coplanar plane. There may be a deviation of a predetermined angle between two parallel or perpendicular antenna elements. In one embodiment, the predetermined threshold may be less than or equal to a threshold of 1 mm, for example, the predetermined threshold may be 0.5 mm or 0.1 mm. In one embodiment, the predetermined angle may be an angle within the range of ±10°, for example, the predetermined angle deviation is ±5°.

[0061] The technical solutions of the embodiments of this application will now be described with reference to the accompanying drawings.

[0062] The technical solution of this application can be applied to various communication devices that include radio frequency transmitting circuits. This communication device can be deployed on land, including indoors or outdoors, handheld or vehicle-mounted. It can also be deployed on water (such as ships). Furthermore, it can be deployed in the air (e.g., on airplanes, balloons, and satellites). For example, this communication device can be a terminal or a base station. For example, the terminal includes, but is not limited to: mobile phone, tablet computer, laptop computer, PDA, mobile internet device (MID), wearable device (e.g., smartwatch, smart bracelet, pedometer, etc.), in-vehicle device (e.g., car, bicycle, electric vehicle, airplane, ship, train, high-speed rail, etc.), virtual reality (VR) device, augmented reality (AR) device, wireless terminal in industrial control, smart home device (e.g., refrigerator, television, air conditioner, electricity meter, etc.), smart robot, workshop equipment, wireless terminal in self-driving, wireless terminal in remote medical surgery, wireless terminal in smart grid, wireless terminal in transportation safety, wireless terminal in smart city, or wireless terminal in smart home, flying equipment (e.g., smart robot, hot air balloon, drone, airplane), radio frequency front-end module, low noise amplifier, etc.

[0063] Figure 1 This is a structural diagram of a communication device provided in an embodiment of this application, using a mobile phone as an example. The communication device includes a chip 10 and at least one antenna 20, with the antenna 20 coupled to the chip 10. Those skilled in the art will understand that the structure of the communication device provided in this embodiment does not constitute a limitation on the structure, and may include more or fewer components than shown, or combine certain components, or have different component arrangements.

[0064] In some embodiments, refer to Figure 1 Chip 10 may include an RF transmitting circuit TX, an RF receiving circuit RX, and an RF transceiver 40. Both the RF transmitting circuit TX and the RF receiving circuit RX are coupled to the RF transceiver 40. A filter 30 may also be coupled between the RF transmitting circuit TX and the RF transceiver 40, and between the RF receiving circuit RX and the RF transceiver 40. A filter 30 may also be coupled between the RF transmitting circuit TX and the antenna 20, and between the RF receiving circuit RX and the antenna 20.

[0065] The baseband signal is transmitted to the RF transmitting circuit TX via the RF transceiver 40. The RF transmitting circuit TX amplifies the received RF signal and outputs it to the antenna 20, which then transmits it. The RF transmitting circuit TX includes a power amplifier (PA) circuit 200, which is used to amplify the power of the RF signal.

[0066] The radio frequency (RF) receiving circuit RX receives the RF signal from the antenna. The RF signal is amplified by the RF receiving circuit RX and then output, and transmitted to the baseband via the RF transceiver 40. The RF receiving circuit RX includes a low noise amplifier (LNA) circuit 100, which is used to amplify weak signals and minimize noise.

[0067] In some embodiments, to meet different application communication scenarios, the low-noise amplifier circuit 100 needs to switch between different operating frequency bands to adapt to the expansion of required frequency bands. For example, the low-noise amplifier circuit may include multiple input circuits, switching circuits, and output circuits. The input circuits are used to perform the first amplification of the radio frequency signal, and the output circuit is used to perform the second amplification of the radio frequency signal. Multiple input circuits amplify radio frequency signals of different frequency bands, and the switching circuits enable the low-noise amplifier circuit to process radio frequency signals of different frequency bands.

[0068] This configuration, in communication scenarios with a wider processing frequency band, requires an increased number of input circuits, leading to a larger area occupied by the low-noise amplifier circuit on the chip and increased cost. Furthermore, since each input circuit requires a corresponding independent matching circuit, the increased number of matching devices results in an increased number of input ports (Pads) on the chip for coupling with the matching circuit, further increasing the area occupied by the low-noise amplifier circuit on the chip.

[0069] Figure 2 This is a structural diagram of a low-noise amplifier circuit provided in an embodiment of this application. (Refer to...) Figure 2 In view of this, in a low-noise amplifier circuit 100 provided in the embodiments of this application, the low-noise amplifier circuit 100 may include a first amplifier circuit D1, a second amplifier circuit D2 and a third amplifier circuit D3.

[0070] The first amplifier circuit D1 is used to receive and process radio frequency signals in the first frequency band. The second amplifier circuit D2 is used to receive and process radio frequency signals in the second frequency band. The third amplifier circuit D3 is coupled to the first amplifier circuit D1 and the second amplifier circuit D2 in a switchable manner, and the third amplifier circuit D3 is used to process radio frequency signals from the first amplifier circuit D1 or the second amplifier circuit D2.

[0071] When the first amplifier circuit D1 and the third amplifier circuit D3 are connected, and the second amplifier circuit D2 and the third amplifier circuit D3 are disconnected, the low-noise amplifier circuit 100 can process radio frequency signals in the first frequency band. When the second amplifier circuit D2 and the third amplifier circuit D3 are connected, and the first amplifier circuit D1 and the third amplifier circuit D3 are disconnected, the low-noise amplifier circuit 100 can process radio frequency signals in the second frequency band. Through the above settings, the low-noise amplifier in this embodiment can switch between the first and second frequency bands by processing radio frequency signals.

[0072] For example, after the low-noise amplifier circuit 100 receives a radio frequency (RF) signal, the first amplifier circuit D1 or the second amplifier circuit D2 can amplify the RF signal for the first time, and the third amplifier circuit D3 can amplify the RF signal for the second time. In this embodiment, the circuit that amplifies the RF signal for the first time can be referred to as the first-stage amplifier circuit, and the circuit that amplifies the RF signal for the second time can be referred to as the second-stage amplifier circuit. In some embodiments, the first-stage amplifier circuit may not be limited to the aforementioned first amplifier circuit D1 and second amplifier circuit D2; the number of first-stage amplifier circuits may be three or more.

[0073] The low-noise amplifier circuit 100 may further include interstage matching devices 130, the number of which is coupled to the first amplifier circuit D1 and the third amplifier circuit D3 is greater than the number of which is coupled to the second amplifier circuit D2 and the third amplifier circuit D3.

[0074] In some embodiments, the interstage matching device 130 may include at least one capacitor or at least one inductor. For example, the capacitor may be an adjustable capacitor, and the inductor may be an adjustable inductor. This application does not limit the specific structure or number of the interstage matching device 130.

[0075] Interstage matching device 130 coupled to the first amplifier circuit D1 and the third amplifier circuit D3 constitutes a first interstage matching circuit. This first interstage matching circuit is used to reduce impedance mismatch of the radio frequency signal between the first amplifier circuit D1 and the third amplifier circuit D3 within a first frequency band. Interstage matching device 130 coupled to the second amplifier circuit D2 and the third amplifier circuit D3 constitutes a second interstage matching circuit. This second interstage matching circuit is used to reduce impedance mismatch of the radio frequency signal between the second amplifier circuit D2 and the third amplifier circuit D3 within a second frequency band.

[0076] In this embodiment, the relative bandwidth of the first frequency band can be greater than the relative bandwidth of the second frequency band. Here, "relative bandwidth" can be understood as the ratio of twice the difference between the upper and lower frequency limits to the sum of the upper and lower frequency limits. Since the number of interstage matching devices 130 coupled in the first amplifier circuit D1 and the third amplifier circuit D3 is greater than the number of interstage matching devices 130 coupled in the second amplifier circuit D2 and the third amplifier circuit D3, the first interstage matching circuit can perform impedance matching for RF signals with a larger relative bandwidth, and the second interstage matching circuit can perform impedance matching for RF signals with a smaller relative bandwidth. Through the above configuration, the low-noise amplifier circuit can switchably process RF signals with either a larger or smaller relative bandwidth.

[0077] For example, the relative bandwidth of the first frequency band is greater than 25%, and the relative bandwidth of the second frequency band is less than 25%. In this context and in the embodiments described below, a relative bandwidth greater than 25% (i.e., the first frequency band) can be referred to as broadband, and a relative bandwidth less than 25% (i.e., the second frequency band) can be referred to as narrowband. For example, the frequency range of the first frequency band can be 1.5GHz-2.5GHz, where the upper limit frequency can be 2.5GHz, the lower limit frequency can be 1.5GHz, and the relative bandwidth can be 50%; the frequency range of the second frequency band can be 2.5GHz-2.7GHz, where the upper limit frequency can be 2.7GHz, the lower limit frequency can be 2.5GHz, and the relative bandwidth can be 7.69%.

[0078] The embodiments of this application can realize the switching between different amplifier circuits, which helps to save the area of ​​the low-noise amplifier circuit 100 on the chip, thereby helping to reduce costs.

[0079] In one embodiment, since the number of inter-stage matching devices 130 in the first inter-stage matching circuit is greater than the number of inter-stage matching devices 130 in the second inter-stage matching circuit, the first inter-stage matching circuit can perform impedance matching for radio frequency signals with a relatively wide bandwidth. The circuit used to process radio frequency signals in the first frequency band can be called a wideband LNA. The second inter-stage matching circuit can perform impedance matching for radio frequency signals with a relatively narrow bandwidth. The circuit used to process radio frequency signals in the second frequency band can be called a narrowband LNA. In communication scenarios that process a wide frequency band, compared to switching between multiple narrowband LNAs, the embodiments of this application can realize the switching between wideband LNAs and narrowband LNAs, which is beneficial to saving the area of ​​the low-noise amplifier circuit 100 on the chip, thereby reducing costs.

[0080] In some embodiments, the low-noise amplifier circuit 100 may further include an input matching circuit 110. The input matching circuit 110 is coupled to the first amplifier circuit D1 and the second amplifier circuit D2, respectively, and is used to receive radio frequency signals and perform impedance matching on the input radio frequency signals.

[0081] Figure 3 This is a structural diagram of another low-noise amplifier circuit provided in an embodiment of this application. (Combined with...) Figure 2 and Figure 3 As shown, the input matching circuit 110 may include an input inductor L9, wherein one end of the input inductor L9 (e.g., the port of RF in) is used to receive radio frequency signals, and the other end of the input inductor L9 is coupled to the first amplifier circuit D1 and the second amplifier circuit D2, respectively. Of course, the input matching circuit 110 may also include other structures, and the specific structure of the input matching circuit 110 is not limited in this embodiment.

[0082] With the above configuration, both the first amplifier circuit D1 and the second amplifier circuit D2 are coupled to the same input matching circuit 110, which helps reduce the number of input matching circuits 110, thereby reducing the area occupied by the low-noise amplifier circuit 100 and facilitating cost reduction. Simultaneously, the first amplifier circuit D1 and the second amplifier circuit D2 share a single port (Pad) coupled to the input matching circuit 110, which further reduces the number of ports and thus further reduces the area occupied by the low-noise amplifier circuit 100.

[0083] In some embodiments, combined with Figure 2 and Figure 3As shown, the low-noise amplifier circuit 100 may further include an output matching circuit 120, which is coupled to the third amplifier circuit D3. The output matching circuit 120 is used to perform impedance matching on the radio frequency signal from the third amplifier circuit D3 and output the impedance-matched radio frequency signal.

[0084] For example, the output matching circuit 120 may include an output biasing component 121 and an output matching network 122.

[0085] The output bias component 121 may include a parallel-coupled adjustable inductor Ld8, an adjustable resistor Rd8, and an adjustable capacitor Cd8. The output matching network 122 may include at least one adjustable capacitor. The output terminal of the output matching network 122 may serve as the output terminal of the low-noise amplifier circuit 100 (e.g., the RF OUT port) for outputting the RF signal processed by the low-noise amplifier circuit 100.

[0086] Figure 4 A structural diagram of an output matching network provided in an embodiment of this application; Figure 5 A structural diagram of another output matching network provided in an embodiment of this application; Figure 6 This is a structural diagram of another output matching network provided in an embodiment of this application.

[0087] In some examples, combined Figure 3 and Figure 4 As shown, the output matching network 122 may include adjustable capacitors C81 and C82. One end of adjustable capacitor C81 is coupled to the node between the third amplifier circuit D3 and the output bias component 121, and the other end of adjustable capacitor C81 serves as the output terminal of the low-noise amplifier circuit 100. One end of adjustable capacitor C82 is coupled to the node between the third amplifier circuit D3 and adjustable capacitor C81, and the other end of adjustable capacitor C82 is grounded.

[0088] In some examples, combined Figure 3 and Figure 5 As shown, the output matching network 122 may include an adjustable capacitor C83 and an adjustable inductor L81. One end of the adjustable capacitor C83 is coupled to the node between the third amplifier circuit D3 and the output bias component 121, and the other end of the adjustable capacitor C83 serves as the output terminal of the low-noise amplifier circuit 100. One end of the adjustable inductor L81 is coupled to the output terminal of the adjustable capacitor C83, and the other end of the adjustable inductor L81 is grounded.

[0089] In some examples, combined Figure 3 and Figure 6As shown, the output matching network 122 may include series-coupled adjustable capacitors C84 and C85. Adjustable capacitor C84 is coupled between the node between the third amplifier circuit D3 and the output bias component 121 and adjustable capacitor C85. The other end of adjustable capacitor C85 serves as the output terminal of the low-noise amplifier circuit 100. The output matching network 122 may also include an adjustable inductor L82. One end of adjustable inductor L82 is coupled between the node between adjustable capacitors C84 and C85, and the other end of adjustable inductor L82 is grounded.

[0090] In this embodiment, the adjustable capacitor may include multiple capacitors coupled in parallel, and at least one capacitor is connected in series with a switch. The adjustable performance of the capacitor is achieved by controlling the number of switches that are turned on and off. Similarly, the adjustable inductor in this embodiment may include multiple inductors coupled in series, and at least one inductor is connected in parallel with a bypass switch. The adjustable performance of the inductor is achieved by controlling the number of bypass switches that are turned on and off.

[0091] Of course, the output matching network 122 may also include other structures, and the specific structure of the output matching circuit 120 is not limited in this embodiment.

[0092] In some embodiments, combined with Figure 2 and Figure 3 The first amplifier circuit D1 includes a first transistor T1. The gate of the first transistor T1 can be coupled to the input matching circuit 110. The gate of the first transistor T1 can be used to receive radio frequency signals. The drain of the first transistor T1 can be coupled to the third amplifier circuit D3. The drain of the first transistor T1 can be used to output the processed radio frequency signal.

[0093] For example, the gate of the first transistor T1 can be coupled to the input matching circuit 110 through the DC blocking capacitor C91, and the drain of the first transistor T1 can be coupled to the third amplifier circuit D3 through the switch K1.

[0094] In addition, the second amplifier circuit D2 includes a second transistor T2, the gate of which can be coupled to the input matching circuit 110, the gate of which can be used to receive radio frequency signals, the drain of which can be coupled to the third amplifier circuit D3, and the drain of which can be used to output the processed radio frequency signal.

[0095] For example, the gate of the second transistor T2 can be coupled to the input matching circuit 110 through the DC blocking capacitor C92, and the drain of the second transistor T2 can be coupled to the third amplifier circuit D3 through the switch K2.

[0096] Furthermore, in embodiments where the first-stage amplifier circuit includes three or more amplifier circuits, each amplifier circuit may include a transistor Tn, and the gate of transistor Tn may be coupled to the input matching circuit 110 via a DC blocking capacitor C9n, and the drain of transistor Tn may be coupled to the third amplifier circuit D3 via a switch Kn. The DC blocking capacitors C91, C92, ..., and C9n are used to isolate DC signals. Furthermore, an interstage matching device is also coupled between transistor Tn and the third amplifier circuit D3, so that transistor Tn and the coupled interstage matching device together constitute a wideband LNA or a narrowband LNA. The embodiments of this application do not limit the number of wideband LNAs and narrowband LNAs.

[0097] In the embodiments of this application, the first transistor T1 and the second transistor T2 can both be common-source transistors, and both the first transistor T1 and the second transistor T2 have amplification functions.

[0098] In some embodiments, the third amplifier circuit D3 may include a third transistor T3, which may be coupled to the drain of the first transistor T1 and the drain of the second transistor T2, respectively, so that the third transistor T3 can be used to receive radio frequency signals from the first transistor T1 or the second transistor T2. The drain of the third transistor T3 is coupled to the output matching circuit 120 so that the radio frequency signal amplified a second time by the third transistor T3 is output to the output matching circuit 120.

[0099] In some embodiments, combined with Figure 2 and Figure 3 The source of the third transistor T3 is coupled to the drain of the first transistor T1 and the drain of the second transistor T2 in a switchable manner. For example, the first interstage matching circuit can be coupled between the drain of the first transistor T1 and the drain of the third transistor T3, and the second interstage matching circuit can be coupled between the drain of the second transistor T2 and the drain of the third transistor T3.

[0100] With the above settings, the third transistor T3 is a common-gate (CG) transistor, and the third transistor T3 can perform the amplification function.

[0101] Furthermore, the interstage matching devices 130 can all be coupled between the drain of the first transistor T1 and the source of the third transistor T3. For example, a first interstage matching circuit can be provided between the first amplifier circuit D1 and the third amplifier circuit D3, and the second interstage matching circuit between the second amplifier circuit D2 and the third amplifier circuit D3 is omitted. That is, all the interstage matching devices 130 in the low-noise amplifier circuit 100 are the interstage matching devices 130 in the first interstage matching circuit.

[0102] With the above configuration, the number of interstage matching devices 130 coupled between the first amplifier circuit D1 and the third amplifier circuit D3 is greater than the number of interstage matching devices 130 coupled between the second amplifier circuit D2 and the third amplifier circuit D3. The first amplifier circuit D1 and the interstage matching devices 130 can process radio frequency signals with relatively wide bandwidth, while the second amplifier circuit D2 can process radio frequency signals with relatively narrow bandwidth, so that the low-noise amplifier circuit 100 can switch between wideband and narrowband processing of radio frequency signals.

[0103] Figure 7 A structural diagram of an interstage matching device provided in an embodiment of this application; Figure 8 A structural diagram of another interstage matching device provided in an embodiment of this application; Figure 9 A structural diagram of another interstage matching device provided in an embodiment of this application; Figure 10 This is a structural diagram of another interstage matching device provided in an embodiment of this application.

[0104] In some examples, combined Figures 7 to 10 As shown, the interstage matching device 130 may include a first inductor L71 and a first capacitor C71. Wherein, Figures 7 to 10 The first capacitor C71 and the first inductor L71 are both adjustable devices.

[0105] In this configuration, one end of the first inductor L71 is coupled to the drain of the first transistor T1, and the other end of the first inductor L71 is coupled to the source of the third transistor T3 in a switchable manner. One end of the first capacitor C71 is coupled to the first inductor L71, and the other end of the first capacitor C71 is grounded.

[0106] For example, combining Figure 3 and Figure 7 As shown, one end of the first capacitor C71 can be coupled to the node between the source of the third transistor T3 and the first inductor L71. Furthermore, both the first inductor L71 and the first capacitor C71 can be coupled to the source of the third transistor T3 via switch K1. With the above configuration, the interstage matching device 130 can perform impedance matching for the radio frequency signal.

[0107] Or, combine Figure 3 and Figure 8 As shown, one end of the first capacitor C71 can be coupled to the node between the drain of the first transistor T1 and the first inductor L71. Furthermore, the first inductor L71 can also be coupled to the source of the third transistor T3 via switch K1.

[0108] In some examples, combined Figure 3 and Figure 9As shown, the interstage matching device 130, in addition to including a first inductor L71 and a first capacitor C71, may also include an adjustable capacitor C72 and an adjustable inductor L72, based on... Figure 8 In the structure, one end of the adjustable capacitor C72 can be coupled to the node between the source of the third transistor T3 and the first inductor L71, and the other end of the adjustable capacitor C72 is grounded. The adjustable inductor L72 can be coupled between the first inductor L71 and the first capacitor C71.

[0109] Or, combine Figure 3 and Figure 10 As shown, the interstage matching device 130, in addition to including the first inductor L71 and the first capacitor C71, may also include an adjustable inductor L73, based on... Figure 8 In the structure, the adjustable inductor L73 can be coupled between the first inductor L71 and the drain of the first transistor T1.

[0110] Of course, when the third transistor T3 is a common gate transistor, the interstage matching device 130 may also include other structures. In this embodiment, the specific structure of the output matching circuit 120 is not limited.

[0111] Continue to refer to Figure 2 and Figure 3 The first amplifier circuit D1 may further include a first tuning circuit 104, which is coupled between the source and gate of the first transistor T1. The second amplifier circuit D2 further includes a second tuning circuit 105, which is coupled between the source and gate of the second transistor T2.

[0112] By providing a first tuning circuit 104, impedance matching is further provided for the radio frequency signal in the first frequency band. By providing a second tuning circuit 105, impedance matching is further provided for the radio frequency signal in the second frequency band. The specific structures of the first tuning circuit 104 and the second tuning circuit 105 are not limited in this embodiment.

[0113] For example, Figure 11 This is a structural diagram of a first tuning circuit provided in an embodiment of this application, combined with... Figure 11 As shown, the first tuning circuit 104 may include a plurality of third capacitors C1n coupled in parallel, at least one of the third capacitors C1n being coupled to the gate of the first transistor T1 in a switchable manner. By controlling the number of third capacitors C1n that are connected to the gate of the first transistor T1, the adjustability of the first tuning circuit 104 can be achieved, thereby facilitating the adjustment of the impedance matching provided by the first tuning circuit 104. Alternatively, in some embodiments, the first tuning circuit 104 may include an adjustable capacitor.

[0114] For example, Figure 12This application provides a structural diagram of a second tuning circuit according to an embodiment of the present application, combined with... Figure 12 As shown, the second tuning circuit 105 includes a plurality of fourth capacitors C2n coupled in parallel, at least one of which is coupled to the gate of the second transistor T2 in a switchable manner. By controlling the number of fourth capacitors C2n that are connected to the gate of the second transistor T2, the number of fourth capacitors C2n coupled in parallel can be adjusted, thereby achieving the adjustability of the second tuning circuit 105 and facilitating the adjustment of the impedance matching provided by the second tuning circuit 105. Alternatively, in some embodiments, the second tuning circuit 105 may include an adjustable capacitor.

[0115] Continue to refer to Figure 3 The radio frequency receiving circuit may also include a third tuning circuit 106, one end of which is coupled to the source of the first transistor T1 and the source of the second transistor T2, and the other end of which is grounded.

[0116] By providing a third tuning circuit 106, impedance matching is further provided for the radio frequency signals in the first and second frequency bands. This application embodiment does not limit the specific structure of the third tuning circuit 106.

[0117] For example, Figure 13 This application provides a structural diagram of a third tuning circuit according to an embodiment of the present application, combined with... Figure 13 As shown, the third tuning circuit 106 may include a plurality of fourth inductors Ln coupled in series, at least one of which is coupled in parallel with a switch. When there are multiple fourth inductors Ln, each inductor Ln can be coupled in parallel with a corresponding switch. By controlling the number of switches turned on in the third tuning circuit 106, the number of fourth inductors Ln coupled in series can be adjusted, thereby achieving the adjustability of the third tuning circuit 106 and facilitating the adjustment of the impedance matching provided by the third tuning circuit 106. Alternatively, in some embodiments, the third tuning circuit 106 may include an adjustable inductor.

[0118] Figure 14 This is a structural diagram of another low-noise amplifier circuit provided in an embodiment of this application.

[0119] In some embodiments, refer to Figure 14 The gate of the third transistor T3 is coupled to the drain of the first transistor T1 and the drain of the second transistor T2 in a switchable manner. For example, the first interstage matching circuit can be coupled between the drain of the first transistor T1 and the gate of the third transistor T3, and the second interstage matching circuit can be coupled between the drain of the second transistor T2 and the gate of the third transistor T3.

[0120] With the above settings, the third transistor T3 is a common-source (CS) transistor, and the third transistor T3 can perform the amplification function.

[0121] Part of the first-stage inter-matching circuit can be reused as a second-stage inter-matching circuit. For example, some inter-stage matching devices 130 constitute the first sub-circuit 131, and some inter-stage matching devices 130 constitute the second sub-circuit 132. One end of the first sub-circuit 131 is coupled to the gate of the third transistor T3, and the other end of the first sub-circuit 131 is coupled to the second sub-circuit 132 through the inter-stage capacitor Cg1. The second sub-circuit 132 is coupled to the drain of the first transistor T1 in a switchable manner. The other end of the first sub-circuit 131 is also coupled to the drain of the second transistor T2 in a switchable manner through the inter-stage capacitor Cg1. The inter-stage capacitor Cg1 can be an adjustable device.

[0122] With the above configuration, the first sub-circuit 131, the interstage capacitor Cg1, and the second sub-circuit 132 together constitute the first interstage matching circuit, and the first sub-circuit 131 and the interstage capacitor together constitute the second interstage matching circuit. This ensures that the number of components in the first interstage matching circuit is greater than the number of components in the second interstage matching circuit. The first amplifier circuit D1 and the first interstage matching circuit can process broadband radio frequency signals, while the second amplifier circuit D2 and the second interstage matching circuit can process narrowband radio frequency signals. This allows the low-noise amplifier circuit 100 to switch between broadband and narrowband processing of radio frequency signals.

[0123] Figure 15 A structural diagram of a first sub-circuit provided in an embodiment of this application; Figure 16 A structural diagram of another first sub-circuit provided in an embodiment of this application; Figure 17 A structural diagram of another first sub-circuit provided in an embodiment of this application; Figure 18 This is a structural diagram of another first sub-circuit provided in an embodiment of this application.

[0124] For example, the first sub-circuit 131 may include a second inductor L61 and a second capacitor C61. Wherein, Figures 15 to 18 The second capacitor C61 and the second inductor L61 are both adjustable devices.

[0125] Among them, combined Figure 14 and Figure 15 As shown, one end of the second inductor L61 is coupled to the second sub-circuit 132, and the other end of the second inductor L61 is coupled to the gate of the third transistor T3. One end of the second capacitor C61 is coupled to the second inductor L61, and the other end of the second capacitor C61 is grounded.

[0126] For example, combining Figure 14 and Figure 15As shown, one end of the second capacitor C61 can be coupled to the node between the gate of the third transistor T3 and the second inductor L61. Furthermore, the second inductor L61 can also be coupled to the drain of the first transistor T1 via switch K1. With the above configuration, the interstage matching device 130 can perform impedance matching for the radio frequency signal.

[0127] Or, combine Figure 14 and Figure 16 As shown, one end of the second capacitor C61 can be coupled to the node between the second sub-circuit 132 and the second inductor L61. Furthermore, the second inductor L61 can also be coupled to the drain of the first transistor T1 via switch K1.

[0128] In some examples, combined Figure 14 and Figure 17 As shown, the interstage matching device 130 may further include an adjustable capacitor C62 and an adjustable inductor L62, based on Figure 16 In the structure, one end of the adjustable capacitor C62 can be coupled to the node between the gate of the third transistor T3 and the second inductor L61, and the other end of the adjustable capacitor C62 is grounded. The adjustable inductor L62 can be coupled between the second inductor L61 and the second capacitor C61.

[0129] Or, combine Figure 14 and Figure 18 As shown, the interstage matching device 130 may further include an adjustable inductor L63, based on Figure 16 In the structure, the adjustable inductor L63 can be coupled between the second inductor L61 and the drain of the first transistor T1.

[0130] Of course, when the third transistor T3 is a common-source transistor, the first sub-circuit 131 may also include other structures. In this embodiment, the specific structure of the output matching circuit 120 is not limited.

[0131] Figure 19 A structural diagram of a second sub-circuit provided in an embodiment of this application; Figure 20 A structural diagram of another second sub-circuit provided in an embodiment of this application; Figure 21 This is a structural diagram of another second sub-circuit provided in an embodiment of this application.

[0132] For example, refer to Figures 19 to 21 The second sub-circuit 132 may include a third inductor L51, combined with Figure 14 As shown, one end of the third inductor L51 is coupled to the interstage capacitor Cg1, and the other end of the third inductor L51 is coupled to the drain of the first transistor T1 through the switch K1.

[0133] In some examples, combined Figure 14 and Figure 20The second sub-circuit 132 includes a third inductor L51 and an adjustable capacitor C51. One end of the adjustable capacitor C51 is coupled to the node between the third inductor L51 and the interstage capacitor Cg1, and the other end of the adjustable capacitor C51 is grounded.

[0134] In some examples, combined Figure 14 and Figure 21 The second sub-circuit 132 includes a third inductor L51 and an adjustable capacitor C52. One end of the adjustable capacitor C52 is coupled to the node between the third inductor L51 and the drain of the first transistor T1, and the other end of the adjustable capacitor C52 is grounded.

[0135] With the above configuration, when switch K1 is closed and switch K2 is open, the first sub-circuit 131, the second sub-circuit 132, and the interstage capacitor Cg1 together constitute the first interstage matching circuit. When switch K1 is open and switch K2 is closed, the first sub-circuit 131 and the interstage capacitor Cg1 together constitute the second interstage matching circuit. This ensures that the number of components in the first interstage matching circuit is greater than the number of components in the second interstage matching circuit.

[0136] Furthermore, the source of the third transistor T3 can also be coupled to the second sub-circuit 132 through an inductor Ls, which has a relatively large value. Additionally, the source of the third transistor T3 is grounded through a capacitor Cs to provide a radio frequency reference potential for the third transistor T3; the capacitor Cs also serves to isolate DC signals.

[0137] Of course, when the third transistor T3 is a common-source transistor, the interstage matching device 130 may also include other structures. In this embodiment, the specific structure of the output matching circuit 120 is not limited.

[0138] Continue to refer to Figure 14 In some embodiments, when the third transistor T3 is a common-source transistor, the output matching circuit 120, in addition to including the output bias component 121 and the output matching network 122, may also include a series-coupled output capacitor Cd and an output resistor Rd, with the output capacitor Cd and output resistor Rd coupled between the drain and gate of the third transistor T3. The output resistor Rd can be an adjustable device. This configuration facilitates further impedance matching of the RF signal output by the third transistor T3.

[0139] Furthermore, when the third transistor T3 is a common-source transistor, it may also include a first tuning circuit 104, a second tuning circuit 105, and a third tuning circuit 106, which will not be described in detail here.

[0140] Figure 22 This is a structural diagram of another low-noise amplifier circuit provided in an embodiment of this application.

[0141] Reference Figure 22 In some embodiments, the gate of the third transistor T3 is coupled to the drain of the first transistor T1 in a switchable manner, and the source of the third transistor T3 is coupled to the drain of the second transistor T2 in a switchable manner. For example, a first interstage matching circuit may be coupled between the drain of the first transistor T1 and the gate of the third transistor T3, and a second interstage matching circuit may be coupled between the drain of the second transistor T2 and the source of the third transistor T3.

[0142] With the above configuration, when the first transistor T1 and the third transistor T3 are turned on, the gate of the third transistor T3 receives the first amplified radio frequency signal. The third transistor T3 is a common-source transistor and thus functions as an amplifier. When the second transistor T2 and the third transistor T3 are turned on, the source of the third transistor T3 receives the first amplified radio frequency signal. The third transistor T3 is a common-gate transistor and thus functions as an amplifier.

[0143] In some embodiments, the interstage matching devices 130 are all coupled between the drain of the first transistor T1 and the gate of the third transistor T3.

[0144] For example, some of the interstage matching devices 130 can constitute a first sub-circuit 131, and some of the interstage matching devices 130 can constitute a second sub-circuit 132. The interstage matching devices 130 may also include an interstage capacitor Cg2. The interstage capacitor Cg2 can be an adjustable device. The specific structures of the first sub-circuit 131 and the second sub-circuit 132 can be as described in the above embodiments, and will not be repeated here.

[0145] and Figure 14 The difference lies in that one end of the interstage capacitor Cg2 is coupled to the node between the gate of the third transistor T3 and the first sub-circuit 131, while the other end of the interstage capacitor Cg2 is grounded via switch Kg3. Furthermore, the first sub-circuit 131 is coupled to the gate of the third transistor T3 via switch Kg2.

[0146] For example, the second transistor T2 is coupled to the source of the third transistor T3 via switch K2. That is, no interstage matching device 130 is provided between the second transistor T2 and the third transistor T3. In some embodiments, the source of the third transistor T3 can also be coupled to the second sub-circuit 132 via an inductor Ls, where the inductor Ls has a large value. The source of the third transistor T3 is also grounded via a capacitor Cs to provide a radio frequency reference potential for the third transistor T3. Furthermore, the inductor Ls is coupled to the source of the third transistor T3 via switch Ks1, and the capacitor Cs is coupled to the source of the third transistor T3 via switch Ks2.

[0147] When the low-noise amplifier circuit 100 switches to the broadband LNA, switches K1, Kg2, Ks1 and Ks2 are closed, and switches K2 and Kg3 are open. The first sub-circuit 131 and the second sub-circuit 132 together form the first interstage matching circuit. The inductor Ls is used to isolate the radio frequency signal and pass the DC signal, and the capacitor Cs is used to isolate the DC signal.

[0148] When the low-noise amplifier circuit 100 switches to narrowband LNA, switches K1, Kg2, Ks1, and Ks2 are open, while switches K2 and Kg3 are closed. Interstage capacitor Cg2 is used to adjust the resonant frequency, and the second-stage interstage matching circuit is omitted. With this setup, the number of components in the first-stage interstage matching circuit is greater than the number of components in the second-stage interstage matching circuit.

[0149] When the third transistor T3 is a common-source transistor or a common-gate transistor, the low-noise amplifier circuit 100 may also include a first tuning circuit 104, a second tuning circuit 105 and a third tuning circuit 106, which will not be described in detail here.

[0150] Alternatively, in some embodiments, the source of the third transistor T3 is coupled to the drain of the first transistor T1 in a switchable manner, and the gate of the third transistor T3 is coupled to the drain of the second transistor T2 in a switchable manner. For example, a first-stage matching circuit can be coupled between the drain of the first transistor T1 and the source of the third transistor T3, and a second-stage matching circuit can be coupled between the drain of the second transistor T2 and the gate of the third transistor T3. With the above configuration, when the first transistor T1 and the third transistor T3 are turned on, the third transistor T3 is a common-gate transistor and can perform an amplification function. When the second transistor T2 and the third transistor T3 are turned on, the third transistor T3 is a common-source transistor and can perform an amplification function.

[0151] In some embodiments, the low-noise amplifier circuit 100 may further include a second power supply circuit 102, which includes a plurality of second output terminals for outputting a plurality of different bias voltage signals.

[0152] For example, the second power supply circuit 102 can be a bandgap (reference source generation) module, which may include: multiple transistors M2, operational amplifier OP2, a resistor array, and diode M3. Taking transistor M2 as a PMOS transistor as an example, the output terminal of operational amplifier OP2 is coupled to the gate of transistor M2, the input terminal of operational amplifier OP2 is coupled to diode M3, the source of transistor M2 is coupled to the voltage input terminal, the drain of transistor M2 is coupled to the resistor array, and the resistor array is coupled to the output terminal of the bandgap. The resistor array includes multiple series-coupled resistors Rb, where each resistor Rb is coupled to one output terminal of the bandgap.

[0153] In some embodiments, the gate of the first transistor T1 is switchably coupled to one of a plurality of second output terminals. In some embodiments, the gate of the second transistor T2 is switchably coupled to one of a plurality of second output terminals.

[0154] For example, multiple second output terminals of the second power supply circuit 102 can be coupled to the gates of the first transistor T1 and the second transistor T2 via a switch array 180. By controlling the switch array 180, the second power supply circuit 102 can provide different bias voltage signals to the first transistor T1 and the second transistor T2, realizing an adjustable bias voltage design for the first transistor T1 and the second transistor T2. This allows the low-noise amplifier circuit 100 to achieve different linearities and noise performances, enabling it to switch between different standards. Furthermore, the output voltage of the bandgap module has load-carrying capacity. Alternatively, the output voltage of the bandgap module does not have load-carrying capacity and can provide a small supply current to the gates of the first transistor T1 and the second transistor T2.

[0155] In addition, a resistor R91 can be coupled between the second power supply circuit 102 and the gate of the first transistor T1, and a resistor R92 can be coupled between the second power supply circuit 102 and the gate of the second transistor T2. Resistors R91 and R92 are used to prevent radio frequency signals from entering the second power supply circuit 102.

[0156] In some embodiments, combined with Figure 2 , Figure 3 , Figure 14 as well as Figure 22 As shown, the low-noise amplifier circuit 100 may include a first power supply circuit 101, which includes a plurality of first output terminals for outputting a plurality of different bias voltage signals.

[0157] For example, the first power supply circuit 101 can be an LDO (low dropout regulator) module, which may include: an operational amplifier OP1, a voltage regulator transistor M0, a sampling circuit, and a load capacitor C0. Taking the voltage regulator transistor M0 as a PMOS transistor as an example, the output of the operational amplifier OP1 is coupled to the gate of the voltage regulator transistor M0, the source of the voltage regulator transistor M0 is coupled to the voltage input terminal, the drain of the voltage regulator transistor M0 is coupled to the sampling circuit, the output of the sampling circuit is coupled to the non-inverting input terminal of the operational amplifier OP1, one end of the load capacitor C0 is coupled to the voltage input terminal of the LDO, and the other end is coupled to ground. The sampling circuit may include multiple resistors Ra connected in series, wherein each resistor Ra is coupled to one output terminal of the LDO.

[0158] In some embodiments, the gate of the third transistor T3 is switchably coupled to one of a plurality of first output terminals. In some embodiments, the output matching circuit 120 is switchably coupled to one of a plurality of first output terminals.

[0159] For example, multiple first output terminals of the first power supply circuit 101 can be coupled to the gate of the third transistor T3 and the output matching circuit 120 through the switch array 190. By controlling the switch arrays 190 and 180, the first power supply circuit 101 can provide different bias voltage signals to the third transistor T3 and the output matching circuit 120, realizing an adjustable power supply bias voltage design for the third transistor T3 and the output matching circuit 120. This allows the low-noise amplifier circuit 100 to achieve different linearities and noise performances, enabling the low-noise amplifier circuit 100 to switch between different standards. Furthermore, the output voltage of the LDO module has load-carrying capacity, providing a large supply current to the drain and gate of the third transistor T3.

[0160] In addition, a resistor R80 can be coupled between the gate of the first power supply circuit 101 and the third transistor T3. This resistor is used to prevent radio frequency signals from entering the first power supply circuit 101.

[0161] Furthermore, the structures of the first power supply circuit and the second power supply circuit provided in the embodiments of this application do not constitute a limitation on the structure. They may include more or fewer components than shown in the figure, or combine certain components, or have different component arrangements.

[0162] Figure 23 This is a structural diagram of another low-noise amplifier circuit provided in an embodiment of this application.

[0163] In some embodiments, refer to Figure 23This application embodiment also provides a low-noise amplifier circuit 100, which may include an input matching circuit 110, a first amplifier circuit D1, a second amplifier circuit D2, a third amplifier circuit D3, and an output matching circuit 120.

[0164] The input matching circuit 110 receives and impedance-matches the radio frequency (RF) signal. A first amplifier circuit D1, coupled to the input matching circuit 110, processes RF signals in a first frequency band. A second amplifier circuit D2, also coupled to the input matching circuit 110, processes RF signals in a second frequency band. A third amplifier circuit D3 is selectively coupled to both the first and second amplifier circuits D1 and D2, and processes RF signals from either the first or second amplifier circuit. An output matching circuit 120, coupled to the third amplifier circuit D3, performs impedance matching on the RF signal from the third amplifier circuit D3 and outputs the impedance-matched RF signal.

[0165] For example, the specific structures of the input matching circuit 110, the first amplifier circuit D1, the second amplifier circuit D2, the third amplifier circuit D3, and the output matching circuit 120 can be as described in the above embodiments, and will not be repeated in this application embodiment. In this application embodiment, the inter-stage matching device 130 can be omitted. Both the circuit for processing the first frequency band RF signal and the circuit for processing the second frequency band RF signal can be referred to as a narrowband LNA. In this application embodiment, the processing of RF signals can achieve switching between narrowband LNAs. The first amplifier circuit D1 and the second amplifier circuit D2 share a port coupled to the input matching circuit 110, which helps to reduce the number of ports and thus reduce the area occupied by the low-noise amplifier circuit 100.

[0166] Furthermore, the low-noise amplifier circuit 100 may also include a first tuning circuit 104, a second tuning circuit 105, and a third tuning circuit 106, and the specific structures of the first tuning circuit 104, the second tuning circuit 105, and the third tuning circuit 106 may be as described in the above embodiments, and will not be repeated in this application embodiment.

[0167] In addition, the low-noise amplifier circuit 100 can also use the first power supply circuit 101 to adjust the bias power supply voltage of the third amplifier circuit D3 and the output matching circuit 120, and use the second power supply circuit 102 to adjust the bias power supply voltage of the first amplifier circuit D1 and the second amplifier circuit D2. The specific structures of the first power supply circuit 101 and the second power supply circuit 102 can be as described in the above embodiments, and will not be repeated in this application embodiment.

[0168] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A low-noise amplifier circuit, characterized in that, include: The first amplifier circuit is used to receive and process radio frequency signals in the first frequency band; The second amplifier circuit is used to receive and process radio frequency signals in the second frequency band; A third amplifier circuit is coupled to the first amplifier circuit and the second amplifier circuit in a switchable manner, and the third amplifier circuit is used to process the radio frequency signal from the first amplifier circuit or the second amplifier circuit. The number of interstage matching devices coupled between the first amplifier circuit and the third amplifier circuit is greater than the number of interstage matching devices coupled between the second amplifier circuit and the third amplifier circuit.

2. The low-noise amplifier circuit according to claim 1, characterized in that, The relative bandwidth of the first frequency band is greater than the relative bandwidth of the second frequency band.

3. The low-noise amplifier circuit according to claim 1 or 2, characterized in that, The relative bandwidth of the first frequency band is greater than or equal to 25%, and the relative bandwidth of the second frequency band is less than 25%.

4. The low-noise amplifier circuit according to any one of claims 1-3, characterized in that, The first amplifier circuit includes a first transistor, the gate of which is used to receive the radio frequency signal, and the drain of which is used to output the processed radio frequency signal. The second amplifier circuit includes a second transistor, the gate of which is used to receive the radio frequency signal, and the drain of which is used to output the processed radio frequency signal. The third amplifier circuit is coupled to the drain of the first transistor and the drain of the second transistor in a switchable manner.

5. The low-noise amplifier circuit according to claim 4, characterized in that, The third amplifier circuit includes a third transistor, the source of which is coupled to the drain of the first transistor and the drain of the second transistor in a switchable manner.

6. The low-noise amplifier circuit according to claim 5, characterized in that, The interstage matching devices are all coupled between the drain of the first transistor and the source of the third transistor.

7. The low-noise amplifier circuit according to claim 5 or 6, characterized in that, The interstage matching device includes a first inductor and a first capacitor. One end of the first inductor is coupled to the drain of the first transistor, and the other end of the first inductor is coupled to the source of the third transistor in a switchable manner. One end of the first capacitor is coupled to the first inductor, and the other end of the first capacitor is grounded.

8. The low-noise amplifier circuit according to claim 4, characterized in that, The third amplifier circuit includes a third transistor, the gate of which is electrically and in a switchable manner coupled to the drain of the first transistor and the drain of the second transistor.

9. The low-noise amplifier circuit according to claim 8, characterized in that, Some of the interstage matching devices constitute a first sub-circuit, and some of the interstage matching devices constitute a second sub-circuit. One end of the first sub-circuit is coupled to the gate of the third transistor, and the other end of the first sub-circuit is coupled to the second sub-circuit through an interstage capacitor. The second sub-circuit is coupled to the drain of the first transistor in a switchable manner. The other end of the first sub-circuit is also coupled to the drain of the second transistor in a switchable manner through the interstage capacitor.

10. The low-noise amplifier circuit according to claim 9, characterized in that, The first sub-circuit includes a second inductor and a second capacitor. The second inductor is coupled between the gate of the third transistor and the interstage capacitor. One end of the second capacitor is coupled to the second inductor, and the other end of the second capacitor is grounded. The second sub-circuit also includes a third inductor, one end of which is coupled to the interstage capacitor, and the other end of which is coupled to the drain of the first transistor in a switchable manner.

11. The low-noise amplifier circuit according to claim 4, characterized in that, The third amplifier circuit includes a third transistor, the gate of which is coupled to the drain of the first transistor in a switchable manner, and the source of which is coupled to the drain of the second transistor in a switchable manner.

12. The low-noise amplifier circuit according to claim 11, characterized in that, The interstage matching devices are all coupled between the drain of the first transistor and the gate of the third transistor.

13. The low-noise amplifier circuit according to any one of claims 5-12, characterized in that, The low-noise amplifier circuit further includes an output matching circuit, which is coupled to the drain of the third transistor. The output matching circuit is used to perform impedance matching on the radio frequency signal from the third amplifier circuit and output the impedance-matched radio frequency signal.

14. The low-noise amplifier circuit according to claim 13, characterized in that, The low-noise amplifier circuit includes a first power supply circuit, which includes a plurality of first output terminals, and the plurality of first output terminals are used to output a plurality of different bias voltage signals. The gate of the third transistor can be switched to be coupled to one of the plurality of first output terminals, or the output matching circuit can be switched to be coupled to one of the plurality of first output terminals.

15. The low-noise amplifier circuit according to any one of claims 4-14, characterized in that, It also includes an input matching circuit, which is coupled to the first amplifier circuit and the second amplifier circuit respectively. The input matching circuit is used to receive the radio frequency signal and perform impedance matching on the radio frequency signal.

16. The low-noise amplifier circuit according to claim 15, characterized in that, The low-noise amplifier circuit includes a second power supply circuit, which includes a plurality of second output terminals, and the plurality of second output terminals are used to output a plurality of different bias voltage signals. The first amplifier circuit includes a first transistor, the gate of which is switchably coupled to one of a plurality of second output terminals; or, The second amplifier circuit includes a second transistor whose gate is switchably coupled to one of a plurality of second output terminals.

17. The low-noise amplifier circuit according to any one of claims 4-16, characterized in that, The first amplifier circuit further includes a first tuning circuit, which is coupled between the source and the gate of the first transistor. The second amplifier circuit further includes a second tuning circuit coupled between the source and the gate of the second transistor.

18. The low-noise amplifier circuit according to any one of claims 4-17, characterized in that, The low-noise amplifier circuit further includes a third tuning circuit, one end of which is coupled to the source of the first transistor and the source of the second transistor, respectively, and the other end of which is grounded.

19. A chip, characterized in that, Includes the low-noise amplifier circuit according to any one of claims 1-18.

20. A communication device, characterized in that, It also includes at least one antenna and a chip as described in claim 19 above, the chip being coupled to the antenna.

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