A low-temperature readout circuit applied to an SNSPD array

Abstract

The application discloses a kind of cryogenic readout circuit applied to SNSPD array, it is related to readout circuit technical field.The application includes first-stage amplifier, second-stage amplifier, third-stage amplifier and fourth-stage amplifier in turn cascaded, and the imbalance storage circuit across the input end of first-stage amplifier and the input end of third-stage amplifier.The input end of first-stage amplifier is connected with the input end of second-stage amplifier, the input end of second-stage amplifier is connected with the input end of third-stage amplifier through AC coupling capacitor, the input end of third-stage amplifier is connected with the input end of fourth-stage amplifier, and the imbalance storage circuit is crossed between the input end of first-stage amplifier and the input end of third-stage amplifier.The application adopts low-power multi-stage amplification architecture and combines imbalance storage technology, can realize accurate readout of weak high-speed pulse signal in large-scale SNSPD array, while meeting the heat load limit requirements of cryogenic refrigeration system.

Description

Technical Field

[0001] This invention relates to the field of readout circuit technology, specifically a low-temperature readout circuit applied to SNSPD arrays. Background Technology

[0002] Superconducting nanowire single-photon detectors, with their superior detection efficiency, extremely low dark count rate, and excellent temporal resolution, have become a key core technology in the field of single-photon detection. With the development of applications such as quantum imaging and precision optical field analysis, single-photon detectors are inevitably evolving from single-pixel to large-scale arrays. Traditional solutions using broadband analog amplification technology to process high-speed pulse signals at room temperature generate power consumption far exceeding the thermal budget of the cooling system when the array size increases. To meet the thermal load limitations of large-scale arrays, the readout circuitry must be located in a cryogenic environment and employ a low-voltage, low-power, multi-stage cascaded architecture to directly amplify and read out the weak signals output by the array.

[0003] However, under the dual constraints of cryogenic temperatures and low power supply voltage, multi-stage amplifier circuits face an extremely severe technical bottleneck: mismatch in semiconductor transistor devices leads to significant input offset voltage in the preamplifier stage. Because the photon pulse signals output by the superconducting nanowire single-photon detector array are extremely weak, high-magnification amplification by multiple cascaded circuits is necessary to reach the range recognizable by subsequent stages. Under low-voltage power supply conditions, the input offset voltage generated by the first-stage amplifier is amplified drastically by the subsequent cascaded network. This easily causes the subsequent amplifier circuit to prematurely enter the nonlinear region or even saturate completely, preventing the true weak pulse signal from being properly amplified and extracted, and causing the system to lose its ability to recognize weak signals. Traditional offset calibration techniques often require the introduction of complex active feedback loops to achieve high-precision elimination, but this generates additional static power consumption, directly violating the stringent thermal balance limitations of cryogenic environments.

[0004] Therefore, this invention proposes a low-temperature readout circuit for SNSPD arrays. Summary of the Invention

[0005] The purpose of this invention is to provide a low-temperature readout circuit for SNSPD arrays, which effectively eliminates the influence of input offset voltage without introducing additional active power consumption, and avoids saturation of the amplification link due to excessive offset voltage, thereby ensuring accurate amplification and normal readout of extremely weak signals in superconducting nanowire single-photon detector arrays.

[0006] To achieve the above objectives, the present invention provides the following technical solution: a low-temperature readout circuit for SNSPD arrays, comprising a first-stage amplifier, a second-stage amplifier, a third-stage amplifier, and a fourth-stage amplifier cascaded in sequence; The output of the first stage amplifier is connected to the input of the second stage amplifier. The output of the second stage amplifier is connected to the input of the third stage amplifier through an AC coupling capacitor. The output of the third stage amplifier is connected to the input of the fourth stage amplifier. The output of the fourth stage amplifier serves as the output of the entire readout circuit. An offset storage circuit is connected between the input terminal of the first stage amplifier and the input terminal of the third stage amplifier. The offset storage circuit includes an offset storage capacitor connected between the output terminal of the second stage amplifier and the input terminal of the third stage amplifier, a switch disposed on the path from the signal input to the input terminal of the first stage amplifier, a switch disposed on the path from the input terminal of the first stage amplifier to ground, and a switch disposed on the path from the offset storage capacitor to ground between the input terminal of the third stage amplifier and the input terminal of the third stage amplifier.

[0007] Furthermore, the first stage amplifier adopts a diode-loaded differential amplifier structure, the second stage amplifier adopts a latch-loaded differential amplifier structure, the third stage amplifier adopts a self-biased differential amplifier structure, and the fourth stage amplifier adopts a source follower structure. The input terminal of the first stage amplifier receives the differential signal output by the SNSPD array, the input terminal of the second stage amplifier receives the differential signal output by the first stage amplifier, the input terminal of the third stage amplifier receives the differential signal output by the second stage amplifier through an AC coupling capacitor, and the input terminal of the fourth stage amplifier receives the single-ended signal output by the third stage amplifier.

[0008] Furthermore, the first-stage amplifier includes transistor M1 and transistor M... 2A Transistor M 2B Transistor M 3A and transistor M 3B ; The drain of transistor M1 and transistor M 2A The source is connected to the power supply VDD, and the gate is connected to the bias voltage V. bias Connected; The transistor M 2A The gate of transistor M is connected to ground (GND), and the drain is connected to transistor M. 3A The drain and source are connected to the drain of transistor M1; The transistor M 2B The source of is connected to the drain of transistor M1, and the drain is connected to the source of transistor M1. 3B The drain, gate, and offset of transistor M in the memory circuit 13A Drain connected; The transistor M 3A The drain is connected to the gate, the source is connected to ground (GND), and the drain is connected to the transistor M.2A Drain connected; The transistor M 3B The drain is connected to the gate, the source is connected to ground (GND), and the drain is connected to transistor M. 2B Drain connected; The transistor M 3A Transistor M 3B The drain output is connected to the input of the second-stage amplifier.

[0009] Furthermore, the second-stage amplifier includes transistor M. 4A Transistor M 4B Transistor M 5A Transistor M 5B Transistor M 6A Transistor M 6B ; The transistor M 4A The source is connected to the power supply VDD, and the drain is connected to the gate; The transistor M 4B The source is connected to the power supply VDD, and the drain is connected to the gate; The transistor M 5A The source is connected to the power supply VDD, and the drain is connected to the transistor M. 4A The drain and gate of transistor M are connected. 4B The drain electrode; The transistor M 5B The source is connected to the power supply VDD, and the drain is connected to the transistor M. 4B The drain and gate of transistor M are connected. 4A The drain electrode; The transistor M 6A The gate of the transistor is connected to the negative output terminal of the first-stage amplifier, the source is connected to ground (GND), and the drain is connected to transistor M. 4A The drains are connected; The transistor M 6B The gate of the transistor is connected to the positive output terminal of the first-stage amplifier, the source is connected to ground (GND), and the drain is connected to transistor M. 4B The drains are connected; The transistor M 6A The drain output is connected to the offset storage capacitor C2, and the transistor M 6B The drain output connection is misaligned, and the storage capacitor C1 is used.

[0010] Furthermore, the third-stage amplifier includes transistor M7 and transistor M... 8A Transistor M 8B Transistor M 9A Transistor M 9B Transistor M 10 ; The source of transistor M7 is connected to power supply VDD, and its gate is connected to transistor M. 8A The drain of the transistor is connected to the drain of transistor M. 8A The source pole; The transistor M 8A The source of transistor M7 is connected to the drain of transistor M7, and the drain of transistor M7 is connected to the source of transistor M7. 9A The drain and gate of transistor M are connected. 9A The gate; The transistor M 9A Source-connected transistor M 10 The drain of the transistor is connected to the gate of transistor M7, and the gate is connected to the offset storage capacitor C2. The transistor M 8B The source of transistor M7 is connected to the drain of transistor M7, and the drain of transistor M7 is connected to the source of transistor M7. 9B The drain and gate of transistor M are connected. 9B The gate; The transistor M 9B Source-connected transistor M 10 The drain of the transistor is connected to the input of the fourth-stage amplifier, and the gate is connected to transistor M. 8B The gate; The transistor M 10 The source is connected to ground (GND), the gate is connected to the gate of transistor M7, and the drain is connected to transistor M... 9B The source pole.

[0011] Furthermore, the fourth-stage amplifier includes transistor M. 11 Transistor M 12 ; The transistor M 11 The drain is connected to the power supply VDD, the source is connected to the fourth stage output, and the gate is connected to the third stage output. The transistor M 12 The source is connected to ground (GND), the gate is connected to the bias voltage, and the drain is connected to transistor M. 11 The source and pole are connected.

[0012] Furthermore, the offset storage circuit includes transistor M. 13A Transistor M 13B Transistor M 14A Transistor M 14B Transistor M 15A Transistor M 15B Transistor M 16A Transistor M 16B Offset storage capacitor C1 and offset storage capacitor C2; One end of the offset storage capacitor C1 is connected to transistor M. 6BThe drain of one end is connected to transistor M. 8B The gate; One end of the offset storage capacitor C2 is connected to transistor M. 6A The drain of one end is connected to transistor M. 8A The gate; The transistor M 13A The gate is connected to the enable signal EN, the drain is connected to the signal input, and the source is connected to the transistor M. 14A The drain electrode; The transistor M 13B The gate is connected to the enable signal ENB, the drain is connected to ground GND, and the source is connected to transistor M. 14A The drain electrode; The transistor M 14A The gate is connected to the enable signal ENB, the source is connected to the signal input, and the drain is connected to the transistor M. 14B The drain electrode; The transistor M 14B The gate is connected to the enable signal EN, the source is connected to ground GND, and the drain is connected to transistor M. 14A The drain electrode; The transistor M 15A The gate connection enable signal EN and the drain connection bias voltage V are used for connection. AZ Source connection misalignment storage capacitor C1; The transistor M 15B The gate connection enable signal EN, and the source connection bias voltage V AZ The drain connection is misaligned, and the storage capacitor C2 is also misaligned. The transistor M 16A The gate connection enable signal ENB and the source connection bias voltage V are connected. AZ The drain connection is misaligned, and the storage capacitor C1 is also misaligned. The transistor M 16B The gate connection enable signal ENB and the drain connection bias voltage V are connected. AZ Source connection misalignment storage capacitor C2.

[0013] Furthermore, in the offset storage circuit, the switch located on the path from the signal input to the input terminal of the first-stage amplifier is a transistor M. 13A and transistor M 14A The complementary first transmission gate is formed; The switch located on the path from the input terminal of the first-stage amplifier to ground is a transistor M. 13B and transistor M 14B The complementary second transmission gate is formed; The switch located on the ground path between the offset storage capacitor and the input terminal of the third-stage amplifier includes a transistor M.15A With transistor M 16A The third transmission gate is constructed, and the transistor M is used to construct it. 15B With transistor M 16B The fourth transmission gate is formed.

[0014] Furthermore, the transistors M1 and M 2A M 2B M 4A M 4B M 5A M 5B M7, M 8A M 8B M 14A M 14B M 15A M 15B Set as a PMOS transistor, transistor M 3A M 3B M 6A M 6B M 9A M 9B M 10 M 11 M 12 M 13A M 13B M 16A M 16B Configured as an NMOS transistor; The transistors M1 and M 12 The gate bias voltages are equal, both being V. bias ; The transistor M 15A M 16B The drain bias voltage and transistor M 15B M 16A The source bias voltages are equal, both being V. AZ ; The transistor M 13A M 14B M 15A M 15B The gate voltages are equal, both being enable signals EN; The transistor M 13B M 14A M 16A M 16B The gate voltages are equal, both being the enable signal ENB, which is the inverted signal of EN.

[0015] Furthermore, this includes the offset voltage storage state and the signal readout operating state; In the offset voltage storage state, the offset storage circuit collects the input offset voltage generated by the first stage amplifier and the second stage amplifier, and stores the amplified offset voltage on the offset storage capacitor; In the signal readout working state, the weak signal output by the SNSPD array is amplified by the first stage amplifier and the second stage amplifier. The offset voltage stored on the offset storage capacitor is subtracted from the current amplified signal voltage to eliminate the influence of the input offset voltage. The signal after offset elimination is amplified step by step by the third stage amplifier and the fourth stage amplifier before being output.

[0016] The present invention has at least the following beneficial effects: 1. This invention adopts a four-stage cascaded amplifier readout circuit architecture. The amplifiers at each stage transmit signals sequentially through direct coupling or AC coupling. The overall circuit structure is simple and the number of components is small. No additional complex bias or reference circuits are required. Therefore, it can operate stably under low-voltage power supply conditions in low-temperature environments, significantly reducing single-channel power consumption. This feature enables the invention to keep the total power consumption within the thermal budget of the cooling system when the SNSPD array scale is expanded. This effectively overcomes the bottleneck problem of traditional broadband analog amplification schemes restricting array scale due to excessive power consumption, and provides a feasible low-power solution for the readout circuit of large-scale quantum imaging systems.

[0017] 2. This invention connects an offset storage circuit between the input terminals of the first-stage amplifier and the third-stage amplifier. By utilizing the timing of multiple transmission gate switches controlled by the enable signal, the input offset voltage generated by the first two stages of amplifiers is amplified and stored on a capacitor during the offset storage stage. During the normal signal readout stage, this stored voltage is subtracted from the offset component in the signal path, thereby effectively canceling the input offset voltage at the circuit level. This mechanism can significantly reduce the impact of offset voltage on the amplification of weak signals, ensuring that the high-speed weak pulse signal output by the SNSPD array can still be accurately identified by the subsequent circuits after multi-stage amplification, effectively improving the detection capability of the readout circuit for weak signals.

[0018] 3. The first-stage amplifier of this invention adopts a diode-loaded differential amplifier structure, which has a large input bandwidth and can completely receive the high-speed pulse signal output by the SNSPD array without producing significant waveform distortion. The second-stage amplifier adopts a latch-loaded differential amplifier structure, which has negative exponential time-domain response characteristics and can quickly track and amplify the signal after the first-stage pre-amplification, effectively shortening the transmission delay. The third-stage amplifier adopts a self-biased differential amplifier structure with sufficient slew rate, which can achieve differential-to-single-ended output while further amplifying the signal. The fourth-stage amplifier adopts a source follower structure, which provides low impedance output to drive the subsequent load. The four amplifiers each play to their different advantages and work together to ensure that the entire readout circuit has good time-domain response characteristics and driving capability while ensuring sufficient gain and bandwidth, fully adapting to the multiple requirements of SNSPD array readout for speed, gain and output impedance.

[0019] Of course, any product implementing this invention does not necessarily need to achieve all of the advantages described above at the same time. Attached Figure Description

[0020] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0021] Figure 1 This is a schematic diagram of the topology of the readout circuit described in this invention; Figure 2 A schematic diagram of the external control signals used in this invention when the signal transmission time is 100µs; Figure 3 The output and external control signal simulation waveforms of this invention are shown when the input signal amplitude is 1mV, the period is 1us, and a total of 10 cycles are input. Figure 4 The output and external control signal simulation waveforms of this invention are shown when the input signal amplitude is 1mV, the period is 1us, and a total of 100 cycles are input. Detailed Implementation

[0022] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0023] This application provides a low-temperature readout circuit for superconducting nanowire single-photon detector (SNSPD) arrays. In the field of single-photon detection, SNSPDs have become core devices due to their high detection efficiency and low dark count rate. However, as applications evolve towards large-scale quantum imaging arrays, the system places extremely high demands on the signal readout at the back end. Traditional room-temperature broadband analog amplification schemes lead to a sharp increase in power consumption when dealing with large array sizes, far exceeding the thermal load limit of cryogenic cooling systems. While directly placing the readout circuit in an extremely low-temperature environment can meet thermal load limitations and reduce transmission losses, the extremely low temperature and low-voltage power supply environment can cause severe process deviations in semiconductor devices, resulting in extremely large input offset voltages. These offset voltages can easily cause premature saturation of subsequent circuits in multi-stage amplification links, completely drowning out weak photon pulse signals. Therefore, this application discloses a novel low-voltage, low-power readout architecture that effectively eliminates input offset voltages from the underlying physical structure by cleverly bridging offset storage circuits in multi-stage cascaded links, ensuring high-fidelity extraction of weak pulse signals.

[0024] Please see Figure 1 The present invention provides a technical solution: a low-temperature readout circuit for SNSPD arrays, comprising a first-stage amplifier, a second-stage amplifier, a third-stage amplifier and a fourth-stage amplifier cascaded in sequence; The output of the first-stage amplifier is connected to the input of the second-stage amplifier. The output of the second-stage amplifier is connected to the input of the third-stage amplifier through an AC coupling capacitor. The output of the third-stage amplifier is connected to the input of the fourth-stage amplifier. The output of the fourth-stage amplifier serves as the output of the entire readout circuit. An offset storage circuit is connected between the input terminals of the first-stage amplifier and the input terminals of the third-stage amplifier. The offset storage circuit includes an offset storage capacitor connected between the output terminal of the second stage and the input terminal of the third stage, a switch on the path from the signal input to the input terminal of the first-stage amplifier, a switch on the path from the input terminal of the first-stage amplifier to ground, and a switch on the path from the offset storage capacitor to ground between the input terminal of the third-stage amplifier and the offset storage capacitor.

[0025] Specifically, in terms of the interstage coupling mechanism, this embodiment abandons the traditional approach of full-link DC coupling and instead adopts a hybrid coupling strategy: except for the second-stage amplifier and the third-stage amplifier, the other adjacent amplifiers (i.e., between the first and second stages, and between the third and fourth stages) are directly DC coupled, with the voltage change at the output of the previous stage amplifier being directly transmitted to the input of the next stage amplifier; while the output of the second-stage amplifier is specifically transmitted to the input of the third-stage amplifier through an AC coupling capacitor; The input of the first-stage amplifier is used to receive the weak differential signal output by the SNSPD array, and the output of the fourth-stage amplifier serves as the final output node of the entire readout circuit. Meanwhile, to solve the offset accumulation problem of the preamplifier stage, this embodiment connects an offset storage circuit between the input of the first-stage amplifier and the input of the third-stage amplifier. It uses the gain of the first two stages to amplify the offset and uses the interstage AC coupling capacitor to retain the charge.

[0026] Regarding the technical solution of this embodiment, the first stage amplifier adopts a diode-loaded differential amplifier structure, the second stage amplifier adopts a latch-loaded differential amplifier structure, the third stage amplifier adopts a self-biased differential amplifier structure, and the fourth stage amplifier adopts a source follower structure. The input of the first-stage amplifier receives the differential signal output from the SNSPD array. The input of the second-stage amplifier receives the differential signal output from the first-stage amplifier. The input of the third-stage amplifier receives the differential signal output from the second-stage amplifier through an AC coupling capacitor. The input of the fourth-stage amplifier receives the single-ended signal output from the third-stage amplifier.

[0027] Regarding the technical solution of this embodiment, in terms of the specific microcircuit topology implementation, to meet the low-noise, high-bandwidth pre-amplification requirements of the front-end signal, the first-stage amplifier adopts a differential amplifier structure with diode-type loads, and its core components include transistor M1 and transistor M2. 2A Transistor M 2B Transistor M 3A and transistor M 3B ; Among them, the drain of transistor M1 and transistor M 2A The source is connected to the power supply VDD, and the gate is connected to the bias voltage V. bias Connected; transistor M 2A The gate of transistor M is connected to ground (GND), and the drain is connected to transistor M. 3A The drain and source of transistor M1 are connected to the drain of transistor M1; transistor M 2B The source of transistor M1 is connected to the drain of transistor M2, and the drain is connected to transistor M3. 3B The drain, gate, and offset of transistor M in the memory circuit 13A Drain connected; transistor M 3A The drain is connected to the gate, the source is connected to ground (GND), and the drain is connected to transistor M. 2A Drain connected; transistor M 3B The drain is connected to the gate, the source is connected to ground (GND), and the drain is connected to transistor M. 2B Drain connected; transistor M 3A Transistor M 3B The drain output is connected to the input of the second-stage amplifier; transistor M3A The drain of transistor M serves as the negative output terminal of the first-stage amplifier. 3B The drain of the transistor serves as the positive output terminal of the first-stage amplifier. The first-stage amplifier employs a differential amplifier structure with a diode load. This structure offers good swing and sufficient bandwidth, making it suitable for receiving and initially amplifying the weak signals output from the SNSPD array. Transistor M... 3A and transistor M 3B The drain and gate of the diode are shorted to form a diode connection, which serves as the load of the differential pair. This load structure has a low output impedance, which enables the first-stage amplifier to maintain a stable gain over a wide frequency range, meeting the amplification requirements of SNSPD high-speed pulse signals. At the same time, the diode-type load has better linearity and temperature stability than the resistive load, which is beneficial to maintaining the consistency of circuit performance in low-temperature environments.

[0028] The gain of the first stage amplifier for: In the formula, , , respectively transistor M 2A M 2B transistor M 3A M 3B The transconductance value.

[0029] Regarding the technical solution of this embodiment, the second-stage amplifier includes transistor M. 4A Transistor M 4B Transistor M 5A Transistor M 5B Transistor M 6A Transistor M 6B Transistor M 4A The source of transistor M is connected to the power supply VDD, and the drain is connected to the gate. 4B The source of transistor M is connected to the power supply VDD, and the drain is connected to the gate; 5A The source is connected to the power supply VDD, and the drain is connected to the transistor M. 4A The drain and gate of transistor M are connected. 4B The drain of the transistor; transistor M 5B The source is connected to the power supply VDD, and the drain is connected to the transistor M. 4B The drain and gate of transistor M are connected. 4A The drain of the transistor; transistor M 6A The gate of the transistor is connected to the negative output terminal of the first-stage amplifier, the source is connected to ground (GND), and the drain is connected to transistor M. 4A The drains of transistors M are connected; 6BThe gate of the transistor is connected to the positive output terminal of the first-stage amplifier, the source is connected to ground (GND), and the drain is connected to transistor M. 4B The drains of transistors M are connected; 6A Drain output connection misalignment storage capacitor C2, transistor M 6B Drain output connection misalignment storage capacitor C1; The second-stage amplifier employs a differential amplifier structure with a latch load. This structure not only boasts high gain but also exhibits a negative exponential time-domain response, enabling rapid response to signals pre-amplified by the preamplifier and providing a short propagation delay. The latch load is composed of transistor M. 4A M 4B M 5A M 5B Composition, in which transistor M 4A and M 4B For a diode-connected load transistor, transistor M 5A and M 5B Using cross-coupled positive feedback transistors, this structure utilizes a positive feedback mechanism to increase the equivalent output impedance of the second-stage amplifier, thereby achieving a higher voltage gain than traditional differential amplifiers. Simultaneously, the negative exponential response characteristic allows the second-stage amplifier to quickly establish an output voltage after receiving an input signal, reducing signal transmission delay, which is particularly important for the readout of SNSPD signals requiring precise time resolution.

[0030] The gain of the second-stage amplifier is: In the formula, , , Transistor M 4A M 4B transistor M 5A M 5B transistor M 6A M 6B The transconductance value.

[0031] Regarding the technical solution of this embodiment, the third-stage amplifier includes transistor M7 and transistor M... 8A Transistor M 8B Transistor M 9A Transistor M 9B Transistor M 10 ; In this transistor, the source of transistor M7 is connected to the power supply VDD, and the gate is connected to transistor M. 8A The drain of the transistor is connected to the drain of transistor M. 8A The source of the transistor; transistor M 8A The source of transistor M7 is connected to the drain of transistor M7, and the drain of transistor M7 is connected to the source of transistor M7. 9AThe drain and gate of transistor M are connected. 9A Gate of transistor M; 9A Source-connected transistor M 10 The drain of transistor M7 is connected to the gate of transistor M7, and the gate is connected to the offset storage capacitor C2; transistor M7... 8B The source of transistor M7 is connected to the drain of transistor M7, and the drain of transistor M7 is connected to the source of transistor M7. 9B The drain and gate of transistor M are connected. 9B Gate of transistor M; 9B Source-connected transistor M 10 The drain of the transistor is connected to the input of the fourth-stage amplifier, and the gate is connected to transistor M. 8B Gate of transistor M; 10 The source is connected to ground (GND), the gate is connected to the gate of transistor M7, and the drain is connected to transistor M... 9B The source pole; The third-stage amplifier employs a self-biased differential amplifier structure. This structure has a sufficiently large slew rate to further amplify the signal and achieve dual-to-single output conversion. The self-biased structure utilizes transistors M7 and M... 10 Transistor M forms a current mirror load. 8A M 8B M 9A M 9B Forming a differential input pair, the gate of transistor M7 receives the bias voltage through the offset storage capacitor C1. 10 The gate of the transistor is connected to the gate of transistor M7 to form a self-biased current source, which simplifies the circuit design and improves the power supply rejection ratio. At the same time, the self-biased structure has a large output slew rate, which can quickly respond to changes in the input signal, further amplify the differential signal output by the second stage amplifier and convert it into a single-ended signal output to the fourth stage amplifier. The gain of the three-stage amplifier is: In the formula, , Transistor M 8A M 8B transistor M 9A M 9B The transconductance value.

[0032] Regarding the technical solution of this embodiment, the fourth-stage amplifier includes transistor M. 11 Transistor M 12 ; transistor M 11 The drain of transistor M is connected to the power supply VDD, the source is connected to the fourth stage output, and the gate is connected to the third stage output; 12The source is connected to ground (GND), the gate is connected to the bias voltage, and the drain is connected to transistor M. 11 Source and pole connected; The fourth-stage amplifier employs a source follower structure to shift the output DC level. Transistor M 11 As the input transistor of the source follower, its gate receives the single-ended signal output from the third-stage amplifier, and the source follows the output. Transistor M 12 As a current source load, it is transistor M 11 Providing bias current, the source follower structure has a voltage gain close to 1. Its primary function is not to further amplify the signal amplitude, but to provide DC level shifting and low-impedance output drive capability. The output DC level of the fourth-stage amplifier is determined by transistor M. 12 The gate bias voltage Vbias and transistor size determine the output signal. With proper design, the output signal can be adjusted to the DC level range required by the subsequent circuit. At the same time, the low output impedance of the source follower enables it to drive a large capacitive load, ensuring the integrity of the signal during transmission. The gain of the fourth-stage amplifier is: In the formula, , Transistor M 11 transistor M 12 The transconductance value.

[0033] Regarding the technical solution of this embodiment, the offset storage circuit includes transistor M. 13A Transistor M 13B Transistor M 14A Transistor M 14B Transistor M 15A Transistor M 15B Transistor M 16A Transistor M 16B Offset storage capacitor C1 and offset storage capacitor C2; One end of the offset storage capacitor C1 is connected to transistor M. 6B The drain of one end is connected to transistor M. 8B The gate of the transistor; one end of the offset storage capacitor C2 is connected to transistor M. 6A The drain of one end is connected to transistor M. 8A Gate of transistor M; 13A The gate is connected to the external enable signal EN, the drain is connected to the input signal, and the source is connected to transistor M. 14A The drain of the transistor; transistor M 13B The gate is connected to the enable signal ENB, the drain is connected to ground GND, and the source is connected to transistor M. 14A The drain of the transistor; transistor M 14AThe gate is connected to the enable signal ENB, the source is connected to the signal input, and the drain is connected to the transistor M. 14B The drain of the transistor; transistor M 14B The gate is connected to the enable signal EN, the source is connected to ground GND, and the drain is connected to transistor M. 14A The drain of the transistor; transistor M 15A The gate connection enable signal EN and the drain connection bias voltage V are used for connection. AZ Source connection misalignment storage capacitor C1; transistor M 15B The gate connection enable signal EN, and the source connection bias voltage V AZ Drain connection misalignment, storage capacitor C2; transistor M 16A The gate connection enable signal ENB and the source connection bias voltage V are connected. AZ Drain connection misalignment storage capacitor C1; Transistor M 16B The gate connection enable signal ENB and the drain connection bias voltage V are connected. AZ Source connection misalignment storage capacitor C2.

[0034] Through four stages of amplification, the weak signal is amplified to a recognizable range. The fourth stage has a gain of approximately 1, providing a low-impedance output. The offset storage structure is connected across the first and second stages. During the offset voltage storage time, the amplified offset voltage Vos is stored on the capacitor, as follows: in, , The gains of the first-stage amplifier and the second-stage amplifier are V, respectively. os This is the input offset voltage.

[0035] During normal readout working hours, when inputting Vin, the following occurs: The final expression for the output voltage is: The offset storage technology used in the above formula can theoretically completely eliminate the influence of offset voltage.

[0036] Regarding the technical solution of this embodiment, in the offset storage circuit, the switch located on the path from the signal input to the input terminal of the first-stage amplifier is a transistor M. 13A and transistor M 14A The complementary first transmission gate is formed; The switch located on the path from the input of the first-stage amplifier to ground is controlled by transistor M. 13B and transistor M 14B The complementary second transmission gate is formed; The switch located on the path to ground between the offset storage capacitor and the input of the third-stage amplifier includes a transistor M. 15A With transistor M 16A The third transmission gate is constructed, and the transistor M is used to construct it. 15B With transistor M 16B The fourth transmission gate is formed.

[0037] Regarding the technical solution of this embodiment, transistor M 2A ~M 6A With transistor M 2B ~M 6B The dimensions are one-to-one equal, transistor M 8A M 9A With transistor M 8B M 9B The dimensions are one-to-one equal, transistor M 13A ~M 16A With transistor M 13B ~M 16B The equal dimensions of the transistors in the differential amplifier ensure the circuit symmetry of the differential amplifier structure, thereby ensuring that the two paths of the differential signal have matched electrical characteristics and reducing the additional offset voltage caused by process variations. In a differential amplifier, if the transistor dimensions of the two signal paths are mismatched, even if the input differential signal is zero, an output voltage, i.e., an additional offset voltage, will be generated due to the difference in transistor characteristics. By setting the transistor dimensions at corresponding positions to be equal, the mismatch caused by process variations can be minimized, improving the common-mode rejection ratio and offset voltage performance of the differential amplifier.

[0038] Regarding the technical solution of this embodiment, transistors M1 and M 2A M 2B M 4A M 4B M 5A M 5B M7, M 8A M 8B M 14A M 14B M 15A M 15B Set as a PMOS transistor, transistor M 3A M 3B M 6A M 6B M 9A M 9B M 10 M 11 M 12 M 13A M 13B M 16A M16B Configured as an NMOS transistor; Transistors M1, M 12 The gate bias voltages are equal, both being V. bias ; transistor M 15A M 16B The drain bias voltage and transistor M 15B M 16A The source bias voltages are equal, both being V. AZ ; transistor M 13A M 14B M 15A M 15B The gate voltages are equal, both being enable signals EN; transistor M 13B M 14A M 16A M 16B The gate voltages are equal, both being the enable signal ENB, which is the inverted signal of EN.

[0039] The technical solution of this embodiment includes an offset voltage storage state and a signal readout working state; In the offset voltage storage state, the offset storage circuit collects the input offset voltage generated by the first-stage amplifier and the second-stage amplifier, and stores the amplified offset voltage on the offset storage capacitor. In signal readout mode, the weak signal output by the SNSPD array is amplified by the first and second stage amplifiers. The offset voltage stored on the offset storage capacitor is subtracted from the current amplified signal voltage to eliminate the influence of the input offset voltage. The signal after offset elimination is amplified step by step by the third and fourth stage amplifiers before being output.

[0040] To ensure effective signal readout, the offset voltage storage time accounts for only 1% of the total signal transmission time. Taking a 100µs signal transmission time as an example, the circuit offset voltage storage time is approximately 1µs. The timing diagram of the external enable signal EN at this time is shown below. Figure 2 As shown.

[0041] In the offset voltage storage state, the enable signal EN is low and ENB is high, transistor M 13A and transistor M 14A The first transmission gate is disconnected, and transistor M... 13B and transistor M 14B The second transmission gate is activated, shorting the input of the first-stage amplifier to ground; simultaneously, transistor M... 15A and transistor M 16A The third transmission gate is turned on, and transistor M...15B and transistor M 16B The fourth transmission gate is activated, connecting one end of offset storage capacitors C1 and C2 to the bias voltage VAZ. At this time, the first and second stage amplifiers amplify their own input offset voltages and store them on offset storage capacitors C1 and C2, respectively. Specifically, since the input terminal of the first stage amplifier is shorted to ground, the input differential signal is zero. However, the input offset voltage Vos caused by the transistor mismatch between the first and second stage amplifiers is amplified and appears at the output terminal of the second stage amplifier, i.e., at the transistor M. 16A and M 16B The drain of the capacitor. Offset storage capacitors C1 and C2 are charged through the conducting third and fourth transmission gates, storing the amplified offset voltage as charge on the capacitors. The bias voltage VAZ provides a stable charging reference voltage for the capacitors, ensuring that the stored offset voltage has a defined level reference.

[0042] In signal readout mode, the enable signal EN is high and ENB is low, the first transmission gate is on, and the second transmission gate is off. The weak signal output by the SNSPD array is connected to the input of the first-stage amplifier. Simultaneously, the third and fourth transmission gates are off, and the offset voltages stored on offset storage capacitors C1 and C2 are superimposed on the input of the third-stage amplifier, subtracting the signal voltage output by the second-stage amplifier, thus eliminating the influence of the input offset voltage. Specifically, in the signal readout stage, the weak signal Vin output by the SNSPD array, after being amplified by the first and second-stage amplifiers, has the opposite polarity to the voltage stored on the capacitors during the offset voltage storage stage. When the signal voltage output by the second-stage amplifier is transmitted to the input of the third-stage amplifier through the AC coupling capacitor, the offset voltage stored on the offset storage capacitors is superimposed on the input of the third-stage amplifier with the opposite polarity, so that the voltage actually received by the third-stage amplifier is the difference between the signal voltage and the offset voltage, thereby canceling the offset voltage.

[0043] The technical solution of this invention will be further elaborated below with reference to specific simulation experiments: Figure 3 , Figure 4 The simulation results of the circuit designed in this invention are shown below. Figure 3 , Figure 4 The waveform shown in INPUT is the input signal of the circuit designed in this invention, specifically a pulse width signal with an amplitude of 1mV and a period of 1us. Figure 3 , Figure 4 The waveform shown in OUTPUT is the output signal of the circuit designed in this invention when the input is the INPUT signal; Figure 3 , Figure 4The waveform corresponding to EN in this invention is the offset storage voltage enable signal of the circuit designed in this invention when the input is an INPUT signal. Figure 3 The waveform diagrams showing the output and enable signals when a 10-cycle pulse width input signal is displayed show that when EN is low, the circuit is in the offset voltage storage period and does not read any input signal; when EN is high, the circuit can amplify and read the input signal normally. Figure 4 The waveform diagram shows the output and enable signals when a 100µs pulse width signal is input. The circuit designed in this invention can still accurately read weak pulse width input signals.

[0044] In summary, in the readout circuit of this invention, the first-stage amplifier adopts a differential amplifier structure with diode load, which has a good swing and a sufficiently large bandwidth; the second-stage amplifier adopts a differential amplifier structure with latch load, which not only has high gain but also can quickly respond to signals pre-amplified by the preamplifier and has a short propagation delay; the third-stage amplifier adopts a self-biased differential amplifier structure, which has a sufficiently large slew rate to further amplify the signal and achieve dual-to-single output; the fourth-stage amplifier adopts a source follower structure to shift the output DC level, and the offset storage circuit connected between the first and second stages can effectively reduce the input offset voltage and avoid the inability to amplify weak signals properly due to excessive offset voltage; Furthermore, in low-temperature circuits, excessively high drain-source voltage will cause a nonlinear increase in current. The low-temperature readout circuit of this invention has a simple structure, is suitable for low-voltage applications, and has low power consumption characteristics, so it can be used on a large scale in SNSPD arrays. The low-temperature readout circuit of this invention adopts an offset storage circuit, which effectively reduces the input offset voltage and can be applied to the identification of smaller signals.

[0045] In the description of this specification, the references to terms such as "an embodiment," "example," "specific example," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0046] The foregoing has shown and described the basic principles, main features, and advantages of this application. Those skilled in the art should understand that this application is not limited to the above embodiments. The embodiments and descriptions in the specification are merely illustrative of the principles of this application. Various changes and modifications can be made to this application without departing from the spirit and scope thereof, and all such changes and modifications fall within the scope of the claims of this application.

Claims

1. A low-temperature readout circuit for SNSPD arrays, characterized in that, This includes a first-stage amplifier, a second-stage amplifier, a third-stage amplifier, and a fourth-stage amplifier cascaded in sequence. The output of the first stage amplifier is connected to the input of the second stage amplifier. The output of the second stage amplifier is connected to the input of the third stage amplifier through an AC coupling capacitor. The output of the third stage amplifier is connected to the input of the fourth stage amplifier. The output of the fourth stage amplifier serves as the output of the entire readout circuit. An offset storage circuit is connected between the input terminal of the first stage amplifier and the input terminal of the third stage amplifier. The offset storage circuit includes an offset storage capacitor connected between the output terminal of the second stage amplifier and the input terminal of the third stage amplifier, a switch disposed on the path from the signal input to the input terminal of the first stage amplifier, a switch disposed on the path from the input terminal of the first stage amplifier to ground, and a switch disposed on the path from the offset storage capacitor to ground between the input terminal of the third stage amplifier and the input terminal of the third stage amplifier.

2. The low-temperature readout circuit for SNSPD arrays according to claim 1, characterized in that: The first stage amplifier adopts a diode-loaded differential amplifier structure, the second stage amplifier adopts a latch-loaded differential amplifier structure, the third stage amplifier adopts a self-biased differential amplifier structure, and the fourth stage amplifier adopts a source follower structure. The input terminal of the first stage amplifier receives the differential signal output by the SNSPD array, the input terminal of the second stage amplifier receives the differential signal output by the first stage amplifier, the input terminal of the third stage amplifier receives the differential signal output by the second stage amplifier through an AC coupling capacitor, and the input terminal of the fourth stage amplifier receives the single-ended signal output by the third stage amplifier.

3. The low-temperature readout circuit for SNSPD arrays according to claim 2, characterized in that: The first stage amplifier includes transistor M1 and transistor M2. 2A Transistor M 2B Transistor M 3A and transistor M 3B ; The drain of transistor M1 and transistor M 2A The source is connected to the power supply VDD, and the gate is connected to the bias voltage V. bias Connected; The transistor M 2A The gate of transistor M is connected to ground (GND), and the drain is connected to transistor M. 3A The drain and source are connected to the drain of transistor M1; The transistor M 2B The source of is connected to the drain of transistor M1, and the drain is connected to the source of transistor M1. 3B The drain, gate, and offset of transistor M in the memory circuit 13A Drain connected; The transistor M 3A The drain is connected to the gate, the source is connected to ground (GND), and the drain is connected to the transistor M. 2A Drain connected; The transistor M 3B The drain is connected to the gate, the source is connected to ground (GND), and the drain is connected to transistor M. 2B Drain connected; The transistor M 3A Transistor M 3B The drain output is connected to the input of the second-stage amplifier.

4. A low-temperature readout circuit for an SNSPD array according to claim 3, characterized in that: The second-stage amplifier includes transistor M 4A Transistor M 4B Transistor M 5A Transistor M 5B Transistor M 6A Transistor M 6B ; The transistor M 4A The source is connected to the power supply VDD, and the drain is connected to the gate; The transistor M 4B The source is connected to the power supply VDD, and the drain is connected to the gate; The transistor M 5A The source is connected to the power supply VDD, and the drain is connected to the transistor M. 4A The drain and gate of transistor M are connected. 4B The drain electrode; The transistor M 5B The source is connected to the power supply VDD, and the drain is connected to the transistor M. 4B The drain and gate of transistor M are connected. 4A The drain electrode; The transistor M 6A The gate of the transistor is connected to the negative output terminal of the first-stage amplifier, the source is connected to ground (GND), and the drain is connected to transistor M. 4A The drains are connected; The transistor M 6B The gate of the transistor is connected to the positive output terminal of the first-stage amplifier, the source is connected to ground (GND), and the drain is connected to transistor M. 4B The drains are connected; The transistor M 6A The drain output is connected to the offset storage capacitor C2, and the transistor M 6B The drain output connection is misaligned, and the storage capacitor C1 is used.

5. A low-temperature readout circuit for an SNSPD array according to claim 4, characterized in that: The third-stage amplifier includes transistor M7 and transistor M. 8A Transistor M 8B Transistor M 9A Transistor M 9B Transistor M 10 ; The source of transistor M7 is connected to power supply VDD, and its gate is connected to transistor M. 8A The drain of the transistor is connected to the drain of transistor M. 8A The source pole; The transistor M 8A The source of transistor M7 is connected to the drain of transistor M7, and the drain of transistor M7 is connected to the source of transistor M7. 9A The drain and gate of transistor M are connected. 9A The gate; The transistor M 9A Source-connected transistor M 10 The drain of the transistor is connected to the gate of transistor M7, and the gate is connected to the offset storage capacitor C2. The transistor M 8B The source of transistor M7 is connected to the drain of transistor M7, and the drain of transistor M7 is connected to the source of transistor M7. 9B The drain and gate of transistor M are connected. 9B The gate; The transistor M 9B Source-connected transistor M 10 The drain of the transistor is connected to the input of the fourth-stage amplifier, and the gate is connected to transistor M. 8B The gate; The transistor M 10 The source is connected to ground (GND), the gate is connected to the gate of transistor M7, and the drain is connected to transistor M... 9B The source pole.

6. A low-temperature readout circuit for an SNSPD array according to claim 5, characterized in that: The fourth-stage amplifier includes transistor M. 11 Transistor M 12 ; The transistor M 11 The drain is connected to the power supply VDD, the source is connected to the fourth stage output, and the gate is connected to the third stage output. The transistor M 12 The source is connected to ground (GND), the gate is connected to the bias voltage, and the drain is connected to transistor M. 11 The source and pole are connected.

7. A low-temperature readout circuit for an SNSPD array according to claim 6, characterized in that: The offset storage circuit includes transistor M. 13A Transistor M 13B Transistor M 14A Transistor M 14B Transistor M 15A Transistor M 15B Transistor M 16A Transistor M 16B Offset storage capacitor C1 and offset storage capacitor C2; One end of the offset storage capacitor C1 is connected to transistor M. 6B The drain of one end is connected to transistor M. 8B The gate; One end of the offset storage capacitor C2 is connected to transistor M. 6A The drain of one end is connected to transistor M. 8A The gate; The transistor M 13A The gate is connected to the enable signal EN, the drain is connected to the signal input, and the source is connected to the transistor M. 14A The drain electrode; The transistor M 13B The gate is connected to the enable signal ENB, the drain is connected to ground GND, and the source is connected to transistor M. 14A The drain electrode; The transistor M 14A The gate is connected to the enable signal ENB, the source is connected to the signal input, and the drain is connected to the transistor M. 14B The drain electrode; The transistor M 14B The gate is connected to the enable signal EN, the source is connected to ground GND, and the drain is connected to transistor M. 14A The drain electrode; The transistor M 15A The gate connection enable signal EN and the drain connection bias voltage V are used for connection. AZ Source connection misalignment storage capacitor C1; The transistor M 15B The gate connection enable signal EN, and the source connection bias voltage V AZ The drain connection is misaligned, and the storage capacitor C2 is also misaligned. The transistor M 16A The gate connection enable signal ENB and the source connection bias voltage V are connected. AZ The drain connection is misaligned, and the storage capacitor C1 is also misaligned. The transistor M 16B The gate connection enable signal ENB and the drain connection bias voltage V are connected. AZ Source connection misalignment storage capacitor C2.

8. A low-temperature readout circuit for an SNSPD array according to claim 7, characterized in that: In the offset storage circuit, the switch located on the path from the signal input to the input terminal of the first-stage amplifier is a transistor M. 13A and transistor M 14A The complementary first transmission gate is formed; The switch located on the path from the input terminal of the first-stage amplifier to ground is a transistor M. 13B and transistor M 14B The complementary second transmission gate is formed; The switch located on the ground path between the offset storage capacitor and the input terminal of the third-stage amplifier includes a transistor M. 15A With transistor M 16A The third transmission gate is constructed, and the transistor M is used to construct it. 15B With transistor M 16B The fourth transmission gate is formed.

9. A low-temperature readout circuit for an SNSPD array according to claim 1, characterized in that: The transistors M1 and M 2A M 2B M 4A M 4B M 5A M 5B M7, M 8A M 8B M 14A M 14B M 15A M 15B Set as a PMOS transistor, transistor M 3A M 3B M 6A M 6B M 9A M 9B M 10 M 11 M 12 M 13A M 13B M 16A M 16B Configured as an NMOS transistor; The transistors M1 and M 12 The gate bias voltages are equal, both being V. bias ; The transistor M 15A M 16B The drain bias voltage and transistor M 15B M 16A The source bias voltages are equal, both being V. AZ ; The transistor M 13A M 14B M 15A M 15B The gate voltages are equal, both being enable signals EN; The transistor M 13B M 14A M 16A M 16B The gate voltages are equal, both being the enable signal ENB, which is the inverted signal of EN.

10. A low-temperature readout circuit for an SNSPD array according to claim 8, characterized in that, This includes the offset voltage storage state and the signal readout working state; In the offset voltage storage state, the offset storage circuit collects the input offset voltage generated by the first stage amplifier and the second stage amplifier, and stores the amplified offset voltage on the offset storage capacitor; In the signal readout working state, the weak signal output by the SNSPD array is amplified by the first stage amplifier and the second stage amplifier. The offset voltage stored on the offset storage capacitor is subtracted from the current amplified signal voltage to eliminate the influence of the input offset voltage. The signal after offset elimination is amplified step by step by the third stage amplifier and the fourth stage amplifier before being output.

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