A method and system for high-precision analog front-end output and R2R volume collaborative control

Abstract

The application discloses a kind of high-precision analog front-end output and R2R volume collaborative control method and system, belong to volume control technical field, including: based on the DAC type R2R ladder resistance network of independent reference voltage input terminal realization.For R2R code word switching, each branch on-off timing is arranged according to bit weight difference value gradient stagger;By integrated current DAC, difference mode compensation current is injected to front-end in-phase input bias node, to bias stable state as sampling effective determination condition;R2R output voltage is converted to front-end output end equivalent reference plane, and then difference coupling operation is carried out, to obtain collaborative error amount;Collaborative error amount is decomposed into amplitude and timing component, and double working mode decoupling closed-loop control is used, and parameter output instruction is locked after convergence.The application significantly suppresses switching transient impact and audible distortion, ensures volume consistency and linearity, and is suitable for mass production audio equipment.

Description

Technical Field

[0001] This invention relates to the field of volume control technology, specifically to a method and system for high-precision analog preamp output and R2R volume coordinated control. Background Technology

[0002] In audio systems that use DAC-type R2R ladder resistor networks with independent reference voltage inputs for digital volume control, when digital codewords are switched, the switching actions of each branch in the R2R network often occur simultaneously or in a disordered timing sequence, resulting in significant transient voltage and current interference at the output nodes.

[0003] Such transient interference can easily affect the bias operating point of the preamplifier through signal path or power supply coupling, causing the preamplifier to deviate from its stable static operating state at the moment of switching, thereby introducing audible transient distortion or noise at the audio output.

[0004] Taking the major carry codeword switching from 01111111 to 10000000 as an example, at this time, the high-weight branch and multiple low-weight branches flip simultaneously. The resulting current spike will cause the bias current of the preamplifier to fluctuate instantaneously, resulting in a noticeable "click" sound in the output signal or a sharp increase in short-term harmonic distortion. This artifact is more prominent at low volumes or when the preamplifier gain is high, which seriously affects the continuity and purity of the sound quality. Summary of the Invention

[0005] In view of the above-mentioned problems, the present invention provides a method and system for high-precision analog preamp output and R2R volume coordinated control.

[0006] Therefore, the technical problem solved by this invention is: how to suppress the high rate of change voltage surge of the DAC-type R2R digital volume network at the moment of code word switching, to offset its disturbance to the differential operating point of the preamplifier, and to eliminate the "click" sound and transient harmonic distortion during the volume switching process; at the same time, to overcome the influence of non-ideal factors such as temperature drift, device discreteness, and load effect, and to achieve high-precision coordination between analog preamplifier output and R2R volume control without destroying the consistency of volume control or sacrificing the full-range linearity of R2R.

[0007] To solve the above-mentioned technical problems, the present invention provides the following technical solution: a method for high-precision analog preamplifier output and R2R volume coordinated control, the method being implemented based on a DAC-type R2R stepped resistor network with an independent reference voltage input terminal, comprising the following steps: staggering the on / off timing of each branch of the R2R stepped resistor network during adjacent codeword switching, generating a bit switching timing diagram based on the bit weight difference between the current codeword and the target codeword; injecting differential-mode compensation current into the non-inverting input bias node of the preamplifier via the integrated current DAC through a current-limiting isolation network using the bit switching timing diagram, obtaining a bias stable state; using the bias stable state as the valid sampling criterion, pre-calculating the preamplifier based on the static calibration... The amplitude-frequency transfer function and group delay parameters are used to calculate the output node voltage of the R2R stepped resistor network to the equivalent reference plane at the output of the preamplifier. Differential coupling is then performed to obtain the cooperative error. This cooperative error is decomposed into amplitude error and timing error components. The amplitude error component is fed back to the reference voltage of the R2R stepped resistor network, and the timing error component performs closed-loop correction on the interleaving interval of the bit switching timing diagram. A dual-mode design is adopted: in normal operation mode, the reference voltage maintains the calibrated global value; in calibration mode, the reference voltage is adjusted in a ramp manner at the zero-crossing point of the audio signal. When the cooperative error converges to within the accuracy threshold, the current interleaving interval is locked, and a cooperative control command is output.

[0008] As a preferred embodiment of the high-precision analog preamplifier output and R2R volume coordinated control method described in this invention, the step of performing the interleaved arrangement includes: arranging each branch in the R2R ladder resistor network according to its bit weight from high to low, and calculating the bit weight difference between each branch of adjacent codewords; based on the bit weight difference, allocating priority switching time slots to the branches corresponding to the bit weight differences in the first N positions, and allocating delay time slots to the remaining branches to form a gradient distribution; using the combination of the current codeword and the target codeword as the index key, performing a nearest neighbor search in the historical codeword feature library to obtain the historical optimal parameter set; and weighting and fusing the historical optimal parameter set with the real-time interleaving interval according to a preset weight to generate a bit switching timing diagram.

[0009] As a preferred embodiment of the high-precision analog preamplifier output and R2R volume coordinated control method described in this invention, the step of injecting the compensation current includes: extracting the node voltage prediction offset of the R2R stepped resistor network according to the priority switching time slot and delay time slot of each branch in the bit switching timing diagram; converting the node voltage prediction offset into the compensation current value of the corresponding time slot according to the pre-calibrated full-range transmission characteristic curve of the preamplifier bias node voltage-compensation current; injecting the corrected compensation current value into the non-inverting input bias node of the preamplifier at the beginning of the corresponding time slot using a single-ended differential injection method, while keeping the reference bias unchanged at the inverting input; and obtaining the bias stable state in response to the change of the preamplifier's static operating current within the time window covered by the bit switching timing diagram being less than a preset threshold.

[0010] As a preferred embodiment of the high-precision analog preamplifier output and R2R volume coordinated control method described in this invention, the step of correcting the compensation current value based on the temperature distribution vector includes: setting up temperature sampling points at key nodes of each branch of the R2R stepped resistor network and at the preamplifier bias node, collecting the temperature value of each sampling point according to a preset sampling period, and constructing a temperature distribution vector; calculating the position weight difference value offset caused by temperature change based on the temperature distribution vector and the temperature coefficient parameters of each branch resistor; superimposing the position weight difference value offset onto the original position weight difference value, and recalculating according to the full-range transmission characteristic curve of the preamplifier bias node to obtain the corrected compensation current value.

[0011] As a preferred embodiment of the high-precision analog preamplifier output and R2R volume collaborative control method described in this invention, the differential coupling operation includes the following steps: employing a dual-ADC synchronous sampling architecture, using the bit switching start time as the synchronization reference, performing dual-band dual-window sampling: the audio steady-state frequency band is sampled using a long window with a low sampling rate before and after switching, and the switching transient disturbance frequency band is sampled using a short window with a high sampling rate including the switching process; the output node voltage of the R2R stepped resistor network and the output voltage of the preamplifier are sampled; the two sets of voltages are weighted and subtracted in the frequency domain according to their respective frequency component weights to obtain an intermediate difference set within the sampling window; the amplitude and phase deviation of the intermediate difference set is extracted to obtain an intermediate error; and the intermediate error is fused and corrected according to the weighted harmonic distortion index to obtain a collaborative error.

[0012] As a preferred embodiment of the high-precision analog preamplifier output and R2R volume collaborative control method described in this invention, the step of performing fusion correction includes: performing spectrum analysis on the output voltage of the preamplifier to extract the amplitude vectors of the second to Mth harmonics; using the fundamental frequency amplitude of the audio as a normalization reference, weighting and summing the ratios of each harmonic amplitude to the fundamental frequency amplitude in the amplitude vector according to the perception weight coefficients of each harmonic to construct a weighted harmonic distortion function and calculate the weighted harmonic distortion index; and weighting and fusing the weighted harmonic distortion index with the intermediate error to obtain the collaborative error.

[0013] As a preferred embodiment of the high-precision analog preamp output and R2R volume collaborative control method described in this invention, the step of closed-loop correction of the interleaving interval of the bit switching timing diagram includes: extracting amplitude error components mainly based on the amplitude deviation of the audio frequency band, and extracting timing error components mainly based on the phase deviation of the switching transient frequency band; in calibration mode, according to a preset correspondence, converting the amplitude error components into voltage adjustment amounts at the reference voltage terminal, and converting the timing error components into interleaving interval correction amounts; in calibration mode, applying the voltage adjustment amounts in a ramp manner at the zero-crossing point of the audio signal to the reference voltage terminal of the R2R stepped resistor network; taking the minimization of the collaborative error amount as the optimization objective, determining the iterative adjustment direction of the delay slot duration according to the gradient descent strategy; in response to the collaborative error amount converging to within the accuracy threshold, locking the current interleaving interval, stopping the correction, and outputting a collaborative control command.

[0014] As a preferred embodiment of the high-precision analog preamp output and R2R volume collaborative control method described in this invention, the gradient descent strategy includes the following steps: calculating the gradient value of the collaborative error amount relative to the delay slot duration; determining the sign of the gradient value; if the gradient value is positive, determining the iterative adjustment direction to shorten the delay slot duration; if the gradient value is negative, determining the iterative adjustment direction to extend the delay slot duration.

[0015] As a preferred embodiment of the method for high-precision analog preamp output and R2R volume collaborative control described in this invention, the step of locking the current interleaving interval includes: preset the number of consecutive iterations, the adaptive error dead zone, and the harmonic suppression threshold; when the collaborative error amount converges to within the precision threshold within the preset number of consecutive iterations, and the weighted harmonic distortion index drops below the preset harmonic suppression threshold and the error fluctuation is less than the adaptive error dead zone, the current interleaving interval is locked, the correction is stopped, and a low harmonic distortion collaborative control command is output.

[0016] This invention provides a system for high-precision analog preamp output and R2R volume coordinated control.

[0017] To solve the above technical problems, the present invention provides the following technical solution: a system for high-precision analog preamplifier output and R2R volume coordinated control, the system being used to control a DAC-type R2R stepped resistor network with an independent reference voltage input terminal and a preamplifier, comprising: a timing control module for interleaving the on / off timing of each branch of the R2R stepped resistor network during adjacent codeword switching to generate a bit switching timing diagram; a bias compensation module for injecting compensation current into the non-inverting input bias node of the preamplifier according to the bit switching timing diagram to obtain a stable bias state; and error coupling. The module is used to perform differential coupling calculations on the output node voltage of the R2R stepped resistor network and the output voltage of the preamplifier, using the bias stable state as the sampling validity determination condition, to obtain the cooperative error quantity; the closed-loop correction module is used to decompose the cooperative error quantity into an amplitude error component and a timing error component, the amplitude error component is fed back to the reference voltage terminal of the R2R stepped resistor network, and the timing error component performs closed-loop correction on the interleaving interval of the bit switching timing diagram. In response to the cooperative error quantity converging to within the accuracy threshold, the current interleaving interval is locked and a cooperative control command is output.

[0018] The beneficial effects of this invention are as follows: By using the bias stable state as the gating condition, frequency-domain weighted differential coupling calculations are performed on the output node voltage of the R2R stepped resistor network and the output voltage of the preamplifier. The amplitude and phase deviations are extracted and fused with the weighted harmonic distortion index to obtain the cooperative error. This cooperative error is then fed back to the reference voltage terminal of the R2R stepped resistor network. Simultaneously, the delay slot duration in the bit switching timing diagram is corrected in a closed loop according to the gradient descent strategy. The preamplifier bias stability is maintained by differential mode compensation injection through an integrated current DAC via a current-limiting isolation network. The accuracy of error calculation is ensured by dual-ADC dual-band sampling aligned with the reference plane. Volume jumps are avoided by dual operating modes and ramp zero-crossing adjustment. Transient interference of the R2R network output node on the preamplifier bias state during codeword switching is suppressed, and harmonic distortion and audible artifacts during switching are reduced. This achieves high-precision cooperative control of the analog preamplifier output and R2R volume. Attached Figure Description

[0019] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1 The above is a flowchart of a method for high-precision analog preamp output and R2R volume coordinated control provided in one embodiment of the present invention. Detailed Implementation

[0021] To make this invention more easily understood, the specific embodiments of the invention will be described in detail below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this invention, not all of them. Based on the embodiments of this invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the protection scope of this invention.

[0022] Example 1, referring to Figure 1 This is one embodiment of the present invention, which provides a method for high-precision analog preamplifier output and R2R volume coordinated control. The method is implemented based on a DAC-type R2R stepped resistor network with an independent reference voltage input, and includes:

[0023] When switching between adjacent codewords, the on / off timing of each branch of the R2R ladder resistor network is staggered, and a bit switching timing diagram is generated based on the bit weight difference between the current codeword and the target codeword.

[0024] Using the bit switching timing diagram, differential mode compensation current is injected from the integrated current DAC through a current limiting isolation network into the non-inverting input bias node of the front-stage amplifier to obtain a stable bias state.

[0025] Using the aforementioned bias stable state as the valid sampling criterion, the output node voltage of the R2R stepped resistor network is pre-calculated to the equivalent reference plane at the output of the preamplifier based on the amplitude-frequency transfer function and group delay parameter of the preamplifier obtained by static calibration, and differential coupling operation is performed to obtain the cooperative error amount.

[0026] The cooperative error is decomposed into amplitude error and timing error components. The amplitude error component is fed back to the reference voltage terminal of the R2R stepped resistor network, and the timing error component performs closed-loop correction on the interleaving interval of the bit switching timing diagram. A dual-operating-mode design is adopted: in normal operating mode, the reference voltage maintains the calibrated global value; in calibration mode, the reference voltage is adjusted in a ramp manner at the zero-crossing point of the audio signal. In response to the cooperative error converging to within the accuracy threshold, the current interleaving interval is locked, and a cooperative control command is output.

[0027] Taking the major carry codeword switching from 0111111 to 1000000 as an example, at this time, the high-weight branch and multiple low-weight branches flip simultaneously. The resulting high rate of change voltage surge will cause the bias current of the preamplifier to fluctuate instantaneously, resulting in a noticeable "click" sound in the output signal or a sharp increase in short-term harmonic distortion. This artifact is more prominent at low volumes or when the preamplifier gain is high, which seriously affects the continuity and purity of the sound quality.

[0028] By using the bias stability state as the valid sampling criterion, frequency-domain weighted differential coupling calculations are performed on the output node voltage of the R2R stepped resistor network and the output voltage of the preamplifier. The amplitude and phase deviations are extracted and fused with the weighted harmonic distortion index to obtain the cooperative error. The cooperative error is then decomposed into amplitude and timing components for feedback control. Predictive compensation current injection maintains the stability of the preamplifier bias, and decoupled closed-loop feedback precisely adjusts the interleaving interval and reference voltage. This suppresses transient interference from the R2R network output node on the preamplifier bias state during codeword switching, reduces harmonic distortion and audible artifacts during switching, and achieves high-precision cooperative control of the analog preamplifier output and R2R volume.

[0029] Example 2, refer to Figure 1 As an embodiment of the present invention, based on the previous embodiment, a method for high-precision analog preamp output and R2R volume coordinated control is provided, including the following steps:

[0030] This embodiment adopts a dual-mode sampling strategy: during the factory calibration and power-on self-test stages, 4 GHz high-speed dual ADC sampling, 500 ns full-window FFT and complete closed-loop iteration are enabled to generate optimal parameters offline and store them in the historical codeword feature library; during the normal playback stage, only the parameters in the historical library are called and fine-tuned with low-speed temperature sampling, without performing high-speed sampling and real-time closed-loop calculation, to ensure the feasibility and real-time performance of mass-produced equipment.

[0031] S1. When switching between adjacent codewords, the on / off timing of each branch of the R2R ladder resistor network is staggered. Based on the bit weight difference between the current codeword and the target codeword, a bit switching timing diagram is generated.

[0032] Specifically, the R2R ladder resistor network consists of multiple branches connected in parallel from 101 to 10n. Each branch corresponds to a bit in a digital codeword. The resistance of each branch is combined with two values, R and 2R, to form a ladder structure. The contribution of each branch to the output voltage when switching between on and off states is proportional to the bit weight of its position. Due to the differences in parasitic parameters and driving capabilities of each branch's driving circuit, if all branches operate simultaneously when adjacent codewords switch, unpredictable voltage glitches will be introduced at the moment of switching.

[0033] For ease of explanation, the following example uses an 8-bit DAC-type R2R ladder resistor network with an independent reference voltage input, where the switching of adjacent codewords causes all bit branches to flip simultaneously, representing the major-carry scenario. This scenario best demonstrates the technical effect of the staggered arrangement: Suppose the current codeword is 01111111 (decimal 127), and the target codeword is 10000000 (decimal 128). The two values ​​are adjacent and differ by one minimum resolution unit.

[0034] The steps for performing the staggered arrangement include S1.1 to S1.4:

[0035] S1.1 Arrange each branch in the R2R ladder resistor network in descending order of bit weight, and calculate the bit weight difference between each branch of adjacent codewords.

[0036] Specifically, the 8 branches are numbered b7, b6, b5, b4, b3, b2, b1, and b0 in descending order of their position weights, with corresponding position weights of... That is, 128, 64, 32, 16, 8, 4, 2, 1;

[0037] For each branch, subtract its value in the target codeword from its value in the current codeword, take the absolute value, and then multiply it by the corresponding bit weight of the branch to obtain the bit weight difference value of the branch. If a branch has the same value in the current codeword and the target codeword, its bit weight difference value is 0, indicating that the branch does not need to take any action this time and will not participate in the subsequent time slot allocation.

[0038] In this embodiment, the current codeword 01111111 and the target codeword 10000000 are compared bit by bit: b7 changes from 0 to 1, with a bit weight difference of 128; b6 to b0 all change from 1 to 0, with bit weight differences of 64, 32, 16, 8, 4, 2, and 1 respectively. Therefore, the set of bit weight differences for this switch is {128, 64, 32, 16, 8, 4, 2, 1}.

[0039] S1.2 Based on the position weight difference value, priority switching time slots are allocated to the branches corresponding to the position weight difference values ​​in the first N positions, and delay time slots are allocated to the remaining branches to form a gradient distribution.

[0040] The number of priority switching branches N (a positive integer, which can be preset according to the number of bits and accuracy requirements of the R2R stepped resistor network) is pre-set.

[0041] The branch position weight difference values ​​are sorted from largest to smallest. The switching time of the branch corresponding to the top N positions is set as the starting reference time t0 of this switching window (no delay is applied, and the action is prioritized). The remaining branches after the Nth position are applied with progressively increasing delay durations according to the position weight difference values ​​from high to low, forming an arithmetic sequence delay distribution with time step τ as the common difference, i.e., gradient distribution.

[0042] The larger the position weight difference, the greater the change in the contribution of that branch to the output voltage, and therefore the earlier it will act; the smaller the position weight difference, the later the action time. This allows the multiple switching actions that might have been concentrated at the same moment to be separated on the time axis according to the position weight, so that the total switching current impact changes from instantaneous concentration to dispersion, continuity and predictability.

[0043] Specifically, based on expert experience, N=3 is preset, and the time step (i.e., real-time staggered interval) is calculated in real time in this step. The time interval is 50 nanoseconds. The top three positions in the weight difference ranking, b7, b6, and b5, are assigned priority switching time slots, with a switching time of t0=0 nanoseconds for all three.

[0044] The remaining b4, b3, b2, b1, and b0 are allocated delay slots in descending order of their bit weight differences:

[0045] b4 is nanosecond, b3 is nanosecond, b2 is nanosecond, b1 is nanosecond, b0 is Nanoseconds, forming a gradient distribution with a tolerance of 50 nanoseconds.

[0046] S1.3 Using the combination of the current codeword and the target codeword as the index key, perform a nearest neighbor search in the historical codeword feature database to obtain the historical optimal parameter set.

[0047] Specifically, the historical codeword feature library pre-stores multiple combinations of (current codeword, target codeword) that have occurred previously, and the optimal interleaving parameters (including the number of priority switching branches, interleaving interval step size, etc., collectively referred to as the historical optimal parameter set) determined by the subsequent closed-loop correction steps of this invention.

[0048] When there is no completely identical record for the current codeword and target codeword combination in the historical codeword feature database, the current combination is used as the query key. The distance between the current combination and each stored key value in the database is calculated (for example, the sum of the absolute values ​​of the difference between the current codeword values ​​and the absolute values ​​of the difference between the target codeword values ​​can be used as the distance metric, or other distance metrics can be used). The record with the smallest distance is taken as the nearest neighbor, and its corresponding historical optimal parameter set is output.

[0049] The historical codeword feature library is stored in non-volatile memory and uses multi-temperature dimension segmented storage. It only includes parameter combinations that have been corrected in a closed loop and meet the locking conditions. When the device is powered on, the temperature validity of the historical parameters is verified. During operation, if the temperature drift exceeds the temperature range, background calibration is triggered.

[0050] In this embodiment, assume that the historical codeword feature database contains record one:

[0051] Current codeword 01111110 (126), target codeword 10000001 (129), historical optimal parameter set is Record 2: Current codeword 01111100 (124), target codeword 10000011 (131), historical optimal parameter set is .

[0052] Calculate the distance using the query key (127, 128): the distance to record 1 is |127-126|+|128-129|=2; the distance to record 2 is |127-124|+|128-131|=6. Record 1 has the smallest distance and is determined as the nearest neighbor. Obtain the historical optimal parameter set. .

[0053] S1.4. The historical optimal parameter set and the real-time interleaving interval are weighted and fused according to a preset weight to generate a bit switching timing diagram.

[0054] Pre-set the weights w1 and w2 (w1+w2=1) of the historical optimal parameter set. In an optional implementation, the values ​​of the two are adjusted according to the matching distance obtained in step S1.3. The smaller the matching distance, the higher the reliability of the historical parameters, and w1 can be taken as a larger value.

[0055] Get The result calculated in step S1.2 The final interleaving interval is obtained by weighting and summing according to the preset weights, and the specific time of each delay slot is redetermined based on this interval to generate a complete bit switching timing diagram.

[0056] In this example, based on expert experience, w1=0.6 and w2=0.4 are set. Then the final interleaving interval is expressed as... nanosecond;

[0057] Since both the historical optimal parameter set and the number of priority switching branches calculated in real time are N=3, no adjustment is needed. Based on this, the final bit switching timing diagram for this switching is generated as shown in Table 1:

[0058] Table 1. Final bit switching timing diagram for this switchover

[0059] b7 128 128 Priority slots t0=0ns b6 64 64 Priority slots t0=0ns b5 32 32 Priority slots t0=0ns b4 16 16 Delayed time slot t0 + final interleaving interval = 47ns b3 8 8 Delayed time slot The final interleaving interval t0+2 is 94ns. b2 4 4 Delayed time slot The final interleaving interval t0+3 is 141 ns. b1 2 2 Delayed time slot The final interleaving interval t0+4 is 188ns. b0 1 1 Delayed time slot The final interleaving interval t0+5 is 235ns.

[0060] This timing diagram for the switching process integrates the interleaving parameters calculated in real time during this switching process, as well as the optimal empirical parameters that have been converged and verified in similar historical switching scenarios. It balances real-time adaptability with historical stability, and its results will serve as the timing basis for injecting compensation current into the bias control terminal of the front amplifier in subsequent steps.

[0061] It should be noted that the specific values ​​of the number of bits, codeword values, time step, weight coefficients, etc. mentioned above are all exemplary descriptions given to facilitate understanding of the technical solution of the present invention, and should not be construed as limiting the scope of protection of the present invention; those skilled in the art can adjust the above parameters accordingly based on the actual number of bits, accuracy requirements and application scenarios of the R2R stepped resistor network.

[0062] S2. Through the bit switching timing diagram, differential mode compensation current is injected into the non-inverting input bias node of the front-stage amplifier by the integrated current DAC through the current limiting isolation network to obtain a bias stable state.

[0063] It is important to know that the output node of the R2R ladder resistor network is directly connected to the input (summing node) of the preamplifier. The transient voltage change of the node caused by bit switching will be coupled to the preamplifier through this connection, disturbing its quiescent operating point (such as input stage tail current, mirror branch current, etc.). If not compensated, this disturbance will manifest as transient noise in the audio signal.

[0064] To maintain consistency between the previous and subsequent examples, the aforementioned example of an 8-bit DAC-type R2R ladder resistor network with an independent reference voltage input and the switching from codeword 01111111 (127, current codeword) to 10000000 (128, target codeword) is used. Based on expert experience, the reference voltage Vref of this R2R ladder resistor network is set to 5.12V, which is the node voltage change corresponding to each weight unit. That is, 20 millivolts.

[0065] Specifically, the step of injecting the compensation current includes S2.1 to S2.4:

[0066] S2.1. Based on the priority switching time slot and delay time slot of each branch in the bit switching timing diagram, extract the node voltage prediction offset of the R2R ladder resistor network.

[0067] For each branch in the same time slot in the position switching timing diagram, multiply its position weight difference value by the node voltage change according to its respective on / off direction (positive for 0 to 1, negative for 1 to 0). Then sum them up to obtain the node voltage prediction offset corresponding to the time slot;

[0068] The above calculations are performed sequentially for each time slot to obtain a sequence of predicted node voltage offsets covering the entire bit switching timing diagram.

[0069] This sequence characterizes the predictable trajectory of the output node voltage changes in the R2R stepped resistor network during switching, distributed across time slots, and serves as the direct basis for subsequent calculation of the compensation current.

[0070] Specifically, according to the aforementioned timing diagram, the calculation is performed slot by slot: within the t0=0 nanosecond slot, b7 (0 to 1, +128×0.02V=+2.56V), b6 (1 to 0, -64×0.02V=-1.28V), and b5 (1 to 0, -32×0.02V=-0.64V) operate simultaneously. The sum of these three values ​​gives the predicted voltage offset of the slot node as +2.56-1.28-0.64=+0.64V.

[0071] Within the 47-nanosecond time slot, only b4 operates (from 1 to 0), with an offset of -16 × 0.02V = -0.32V; within the 94-nanosecond time slot, b3 operates, with an offset of -0.16V; within the 141-nanosecond time slot, b2 operates, with an offset of -0.08V; within the 188-nanosecond time slot, b1 operates, with an offset of -0.04V; and within the 235-nanosecond time slot, b0 operates, with an offset of -0.02V. Therefore, the node voltage prediction offset sequence is {+0.64V, -0.32V, -0.16V, -0.08V, -0.04V, -0.02V}, corresponding to the time slot start times {0, 47, 94, 141, 188, 235} nanoseconds.

[0072] S2.2. Based on the pre-calibrated full-range transmission characteristic curve of the bias node voltage-compensation current of the preamplifier, the predicted offset of the node voltage is converted into the compensation current value of the corresponding time slot.

[0073] The full-range transfer characteristic curve of the preamplifier bias node characterizes the conversion relationship between the injected current at the bias control terminal and its ability to cancel the preamplifier operating point disturbance. This is an inherent characteristic parameter of the amplifier bias circuit, calibrated using the step injection method: different amplitude currents are injected into the bias node in steps, the corresponding node voltage changes are measured, and the full-range transfer curve is fitted. This can be pre-characterized through simulation or actual measurement. The absolute values ​​of the predicted voltage offsets of each time slot node obtained in S2.1 are then assigned to the corresponding values ​​on the transfer characteristic curve, thus obtaining the compensation current value for each time slot.

[0074] The direction of the compensation current injection is opposite to the direction of the bias disturbance caused by the time slot offset, so as to achieve the cancellation effect.

[0075] In this embodiment, the equivalent transconductance parameter of the preamplifier bias control terminal is set to 2 mA / V.

[0076] Based on the offset sequence obtained in step S2.1, the following values ​​are calculated: t0 time slot, 2mA / V × 0.64V = 1.28mA; 47ns time slot, 2mA / V × 0.32V = 0.64mA; 94ns time slot, 2mA / V × 0.16V = 0.32mA; 141ns time slot, 2mA / V × 0.08V = 0.16mA; 188ns time slot, 2mA / V × 0.04V = 0.08mA; 235ns time slot, 2mA / V × 0.02V = 0.04mA. The resulting compensation current value sequence is {1.28mA, 0.64mA, 0.32mA, 0.16mA, 0.08mA, 0.04mA}, which has the same multiple relationship with the position weight of each time slot and has not yet undergone temperature correction.

[0077] S2.3. Correct the compensation current value according to the temperature distribution vector to obtain the corrected compensation current value.

[0078] The steps for correcting the compensation current value based on the temperature distribution vector include A1~A3:

[0079] A1. Set up temperature sampling points at the key nodes of each branch of the R2R stepped resistor network and at the bias node of the preamplifier. Collect the temperature value of each sampling point according to the preset sampling period and construct the temperature distribution vector.

[0080] A temperature sampling point is set up at each critical node of each branch of the R2R stepped resistor network (such as the connection point between the branch resistor and the switch), and another temperature sampling point is set up at the bias node of the preamplifier. Temperature values ​​are collected synchronously from all sampling points according to a preset sampling period to form a temperature distribution vector with a dimension corresponding to the number of branches plus one.

[0081] The reason for setting up sampling points for each branch instead of just performing overall single-point temperature measurement is that the R2R stepped resistor network has a spatial distribution on the circuit board. The distance between each branch and the heat source (such as the driving device or the preamplifier itself) is different, and there may be local temperature gradients. If only the overall temperature is uniformly compensated, it will not be able to reflect the relative deviation between different branches. The temperature sampling value of the bias node is used as an overall verification reference for subsequent implementations to dynamically calibrate the equivalent transconductance parameter.

[0082] Specifically, in this embodiment, an 8-bit R2R stepped resistor network plus a preamplifier bias node, totaling 9 temperature sampling points, are collected at a preset sampling period (e.g., once every 100 microseconds). The temperature distribution vector obtained within a certain sampling period is [T=T b7 T b6 T b5 T b4 T b3 T b2 T b1 T b0 T bias [25.0℃, 25.1℃, 25.0℃, 30.0℃, 25.2℃, 24.9℃, 25.1℃, 27.3℃]. It can be seen that the critical node temperature of branch b4 (30.0℃) is significantly higher than that of the other branches (all between 24.9℃ and 25.2℃), suggesting that the critical node of this branch is closer to heat-generating devices in the board layout; the bias node temperature of 27.3℃ is because the power consumption of the preamplifier itself is slightly higher than the ambient temperature.

[0083] A2. Based on the temperature distribution vector and the temperature coefficient parameters of each branch resistance, calculate the offset of the position weight difference caused by temperature change.

[0084] Specifically, let the calibration reference temperature of the R2R stepped resistor network be... The temperature coefficient parameter of each branch resistor is α, which characterizes the relative deviation rate of the resistance value with temperature. Each branch can take the same or different values, depending on the actual resistor selection.

[0085] For each branch, the temperature sample value of that branch is compared with the reference temperature. difference Combining the location weight and temperature coefficient parameters of this branch, the location weight difference offset of this branch is calculated as location weight multiplied by temperature coefficient parameter multiplied by... .

[0086] R2R stepped resistor networks rely on the resistance ratio between branches to achieve position weight allocation. If the resistance value of a branch deviates from the reference temperature due to local temperature deviation, the actual contribution of the branch to the output voltage will deviate from the theoretical position weight value. The deviation is proportional to the branch's temperature deviation, temperature coefficient parameter, and its own position weight.

[0087] For example, based on expert experience, the R2R stepped resistor network calibration reference temperature in this embodiment is set... The temperature coefficient parameter of the resistance of each branch is uniformly taken as α=200ppm / ℃ (i.e. 0.0002 / ℃).

[0088] Taking branch b4 as an example, its temperature deviation The offset of the position weight difference = 16 × 0.0002 × 5.0 = 0.016;

[0089] Similarly, the offset of branch b6 can be calculated as 64 × 0.0002 × 0.1 = 0.00128, the offset of branch b3 = 8 × 0.0002 × 0.2 = 0.00032, the offset of branch b1 = 2 × 0.0002 × (-0.1) = -0.00004, the offset of branch b0 = 1 × 0.0002 × 0.1 = 0.00002, and the offsets of branches b7, b5, and b2 are all 0 because the temperature deviation is 0.

[0090] Based on expert experience, the preset threshold for the significance of the offset was set to 0.01. Only the offset of branch b4 (0.016) exceeded this threshold and was determined to be a branch that needed correction. The offsets of the other branches were below the threshold and had negligible impact on the compensation accuracy, so they were not corrected in this round.

[0091] When the temperature deviation exceeds the approximate range of ±10℃, a pre-calibrated temperature correction lookup table is used for accurate compensation: the input to the lookup table is the current temperature and the branch position weight, and the output is the position weight correction coefficient, the compensation current correction coefficient, and the staggered interval correction coefficient. The intermediate temperature is calculated by linear interpolation. The lookup table is obtained by calibrating the high and low temperature chamber point by point in the range of -40℃ to 85℃ with a step size of 5℃.

[0092] A3. After superimposing the offset of the position weight difference value onto the original position weight difference value, recalculate according to the full-range transmission characteristic curve of the bias node of the preamplifier to obtain the corrected compensation current value.

[0093] For the branch that needs to be corrected in step A2, add its position weight difference offset to the original position weight difference obtained in S1.1 to get the corrected position weight difference value; recalculate the compensation current value of the time slot where the branch is located according to the same conversion path as in steps S2.1 and S2.2, which is the corrected compensation current value.

[0094] Specifically, for branch b4, the corrected position weight difference value = 16 + 0.016 = 16.016; the corrected node voltage prediction offset = 16.016 × 0.02V = 0.32032V; the corrected compensation current value = 2mA / V × 0.32032V = 0.64064mA (an increase of approximately 0.64 microamps compared to the original 0.64mA).

[0095] For the remaining time slots, since the offset did not exceed the significance threshold, the compensation current values ​​remained unchanged from the results obtained in S2.2. The summarized corrected compensation current values ​​are shown in Table 2.

[0096] Table 2. Schematic diagram of compensation current values

[0097] 0ns b7, b6, b5 1.28000mA 1.28000mA (Offset below threshold, no correction) 47ns b4 0.64000mA 0.64064mA 94ns b3 0.32000mA 0.32000mA (Offset below threshold, no correction) 141ns b2 0.16000mA 0.16000mA 188ns b1 0.08000mA 0.08000mA 235ns b0 0.04000mA 0.04000mA

[0098] As shown in Table 2, the compensation current for branch b4 was corrected from 0.64000mA to 0.64064mA due to local temperature deviation.

[0099] S2.4. Using a single-ended differential injection method, the corrected compensation current value is injected into the non-inverting input bias node of the preamplifier at the beginning of the corresponding time slot, while the inverting input maintains the reference bias unchanged. The compensation current is injected through a megohm-level high impedance and isolated from the signal path. The bias stability state is obtained when the change in the static operating current of the preamplifier within the time window covered by the in-situ switching timing diagram is less than a preset threshold.

[0100] Specifically, according to the corrected compensation current value sequence obtained in step S2.3, at the beginning of each time slot in the on-time switching timing diagram, a compensation current of the corresponding value and opposite direction is injected into the non-inverting input bias node of the front amplifier.

[0101] Meanwhile, within the entire time window covered by the bit switching timing diagram, the quiescent operating current of the preamplifier is continuously monitored, and its change within the window (such as peak-to-peak value) is calculated. A threshold for the change in quiescent operating current is preset. If the monitored change is less than the preset threshold, it is determined that the operating point disturbance of the preamplifier during this bit switching process has been effectively suppressed, and a bias stable state has been obtained. If it is not less than the threshold, it indicates that the current compensation is still insufficient, and further closed-loop correction is required in subsequent steps.

[0102] Based on expert experience, the preset threshold for static operating current variation in this embodiment is 5 microamps.

[0103] Reverse compensation currents of 1.28000mA, 0.64064mA, 0.32000mA, 0.16000mA, 0.08000mA, and 0.04000mA were injected into the bias control terminal of the preamplifier at 0 nanoseconds, 47 nanoseconds, 94 nanoseconds, 141 nanoseconds, 188 nanoseconds, and 235 nanoseconds, respectively.

[0104] Monitoring revealed that within a time window covering 0–235 nanoseconds (extended to 300 nanoseconds to account for the setup time after the last position switch), the change in the static operating current of the preamplifier was 3.4 microamps, which is less than the preset threshold of 5 microamps. Therefore, the bias was determined to be stable.

[0105] S3. Using the bias stable state as the sampling validity criterion, the output node voltage of the R2R stepped resistor network is converted to the equivalent reference plane at the output of the preamplifier based on the amplitude-frequency transfer function and group delay parameter of the preamplifier obtained by static calibration, and differential coupling operation is performed to obtain the cooperative error.

[0106] It should be noted that the bias steady state is used as a valid sampling condition. This means that only when the static operating point of the current stage amplifier is no longer disturbed by the transient current impact of bit switching, the difference between the output node voltage sampled at this moment and the output voltage of the preamplifier can truly reflect the steady-state coupling error between the R2R network and the preamplifier in the volume coordination control dimension, without mixing in the transient noise components that have not yet been eliminated, thus ensuring the validity of the subsequent differential coupling operation results.

[0107] Specifically, the steps for performing the differential coupling operation include S3.1 to S3.4:

[0108] S3.1. A dual-ADC synchronous sampling architecture is adopted, with the start time of bit switching as the synchronization reference, and dual-band dual-window sampling is performed: the audio steady-state frequency band is sampled with a long window and a low sampling rate before and after switching, and the switching transient disturbance frequency band is sampled with a short window and a high sampling rate including the switching process. The output node voltage of the R2R stepped resistor network and the output voltage of the preamplifier are sampled.

[0109] Sampling and Calculation Link Description: This section is only executed during the factory calibration / power-on self-test phase. The FPGA provides the same trigger signal to synchronously start the dual-channel ADCs. The sampled data is first stored in the on-chip RAM cache, and then the spectrum is calculated by the FPGA hardware FFT accelerator. Subsequent error fusion and iterative control are implemented by digital logic units, all offline, without consuming real-time computing power during normal playback.

[0110] Starting from the moment in step S2.4 when the bias stable state is determined, a preset sampling window is set forward. Within this window, a high-speed ADC is used to synchronously acquire the output node voltage VR2R(t) of the R2R stepped resistor network and the output voltage Vout(t) of the preamplifier, resulting in two sets of time-domain voltage sequences, which serve as the raw data for subsequent frequency domain analysis.

[0111] The length of the sampling window needs to cover the complete time span of the bit switching timing diagram, and additional settling time margin for the preamplifier should be reserved to ensure that the window contains complete information about the switching process and does not miss the steady-state response after bias stabilization.

[0112] In this embodiment, the aforementioned 8-bit R2R ladder resistor network and the codeword switching example from 01111111 to 10000000 are used. The bit switching timing diagram covers 0 to 235 nanoseconds. The preset sampling window length is set to 500 nanoseconds (i.e., 0 to 500 nanoseconds, where 235 to 500 nanoseconds is the setup time margin after the last bit switching). The sampling frequency is set to 4GHz (sampling interval 0.25 nanoseconds). A total of 2000 sampling points are collected within the window to obtain the sequences VR2R(n) and Vout(n) (n=1,2,…,2000).

[0113] The following voltage values ​​are divided into two parts: DC operating point and AC test signal. 2.5600V and 1.2800V are the DC bias operating points of the R2R output terminal and the preamplifier output terminal, respectively. 0.0512V is the peak value of the 1kHz AC test signal superimposed on the R2R output terminal. After being amplified by the preamplifier with a 20x (26dB) AC gain, the peak value of the corresponding AC signal at the output terminal is approximately 1.0240V.

[0114] Three representative sampling values ​​were selected. The first sampling time was 0ns (b7 / b6 / b5 switching). The DC operating point of the R2R output node voltage VR2R_DC was 2.5600V, and the peak value of the superimposed 1kHz AC signal VR2R_AC was 0.0512V. The DC operating point of the preamplifier output voltage Vout_DC was 1.2800V, and the peak value of the superimposed 1kHz AC signal Vout_AC was 0.0510V.

[0115] The second sampling time is 47ns (b4 switching), the DC operating point of the R2R output node voltage is 2.5730V; the DC operating point of the preamplifier output voltage is 1.2865V;

[0116] The third sampling time is 235ns (stabilizing after b0 switching), the DC operating point of the R2R output node voltage is 2.5601V; the DC operating point of the preamplifier output voltage is 1.2801V;

[0117] S3.2. The two sets of voltages are weighted and subtracted in the frequency domain according to their respective frequency component weights to obtain the intermediate difference set within the sampling window.

[0118] Based on the statically calibrated amplitude-frequency transfer function, the amplitude of the AC signal output from R2R is multiplied by the gain of the preceding stage and the compensated group delay phase to convert it into the equivalent value at the output of the preceding stage. This is then subtracted from the actual output voltage of the preceding stage. In this embodiment, the gain at 1kHz is 20 times and the group delay is 5 nanoseconds (ns). After conversion, the equivalent AC peak value at the output of R2R is VR2R_eq = 0.0512V × 20 = 1.0240V.

[0119] Perform Fast Fourier Transform (FFT) on the two sets of time-domain voltage sequences obtained in step S3.1 to obtain their amplitude distribution in the frequency domain; extract several key frequency points (such as the fundamental frequency of the audio test signal and the main frequency of the switching disturbance introduced by the bit switching timing), and pre-set the frequency component weights for each key frequency point that match the sensitivity of human hearing and the degree of coupling effect of switching noise.

[0120] Multiply the converted VR2R_eq and Vout amplitudes at the same frequency point by the weight of that frequency point and then subtract them to obtain the weighted difference value at that frequency point; repeat the above operation for all key frequency points and summarize to obtain the intermediate difference set.

[0121] The main frequency of the switching disturbance, fsw, can be estimated based on the final interleaving interval τ, approximately taking fsw≈1 / (2τ).

[0122] In this example, the R2R network is superimposed with a 1kHz audio test signal with a small amplitude. The key frequency points are the fundamental frequency f0 = 1kHz and the switching perturbation frequency fsw ≈ 1 / (2×47ns) ≈ 10.6MHz.

[0123] Based on the auditory weighting curve (audio frequency bands are more sensitive to human ears and have higher weights) and the proportion of switching noise energy (although it is in the ultrasonic frequency band, it still affects the bias after coupling and has a lower weight), according to expert experience, the preset frequency weights are w(f0)=0.6 and w(fsw)=0.4 (the sum of the weights is 1).

[0124] After performing an FFT on the sequence obtained in step S3.1, the amplitude of the AC signal is extracted: after the conversion, the amplitude of VR2R_eq is 1.0240V at f0 and 2.5600V at fsw; the amplitude of Vout is 1.0200V at f0 and 1.2800V at fsw.

[0125] Calculate the weighted difference: , .

[0126] This yields the intermediate difference set. .

[0127] S3.3 Extract the amplitude and phase deviation from the intermediate difference set to obtain the intermediate error amount.

[0128] Specifically, considering that the bit switching delay not only causes differences in amplitude between the two sets of voltages, but also introduces phase deviation due to the different transmission path delays experienced by different frequency components, for each frequency point in the intermediate difference set, not only is its amplitude difference extracted, but also the phase difference between VR2R and Vout at that frequency point is extracted; the amplitude difference and phase difference are weighted and fused according to preset amplitude weights and phase weights respectively to obtain the error contribution of that frequency point; the error contribution of all frequency points is summed to obtain the intermediate error.

[0129] In this example, the FFT analysis also yields phase information: a phase difference φ(f0) = 2° at f0 (mainly due to the audio signal phase shift caused by the preamplifier group delay), and a phase difference φ(fsw) = 15° at fsw (high-frequency bands are more susceptible to switching delays and parasitic parameters, resulting in more pronounced phase deviations). Assuming amplitude weight ka = 0.7 and phase weight kp = 0.3, the phase values ​​are first normalized by dividing by 180° before being superimposed with the amplitude values.

[0130] The error contribution at point f0 is ;

[0131] The contribution of the fsw point error is .

[0132] Summing the error contributions at each frequency point, we obtain an intermediate error of 0.36291V.

[0133] S3.4. The intermediate error is fused and corrected according to the weighted harmonic distortion index to obtain the cooperative error.

[0134] The steps for fusion correction include B1 to B3:

[0135] B1. Perform spectrum analysis on the output voltage of the preamplifier and extract the amplitude vectors of the second to Mth harmonics.

[0136] Perform FFT spectrum analysis on the preamplifier output voltage sequence Vout(t) acquired in step S3.1. Using the fundamental frequency of the audio test signal as a reference, extract the amplitude values ​​corresponding to the second harmonic to the preset Mth harmonic of the fundamental frequency in sequence to form an amplitude vector, which is used to characterize the degree of nonlinear distortion introduced by the preamplifier in this switching process.

[0137] Assuming M=5, the fundamental frequency f0=1kHz corresponds to an amplitude A1=1.0200V (peak amplitude of the preamplifier output signal). The amplitudes of the second to fifth harmonics are extracted using spectral analysis, as shown in Table 3.

[0138] Table 3. Harmonic Amplitude Diagram

[0139] baseband 1kHz A1=1.0200 2 times 2kHz A2=0.00510 3 times 3kHz A3=0.00255 4 times 4kHz A4=0.00103 5 times 5kHz A5=0.00048

[0140] The amplitude vector is obtained from Table 3. .

[0141] B2. Using the fundamental frequency amplitude as a normalization reference, the ratio of each harmonic amplitude in the amplitude vector to the fundamental frequency amplitude is weighted and summed according to the perception weight coefficient of each harmonic to construct a weighted harmonic distortion function and calculate the weighted harmonic distortion index.

[0142] Divide the amplitude of each harmonic by the fundamental frequency amplitude A1 to obtain the ratio of each harmonic to the fundamental frequency.

[0143] Since the human ear has different auditory sensitivities to different harmonics (lower harmonics are usually more easily perceived), a perception weighting coefficient is pre-set for each harmonic; the weighted harmonic distortion function is constructed by multiplying each ratio by the corresponding perception weighting coefficient and summing the results. The calculated result is the weighted harmonic distortion index.

[0144] Calculate the ratio of each harmonic to the fundamental frequency: % ; % %.

[0145] Based on expert experience, the perception weighting coefficients are set as c2=0.4, c3=0.3, c4=0.2, and c5=0.1.

[0146] ;

[0147] That is, the weighted harmonic distortion index %.

[0148] B3. The weighted harmonic distortion index and the intermediate error amount are weighted and fused to obtain the cooperative error amount.

[0149] Due to the intermediate error Δmid and the weighted harmonic distortion index Since the dimensions are different, the intermediate error must first be normalized according to the reference voltage Vref of the R2R stepped resistor network to convert it into a dimensionless relative error.

[0150] Then, set the fusion weights α (intermediate error weight) and β (harmonic distortion index weight), and sum the normalized intermediate error with the weighted harmonic distortion index to obtain the synergistic error.

[0151] Specifically, taking Vref = 5.12V, we normalize the intermediate error Δmid: %.

[0152] Based on expert experience, the fusion weights are set as α=0.65, β=0.35, and the collaborative error is... .

[0153] The calculation obtained here The initial open-loop cooperative error serves as the starting point for closed-loop iterative optimization and does not represent the achievement of the final locking condition. Final locking requires satisfying three criteria: continuous convergence across multiple rounds, harmonic compliance, and error dead zone. An initial error greater than the accuracy threshold by 1% indicates a significant cooperative deviation in the system, necessitating subsequent closed-loop iterative optimization to bring it below the threshold.

[0154] S4. The cooperative error is decomposed into an amplitude error component and a timing error component. The amplitude error component is fed back to the reference voltage terminal of the R2R stepped resistor network, and the timing error component performs closed-loop correction on the interleaving interval of the bit switching timing diagram. A dual-operating-mode design is adopted: in normal operating mode, the reference voltage maintains the calibrated global value; in calibration mode, the reference voltage is adjusted in a ramp manner at the zero-crossing point of the audio signal. In response to the cooperative error converging to within the accuracy threshold, the current interleaving interval is locked, and a cooperative control command is output.

[0155] Error decomposition rules: Error sources are decomposed by frequency band. The amplitude error component is mainly extracted from the amplitude deviation of the audio frequency band, reflecting the consistency of the output gain; the timing error component is mainly extracted from the phase deviation of the switching transient frequency band, reflecting the matching degree at the switching moment. In this embodiment, the amplitude error component accounts for 70% of the cooperative error, and the timing error component accounts for 30%.

[0156] The step of performing closed-loop correction on the interleaving interval of the bit switching timing diagram includes S4.1 to S4.4:

[0157] S4.1 Based on the preset correspondence between the interleaving interval adjustment amount and the reference voltage terminal control amount, the cooperative error amount is converted into the voltage adjustment amount of the reference voltage terminal.

[0158] A correspondence is pre-calibrated and stored through simulation or actual measurement. This correspondence describes the mapping law between the voltage adjustment amount ΔVref at the reference voltage terminal and the interleaving interval adjustment amount Δτ of the bit switching timing diagram. At the same time, the conversion coefficient kv for amplitude error to voltage adjustment amount and the conversion coefficient kτ for timing error to interleaving interval adjustment amount are given.

[0159] The amplitude error obtained this time is converted to kV to obtain the voltage adjustment amount that should be applied to the reference voltage terminal; the timing error is converted to kτ to obtain the interleaving interval correction amount. The sign of the voltage adjustment amount (increase or decrease) is determined according to the coupling deviation direction corresponding to the amplitude error; if the output node voltage of the R2R stepped resistor network is higher than the output voltage of the preamplifier, the adjustment amount is negative (reducing Vref), and vice versa.

[0160] Pre-calibrated correspondence: For every 10mV change in the reference voltage, the corresponding interleaving interval changes by 5ns. In this embodiment, the pre-calibrated amplitude error conversion factor kv = 40 millivolts (mV) / %, and the timing error conversion factor kτ = 1.5 nanoseconds (ns) / %.

[0161] Based on expert experience, the conversion factor kv is set to 40 mV / % in this embodiment (that is, for every 1 percentage point change in the cooperative error, the reference voltage is adjusted by 40 mV).

[0162] Obtained from S3.4 The amplitude error component is approximately 4.7123% × 70% ≈ 3.2986%, and the timing error component is approximately 4.7123% × 30% ≈ 1.4137%. Furthermore, it is determined that the output voltage at the R2R node is relatively higher than the output voltage of the preamplifier; therefore, the voltage adjustment is negative.

[0163] That is, the reference voltage terminal voltage should be lowered by approximately 131.9 millivolts this time.

[0164] Δτ = -kτ × timing error component = -1.5ns × 1.4137 ≈ -2.1ns. That is, the interleaving interval is shortened by about 2.1 nanoseconds (ns).

[0165] S4.2 In calibration mode, the voltage adjustment amount is applied to the reference voltage terminal of the R2R stepped resistor network in a ramp manner at the zero crossover point of the audio signal; the reference voltage adjustment terminal is connected in series with a second-order RC low-pass filter network with a cutoff frequency of 10Hz, which matches the total duration of the ramp adjustment, taking into account both smoothness and response speed, suppressing adjustment ripple, and updating the delay slot duration of each branch in the bit switching timing diagram according to the interleaving interval correction amount that matches the voltage adjustment amount in the corresponding relationship.

[0166] The voltage adjustment ΔVref is actually applied to the reference voltage terminal of the R2R stepped resistor network, so that it is adjusted from the original reference voltage to the new reference voltage;

[0167] Simultaneously, the interleaving interval correction Δτ is applied to the interleaving interval on which each delay slot in the current bit switching timing diagram is based, to obtain the corrected interleaving interval, and the specific duration of each delay slot is recalculated accordingly, thus completing the update of the bit switching timing diagram.

[0168] The maximum adjustment amount per cycle is preset to 20ns to avoid over-adjustment leading to oscillation. In this embodiment, after applying voltage adjustment, the reference voltage is adjusted from the original Vref=5.12V to the new reference voltage: .

[0169] This correction is applied to the final interleaving interval obtained in step S1.4, which is 47 nanoseconds (ns): =47ns + (-2.1ns) = 44.9ns, and subsequent iterations were used to gradually optimize it.

[0170] Based on this, update the duration of each delay slot in the bit switching timing diagram: slot b4 is updated from 47ns to 44.9ns, slot b3 from 94ns to 89.8ns, slot b2 from 141ns to 134.7ns, slot b1 from 188ns to 179.6ns, and slot b0 from 235ns to 224.5ns (priority slots b7, b6, and b5 remain unchanged at t0=0ns), thus completing the bit switching timing diagram update for this round.

[0171] S4.3. Taking the minimization of the cooperative error as the optimization objective, determine the iterative adjustment direction of the delay slot duration according to the gradient descent strategy.

[0172] Specifically, the steps of the gradient descent strategy include C1~C2:

[0173] C1. Calculate the gradient value of the cooperative error amount relative to the delay slot duration.

[0174] Specifically, a small perturbation is applied based on the current stagger interval. Repeat steps S2 to S3 to obtain the cooperative error after the disturbance. The ratio of the difference between the cooperative error before and after the disturbance to the disturbance amount is used as the gradient value of the cooperative error relative to the delay slot duration. This gradient value characterizes the trend of the cooperative error caused by each unit change in the delay slot duration.

[0175] In this embodiment, a detection perturbation is applied based on the original interleaving interval τ = 47 ns in S1.4. If the interleaving interval is 48 ns, steps S2 to S3 are repeated to calculate the cooperative error after the disturbance. The gradient value is then:

[0176] .

[0177] C2. Determine the sign of the gradient value. If the gradient value is positive, determine that the direction of the iterative adjustment is to shorten the duration of the delay slot; if the gradient value is negative, determine that the direction of the iterative adjustment is to extend the duration of the delay slot.

[0178] Specifically, a positive gradient value indicates that increasing the delay slot duration will lead to an increase in the amount of cooperative error, so iterative adjustments should be made in the direction of shortening the delay slot duration; conversely, a negative gradient value indicates that adjustments should be made in the direction of extending the delay slot duration.

[0179] The gradient value obtained in this calculation is grad≈ Since the value is positive, the direction of adjustment in this iteration is determined to be to shorten the delay time slot. This direction is consistent with the adjustment direction obtained in S4.2 based on the preset correspondence (the interleaving interval is shortened from 47ns to about 30ns). The two corroborate each other, indicating that the adjustment of shortening the interleaving interval in this iteration is the correct direction to bring the cooperative error amount to converge.

[0180] S4.4 In response to the convergence of the cooperative error amount to within the accuracy threshold, lock the current interleaving interval, stop the correction, and output a cooperative control command.

[0181] The steps to lock the current interleaving interval include D1~D2:

[0182] D1. In this embodiment, the preset number of iterations is 3. This means that the cooperative error calculated in three consecutive iterations (including the current iteration) must be less than the accuracy threshold of 1%, and the weighted harmonic distortion index must be less than the preset harmonic suppression threshold of 0.25%. Simultaneously, the error fluctuation must be less than the adaptive dead zone (0.1% of the current amplitude) before the current interleaving interval can be locked. The adaptive error dead zone refers to the range within which error fluctuation is considered stable, avoiding frequent adjustments.

[0183] D2. When the cooperative error amount converges to within the accuracy threshold within the number of iterations, and the weighted harmonic distortion index drops below the preset harmonic suppression threshold, the current interleaving interval is locked, the correction is stopped, and a cooperative control command with low harmonic distortion is output.

[0184] For example, the direction is adjusted (shortened) using the aforementioned staggered interval, and three consecutive rounds of iterative calculations are performed:

[0185] Round 1 (τ=29.95ns, i.e., the staggered interval after adjustment in step S4.2): Repeat steps S2~S3 to obtain the cooperative error. Weighted harmonic distortion index The error in this iteration is still greater than the accuracy threshold, so the iteration continues.

[0186] Round 2: Based on the gradient judgment in steps C1~C2 (the detection gradient in this round is still positive, so continue to fine-tune along the shortening direction), the staggered interval is further adjusted to τ=25.60ns, and steps S2~S3 are executed again, resulting in... , The error of this round is less than the accuracy threshold of 1%, and the harmonics are less than the suppression threshold of 0.25%, which meets the single-round convergence condition;

[0187] Round 3: Based on gradient detection, the gradient value in this round is close to zero (grad≈+0.021% / nanosecond), indicating that the cooperative error is becoming insensitive to changes in the delay slot duration. The interleaving interval remains at τ=25.60ns without adjustment. Steps S2~S3 are executed again, yielding... %, %, still meets the single-round convergence condition.

[0188] Since the cooperative error values ​​(0.852%, 0.585%, and 0.576%) obtained from three consecutive iterations (preset number of iterations) have all converged to within the accuracy threshold of 1%, and the weighted harmonic distortion index (0.213%, 0.194%, and 0.192%) has all decreased to below the preset harmonic suppression threshold of 0.25%, the locking condition is met. Therefore, it is determined that the interleaving interval for this switch (current codeword 01111111, target codeword 10000000) has converged and stabilized, and the current interleaving interval is locked. At nanosecond intervals, subsequent corrections cease, and the output carries the interleaving interval parameter (including the number of priority switching branches N=3 and the interleaving interval). Reference voltage Low harmonic distortion coordinated control commands (etc.);

[0189] At the same time, the codeword combination (127, 128) and the converged parameters {N=3, τ=25.60ns} are reversed and stored in the historical codeword feature database as a new record.

[0190] Example 3 is an embodiment of the present invention, which provides a system for high-precision analog preamplifier output and R2R volume coordinated control. The system is used to control a DAC-type R2R stepped resistor network with an independent reference voltage input and a preamplifier, including:

[0191] The timing control module is used to interleave the on / off timing of each branch in the R2R ladder resistor network when switching between adjacent codewords, and generate a bit switching timing diagram.

[0192] The bias compensation module includes an integrated current DAC, a current limiting isolation network, and a temperature sampling unit, which is used to inject compensation current into the non-inverting input bias node of the preamplifier according to the bit switching timing diagram to obtain a stable bias state.

[0193] The error coupling module is used to determine the effective sampling condition based on the bias stable state, and to pre-calculate the output node voltage of the R2R stepped resistor network to the equivalent reference plane of the output terminal of the preamplifier according to the amplitude-frequency transfer function and group delay parameter of the preamplifier obtained by static calibration. The module then performs differential coupling calculation between the output node voltage of the R2R stepped resistor network and the output voltage of the preamplifier to obtain the cooperative error amount.

[0194] The closed-loop correction module is used to feed back the cooperative error to the reference voltage terminal of the R2R stepped resistor network and perform closed-loop correction on the interleaving interval of the bit switching timing diagram; it adopts a dual-operating-mode design: in normal operating mode, the reference voltage maintains the calibrated global value, and in calibration mode, the reference voltage is adjusted in a ramp manner and applied at the zero-crossing point of the audio signal; it outputs cooperative control commands.

[0195] It should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the technical solutions of the present invention.

Claims

1. A method for high-precision analog preamp output and R2R volume coordinated control, characterized in that, The method is based on a DAC-type R2R stepped resistor network with an independent reference voltage input, and includes the following steps: When switching between adjacent codewords, the on / off timing of each branch of the R2R ladder resistor network is staggered, and a bit switching timing diagram is generated based on the bit weight difference between the current codeword and the target codeword. Using the bit switching timing diagram, differential mode compensation current is injected from the integrated current DAC through a current limiting isolation network into the non-inverting input bias node of the front-stage amplifier to obtain a stable bias state. Using the aforementioned bias stable state as the valid sampling criterion, the output node voltage of the R2R ladder resistor network is pre-calculated to the equivalent reference plane at the output of the preamplifier based on the amplitude-frequency transfer function and group delay parameter of the preamplifier obtained by static calibration, and differential coupling operation is performed to obtain the cooperative error amount. The cooperative error is decomposed into amplitude error component and timing error component. The amplitude error component is fed back to the reference voltage terminal of the R2R stepped resistor network. The timing error component performs closed-loop correction on the interleaving interval of the bit switching timing diagram. In response to the cooperative error convergence to within the accuracy threshold, the current interleaving interval is locked and a cooperative control command is output. In normal mode, the reference voltage maintains the calibrated global value. In calibration mode, the reference voltage is adjusted in a ramp manner at the zero crossover point of the audio signal.

2. The method for high-precision analog preamp output and R2R volume coordinated control as described in claim 1, characterized in that, The steps for performing the staggered arrangement include: Arrange the branches of the R2R ladder resistor network in descending order of bit weight, and calculate the bit weight difference of each branch between adjacent codewords. Based on the position weight difference value, priority switching time slots are allocated to the branches corresponding to the position weight difference values ​​in the first N positions, and delay time slots are allocated to the remaining branches to form a gradient distribution. Using the combination of the current codeword and the target codeword as the index key, perform a nearest neighbor search in the historical codeword feature database to obtain the historical optimal parameter set; The historical optimal parameter set and the real-time interleaving interval are weighted and fused according to a preset weight to generate a bit switching timing diagram.

3. The method for high-precision analog preamp output and R2R volume coordinated control as described in claim 2, characterized in that, The step of injecting the compensation current includes: Based on the priority switching time slot and delay time slot of each branch in the bit switching timing diagram, extract the node voltage prediction offset of the R2R ladder resistor network. Based on the pre-calibrated full-range transfer characteristic curve of the bias node voltage-compensation current of the preamplifier, the predicted offset of the node voltage is converted into the compensation current value of the corresponding time slot. Using a single-ended differential injection method, the corrected compensation current value is injected into the non-inverting input bias node of the front-stage amplifier at the beginning of the corresponding time slot, while the inverting input maintains the reference bias unchanged. The bias stable state is obtained when the change in the static operating current of the preamplifier within the time window covered by the in-situ switching timing diagram is less than a preset threshold.

4. The method for high-precision analog preamp output and R2R volume coordinated control as described in claim 3, characterized in that, The steps for correcting the compensation current value based on the temperature distribution vector include: Temperature sampling points are set up at key nodes of each branch of the R2R stepped resistor network and at the bias node of the preamplifier. Temperature values ​​of each sampling point are collected according to a preset sampling period to construct a temperature distribution vector. Based on the temperature distribution vector and the temperature coefficient parameters of each branch resistance, the offset of the position weight difference caused by temperature change is calculated. After superimposing the offset of the position weight difference value onto the original position weight difference value, the value is recalculated according to the full-range transmission characteristic curve of the bias node of the preamplifier to obtain the corrected compensation current value.

5. The method for high-precision analog preamp output and R2R volume coordinated control as described in claim 4, characterized in that, The steps for performing the differential coupling operation include: A dual-ADC synchronous sampling architecture is adopted, with the start time of bit switching as the synchronization reference, and dual-band dual-window sampling is performed: the audio steady-state frequency band is sampled with a long window and a low sampling rate before and after switching, and the switching transient disturbance frequency band is sampled with a short window and a high sampling rate including the switching process. The output node voltage of the R2R ladder resistor network and the output voltage of the preamplifier are sampled. The two sets of voltages are weighted and subtracted in the frequency domain according to their respective frequency component weights to obtain the intermediate difference set within the sampling window; The amplitude and phase deviations of the intermediate difference set are extracted to obtain the intermediate error amount; The intermediate error is fused and corrected based on the weighted harmonic distortion index to obtain the cooperative error.

6. The method for high-precision analog preamp output and R2R volume coordinated control as described in claim 5, characterized in that, The steps for performing fusion correction include: Spectral analysis is performed on the output voltage of the preamplifier to extract the amplitude vectors of the second to Mth harmonics; Using the fundamental frequency amplitude of the audio as a normalization reference, the ratio of each harmonic amplitude in the amplitude vector to the fundamental frequency amplitude is weighted and summed according to the perceptual weighting coefficient of each harmonic to construct a weighted harmonic distortion function and calculate the weighted harmonic distortion index. The weighted harmonic distortion index and the intermediate error are weighted and fused to obtain the cooperative error.

7. The method for high-precision analog preamp output and R2R volume coordinated control as described in claim 6, characterized in that, The steps for closed-loop correction of the interleaving interval of the bit switching timing diagram include: The amplitude error component is mainly extracted based on the amplitude deviation of the audio frequency band, and the timing error component is mainly extracted based on the phase deviation of the switching transient frequency band. In calibration mode, based on the preset correspondence, the amplitude error component is converted into the voltage adjustment amount of the reference voltage terminal, and the timing error component is converted into the interleaving interval correction amount. In calibration mode, the voltage adjustment is applied in a ramp manner to the reference voltage terminal of the R2R stepped resistor network at the zero-crossing point of the audio signal; With minimizing the cooperative error as the optimization objective, the iterative adjustment direction of the delay slot duration is determined according to the gradient descent strategy; In response to the convergence of the cooperative error amount to within the accuracy threshold, the current interleaving interval is locked, the correction is stopped, and a cooperative control command is output.

8. The method for high-precision analog preamp output and R2R volume coordinated control as described in claim 7, characterized in that, The steps of the gradient descent strategy include: Calculate the gradient value of the cooperative error relative to the duration of the delay slot; Determine the sign of the gradient value. If the gradient value is positive, determine that the direction of the iterative adjustment is to shorten the duration of the delay slot; if the gradient value is negative, determine that the direction of the iterative adjustment is to extend the duration of the delay slot.

9. The method for high-precision analog preamp output and R2R volume coordinated control as described in claim 8, characterized in that, The steps to lock the current interleaving interval include: Preset the number of consecutive iterations, adaptive error dead zone, and harmonic suppression threshold; When the cooperative error amount converges to within the accuracy threshold within a consecutive preset number of iterations, and the weighted harmonic distortion index drops below the preset harmonic suppression threshold and the error fluctuation is less than the adaptive error dead zone, the current interleaving interval is locked, the correction is stopped, and a cooperative control command with low harmonic distortion is output.

10. A system for high-precision analog preamplifier output and R2R volume coordinated control, employing the method for high-precision analog preamplifier output and R2R volume coordinated control as described in any one of claims 1 to 9, characterized in that, The system is used to control a DAC-type R2R stepped resistor network with an independent reference voltage input and a preamplifier, including: The timing control module is used to interleave the on / off timing of each branch in the R2R ladder resistor network when switching between adjacent codewords, and generate a bit switching timing diagram. The bias compensation module is used to inject compensation current into the non-inverting input bias node of the preamplifier according to the bit switching timing diagram to obtain a stable bias state. The error coupling module is used to perform differential coupling calculations on the output node voltage of the R2R ladder resistor network and the output voltage of the preamplifier, with the bias stable state as the valid sampling condition, to obtain the cooperative error amount. The closed-loop correction module is used to decompose the cooperative error into amplitude error component and timing error component. The amplitude error component is fed back to the reference voltage terminal of the R2R stepped resistor network, and the timing error component performs closed-loop correction on the interleaving interval of the bit switching timing diagram. In response to the cooperative error convergence to within the accuracy threshold, the current interleaving interval is locked and a cooperative control command is output.

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