High voltage rail-to-rail operational amplifier

Abstract

The application provides a high-voltage rail-to-rail operational amplifier, an input stage circuit comprising a signal input module and a current compensation module, the signal input module being configured to receive an input signal and generate an output current output to an intermediate stage circuit, and the current compensation module being configured to provide a compensation current to the output current of the signal input module when an actual value of the input signal is close to a positive power supply value or a negative power supply value. The high-voltage rail-to-rail operational amplifier of the application is provided with the current compensation module in the input stage circuit, and the output current output from the input stage circuit to the intermediate stage circuit is compensated when the actual value of the input signal is close to the positive power supply value or the negative power supply value, so that the transconductance of the input stage circuit can be kept constant, and the entire range of the power supply voltage can be used as the working range of the input signal.

Description

Technical Field

[0001] This application relates to the field of electronic circuit technology, specifically to a high-voltage rail-to-rail operational amplifier. Background Technology

[0002] With the rapid development of power electronic systems towards higher voltage and higher power, the application demand for high-voltage integrated circuits in industrial control, new energy conversion, and automotive electronics is growing exponentially. Operational amplifiers, as the core building blocks of analog circuits, directly determine the dynamic range and reliability of the entire system. However, the operating range (also known as the swing) of the input signal of existing traditional operational amplifiers is typically only 60%-80% of the power supply voltage, which is insufficient to meet the requirements of high-voltage circuits for processing the full swing of the input signal. Summary of the Invention

[0003] The purpose of this application is to provide a high-voltage rail-to-rail operational amplifier capable of processing the full swing of the input signal.

[0004] To achieve the above objectives, this application provides the following technical solution: A high-voltage rail-to-rail operational amplifier includes: an input stage circuit, an intermediate stage circuit, and an output stage circuit coupled in sequence. The input stage circuit, the intermediate stage circuit, and the output stage circuit are all coupled between a positive voltage terminal and a negative voltage terminal of a power supply. The power supply voltage at the positive voltage terminal is a positive power supply value, and the power supply voltage at the negative voltage terminal is a negative power supply value. The input stage circuit includes a signal input module and a current compensation module. The signal input module is used to receive an input signal and generate an output current to output to the intermediate stage circuit. The current compensation module is used to provide compensation current to the output current of the signal input module when the actual value of the input signal is close to the positive or negative value of the power supply. The intermediate stage circuit is used to amplify the gain under the action of the output current, output an intermediate voltage to the output stage circuit, and clamp the intermediate voltage to a preset range. The output stage circuit is used to output the target voltage under the control of the intermediate voltage.

[0005] In one embodiment, the signal input module includes: a first bias unit, a second bias unit, a first input unit, and a second input unit; The first bias unit is coupled between the first input unit and the positive voltage terminal of the power supply, and is used as a first current source to provide the first input current. The second bias unit is coupled between the second input unit and the negative voltage terminal of the power supply, and is used as a second current source to provide the second input current; The first input unit is coupled to the current compensation module and outputs a first output current to the intermediate stage circuit based on the first input current and the first compensation current provided by the current compensation module. The second input unit is coupled to the current compensation module and outputs a second output current to the intermediate stage circuit based on the second input current and the second compensation current provided by the current compensation module.

[0006] In one embodiment, the first input unit includes a first P-transistor and a second P-transistor, the second input unit includes a first N-transistor and a second N-transistor, the first bias unit includes a third P-transistor, and the second bias unit includes a third N-transistor. The gate terminals of the first P-type transistor and the first N-type transistor are coupled to form a first signal input terminal, and the gate terminals of the second P-type transistor and the second N-type transistor are coupled to form a second signal input terminal. The source terminals of the first P-tube and the second P-tube are coupled to the drain terminal of the third P-tube. The source terminal of the third P-tube is coupled to the positive voltage terminal of the power supply. The gate terminal of the third P-tube is coupled to the operating voltage of the P-tube. The drain terminals of the first P-tube and the second P-tube are respectively coupled to the intermediate stage circuit. The source terminals of the first N-transistor and the second N-transistor are coupled to the drain terminal of the third N-transistor. The source terminal of the third N-transistor is coupled to the negative voltage terminal of the power supply. The gate terminal of the third N-transistor is coupled to the operating voltage of the N-transistor. The drain terminals of the first N-transistor and the second N-transistor are respectively coupled to the intermediate stage circuit.

[0007] In one embodiment, the current compensation module includes: a first compensation unit and a second compensation unit; The first compensation unit is coupled to the first input unit and is used to provide the first compensation current to the first input unit for current compensation when the actual value of the input signal is close to the negative value of the power supply. The second compensation unit is coupled to the second input unit and is used to provide the second compensation current to the second input unit for current compensation when the actual value of the input signal is close to the positive value of the power supply.

[0008] In one embodiment, the first compensation unit includes a fourth P-tube, a fifth P-tube, and a sixth N-tube, and the second compensation unit includes a sixth P-tube, a fourth N-tube, and a fifth N-tube; The source terminals of the fourth P-tube and the fifth P-tube are coupled to the positive voltage terminal of the power supply. The gate terminals of the fourth P-tube and the fifth P-tube are coupled to the drain terminal of the fourth P-tube. The drain terminal of the fifth P-tube is coupled to the coupling point of the first bias unit and the first input unit. The drain terminal of the fourth P-tube is coupled to the drain terminal of the sixth N-tube. The source terminal of the sixth N-tube is coupled to the coupling point of the second bias unit and the second input unit. The gate terminal of the sixth N-tube is coupled to the operating voltage of the N-tube. The source terminals of the fourth N-transistor and the fifth N-transistor are coupled to the negative voltage terminal of the power supply. The gate terminals of the fourth N-transistor and the fifth N-transistor are coupled to the drain terminal of the fourth N-transistor. The drain terminal of the fifth N-transistor is coupled to the coupling point of the second bias unit and the second input unit. The drain terminal of the fourth N-transistor is coupled to the drain terminal of the sixth P-transistor. The source terminal of the sixth P-transistor is coupled to the coupling point of the first bias unit and the first input unit. The gate terminal of the sixth P-transistor is coupled to the operating voltage of the P-transistor.

[0009] In one embodiment, the intermediate stage circuit includes a gain amplification unit and a coupled voltage clamping structure; The gain amplification unit is used to amplify the gain under the action of the output current provided by the input stage circuit and output an intermediate voltage. The voltage clamping structure is used to clamp the intermediate voltage output by the gain amplification unit to a preset range.

[0010] In one embodiment, the gain amplification unit includes a seventh P-transistor, an eighth P-transistor, a tenth P-transistor, an eleventh P-transistor, a seventh N-transistor, an eighth N-transistor, a tenth N-transistor, an eleventh N-transistor, a first resistor, and a second resistor; the voltage clamping structure includes a ninth P-transistor, a twelfth P-transistor, a ninth N-transistor, and a twelfth N-transistor. The source terminals of the seventh P-tube and the tenth P-tube are coupled to the positive voltage terminal of the power supply. The source terminal of the eighth P-tube is coupled to the drain terminal of the seventh P-tube. The source terminal of the ninth P-tube is coupled to the drain terminal of the eighth P-tube. The drain terminal of the ninth P-tube is coupled to the first terminal of the first resistor. The source terminal of the eleventh P-tube is coupled to the drain terminal of the tenth P-tube. The source terminal of the twelfth P-tube is coupled to the drain terminal of the eleventh P-tube. The drain terminal of the twelfth P-tube is coupled to the first terminal of the second resistor. The gate terminals of the seventh P-tube and the tenth P-tube are coupled to the drain terminal of the eighth P-tube. The gate terminals of the eighth P-tube and the eleventh P-tube are coupled to the operating voltage of the P-tube. The gate terminals of the ninth P-tube and the twelfth P-tube are coupled to the clamping control voltage of the P-tube. The drain terminals of the seventh P-tube and the tenth P-tube are also coupled to the output terminal of the signal input module. The source terminals of the seventh N-transistor and the tenth N-transistor are coupled to the negative voltage terminal of the power supply. The source terminal of the eighth N-transistor is coupled to the drain terminal of the seventh N-transistor. The source terminal of the ninth N-transistor is coupled to the drain terminal of the eighth N-transistor. The drain terminal of the ninth N-transistor is coupled to the second terminal of the first resistor. The source terminal of the eleventh N-transistor is coupled to the drain terminal of the tenth N-transistor. The source terminal of the twelfth N-transistor is coupled to the drain terminal of the eleventh N-transistor. The drain terminal of the twelfth N-transistor is coupled to the second terminal of the second resistor. The gate terminal of the seventh N-transistor and the... The gate of the 10N transistor is coupled to the drain of the 8th N transistor. The gates of the 8th and 11th N transistors are coupled to the operating voltage of the N transistors. The gates of the 9th and 12th N transistors are coupled to the clamping control voltage of the N transistors. The drains of the 7th and 10th N transistors are also coupled to the output of the signal input module. The drains of the 11th P transistor and the 11th N transistor serve as the first and second outputs of the intermediate stage circuit, respectively, and are coupled to the output stage circuit.

[0011] In one embodiment, the output stage circuit includes: a thirteenth P-transistor and a thirteenth N-transistor; The source terminal of the thirteenth P-transistor is coupled to the positive voltage terminal of the power supply, the source terminal of the thirteenth N-transistor is coupled to the negative voltage terminal of the power supply, the gate terminals of the thirteenth P-transistor and the gate terminals of the thirteenth N-transistor are respectively coupled to the output terminal of the intermediate stage circuit, and the drain terminals of the thirteenth P-transistor and the drain terminals of the thirteenth N-transistor are coupled to the signal output terminal.

[0012] In one embodiment, the high-voltage rail-to-rail operational amplifier further includes a compensation capacitor circuit coupled between the intermediate stage circuit and the output stage circuit, the compensation capacitor circuit including a first capacitor and a second capacitor; One end of the first capacitor and the second capacitor are respectively coupled to the intermediate stage circuit, and the other end of the first capacitor and the second capacitor are coupled to the output terminal of the output stage circuit.

[0013] In one embodiment, the high-voltage rail-to-rail operational amplifier further includes: a fourteenth P-tube, a fifteenth P-tube, a fourteenth N-tube, a fifteenth N-tube, and a current source; The source terminal of the fourteenth P transistor is coupled to the positive voltage terminal of the power supply, the gate terminal of the fourteenth P transistor is coupled to the drain terminal of the fourteenth P transistor, the drain terminal of the fourteenth P transistor is coupled to the source terminal of the fifteenth P transistor, the gate terminal of the fifteenth P transistor is coupled to the drain terminal of the fifteenth P transistor, and the drain terminal of the fifteenth P transistor is coupled to the first terminal of the current source. The source terminal of the fourteenth N transistor is coupled to the negative voltage terminal of the power supply, the gate terminal of the fourteenth N transistor is coupled to the drain terminal of the fourteenth N transistor, the drain terminal of the fourteenth N transistor is coupled to the source terminal of the fifteenth N transistor, the gate terminal of the fifteenth N transistor is coupled to the drain terminal of the fifteenth N transistor, and the drain terminal of the fifteenth N transistor is coupled to the second terminal of the current source. The drain terminal of the fifteenth P-transistor outputs the P-transistor clamping control voltage, and the drain terminal of the fifteenth N-transistor outputs the N-transistor clamping control voltage.

[0014] Compared with the prior art, the technical solution of this application has the following beneficial effects: This application presents a high-voltage rail-to-rail operational amplifier with a current compensation module in the input stage circuit. When the actual value of the input signal is close to the positive or negative value of the power supply, the output current from the input stage circuit to the intermediate stage circuit is compensated. The transconductance of the input stage circuit can remain constant, so the entire range of the power supply voltage can be used as the operating range of the input signal. This application can achieve complete rail-to-rail operation and can process the full swing of the input signal to achieve full swing operation.

[0015] The high-voltage rail-to-rail operational amplifier of this application has a voltage clamping structure in the intermediate stage circuit, which clamps the intermediate voltage output from the intermediate stage circuit to the output stage circuit within a preset range, thereby preventing damage to the output stage circuit.

[0016] This application presents a high-voltage rail-to-rail operational amplifier with a compensation capacitor circuit between the intermediate stage circuit and the output stage circuit. Utilizing the Miller effect, a secondary pole appears in the loop gain amplitude-frequency and phase-frequency simulation diagram. Without the compensation capacitor circuit, only the primary pole would appear. This application can expand the phase margin by combining the primary and secondary poles, thereby enhancing the system stability. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 A schematic diagram of the circuit structure of a high-voltage rail-to-rail operational amplifier provided in this application; Figure 2 The simulation diagram of the loop gain amplitude frequency and phase frequency of a high-voltage rail-to-rail operational amplifier provided in this application. Detailed Implementation

[0019] The technical solutions in the embodiments of this application will be clearly and completely described below. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application. It should be noted that the order of description of the following embodiments is not intended to limit the preferred order of the embodiments of this application. Moreover, in the following embodiments, the description of each embodiment has its own emphasis, and for parts not described in detail in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0020] Please see Figure 1 As shown, this application provides a high-voltage rail-to-rail operational amplifier (abbreviated as op-amp), which may include: an input stage circuit 1, an intermediate stage circuit 2, and an output stage circuit 3 coupled in sequence. The input stage circuit 1, the intermediate stage circuit 2, and the output stage circuit 3 are all coupled between a positive power supply voltage terminal VSH and a negative power supply voltage terminal VSL. The power supply voltage of the positive power supply voltage terminal VSH is a positive power supply value, and the power supply voltage of the negative power supply voltage terminal VSL is a negative power supply value.

[0021] The input stage circuit 1 may include a signal input module 11 and a current compensation module 12. The signal input module 11 has a positive signal input terminal inp and a negative signal input terminal inn, which are used to receive input signals and generate output current to output to the intermediate stage circuit. The current compensation module 12 is used to provide compensation current to the output current of the signal input module 11 when the actual value of the input signal is close to the positive or negative value of the power supply.

[0022] In this embodiment, the intermediate stage circuit 2 is used to amplify the gain under the action of the output current, output an intermediate voltage to the output stage circuit, and clamp the intermediate voltage to a preset range.

[0023] In this embodiment, the output stage circuit 3 is used to output the target voltage under the control of the intermediate voltage.

[0024] In the operational amplifier input stage circuit 1 of this application, the current compensation module 12 compensates for the output current of the signal input module 11 when the actual value of the input signal is close to the positive or negative power supply value. Without the current compensation module 12, when the actual value of the input signal is close to the positive or negative power supply value, the internal circuit connected to either the positive input terminal inp or the negative input terminal inn of the signal input module 11 will be turned off and stop working, and the output current of the corresponding signal input module 11 will be almost halved (when the actual value of the input signal is in the middle range between the positive and negative power supply values, the internal circuits connected to both the positive input terminal inp and the negative input terminal inn of the signal input module 11 are both in operation). The change in output current caused by the voltage variation of the input signal will cause a change in transconductance (the transconductance of the input stage circuit 1 of this application is always equivalent to the output current of the input stage circuit 1), that is, the transconductance cannot be conserved. This will further lead to changes in gain, unity-gain bandwidth, poor phase margin, and difficulty in frequency compensation. Therefore, the range of adjacent positive or negative power supply values ​​cannot be regarded as the normal operating voltage range. That is, as mentioned in the background art, the operating range of the input signal of the conventional operational amplifier is usually only 60%-80% of the power supply voltage. However, in the operational amplifier of this application, because the current compensation module 12 in the input stage circuit 1 compensates for the current, the transconductance of the input stage circuit 1 can remain constant. Therefore, the entire range between the positive and negative power supply values ​​can be regarded as the operating range of the input signal. Therefore, the operational amplifier of this application is completely rail-to-rail, and can also be said to be able to process the full swing of the input signal and achieve full swing operation.

[0025] In one embodiment, the signal input module 11 may include: a first bias unit 113, a second bias unit 114, a first input unit 111, and a second input unit 112.

[0026] The first bias unit 113 is coupled between the first input unit 111 and the positive voltage terminal VSH of the power supply, and is used as a first current source to provide the first input current.

[0027] In this embodiment, the second bias unit 114 is coupled between the second input unit 112 and the negative voltage terminal VSL of the power supply, and is used as a second current source to provide a second input current.

[0028] In this embodiment, the first input unit 111 is coupled to the current compensation module 12, and outputs a first output current to the intermediate stage circuit 2 based on the first input current and the first compensation current provided by the current compensation module 12.

[0029] In this embodiment, the second input unit 112 is coupled to the current compensation module 12, and outputs a second output current to the intermediate stage circuit 2 based on the second input current and the second compensation current provided by the current compensation module 12.

[0030] In one embodiment, the signal input module 11 is a folded cascode structure. The first input unit 111 includes a first P-tube 701 and a second P-tube 702, the second input unit 112 includes a first N-tube 801 and a second N-tube 802, the first bias unit 113 includes a third P-tube 703, and the second bias unit 114 includes a third N-tube 803. The gate terminals of the first P-tube 701 and the first N-tube 801 are coupled to form a first signal input terminal, and the gate terminals of the second P-tube 702 and the second N-tube 802 are coupled to form a second signal input terminal. The first signal input terminal and the second signal input terminal serve as the positive signal input terminal inp and the negative signal input terminal inn, respectively. The source terminals of the first P-tube 701 and the second P-tube 702 are coupled to the drain terminal of the third P-tube 703. The source terminal of the third P-tube 703 is coupled to the positive voltage terminal VSH of the power supply, and the gate terminal of the third P-tube 703 is coupled to the operating voltage of the P-tubes. The drain terminals of the first P-tube 701 and the second P-tube 702 are respectively coupled to the intermediate stage circuit 2. The source terminals of the first N-tube 801 and the second N-tube 802 are coupled to the drain terminal of the third N-tube 803. The source terminal of the third N-tube 803 is coupled to the negative voltage terminal VSL of the power supply, and the gate terminal of the third N-tube 803 is coupled to the operating voltage of the N-tubes. The drain terminals of the first N-tube 801 and the second N-tube 802 are respectively coupled to the intermediate stage circuit 2.

[0031] To clarify, the P-type transistors mentioned above (and throughout the text) refer to PMOS transistors, which have source, drain, and gate terminals. They conduct when the voltage difference (Vgs) between the gate and source terminals is greater than the threshold voltage. Similarly, the N-type transistors mentioned above (and throughout the text) refer to NMOS transistors, which also have source, drain, and gate terminals. They conduct when the voltage difference (Vgs) between the gate and source terminals is greater than the threshold voltage. For operational amplifiers (op-amps), their input signal has a voltage range that allows the op-amp to operate normally, often referred to as the operating voltage range, such as AB. The power supply voltage coupled to the op-amp also has a certain range, such as CD, where C and D represent the negative and positive values ​​of the power supply voltage, respectively. In typical op-amps, A is slightly greater than C (A is adjacent to C), and B is slightly less than D (B is adjacent to D). Therefore, the range of AB is approximately 60%-80% of the CD range. This application does not intend to discuss how much A is greater than C to be considered a neighbor of C, or how much B is less than D to be considered a neighbor of D, because the values ​​of A, B, C, and D for different products can be designed by those skilled in the art according to different actual situations. Moreover, this application can achieve A equal to C and B equal to D. Therefore, in the following examples, endpoint values ​​will be used to illustrate the principle more easily.

[0032] The following example illustrates some of the principles involved in this application. In this application, the operating voltages of the P-tube and the N-tube are fixed values, and the third P-tube 703 and the third N-tube 803 are continuously turned on. When the input signal voltage is high (e.g., when the power supply is positive), the gate-source voltage difference between the first P-tube 701 and the second P-tube 702 is insufficient to turn them on, thus turning them off. Consequently, neither the first P-tube 701 nor the second P-tube 702 outputs current to the intermediate stage circuit 2. Only the first N-tube 801 and the second N-tube 802 are turned on, and their drains output a second output current to the intermediate stage circuit 2. This second output current is the current flowing through the third N-tube 803, which is the second input current provided by the third N-tube 803. When the input signal voltage is low (e.g., when the power supply is negative), the gate-source voltage difference between the first N-tube 801 and the second N-tube 802 is insufficient to turn them on, thus turning them off. When 2 is closed, correspondingly, neither the drain of the first N-channel transistor 801 nor the second N-channel transistor 802 outputs current to the intermediate stage circuit 2. At this time, only the first P-channel transistor 701 and the second P-channel transistor 702 are turned on, and the drain of the first P-channel transistor 701 and the second P-channel transistor 702 outputs the first output current to the intermediate stage circuit 2. Its value is the current flowing through the third P-channel transistor 703, which is the first input current provided by the third P-channel transistor 703. When the voltage of the input signal is at the intermediate level, the gate-source voltage difference of the first P-channel transistor 701 and the second P-channel transistor 702 turns on the first P-channel transistor 701 and the second P-channel transistor 702. The gate-source voltage difference of the first N-channel transistor 801 and the second N-channel transistor 802 turns on the first N-channel transistor 801 and the second N-channel transistor 802. The drain of the first P-channel transistor 701 and the second P-channel transistor 702 and the drain of the first N-channel transistor 801 and the second N-channel transistor 802 both output current to the intermediate stage circuit 2. Its value is the sum of the first input current and the second input current. Therefore, without the current compensation module 12 of this application, such changes in output current would cause changes in transconductance, meaning that transconductance could not be conserved. This would further lead to changes in gain and unity-gain bandwidth, poor phase margin, and difficulties in frequency compensation. Therefore, this application provides a current compensation module 12 in the input stage circuit 1 to compensate for the output current of the input stage circuit 1 when needed, thereby maintaining transconductance conservation.

[0033] In one embodiment, the current compensation module 12 may include: a first compensation unit 121 and a second compensation unit 122.

[0034] The first compensation unit 121 is coupled to the first input unit 111 and is used to provide the first compensation current to the first input unit 111 for current compensation when the actual value of the input signal is close to the negative value of the power supply.

[0035] In this embodiment, the second compensation unit 122 is coupled to the second input unit 112 and is used to provide the second compensation current to the second input unit 112 for current compensation when the actual value of the input signal is close to the positive value of the power supply.

[0036] In one embodiment, the first compensation unit 121 may include a fourth P-tube 704, a fifth P-tube 705, and a sixth N-tube 806, and the second compensation unit 122 may include a sixth P-tube 706, a fourth N-tube 804, and a fifth N-tube 805.

[0037] The source terminals of the fourth P-tube 704 and the fifth P-tube 705 are coupled to the positive voltage terminal VSH of the power supply. The gate terminals of the fourth P-tube 704 and the fifth P-tube 705 are coupled to the drain terminal of the fourth P-tube 704. The drain terminal of the fifth P-tube 705 is coupled to the drain terminal of the third P-tube 703 (which is also the coupling point between the first bias unit 113 and the first input unit 111). Figure 1 At point a), the drain of the fourth P-tube 704 is coupled to the drain of the sixth N-tube 806, and the source of the sixth N-tube 806 is coupled to the drain of the third N-tube 803 (which is also the coupling point between the second bias unit 114 and the second input unit 112). Figure 1 (at point b), the gate terminal of the sixth N-transistor 806 is coupled to the operating voltage of the N-transistor.

[0038] The source terminals of the fourth N-channel transistor 804 and the fifth N-channel transistor 805 are coupled to the negative voltage terminal VSL of the power supply. The gate terminals of the fourth N-channel transistor 804 and the fifth N-channel transistor 805 are coupled to the drain terminal of the fourth N-channel transistor 804. The drain terminal of the fifth N-channel transistor 805 is coupled to the drain terminal of the third N-channel transistor 803 (which is also the coupling point between the second bias unit 114 and the second input unit 112). Figure 1 (Point b), the drain of the fourth N-transistor 804 is coupled to the drain of the sixth P-transistor 706, and the source of the sixth P-transistor 706 is coupled to the drain of the third P-transistor 703 (which is also the coupling point between the first bias unit 113 and the first input unit 111). Figure 1 (Point a) The gate terminal of the sixth P-tube 706 is coupled to the operating voltage of the P-tube.

[0039] The specific working principle of the current compensation module 12 is as follows: When the input signal voltage is high (for example, when the power supply is positive), the gate-source voltage difference between the first P transistor 701 and the second P transistor 702 is insufficient to turn on the first P transistor 701 and the second P transistor 702, thus turning off the first P transistor 701 and the second P transistor 702 (correspondingly, at this time, there is no current flowing to the intermediate stage circuit 2 at the drain of the first P transistor 701 and the second P transistor 702, that is, the first output current is actually 0, but at this time the first N transistor 801 and the second N transistor 802 are still in the conducting state). Correspondingly, the drain of the third P transistor 703 (that is, the coupling point between the first bias unit 113 and the first input unit 111, Figure 1 Point a) is in a floating state. Because the third P-transistor 703 is continuously conducting, the voltage at point a is approximately the positive value of the power supply. The gate-source voltage difference of the sixth P-transistor 706 is sufficient to turn it on. The current mirror branch of the sixth P-transistor 706 and the fourth N-transistor 804 is used to mirror the current to the fifth N-transistor 805. The current flowing through the fifth N-transistor 805 is then transferred to... Figure 1 Point b (the coupling point between the second bias unit 114 and the second input unit 112) thus flows through Figure 1 The current at point b is actually the sum of the current flowing through the fifth N-transistor 805 and the current flowing through the third N-transistor 803. This is the second compensation unit 122 providing the second compensation current to the second input unit 112 for current compensation. The current at point b can be simply referred to as the sum of the second input current and the second compensation current. This current flows through the drain terminals of the first N-transistor 801 and the second N-transistor 802 to the intermediate stage circuit 2. That is, at this time, the second output current output by the second input unit 112 (input stage circuit 1) to the intermediate stage circuit 2 is actually the sum of the second input current and the second compensation current. When the input signal voltage is low (for example, when the power supply is negative), the gate-source voltage difference between the first N-transistor 801 and the second N-transistor 802 is insufficient to turn on the first N-transistor 801 and the second N-transistor 802, thereby turning off the first N-transistor 801 and the second N-transistor 802 (correspondingly, at this time, the first N-transistor 801 and the second N-transistor 802 are not sufficient to turn on the first N-transistor 801 and the second N-transistor 802). No current flows from the drain of transistor 2 to intermediate stage 2, meaning the actual second output current is 0. However, at this time, the first P-tube 701 and the second P-tube 702 are still conducting. Correspondingly, the drain of the third N-tube 803 (point b in the diagram) is floating. Because the third N-tube 803 is continuously conducting, the voltage at point b is approximately the negative value of the power supply. The gate-source voltage difference of the sixth N-tube 806 is sufficient to turn it on. The current mirrors the sixth N-tube 806 and the fourth P-tube 704, where the current is replicated to the fifth P-tube 705. The current flowing through the fifth P-tube 705 merges into... Figure 1 Point a in the middle, thus flowing through Figure 1The current at point a is actually the sum of the current flowing through the fifth P-tube 705 and the current flowing through the third P-tube 703. This is the first compensation unit 121 providing the first compensation current to the first input unit 111 for current compensation. The current at point a can be simply referred to as the sum of the first input current and the first compensation current. This current flows through the drain terminals of the first P-tube 701 and the second P-tube 702 to the intermediate stage circuit 2. That is, at this time, the first output current from the first input unit 111 (input stage circuit 1) to the intermediate stage circuit 2 is actually the sum of the first input current and the first compensation current. When the input signal voltage is at an intermediate level (e.g., the median value between the positive and negative power supply values), the first P-tube 701, the second P-tube 702, the first N-tube 801, and the second N-tube 802 are all turned on. The voltage at point a deviates slightly from the positive power supply value and decreases, while the voltage at point b deviates slightly from the negative power supply value and increases. The gate-source voltage difference of the sixth P-tube 706 is insufficient to turn it on, so the sixth P-tube 706 is turned off. No current flows into point b from the fifth N-tube 805. The gate-source voltage difference of the sixth N-tube 806 is insufficient to turn it on, so the sixth N-tube 806 is turned off. No current flows into point a from the fifth P-tube 705. That is, at this time, the current... The current compensation module 12 does not compensate for the output current of the signal input module 11. At this time, the output current of the input stage circuit 1 is the sum of the currents output from the drain terminals of the first P transistor 701 and the second P transistor 702 and the currents output from the drain terminals of the first N transistor 801 and the second N transistor 802. At this time, the current output from the drain terminals of the first P transistor 701 and the second P transistor 702 is only the current flowing through the third P transistor 703, and the current output from the drain terminals of the first N transistor 801 and the second N transistor 802 is only the current flowing through the third N transistor 803. That is, the first output current output by the first input unit is the first input current, and the second output current output by the second input unit is the second input current. That is, the output current of the input stage circuit 1 to the intermediate stage circuit 2 is the sum of the first input current and the second input current. Therefore, the output current of the input stage circuit 1 does not change significantly (the parameters of each P transistor and N transistor are properly selected), and transconductance conservation is achieved.

[0040] In fact, even if the voltage of the input signal is not as high as the positive value of the power supply, but is slightly lower than the positive value of the power supply and is close to the positive value of the power supply, the first P transistor 701 and the second P transistor 702 are not completely turned off but are in a semi-conducting and semi-off state. The first input unit 111 still outputs the first output current to the intermediate stage circuit 2, but the first output current is lower than the current value when the first P transistor 701 and the second P transistor 702 are fully turned on. At the same time, the voltage at point a will also cause the sixth P transistor 706 to be in a semi-conducting and semi-off state, not fully turned on. The current flowing through the sixth P transistor 706 is also lower than the current when it is fully turned on, and the current copied to the fifth N transistor 805 is also lower. That is, the actual value of the second compensation current is also lower. At this time, the output current of the input stage circuit 1 is also the sum of the first output current and the second output current. However, because the first output current and the second compensation current are lower than the fully turned-on state, the sum of the currents is almost the same as the sum of the currents in other states, so transconductance can still be guaranteed. Similarly, when the input signal voltage is not as low as the negative power supply value, but slightly higher than the negative power supply value and is close to the negative power supply value, the first N transistor 801 and the second N transistor 802 are not completely off but in a semi-conducting and semi-off state. The second input unit 112 still outputs the second output current to the intermediate stage circuit 2, but the second output current is lower than the current value when the first N transistor 801 and the second N transistor 802 are fully on. At the same time, the voltage at point b will also cause the sixth N transistor 806 to be in a semi-conducting and semi-off state, not fully on. The current flowing through the sixth N transistor 806 is also lower than the current when it is fully on, and the current copied to the fifth P transistor 705 is also lower. That is, the actual value of the first compensation current is also lower. At this time, the output current of the input stage circuit 1 is also the sum of the first output current and the second output current. However, because the second output current and the first compensation current are lower than the fully on state, the sum of the currents is almost the same as the sum of the currents in other states, so transconductance can still be guaranteed. Therefore, as mentioned above, this application does not need to strictly define how much distance from the endpoint can be called the adjacent endpoint value. That is just a name used for the convenience of description. This application can indeed achieve the stability of the output current at any time and maintain the conservation of transconductance.

[0041] In one embodiment, the intermediate stage circuit 2 includes a gain amplification unit (unlabeled) and a coupled voltage clamping structure (unlabeled).

[0042] The gain amplification unit is used to amplify the gain under the action of the output current provided by the input stage circuit 1 and output an intermediate voltage.

[0043] In this embodiment, the voltage clamping structure is used to clamp the intermediate voltage output by the gain amplification unit to a preset range.

[0044] Because in high-voltage circuits, if the intermediate voltage output by intermediate stage circuit 2 is not limited, it may exceed the voltage withstand range of output stage circuit 3, thereby affecting the normal operation of the entire circuit. This application provides a voltage clamping structure in intermediate stage circuit 2 to clamp the intermediate voltage output by intermediate stage circuit 2 to a preset range, which is within the voltage withstand range of output stage circuit 3, so that output stage circuit 3 can continue to operate normally.

[0045] In one embodiment, the gain amplification unit may include a seventh P-transistor 707, an eighth P-transistor 708, a tenth P-transistor 710, an eleventh P-transistor 711, a seventh N-transistor 807, an eighth N-transistor 808, a tenth N-transistor 810, an eleventh N-transistor 811, a first resistor 91, and a second resistor 92; the voltage clamping structure may include a ninth P-transistor 709, a twelfth P-transistor 712, a ninth N-transistor 809, and a twelfth N-transistor 812.

[0046] In this embodiment, the source terminals of the seventh P-tube 707 and the tenth P-tube 710 are coupled to the positive voltage terminal VSH of the power supply. The source terminal of the eighth P-tube 708 is coupled to the drain terminal of the seventh P-tube 707. The source terminal of the ninth P-tube 709 is coupled to the drain terminal of the eighth P-tube 708. The drain terminal of the ninth P-tube 709 is coupled to the first terminal of the first resistor 91. The source terminal of the eleventh P-tube 711 is coupled to the drain terminal of the tenth P-tube 710. The source terminal of the twelfth P-tube 712 is coupled to the drain terminal of the eleventh P-tube 711. The drain terminal of the twelfth P-tube 712 is coupled to the first terminal of the second resistor 92. The gate terminals of the seventh P-tube 707 and the tenth P-tube 710 are coupled to the eighth P-tube 707. The drain of the 8th P-tube 708 and the gate of the eleventh P-tube 711 are coupled to the operating voltage of the P-tubes. The gate of the ninth P-tube 709 and the gate of the twelfth P-tube 712 are coupled to the clamping control voltage of the P-tubes. The drain of the seventh P-tube 707 is also coupled to the drain of the first N-tube 801. The drain of the tenth P-tube 710 is also coupled to the drain of the second N-tube 802. The drain of the first N-tube 801 and the drain of the second N-tube 802 can be collectively referred to as the output terminal of the second input unit 112 that outputs current to the intermediate stage circuit 2. Therefore, the drain of the seventh P-tube 707 and the drain of the tenth P-tube 710 can also be referred to as the output terminal of the signal input module 11. The source terminals of the seventh N-transistor 807 and the tenth N-transistor 810 are coupled to the negative voltage terminal VSL of the power supply. The source terminal of the eighth N-transistor 808 is coupled to the drain terminal of the seventh N-transistor 807. The source terminal of the ninth N-transistor 809 is coupled to the drain terminal of the eighth N-transistor 808. The drain terminal of the ninth N-transistor 809 is coupled to the second terminal of the first resistor 91. The source terminal of the eleventh N-transistor 811 is coupled to the drain terminal of the tenth N-transistor 810. The source terminal of the twelfth N-transistor 812 is coupled to the drain terminal of the eleventh N-transistor 811. The drain terminal of the twelfth N-transistor 812 is coupled to the second terminal of the second resistor 92. The gate terminals of the seventh N-transistor 807 and the tenth N-transistor 810 are coupled to the drain terminal of the eighth N-transistor 808. The gate terminals of the eighth N-transistor 808 and the eleventh N-transistor 811 are coupled to the operating voltage of the N-transistor. The gate terminals of the ninth N-transistor 809 and the twelfth N-transistor 812 are coupled to the clamping control voltage of the N-transistor. The drain terminal of the seventh N-transistor 807 is also coupled to the drain terminal of the first P-transistor 701. The drain terminal of the tenth N-transistor 810 is also coupled to the drain terminal of the second P-transistor 702. The drain terminals of the first P-transistor 701 and the second P-transistor 702 can be collectively referred to as the output terminals of the first input unit 111 that output current to the intermediate stage circuit 2. Therefore, the drain terminals of the seventh N-transistor 807 and the tenth N-transistor 810 can also be referred to as the output terminals of the signal input module 11.

[0047] In this embodiment, the drain terminals of the eleventh P transistor 711 and the eleventh N transistor 811 serve as the first and second output terminals of the intermediate stage circuit 2, respectively, to be coupled to the output stage circuit 3.

[0048] In this embodiment, the intermediate stage circuit 2, also known as the gain stage, has fixed voltages coupled to the gate terminals of each P-transistor and each N-transistor, and each P-transistor and each N-transistor remains in a conducting state during operation. Specifically, for the twelfth P-transistor 712, according to the conduction condition of the P-transistor (the voltage difference between the source and gate voltages must be greater than the threshold voltage), Vo - Vrefp > Vth. Vo is the source voltage of the twelfth P-transistor 712, Vrefp is the gate voltage of the twelfth P-transistor 712 (i.e., the P-transistor clamping control voltage), and Vth is the threshold voltage of the twelfth P-transistor 712. Therefore, Vo > Vrefp + Vth, meaning the lowest voltage at the source terminal of the twelfth P-transistor 712 is only the P-transistor clamping control voltage + the P-transistor threshold voltage. This is also the drain voltage of the eleventh P-transistor 711. The voltage output from the first output terminal of the intermediate stage circuit 2 to the output stage circuit 3 is clamped to a minimum of the P-transistor clamping control voltage + the P-transistor threshold voltage. Similarly, the drain of the eleventh N-channel transistor 811 serves as the second output terminal of the intermediate stage circuit 2, and the voltage output to the output stage circuit 3 is clamped at a maximum of the N-channel transistor clamping control voltage minus the N-channel transistor's threshold voltage. Because the voltage output from the first output terminal of the intermediate stage circuit 2 is clamped at a minimum of the P-channel transistor clamping control voltage plus the P-channel transistor's threshold voltage, and the voltage output from the second output terminal is clamped at a maximum of the N-channel transistor clamping control voltage minus the N-channel transistor's threshold voltage, damage to the output stage circuit 3 can be avoided. The specific principle will be explained in detail later after the internal structure of the output stage circuit 3 is described. Additionally, the first resistor 91 and the second resistor 92 bear a certain voltage drop, ensuring stable circuit operation and helping to reduce power consumption.

[0049] In one embodiment, the ninth P-tube 709, the twelfth P-tube 712, the ninth N-tube 809, and the twelfth N-tube 812 are all high-voltage devices, while the seventh P-tube 707, the eighth P-tube 708, the tenth P-tube 710, the eleventh P-tube 711, the seventh N-tube 807, the eighth N-tube 808, the tenth N-tube 810, and the eleventh N-tube 811 are all low-voltage devices. The terms "high-voltage device" and "low-voltage device" refer to devices with varying voltage withstand capabilities, a well-known basic parameter among those skilled in the art. Specific numerical ranges can be set according to the actual application environment. Because the operational amplifiers in this application are mainly used in high-voltage circuits, it is preferable that all P-tubes and all N-tubes are high-voltage devices. However, because the lowest voltage at the source terminal of the twelfth P-channel transistor 712 is the P-channel clamping control voltage plus the P-channel threshold voltage, and similarly, the highest voltage at the source terminal of the twelfth N-channel transistor 812 is the N-channel clamping control voltage minus the N-channel threshold voltage, the voltage differences between the source, drain, and gate terminals of the seventh P-channel transistor 707, the eighth P-channel transistor 708, the tenth P-channel transistor 710, and the eleventh P-channel transistor 711 are not very large. Since it is not a high-voltage environment, low-voltage devices can be used without considering high-voltage requirements. The same applies to the seventh N-channel transistor 807, the eighth N-channel transistor 808, the tenth N-channel transistor 810, and the eleventh N-channel transistor 811. However, the ninth P-channel transistor 709, the twelfth P-channel transistor 712, the ninth N-channel transistor 809, and the twelfth N-channel transistor 812 still require high-voltage devices to meet high-voltage requirements. This satisfies the voltage requirements of each P-channel and each N-channel transistor while minimizing the overall circuit area (the area occupied by low-voltage devices is smaller than that of high-voltage devices).

[0050] In one embodiment, the output stage circuit 3 may include a thirteenth P-channel transistor 713 and a thirteenth N-channel transistor 813. The source terminal of the thirteenth P-channel transistor 713 is coupled to the positive voltage terminal VSH of the power supply, and the source terminal of the thirteenth N-channel transistor 813 is coupled to the negative voltage terminal VSL of the power supply. The gate terminal of the thirteenth P-channel transistor 713 is coupled to the drain terminal of the eleventh P-channel transistor 711, and the gate terminal of the thirteenth N-channel transistor 813 is coupled to the drain terminal of the eleventh N-channel transistor 811. Since the drain terminals of the eleventh P-channel transistor 711 and the eleventh N-channel transistor 811 are respectively the first and second output terminals of the intermediate stage circuit 2, it can also be said that the gate terminals of the thirteenth P-channel transistor 713 and the thirteenth N-channel transistor 813 are respectively coupled to the output terminals of the intermediate stage circuit 2. The drain terminals of the thirteenth P-channel transistor 713 and the thirteenth N-channel transistor 813 are coupled to the signal output terminal out.

[0051] That is, the output stage circuit 3 mainly includes a P-type transistor and an N-type transistor. The gate terminal of the P-type transistor is coupled to the first output terminal of the intermediate stage circuit 2, and the gate terminal of the N-type transistor is coupled to the second output terminal of the intermediate stage circuit 2. The complete principle by which the voltage clamping structure of the intermediate stage circuit 2 prevents damage to the output stage circuit 3 is as follows: As described above, all P-type transistors and all N-type transistors in the intermediate stage circuit 2 are in a continuously conducting state during normal operation. When the voltage of the input signal is pulled upward, the current in the first P-type transistor 701 and the second P-type transistor 702 of the input stage circuit 1 continuously decreases until they are turned off, the current flowing from the drain terminals of the first P-type transistor 701 and the second P-type transistor 702 to the intermediate stage circuit 2 continuously decreases until it even reaches 0, the current in the first N-type transistor 801 and the second N-type transistor 802 continuously increases, and the current flowing from the drain terminals of the first N-type transistor 801 and the second N-type transistor 802 to the intermediate stage circuit 2 continuously increases, which causes the voltage at the first output terminal of the intermediate stage circuit 2 to drop. The first output terminal of the intermediate stage circuit 2 is coupled to the gate terminal of the P-type transistor in the output stage circuit 3. If the voltage at the first output terminal of the intermediate stage circuit 2 drops too much, it may exceed the withstand voltage of the P-type transistor and cause damage to the device (the source terminal voltage of this P-type transistor remains unchanged). In the present application, due to the voltage clamping structure of the intermediate stage circuit 2, the voltage at the first output terminal of the intermediate stage circuit 2 is clamped at a minimum of the P-type transistor clamping control voltage plus the threshold voltage of the P-type transistor. As long as the specific values of each parameter are pre-designed so that the sum of the P-type transistor clamping control voltage and the threshold voltage of the P-type transistor is greater than the difference between the positive power supply voltage and the withstand voltage of the P-type transistor (for the P-type transistor in the output stage circuit 3, no damage will occur if Vgs < Vp, where Vgs is the differential pressure by which the source terminal voltage is higher than the gate terminal voltage, and Vp is the withstand voltage of the P-type transistor), damage to the P-type transistor in the output stage circuit 3 can be absolutely avoided. Similarly, when the voltage of the input signal drops, the current in the first N-type transistor 801 and the second N-type transistor 802 of the input stage circuit 1 continuously decreases until they are turned off, the current flowing from the drain terminals of the first N-type transistor 801 and the second N-type transistor 802 to the intermediate stage circuit 2 continuously decreases until it even reaches 0, the current in the first P-type transistor 701 and the second P-type transistor 702 continuously increases, and the current flowing from the drain terminals of the first P-type transistor 701 and the second P-type transistor 702 to the intermediate stage circuit 2 continuously increases, which causes the voltage at the second output terminal of the intermediate stage circuit 2 to rise.The second output terminal of the intermediate stage circuit 2 is coupled to the gate terminal of the N-type transistor in the output stage circuit 3. If the voltage at the second output terminal of the intermediate stage circuit 2 rises too much, the withstand voltage of the N-type transistor may be exceeded, resulting in device damage (the source terminal voltage of this N-type transistor remains constant). In the present application, due to the voltage clamping structure of the intermediate stage circuit 2, the voltage at the second output terminal of the intermediate stage circuit 2 is clamped at a maximum value equal to the N-type transistor clamping control voltage minus the threshold voltage of the N-type transistor. As long as the specific values of each parameter are pre-designed to make the difference between the N-type transistor clamping control voltage and the threshold voltage of the N-type transistor smaller than the sum of the negative power supply and the withstand voltage value of the N-type transistor (for the N-type transistor in the output stage circuit 3, damage will not occur if Vgs < Vn, where Vgs is the differential pressure by which the gate terminal voltage is higher than the source terminal voltage, and Vn is the withstand voltage value of the N-type transistor), the damage to the N-type transistor in the output stage circuit 3 can be absolutely avoided.

[0052] In one embodiment, the high-voltage rail-to-rail operational amplifier may further include: a compensation capacitor circuit 4 coupled between the intermediate stage circuit 2 and the output stage circuit 3.

[0053] In this embodiment, the compensation capacitor circuit 4 may include a first capacitor 41 and a second capacitor 42. One end of the first capacitor 41 and one end of the second capacitor 42 are respectively coupled to the intermediate stage circuit 2, and the other end of the first capacitor 41 and the other end of the second capacitor 42 are coupled to the output terminal of the output stage circuit 3.

[0054] Specifically, the first capacitor 41 is coupled between the drain terminal of the tenth P-type transistor 710 and the signal output terminal out, and the second capacitor 42 is coupled between the drain terminal of the tenth N-type transistor 810 and the signal output terminal out. Please refer to Figure 2 The loop gain amplitude-frequency and phase-frequency simulation diagram of the operational amplifier of the present application. In the present application, the compensation capacitor circuit 4 utilizes the Miller effect to make a secondary pole appear in the loop gain amplitude-frequency and phase-frequency simulation diagram ( Figure 2 Q2 therein). If there is no compensation capacitor circuit 4, there will only be a main pole ( Figure 2 Q1 therein). In the present application, the cooperation of the main pole and the secondary pole can expand the phase margin, thereby enhancing system stability.

[0055] In this embodiment, the operating voltages of the P-tube and N-tube are also used in general operational amplifiers. This application can use the bias voltage generation circuit in a general operational amplifier to generate the operating voltages of the P-tube and N-tube. The P-tube clamping control voltage and N-tube clamping control voltage are specifically set for this application. In one embodiment, the high-voltage rail-to-rail operational amplifier further includes a fourteenth P-tube 714, a fifteenth P-tube 715, a fourteenth N-tube 814, a fifteenth N-tube 815, and a current source 93; the source terminal of the fourteenth P-tube 714 is coupled to the positive voltage terminal VSH of the power supply, the gate terminal of the fourteenth P-tube 714 is coupled to the drain terminal of the fourteenth P-tube 714, the drain terminal of the fourteenth P-tube 714 is coupled to the source terminal of the fifteenth P-tube 715, and the gate terminal of the fifteenth P-tube 715 is coupled to the drain terminal of the fifteenth P-tube 715. The drain of the five-p transistor 715 is coupled to the first terminal of the current source 93; the source of the fourteenth N transistor 814 is coupled to the negative voltage terminal VSL of the power supply, the gate of the fourteenth N transistor 814 is coupled to the drain of the fourteenth N transistor 814, the drain of the fourteenth N transistor 814 is coupled to the source of the fifteenth N transistor 815, the gate of the fifteenth N transistor 815 is coupled to the drain of the fifteenth N transistor 815, and the drain of the fifteenth N transistor 815 is coupled to the second terminal of the current source 93; the drain of the fifteenth P transistor 715 outputs the P-transistor clamping control voltage, and the drain of the fifteenth N transistor 815 outputs the N-transistor clamping control voltage.

[0056] Based on the circuit structure described above, the required P-channel clamping control voltage and N-channel clamping control voltage can be generated. It is important to note that the specific value of the P-channel clamping control voltage must be lower than the P-channel operating voltage; otherwise, a situation may occur where the eleventh P-channel 711 in intermediate stage 2 is turned on while the twelfth P-channel 712 is not yet turned on, which is an undesirable situation in this circuit. Similarly, the specific value of the N-channel clamping control voltage must be higher than the N-channel operating voltage; otherwise, a situation may occur where the eleventh N-channel 811 in intermediate stage 2 is turned on while the twelfth N-channel 812 is not yet turned on, which is also an undesirable situation in this circuit. The lower limit of the P-channel clamping control voltage can be calculated based on the aforementioned principle that "the sum of the P-channel clamping control voltage and the P-channel threshold voltage is greater than the difference between the positive power supply value and the P-channel's withstand voltage," which is the positive power supply value minus the P-channel's withstand voltage and then minus the P-channel's threshold voltage. Similarly, the upper limit of the N-channel clamping control voltage can be calculated based on the aforementioned principle that "the difference between the N-channel clamping control voltage and the N-channel's threshold voltage is less than the sum of the negative power supply value and the N-channel's withstand voltage," which is the negative power supply value plus the N-channel's withstand voltage and then the N-channel's threshold voltage. Therefore, in one embodiment, the P-channel clamping control voltage is less than the P-channel's operating voltage and greater than the positive power supply value minus the P-channel's withstand voltage and then minus the P-channel's threshold voltage; the N-channel clamping control voltage is greater than the N-channel's operating voltage and less than the negative power supply value plus the N-channel's withstand voltage and then the N-channel's threshold voltage. Furthermore, these withstand voltage and threshold values ​​are those of high-voltage devices.

[0057] Finally, it should be noted that all MOSFETs in the input stage circuit 1 and output stage circuit 3 of this application are high-voltage devices.

[0058] Compared with the prior art, the technical solution of this application has the following beneficial effects: This application presents a high-voltage rail-to-rail operational amplifier with a current compensation module in the input stage circuit. When the actual value of the input signal is close to the positive or negative value of the power supply, the output current from the input stage circuit to the intermediate stage circuit is compensated. The transconductance of the input stage circuit can remain constant, so the entire range of the power supply voltage can be used as the operating range of the input signal. This application can achieve complete rail-to-rail operation and can process the full swing of the input signal to achieve full swing operation.

[0059] The high-voltage rail-to-rail operational amplifier of this application has a voltage clamping structure in the intermediate stage circuit, which clamps the intermediate voltage output from the intermediate stage circuit to the output stage circuit within a preset range, thereby preventing damage to the output stage circuit.

[0060] This application presents a high-voltage rail-to-rail operational amplifier with a compensation capacitor circuit between the intermediate stage circuit and the output stage circuit. Utilizing the Miller effect, a secondary pole appears in the loop gain amplitude-frequency and phase-frequency simulation diagram. Without the compensation capacitor circuit, only the primary pole would appear. This application can expand the phase margin by combining the primary and secondary poles, thereby enhancing the system stability.

[0061] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of protection of the claims. Furthermore, specific examples have been used in the specification to illustrate the principles and implementation methods of this application. The description of the above embodiments is only for the purpose of helping to understand the method and core ideas of this application, and the content of this specification should not be construed as a limitation of this application.

Claims

1. A high-voltage rail-to-rail operational amplifier, characterized in that, include: The input stage circuit, intermediate stage circuit, and output stage circuit are coupled in sequence. The input stage circuit, intermediate stage circuit, and output stage circuit are all coupled between the positive voltage terminal and the negative voltage terminal of the power supply. The power supply voltage at the positive voltage terminal is a positive value, and the power supply voltage at the negative voltage terminal is a negative value. The input stage circuit includes a signal input module and a current compensation module. The signal input module is used to receive an input signal and generate an output current to output to the intermediate stage circuit. The current compensation module is used to provide compensation current to the output current of the signal input module when the actual value of the input signal is close to the positive or negative value of the power supply. The intermediate stage circuit is used to amplify the gain under the action of the output current, output an intermediate voltage to the output stage circuit, and clamp the intermediate voltage to a preset range. The output stage circuit is used to output the target voltage under the control of the intermediate voltage.

2. The high-voltage rail-to-rail operational amplifier according to claim 1, characterized in that, The signal input module includes: a first bias unit, a second bias unit, a first input unit, and a second input unit; The first bias unit is coupled between the first input unit and the positive voltage terminal of the power supply, and is used as a first current source to provide the first input current. The second bias unit is coupled between the second input unit and the negative voltage terminal of the power supply, and is used as a second current source to provide the second input current; The first input unit is coupled to the current compensation module and outputs a first output current to the intermediate stage circuit based on the first input current and the first compensation current provided by the current compensation module. The second input unit is coupled to the current compensation module and outputs a second output current to the intermediate stage circuit based on the second input current and the second compensation current provided by the current compensation module.

3. The high-voltage rail-to-rail operational amplifier according to claim 2, characterized in that, The first input unit includes a first P-transistor and a second P-transistor, the second input unit includes a first N-transistor and a second N-transistor, the first bias unit includes a third P-transistor, and the second bias unit includes a third N-transistor. The gate terminals of the first P-type transistor and the first N-type transistor are coupled to form a first signal input terminal, and the gate terminals of the second P-type transistor and the second N-type transistor are coupled to form a second signal input terminal. The source terminals of the first P-tube and the second P-tube are coupled to the drain terminal of the third P-tube. The source terminal of the third P-tube is coupled to the positive voltage terminal of the power supply. The gate terminal of the third P-tube is coupled to the operating voltage of the P-tube. The drain terminals of the first P-tube and the second P-tube are respectively coupled to the intermediate stage circuit. The source terminals of the first N-transistor and the second N-transistor are coupled to the drain terminal of the third N-transistor. The source terminal of the third N-transistor is coupled to the negative voltage terminal of the power supply. The gate terminal of the third N-transistor is coupled to the operating voltage of the N-transistor. The drain terminals of the first N-transistor and the second N-transistor are respectively coupled to the intermediate stage circuit.

4. The high-voltage rail-to-rail operational amplifier according to claim 2, characterized in that, The current compensation module includes: a first compensation unit and a second compensation unit; The first compensation unit is coupled to the first input unit and is used to provide the first compensation current to the first input unit for current compensation when the actual value of the input signal is close to the negative value of the power supply. The second compensation unit is coupled to the second input unit and is used to provide the second compensation current to the second input unit for current compensation when the actual value of the input signal is close to the positive value of the power supply.

5. The high-voltage rail-to-rail operational amplifier according to claim 4, characterized in that, The first compensation unit includes a fourth P-tube, a fifth P-tube, and a sixth N-tube; the second compensation unit includes a sixth P-tube, a fourth N-tube, and a fifth N-tube. The source terminals of the fourth P-tube and the fifth P-tube are coupled to the positive voltage terminal of the power supply. The gate terminals of the fourth P-tube and the fifth P-tube are coupled to the drain terminal of the fourth P-tube. The drain terminal of the fifth P-tube is coupled to the coupling point of the first bias unit and the first input unit. The drain terminal of the fourth P-tube is coupled to the drain terminal of the sixth N-tube. The source terminal of the sixth N-tube is coupled to the coupling point of the second bias unit and the second input unit. The gate terminal of the sixth N-tube is coupled to the operating voltage of the N-tube. The source terminals of the fourth N-transistor and the fifth N-transistor are coupled to the negative voltage terminal of the power supply. The gate terminals of the fourth N-transistor and the fifth N-transistor are coupled to the drain terminal of the fourth N-transistor. The drain terminal of the fifth N-transistor is coupled to the coupling point of the second bias unit and the second input unit. The drain terminal of the fourth N-transistor is coupled to the drain terminal of the sixth P-transistor. The source terminal of the sixth P-transistor is coupled to the coupling point of the first bias unit and the first input unit. The gate terminal of the sixth P-transistor is coupled to the operating voltage of the P-transistor.

6. The high-voltage rail-to-rail operational amplifier according to claim 1, characterized in that, The intermediate stage circuit includes a gain amplification unit and a coupled voltage clamping structure. The gain amplification unit is used to amplify the gain under the action of the output current provided by the input stage circuit and output an intermediate voltage. The voltage clamping structure is used to clamp the intermediate voltage output by the gain amplification unit to a preset range.

7. The high-voltage rail-to-rail operational amplifier according to claim 6, characterized in that, The gain amplification unit includes a seventh P-transistor, an eighth P-transistor, a tenth P-transistor, an eleventh P-transistor, a seventh N-transistor, an eighth N-transistor, a tenth N-transistor, an eleventh N-transistor, a first resistor, and a second resistor; the voltage clamping structure includes a ninth P-transistor, a twelfth P-transistor, a ninth N-transistor, and a twelfth N-transistor. The source terminals of the seventh P-tube and the tenth P-tube are coupled to the positive voltage terminal of the power supply. The source terminal of the eighth P-tube is coupled to the drain terminal of the seventh P-tube. The source terminal of the ninth P-tube is coupled to the drain terminal of the eighth P-tube. The drain terminal of the ninth P-tube is coupled to the first terminal of the first resistor. The source terminal of the eleventh P-tube is coupled to the drain terminal of the tenth P-tube. The source terminal of the twelfth P-tube is coupled to the drain terminal of the eleventh P-tube. The drain terminal of the twelfth P-tube is coupled to the first terminal of the second resistor. The gate terminals of the seventh P-tube and the tenth P-tube are coupled to the drain terminal of the eighth P-tube. The gate terminals of the eighth P-tube and the eleventh P-tube are coupled to the operating voltage of the P-tube. The gate terminals of the ninth P-tube and the twelfth P-tube are coupled to the clamping control voltage of the P-tube. The drain terminals of the seventh P-tube and the tenth P-tube are also coupled to the output terminal of the signal input module. The source terminals of the seventh N-transistor and the tenth N-transistor are coupled to the negative voltage terminal of the power supply. The source terminal of the eighth N-transistor is coupled to the drain terminal of the seventh N-transistor. The source terminal of the ninth N-transistor is coupled to the drain terminal of the eighth N-transistor. The drain terminal of the ninth N-transistor is coupled to the second terminal of the first resistor. The source terminal of the eleventh N-transistor is coupled to the drain terminal of the tenth N-transistor. The source terminal of the twelfth N-transistor is coupled to the drain terminal of the eleventh N-transistor. The drain terminal of the twelfth N-transistor is coupled to the second terminal of the second resistor. The gate terminals of the seventh N-transistor and the tenth N-transistor are coupled to the drain terminal of the eighth N-transistor. The gate terminals of the eighth N-transistor and the eleventh N-transistor are coupled to the operating voltage of the N-transistors. The gate terminals of the ninth N-transistor and the twelfth N-transistor are coupled to the clamping control voltage of the N-transistors. The drain terminals of the seventh N-transistor and the tenth N-transistor are also coupled to the output terminal of the signal input module. The drain terminals of the eleventh P transistor and the eleventh N transistor serve as the first and second output terminals of the intermediate stage circuit, respectively, to be coupled to the output stage circuit.

8. The high-voltage rail-to-rail operational amplifier according to claim 1, characterized in that, The output stage circuit includes: a thirteenth P-transistor and a thirteenth N-transistor; The source terminal of the thirteenth P-transistor is coupled to the positive voltage terminal of the power supply, the source terminal of the thirteenth N-transistor is coupled to the negative voltage terminal of the power supply, the gate terminals of the thirteenth P-transistor and the gate terminals of the thirteenth N-transistor are respectively coupled to the output terminal of the intermediate stage circuit, and the drain terminals of the thirteenth P-transistor and the drain terminals of the thirteenth N-transistor are coupled to the signal output terminal.

9. The high-voltage rail-to-rail operational amplifier according to claim 1, characterized in that, The high-voltage rail-to-rail operational amplifier further includes: a compensation capacitor circuit coupled between the intermediate stage circuit and the output stage circuit, the compensation capacitor circuit including a first capacitor and a second capacitor; One end of the first capacitor and the second capacitor are respectively coupled to the intermediate stage circuit, and the other end of the first capacitor and the second capacitor are coupled to the output terminal of the output stage circuit.

10. The high-voltage rail-to-rail operational amplifier according to claim 1, characterized in that, The high-voltage rail-to-rail operational amplifier also includes: a fourteenth P-tube, a fifteenth P-tube, a fourteenth N-tube, a fifteenth N-tube, and a current source; The source terminal of the fourteenth P transistor is coupled to the positive voltage terminal of the power supply, the gate terminal of the fourteenth P transistor is coupled to the drain terminal of the fourteenth P transistor, the drain terminal of the fourteenth P transistor is coupled to the source terminal of the fifteenth P transistor, the gate terminal of the fifteenth P transistor is coupled to the drain terminal of the fifteenth P transistor, and the drain terminal of the fifteenth P transistor is coupled to the first terminal of the current source. The source terminal of the fourteenth N transistor is coupled to the negative voltage terminal of the power supply, the gate terminal of the fourteenth N transistor is coupled to the drain terminal of the fourteenth N transistor, the drain terminal of the fourteenth N transistor is coupled to the source terminal of the fifteenth N transistor, the gate terminal of the fifteenth N transistor is coupled to the drain terminal of the fifteenth N transistor, and the drain terminal of the fifteenth N transistor is coupled to the second terminal of the current source. The drain terminal of the fifteenth P-transistor outputs the P-transistor clamping control voltage, and the drain terminal of the fifteenth N-transistor outputs the N-transistor clamping control voltage.

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