Integrated circuit, negative voltage charge pump circuit, and electronic device

Abstract

The embodiment of the present application discloses an integrated circuit, a negative voltage charge pump circuit and an electronic device. The integrated circuit comprises a semiconductor substrate, a plurality of isolated island structures and an amplifier circuit. The semiconductor substrate has a first doping type. The isolated island structures are arranged at intervals, and each isolated island structure comprises at least a first doped region above the semiconductor substrate, and the first doped region has a second doping type. The amplifier circuit comprises a plurality of functional circuits, and the plurality of functional circuits comprise at least one transistor, and each transistor is formed in a corresponding isolated island structure. In addition, the semiconductor substrate is biased to a first negative potential to enable the amplifier circuit to support a negative voltage common-mode input, and the first negative potential is matched with the circuit structure of the amplifier circuit. Thus, the embodiment of the present application can enable the amplifier circuit in the integrated circuit to simultaneously have the ability to withstand high-voltage common-mode voltage input and negative-voltage common-mode voltage input without increasing the cost too much.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, specifically to an integrated circuit, a negative charge pump circuit, and an electronic device. Background Technology

[0002] Currently, for integrated circuits used in high-voltage and negative common-mode voltage scenarios, the amplifier circuits inside the integrated circuits usually need to be able to withstand both high-voltage and negative common-mode voltage inputs.

[0003] Taking the current sense amplifier (CSA) as an example, it has been widely used in power management, equipment protection, and system monitoring. With the development of industrial equipment, automotive electronics, and high-voltage power systems, the common-mode voltage (VCM) that CSAs need to withstand is constantly increasing, typically reaching 80V, and extending to even higher levels. Simultaneously, in applications such as motor drives and system power-off protection, CSAs also need to handle negative common-mode voltages (e.g., -4V) to ensure accurate and stable current signal detection across the entire operating voltage range.

[0004] However, achieving these capabilities presents numerous challenges for integrated circuits. Among these, the current leakage between the high-voltage well region and the semiconductor substrate due to forward bias in amplifier circuits is particularly significant. Existing technologies typically employ silicon-on-insulator (SOI) technology to isolate the high-voltage well region from the substrate, but this significantly increases manufacturing costs. Alternatively, existing technologies may introduce level-shifting circuitry at the common-mode input, but this introduces additional voltage offset and noise, and may limit dynamic response. Summary of the Invention

[0005] In view of this, the purpose of the present invention is to provide an integrated circuit, a negative voltage charge pump circuit, and an electronic device, so as to enable the amplifier circuit in the integrated circuit to simultaneously withstand high voltage common-mode voltage input and negative voltage common-mode voltage input without increasing the cost, without increasing additional voltage offset and noise, and without affecting the dynamic response.

[0006] In a first aspect, embodiments of the present invention aim to provide an integrated circuit, the integrated circuit comprising: A semiconductor substrate having a first type of doping; Multiple isolation island structures are spaced apart from each other, and each isolation island structure includes at least a first doped region located above the semiconductor substrate, the first doped region having a second doping type; The amplifier circuit includes multiple functional circuits, each including at least one transistor, and each transistor is formed within a corresponding isolation island structure. The semiconductor substrate is biased to a first negative potential so that the amplifier circuit supports negative common-mode input, and the first negative potential matches the circuit structure of the amplifier circuit.

[0007] In a second aspect, embodiments of the present invention aim to provide an electronic device, the device comprising an integrated circuit as described in the first aspect.

[0008] Thirdly, embodiments of the present invention aim to provide a negative voltage charge pump circuit, the negative voltage charge pump circuit comprising: A multi-stage negative pressure charge pump, comprising a multi-stage negative pressure charge pump connected in series, the multi-stage negative pressure charge pump being used to generate a first negative pressure; Each stage of the negative pressure charge pump includes one negative pressure charge pump unit or multiple negative pressure charge pump units connected in parallel.

[0009] The integrated circuit of this invention includes a semiconductor substrate, multiple isolation island structures, and an amplifier circuit. The semiconductor substrate has a first doping type. The isolation island structures are spaced apart, and each isolation island structure includes at least a first doped region located above the semiconductor substrate, the first doped region having a second doping type. The amplifier circuit includes multiple functional circuits, each including at least one transistor, each transistor being formed within a corresponding isolation island structure. Furthermore, the semiconductor substrate is biased to a first negative potential to enable the amplifier circuit to support negative common-mode input, the first negative potential matching the circuit structure of the amplifier circuit. Therefore, this invention allows the amplifier circuit in the integrated circuit to simultaneously withstand high-voltage and negative common-mode inputs without significantly increasing cost, without adding additional voltage offset and noise, and without affecting dynamic response. Attached Figure Description

[0010] The above and other objects, features and advantages of the present invention will become clearer from the following description of embodiments of the invention with reference to the accompanying drawings, in which: Figure 1 This is a schematic diagram of an amplifier circuit in related technologies that uses symmetrical NMOS transistors as differential input pairs; Figure 2 This is a schematic diagram of a high-voltage NMOS transistor in related technologies; Figure 3 This is a schematic diagram of an amplifier circuit in related technologies that uses symmetrical PMOS transistors as differential input pairs; Figure 4 This is a schematic diagram of a high-voltage PMOS transistor in related technologies; Figure 5 This is a schematic diagram of an integrated circuit according to an embodiment of the present invention; Figure 6 This is a schematic diagram of an electrostatic discharge circuit according to an embodiment of the present invention; Figure 7 This is a schematic diagram of a negative voltage charge pump circuit according to an embodiment of the present invention; Figure 8 This is a schematic diagram of a negative voltage charge pump circuit according to an embodiment of the present invention; Figure 9 This is a schematic diagram of a negative voltage charge pump circuit according to an embodiment of the present invention; Figure 10 This is a schematic diagram of a negative pressure charge pump unit according to an embodiment of the present invention; Figure 11 This is a timing diagram of the control level signal according to an embodiment of the present invention. Detailed Implementation

[0011] The present application is described below based on embodiments, but it is not limited to these embodiments. In the detailed description of the present application below, certain specific details are described in detail. Those skilled in the art can fully understand the present application without these details. To avoid obscuring the substance of the present application, well-known methods, processes, flows, elements, and circuits are not described in detail.

[0012] Furthermore, those skilled in the art should understand that the accompanying drawings provided herein are for illustrative purposes only and are not necessarily drawn to scale.

[0013] Unless otherwise expressly specified and limited, the terms "installation," "connection," "linking," and "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components, unless otherwise expressly limited. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0014] For ease of explanation, spatially related terms such as “inside,” “outside,” “below,” “below,” “lower,” “above,” “upper,” etc., are used herein to describe the relationship between one element or feature illustrated in the figure and another. It will be understood that spatially related terms may be intended to encompass different orientations of the device in use or operation besides those depicted in the figure. For example, if the device in the figure is flipped, an element described as “below” or “below” another element or feature would then be positioned “above” that other element or feature. Thus, the exemplified term “below” can encompass both above and below orientations. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially related descriptive terms used herein should be interpreted accordingly.

[0015] Unless the context explicitly requires it, words such as "including" or "contains" throughout the application should be interpreted as including rather than exclusive or exhaustive; that is, meaning "including but not limited to".

[0016] In the description of this application, it should be understood that the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance. Furthermore, in the description of this application, unless otherwise stated, "a plurality of" means two or more.

[0017] Figure 1 This is a schematic diagram of an amplifier circuit using symmetrical NMOS transistors as differential input pairs in related technologies. Figure 1 As shown, amplifier circuit 1 uses symmetrical transistors MN1 and MN2 (both NMOS transistors) as differential input pairs. During actual circuit operation, the non-inverting input terminal INP and the inverting input terminal INN are connected to the gates of symmetrical transistors MN1 and MN2, respectively, to input the differential signal into amplifier circuit 1.

[0018] The common-mode voltage may rise to a high voltage (e.g., 80V). To withstand this high common-mode voltage and protect the tail current IBN, transistor MN0 (an NMOS transistor) requires a high-voltage design. Simultaneously, the common-mode voltage may drop to a negative voltage (e.g., -4V). When the common-mode voltage drops to -4V, the drain of transistor MN0 (i.e., at node S) needs to operate at -5.5V to ensure proper circuit operation. However, when the drain of transistor MN0 operates at -5.5V, the PN junction between the high-voltage well region of transistor MN0 (i.e., the region carrying the drain) and the semiconductor substrate PSUB (fixed at 0V) becomes forward biased, resulting in leakage current. This leakage current clamps the drain potential of transistor MN0 at approximately -0.7V, preventing amplifier circuit 1 from functioning correctly.

[0019] Figure 2This is a schematic diagram of a high-voltage NMOS transistor in related technologies. Figure 2 The high-voltage NMOS transistor shown can be Figure 1 The transistor MN0 in the example. Figure 2 As shown, when the drain D of transistor MN0 operates at -5.5V, the PN junction between the high-voltage well region HVNW of transistor MN0 (that is, the region used to carry the drain D) and the semiconductor substrate PSUB (which is fixed at 0V) will be forward biased, thereby generating leakage current.

[0020] Figure 3 This is a schematic diagram of an amplifier circuit using symmetrical PMOS transistors as differential input pairs in related technologies. Figure 3 As shown, amplifier circuit 3 uses symmetrical transistors MP1 and MP2 (both PMOS transistors) as differential input pairs. During actual circuit operation, the non-inverting input terminal INP and the inverting input terminal INN are connected to the gates of symmetrical transistors MP1 and MN2, respectively, to input the differential signal into amplifier circuit 3.

[0021] The common-mode voltage may rise to a high voltage (e.g., 80V). To withstand this high common-mode voltage, transistors MP3 and MP4 (both PMOS transistors) require a high-voltage transistor design. Simultaneously, the common-mode voltage may drop to a negative voltage (e.g., -4V). When the common-mode voltage drops to -4V, the sources of transistors MP3 and MP4 need to operate at -3V to ensure normal circuit operation. However, when the sources of transistors MP3 and MP4 operate at -3V, the PN junction between the high-voltage well region (i.e., the back gate potential of the high-voltage PMOS transistor, where the back gate is shorted to the source) and the semiconductor substrate PSUB (fixed at 0V) will be forward biased, resulting in leakage current. This leakage current will clamp the source potential of transistors MP3 and MP4 at approximately -0.7V, preventing amplifier circuit 2 from functioning properly.

[0022] Figure 4 This is a schematic diagram of a high-voltage PMOS transistor in related technologies. Figure 4 The high-voltage NMOS transistor shown can be Figure 3 The transistor in MP3 or MP4. For example... Figure 4 As shown, when the source of transistor MP3 or MP4 is operating at -3V, the PN junction between the high-voltage well region HVNW (that is, the back gate potential of the high-voltage PMOS transistor, where the back gate is shorted to the source) and the semiconductor substrate PSUB (which is fixed at 0V) will be forward biased, thereby generating leakage current.

[0023] It should be noted that the amplifier circuits and high-voltage transistor internal structures shown above are for illustrative purposes only. In practical applications, the internal structures of amplifier circuits and high-voltage transistors can be designed and adjusted according to actual needs, and are not limited to specific configurations. Figures 1 to 4 The content shown is as follows. Furthermore, regardless of how the internal device structures of amplifier circuits and high-voltage transistors are designed and adjusted, the current leakage problem caused by forward bias between the high-voltage well region and the semiconductor substrate is a problem that integrated circuits urgently need to solve when applied to high-voltage and negative common-mode voltage scenarios.

[0024] Figure 5 This is a schematic diagram of an integrated circuit according to an embodiment of the present invention. It should be understood that... Figure 5 The integrated circuit shown can be placed in any electronic device, and this application does not limit the electronic device. Figure 5 As shown, integrated circuit 5 includes a semiconductor substrate 51, multiple isolation island structures 52, and an amplifier circuit (not shown in the figure).

[0025] The semiconductor substrate 51 serves as the carrier of the entire integrated circuit, providing necessary physical support for the integrated circuit during and after its fabrication. In this embodiment, the semiconductor substrate 51 has a first doping type. The first doping type can be either N-type or P-type doping.

[0026] Multiple isolation island structures 52 are formed on the semiconductor substrate 51. In this embodiment of the invention, the isolation island structures 52 are spaced apart. Each isolation island structure 52 includes at least a first doped region (as shown in first doped regions 5211, 5221, and 5231) located above the semiconductor substrate 51, and the first doped region has a second doping type. The second doping type can be either N-type doping or P-type doping. It should be understood that in some embodiments, each first doped region can be formed on an epitaxial layer of the semiconductor substrate.

[0027] It should be noted that, in this embodiment of the invention, each isolation island structure 52 can be considered as an independent isolation region. The interior of each isolation island structure 52 can be used as a carrier for forming transistors. Thus, by forming each transistor inside a different isolation island structure 52, this embodiment of the invention can achieve isolation between the transistor and the semiconductor substrate 51, as well as isolation between different transistors. It should be understood that the transistor can be formed directly inside the isolation island structure 52, or it can be formed inside the corresponding doped region surrounded by the isolation island structure 52; this application does not limit this.

[0028] An amplifier circuit refers to a circuit disposed within an integrated circuit device for implementing signal gain and other auxiliary functions. An amplifier circuit may include multiple functional circuits. These multiple functional circuits may include at least one transistor. In this embodiment of the invention, each transistor may be formed within a corresponding isolation island structure 52. Furthermore, in this embodiment of the invention, the semiconductor substrate 51 is biased to a first negative potential so that the amplifier circuit supports negative common-mode input.

[0029] It should be understood that, in order to avoid forward biasing of the PN junction between the first doped region (e.g., the first doped region 5211) in the isolation island structure 52 and the semiconductor substrate 51, the first negative potential needs to be matched with the circuit structure of the amplifier circuit. (Illustratively, with...) Figure 1 Taking the amplifier circuit shown as an example, the first negative voltage potential needs to be lower than the lowest drain potential of transistor MN0. Figure 2 Taking the amplifier circuit shown as an example, the first negative voltage potential needs to be lower than the lowest source potential of transistor MP3. Alternatively, as a preferred configuration, the first negative potential can also be directly configured to the lowest negative voltage potential of the integrated circuit to match all amplifier circuits.

[0030] Alternatively, the amplifier circuit can be a current sense amplifier (CSA) (such as...). Figure 1 and Figure 3 (The amplifier circuit is shown in the figure). It should be understood that in some embodiments, the amplifier circuit may also be an operational amplifier (OPAMP), a programmable gain amplifier (PGA), an instrumentation amplifier (INA), or an analog front-end for various signal acquisitions, etc., and this application does not limit it in this regard.

[0031] Compared to existing technologies, the integrated circuit in this embodiment of the invention can be fabricated using standard BCD (Bipolar-CMOS-DMOS) technology. Therefore, this embodiment of the invention can enable the amplifier circuit in the integrated circuit to simultaneously withstand both high-voltage and negative common-mode voltage inputs without significantly increasing costs, and without adding additional voltage offset or noise, or affecting dynamic response.

[0032] Optionally, in addition to the semiconductor substrate 51, the plurality of isolation island structures 52, and the amplifier circuit, the integrated circuit may also include a plurality of high-voltage isolation well regions 53. The plurality of high-voltage isolation well regions 53 may be formed on the semiconductor substrate 51 on which the isolation island structures 52 are not formed. It should be understood that in some embodiments, the plurality of high-voltage isolation well regions 53 may be formed on the epitaxial layer of the semiconductor substrate 51 on which the isolation island structures 52 are not formed. The plurality of high-voltage isolation well regions 53 can be used to isolate each isolation island structure 52. It should be understood that each high-voltage isolation well region 53 may have a first doping type. The specific shape of each high-voltage isolation well region 53 can be set by the designer according to actual needs, and this application does not limit this. In some embodiments, the specific shape of the high-voltage isolation well region 53 may be determined based on the formed plurality of isolation island structures 52. And, in some embodiments, the plurality of high-voltage isolation well regions 53 may also be replaced by ordinary well regions (i.e., low-voltage well regions). Alternatively, multiple high-voltage isolation trap regions 53 may be disposed only above the semiconductor substrate 51 on which the isolation island structure 52 is not formed. That is, there may be no corresponding high-voltage isolation trap region between two adjacent isolation island structures 52. This application does not impose any restrictions on this.

[0033] Optionally, multiple high-voltage isolation trap regions 53 and multiple isolation island structures 52 can be implemented by depositing an epitaxial layer on a semiconductor substrate 51, and then using a patterned mask to perform corresponding types of ion implantation and thermal diffusion in the corresponding regions of the epitaxial layer. This application does not limit this.

[0034] Optionally, depending on the transistors to be carried, the plurality of isolation island structures 52 can be configured to include at least one first isolation island structure 521. Figure 5 Specifically, there are two (in this case).

[0035] The first isolation island structure 521 serves as a carrier for forming a high-voltage transistor. Specifically, at least one transistor in a plurality of functional circuits may include a first high-voltage transistor (such as...). Figure 1 transistors MN0 and Figure 3 (See transistors MP3 and MP4 in the diagram). The first high-voltage transistor can be configured as a high-voltage transistor where the drain-source voltage difference is greater than a preset voltage threshold. In this embodiment of the invention, the first high-voltage transistor can be formed within the first doped region 5211 of the first isolation island structure 521. It should be understood that the drain-source voltage difference is configured as the absolute value of the voltage difference between the drain voltage and the source voltage. The preset voltage threshold here can be set by those skilled in the art according to the requirements of normal circuit operation; this application does not specifically limit the specific value of the preset voltage threshold.

[0036] Optionally, to meet the operating requirements of high-voltage transistors, the first doped region 5211 of the first isolation island structure 521 can be configured as a high-voltage well region. In addition to including the first doped region 5211, the first isolation island structure 521 can also be configured to include a buried layer 5212 located within the semiconductor substrate 51. The buried layer 5212 is located below the first doped region 5211 and has a second doping type. It should be understood that, as one implementation, the buried layer 5212 can be implemented by pre-implanting ions in a corresponding region of the semiconductor substrate 51 using a patterned mask before depositing the epitaxial layer; this application does not limit this implementation.

[0037] Optionally, to achieve better isolation, the number of first isolation island structures 521 can be multiple, and first high-voltage transistors of different device types can be formed in the first doped regions 5211 of different first isolation island structures 521. For example, high-voltage NMOS transistors and high-voltage PMOS transistors can be formed in different first isolation island structures. In a preferred embodiment, each first high-voltage transistor can correspond to a single first isolation island structure 521. In another embodiment, at least two first high-voltage transistors can correspond to a single first isolation island structure 521, and this application is not limited in this regard. For example, a high-voltage NMOS transistor can be formed individually in the first doped region 5211 of a first isolation island structure 521. As another example, two or more high-voltage NMOS transistors can be simultaneously formed in the first doped region 5211 of a first isolation island structure 521.

[0038] Optionally, depending on the transistors to be carried, the multiple isolation island structures 52 can also be configured to include multiple second isolation island structures 522. Figure 5 Specifically, there are three.

[0039] Among them, multiple second isolation island structures 522 are used as carriers for forming low-voltage transistors. Specifically, at least one transistor in multiple functional circuits may include a second transistor (such as...). Figure 1 Transistors MN1 and MN2 in Figure 3 (See transistors MP1 and MP2 in the diagram). The second transistor is configured such that the drain-source voltage difference is less than a preset voltage threshold. In this embodiment, the second transistor may be formed within the first doped region 5221 of the second isolation island structure 522. It should be understood that the drain-source voltage difference is configured as the absolute value of the voltage difference between the drain voltage and the source voltage. The preset voltage threshold can be set by those skilled in the art according to the requirements of normal circuit operation; this application does not specifically limit the specific value of the preset voltage threshold.

[0040] Optionally, under normal circumstances, the operating environment of the second transistor needs to match the voltage operating range of its back gate. To meet the operating requirements of the second transistor, the first doped regions 5221 of the multiple second isolation island structures 522 can be respectively used as different power supply domains. The multiple power supply domains can be configured to include a negative voltage power supply domain, a low voltage power supply domain, and a high voltage power supply domain (…). Figure 5 The multiple first doped regions 5221 in the circuit can sequentially serve as a negative power supply domain, a low power supply domain, and a high power supply domain. In this implementation, each second transistor can be formed in the negative power supply domain, the low power supply domain, or the high power supply domain based on its back gate voltage operating range. Furthermore, the negative power supply domain can be connected to the ground potential of the integrated circuit (i.e., 0V), the low power supply domain can be configured with a first voltage (e.g., 5V), and the high power supply domain can be connected to the highest potential (e.g., 80V).

[0041] It should be understood that the first voltage here can be provided by an external low-voltage power supply or by the internal low-voltage power supply of the integrated circuit. It should be noted that when the first voltage is provided by an external low-voltage power supply, if the voltage value provided by the external low-voltage power supply meets the required value, the low-voltage power supply domain can be directly electrically connected to the external low-voltage power supply. If the voltage value provided by the external low-voltage power supply does not meet the required value, the external low-voltage power supply can be reduced to the required value (e.g., from 20V to 5V) using a low-dropout regulator (LDO) before being electrically connected to the external low-voltage power supply; this application does not impose any limitations on this. Furthermore, the highest potential here can be configured as the higher of the common-mode input potential of the integrated circuit and the first voltage.

[0042] Optionally, to meet the operational requirements of the second transistor, the high-voltage power supply domain can be configured as a high-voltage well region, while the negative-voltage power supply domain and the low-voltage power supply domain can be configured as ordinary well regions (i.e., low-voltage well regions). Optionally, in part or all of the second isolation island structure 522 (e.g., in the second isolation island 522 structure including the high-voltage power supply domain), a buried layer (e.g., buried layer 5223) within the semiconductor substrate 51 is also included. It should be understood that the buried layer 5223 may be located below the first doped region 5221 and has a second doping type.

[0043] Optionally, the second transistor may include a CMOS transistor, which may be formed using a BCD process. Correspondingly, the first doped region 5221 of the second isolation island structure 522 may further include a second doped region 5222 having a first doping type. The second doped region 5222 may have the opposite doping type to the first doped region 5221. In one implementation, the second transistor (including PMOS and NMOS transistors) is formed within the first doped region 5221. In another implementation, the interiors of the first doped region 5221 and the second doped region 5222 may be used to form different types of MOS devices. Furthermore, as a configuration, the second doped region 5222 in the negative power supply domain may be configured with a second voltage (e.g., -6V). The second voltage is less than the minimum common-mode voltage. The second doped region 5222 in the low-voltage power supply domain may be electrically connected to the ground potential (i.e., 0V) of the integrated circuit. The second doped region 5222 in the high-voltage power domain can be configured to a third voltage (e.g., 75V), which is configured to be the difference between the highest potential (e.g., 80V) and the first threshold (e.g., 5V).

[0044] Optionally, depending on the transistors to be carried, the multiple isolation island structures 52 can also be configured to include a third isolation island structure 523. The third isolation island structure 523 serves as a carrier for the formation of an electrostatic discharge (ESD) circuit. Specifically, when the input voltage range of the integrated circuit is wide (covering -4V to 80V), the ESD circuit requires a high-voltage design. For ESD circuits with high-voltage designs, the ESD circuit typically needs to be isolated separately. In this embodiment, the ESD circuit can be formed separately within the first doped region 5231 of the third isolation island structure 523.

[0045] Optionally, to meet the operational requirements of the electrostatic discharge circuit, the first doped region 5231 of the third isolation island structure 523 can be configured as a high-voltage well region. In addition to including the first doped region 5231, the third isolation island structure 523 can also be configured to include a buried layer 5232 located within the semiconductor substrate 51. The buried layer 5232 is located below the first doped region 5231 and has a second doping type. As one implementation, the buried layer 5232 can be implemented by pre-implanting ions into a corresponding region of the semiconductor substrate 51 using a patterned mask before depositing the epitaxial layer; this application is not limited in this regard. It should be understood that in some embodiments, the first doped region 5231 of the third isolation island structure 523 can also be configured as a normal well region (i.e., a low-voltage well region); this application is not limited in this regard.

[0046] Optionally, the electrostatic discharge circuit can be configured to include a first high-voltage electrostatic discharge device, a second high-voltage electrostatic discharge device, and a low-voltage electrostatic discharge device. The first high-voltage electrostatic discharge device can be reverse-connected between the non-inverting input port of the integrated circuit and the semiconductor substrate, the second high-voltage electrostatic discharge device can be reverse-connected between the inverting input port of the integrated circuit and the semiconductor substrate, and the low-voltage electrostatic discharge device can be positively connected between the ground potential of the integrated circuit and the semiconductor substrate.

[0047] Figure 6 This is a schematic diagram of an electrostatic discharge circuit according to an embodiment of the present invention. Figure 6 As shown, the electrostatic discharge circuit 6 includes a first high-voltage electrostatic discharge device D1, a second high-voltage electrostatic discharge device D2, and a low-voltage electrostatic discharge device D3. The first high-voltage electrostatic discharge device D1 can be reverse-connected between the non-inverting input port 61 of the integrated circuit and the semiconductor substrate 62; the second high-voltage electrostatic discharge device D2 can be reverse-connected between the inverting input port 63 of the integrated circuit and the semiconductor substrate 62; and the low-voltage electrostatic discharge device D3 can be positively connected between the ground potential 64 of the integrated circuit and the semiconductor substrate 62.

[0048] Therefore, by rationally dividing and isolating different power supply areas, embodiments of the present invention can use standard BCD technology to achieve an amplifier circuit compatible with both high-voltage and negative-voltage common-mode input at a lower cost. Simultaneously, embodiments of the present invention can also ensure that each transistor device within the amplifier circuit can be formed in a suitable operating environment and avoid mutual interference between different transistor devices within the amplifier circuit.

[0049] Optionally, the first negative potential can be configured to be generated by a negative voltage charge pump circuit. The multi-stage negative voltage charge pump can be configured to include multiple negative voltage charge pumps connected in series. Each stage of this multi-stage negative voltage charge pump can include one negative voltage charge pump unit or multiple negative voltage charge pump units connected in parallel. It should be understood that a negative voltage charge pump unit is a hardware unit used to implement negative voltage conversion; it can convert an input non-negative voltage into a negative voltage, or it can convert an input negative voltage into a more negative voltage. In this embodiment of the invention, the multi-stage negative voltage charge pump is used to generate the first negative voltage, and the potential of the first negative voltage can be used as the first negative potential described above.

[0050] It should be noted that the negative charge pump circuit can also be integrated into an integrated circuit. Furthermore, as one implementation method, the negative charge pump circuit can be integrated into the integrated circuit as an independent circuit, or it can be integrated into the integrated circuit as a functional circuit of an amplifier circuit; this application does not impose any limitations on this. Specifically, when the negative charge pump circuit is integrated into the integrated circuit as an independent circuit, it can be formed within an independent isolation structure. When the negative charge pump circuit is integrated into the integrated circuit as a functional circuit of an amplifier circuit, the transistors within the negative charge pump circuit can also be formed separately in the corresponding power domains according to actual needs.

[0051] Optionally, the first negative voltage can be generated by a multi-stage negative voltage charge pump in different ways. Illustratively, the first negative voltage can be generated directly by the multi-stage negative voltage charge pump. Alternatively, to suppress ripple in the first negative voltage, it can also be generated by a multi-stage negative voltage charge pump in conjunction with a corresponding ripple suppression field-effect transistor. Furthermore, in addition to generating the first voltage, the negative voltage charge pump circuit can also be used to generate a second voltage. The second voltage can be configured as the voltage of the negative power rail to be provided to relevant circuits in the integrated circuit that require a negative voltage input. It should be understood that, for the second negative voltage, to suppress ripple in the second negative voltage, it can be generated by a multi-stage negative voltage charge pump in conjunction with a corresponding ripple suppression field-effect transistor. In one embodiment, the second negative voltage is used to provide to the second doped region 5222 of the negative voltage power supply domain. It should be noted that, in order to make the first negative voltage the lowest negative voltage potential of the integrated circuit, the first negative voltage can be less than the second negative voltage.

[0052] Figure 7 This is a schematic diagram of a negative voltage charge pump circuit according to an embodiment of the present invention. It should be understood that... Figure 7 The negative voltage charge pump circuit shown can be used to generate a first negative voltage and a second negative voltage. In this circuit, the first negative voltage can be directly generated by a multi-stage negative voltage charge pump. The second negative voltage can be generated by a multi-stage negative voltage charge pump in conjunction with a single ripple-suppressing field-effect transistor. For example... Figure 7 As shown, the negative charge pump circuit 7 includes a multi-stage negative charge pump 71 connected in series and a ripple suppression field-effect transistor MP0.

[0053] The multi-stage negative charge pump 71 includes a first-stage negative charge pump 711, a second-stage negative charge pump 712, and a third-stage negative charge pump 713 connected in series. The first-stage negative charge pump 711 and the second-stage negative charge pump 712 each include one negative charge pump unit. The third-stage negative charge pump 713 includes two negative charge pump units connected in parallel. The output ports of the two negative charge pump units of the third-stage negative charge pump 713 can be used as the first output port and the second output port of the multi-stage negative charge pump 71, respectively. The drain of the ripple suppression field-effect transistor MP0 is electrically connected to the first output port, and the gate of the ripple suppression field-effect transistor MP0 is electrically connected to the second output port. Optionally, the ripple suppression field-effect transistor MP0 can be implemented using a PMOS transistor. In this embodiment of the invention, the first output port of the multi-stage negative charge pump 71 can generate a first negative voltage. The source of the ripple suppression field-effect transistor MP0 can generate a second negative voltage.

[0054] It should be understood that, Figure 7 In the negative voltage charge pump circuit shown, the ripple suppression field-effect transistor MP0 can be used to suppress the ripple of the second negative voltage. It should be noted that for the ripple suppression field-effect transistor, its intrinsic gain can be used to suppress the ripple in the output voltage (i.e., the second negative voltage), and the relationship can be roughly expressed as follows:

[0055] in, This refers to the ripple in the voltage output at the second output port of the multi-stage negative pressure charge pump 71. The ripple of the voltage output at the first output port of the multi-stage negative pressure charge pump 71. For the small-signal transconductance of the ripple suppression field-effect transistor, This is the small-signal output impedance of the ripple suppression field-effect transistor.

[0056] Figure 8 This is a schematic diagram of a negative voltage charge pump circuit according to an embodiment of the present invention. It should be understood that... Figure 8 The negative charge pump circuit shown can be used to generate a first negative voltage and a second negative voltage. Specifically, in this negative charge pump circuit, the first and second negative voltages can be generated by a multi-stage negative charge pump in conjunction with a single ripple-suppressing field-effect transistor. For example... Figure 8 As shown, the negative charge pump circuit 8 includes a multi-stage negative charge pump 81 connected in series and a ripple suppression field-effect transistor MP0.

[0057] The multi-stage negative charge pump 81 includes a first-stage negative charge pump 811, a second-stage negative charge pump 812, and a third-stage negative charge pump 813 connected in series. The first-stage negative charge pump 811 and the second-stage negative charge pump 812 each include one negative charge pump unit. The third-stage negative charge pump 813 includes two negative charge pump units connected in parallel. The output ports of the two negative charge pump units of the third-stage negative charge pump 813 can be used as the first output port and the second output port of the multi-stage negative charge pump 81, respectively. The drain of the ripple suppression field-effect transistor MP0 is electrically connected to the first output port, and the gate of the ripple suppression field-effect transistor MP0 is electrically connected to the second output port. Optionally, the ripple suppression field-effect transistor MP0 can be implemented using a PMOS transistor. In this embodiment of the invention, the source of the ripple suppression field-effect transistor MP0 can generate a second negative voltage and a first negative voltage.

[0058] It should be understood that, Figure 8 In the negative voltage charge pump circuit shown, the ripple suppression field-effect transistor MP0 can be used to suppress the ripple in the second negative voltage and the first negative voltage. The suppression relationship can be referred to the above description, and will not be repeated here.

[0059] Figure 9 This is a schematic diagram of a negative voltage charge pump circuit according to an embodiment of the present invention. It should be understood that... Figure 9 The negative voltage charge pump circuit shown can be used to generate a first negative voltage and a second negative voltage. Specifically, in this negative voltage charge pump circuit, the first and second negative voltages can be generated by a multi-stage negative voltage charge pump in conjunction with two ripple-suppressing field-effect transistors. For example... Figure 9 As shown, the negative pressure charge pump circuit 9 includes a multi-stage negative pressure charge pump 91 connected in series, a first ripple suppression field-effect transistor MP1, and a second ripple suppression field-effect transistor MP2.

[0060] The multi-stage negative charge pump 91 includes a first-stage negative charge pump 911, a second-stage negative charge pump 912, and a third-stage negative charge pump 913 connected in series. The first-stage negative charge pump 911 and the second-stage negative charge pump 912 each include one negative charge pump unit. The third-stage negative charge pump 913 includes two negative charge pump units connected in parallel. The output ports of the two negative charge pump units of the third-stage negative charge pump 913 can be used as the first output port and the second output port of the multi-stage negative charge pump 91, respectively. The drain of the first ripple suppression field-effect transistor MP1 is electrically connected to the first output port, and the gate of the first ripple suppression field-effect transistor MP1 is electrically connected to the second output port. The drain of the second ripple suppression field-effect transistor MP2 is electrically connected to the first output port, and the gate of the second ripple suppression field-effect transistor MP2 is electrically connected to the second output port. Optionally, the ripple suppression field-effect transistors MP1 and MP2 can be implemented using PMOS transistors. In this embodiment of the invention, the source of the first ripple suppression field-effect transistor MP1 can generate a second negative voltage, and the source of the second ripple suppression field-effect transistor MP2 generates a first negative voltage.

[0061] It should be understood that, Figure 9 In the negative voltage charge pump circuit shown, the first ripple suppression field-effect transistor MP1 and the second ripple suppression field-effect transistor MP2 can be used to suppress the ripple in the second negative voltage and the first negative voltage, respectively. Their suppression relationship can be referred to the above description, and will not be repeated here.

[0062] Optionally, in addition to including a multi-stage negative charge pump and a ripple-suppressing MOSFET, the negative charge pump circuit may also include a clock oscillator (as shown in low-dropout regulators 72, 82, and 92) and a low-dropout regulator (as shown in low-dropout regulators 73, 83, and 93). The clock oscillator can be used to provide a clock signal to the multi-stage negative charge pump. The low-dropout regulator can be used to provide power to the clock oscillator and to provide a reference voltage to the multi-stage negative charge pump. It should be understood that the output signal of each stage of the negative charge pump is equal to the difference between the input signal of the negative charge pump and the reference voltage.

[0063] It should be noted that the internal structure of the negative voltage charge pump circuit shown above is for illustrative purposes only. In practical applications, the internal structure of the negative voltage charge pump circuit can be designed and adjusted according to actual needs, and it is not limited to... Figures 7 to 9 The diagram illustrates this. Indicatively, the negative charge pump circuit may also include a calibration circuit. This calibration circuit can be located within the low-dropout regulator to calibrate the output voltage of the negative charge pump circuit based on actual test conditions, thereby addressing process deviations.

[0064] Optionally, each negative pressure charge pump unit in a multi-stage negative pressure charge pump can adopt the same topology.

[0065] Figure 10 This is a schematic diagram of a negative pressure charge pump unit according to an embodiment of the present invention. It should be understood that... Figure 10 The negative charge pump unit shown can be any of the negative charge pump units described above, only the input voltage received by each stage of the negative charge pump unit is different. In this embodiment, the first-stage negative charge pump is described as an example. Figure 10 As shown, the negative voltage charge pump unit includes a first field-effect transistor M1, a second field-effect transistor M2, a third field-effect transistor M3, a fourth field-effect transistor M4, a fifth field-effect transistor M5, a sixth field-effect transistor M6, a first capacitor C0, a second capacitor C1, a third capacitor C2, a fourth capacitor C3, a fifth capacitor C4, and a timing generator 101. The first field-effect transistor M1, the second field-effect transistor M2, the first capacitor C1, and the second capacitor C2 are used to control the on and off states of field-effect transistors M3 and M4. Field-effect transistors M3 and M4 are used to charge or discharge the third capacitor C3 and the fourth capacitor C4, respectively. Field-effect transistors M5 and M6 are used to provide the negative voltage of the fourth capacitor C4 and the third capacitor C3 to the output port OUT, respectively.

[0066] In this embodiment, the sources of the first field-effect transistor M1, the second field-effect transistor M2, the third field-effect transistor M3, and the fourth field-effect transistor M4 are all electrically connected to a common node. This common node serves as the input port IN of the negative charge pump unit. In this embodiment, the common node is electrically connected to the ground potential (i.e., 0V) of the integrated circuit and to the output port OUT of the negative charge pump unit via the first capacitor C0. The drains (i.e., DR1, DR2, DR3, and DR4) of the first field-effect transistor M1, the second field-effect transistor M2, the third field-effect transistor M3, and the fourth field-effect transistor M4 are electrically connected to the timing generator 101 via the second capacitor C1, the third capacitor C2, the fourth capacitor C3, and the fifth capacitor C4, respectively. The gates of the second field-effect transistor M2 and the third field-effect transistor M3 are electrically connected to the drain DR1 of the first field-effect transistor M1. The gates of the first field-effect transistor M1 and the fourth field-effect transistor M4 are electrically connected to the drain DR2 of the second field-effect transistor M2. The source of the fifth field-effect transistor M5 is electrically connected to the output port OUT of the negative voltage charge pump unit, its gate is electrically connected to the drain DR3 of the third field-effect transistor M3, and its drain is electrically connected to the drain DR4 of the fourth field-effect transistor M4. The source of the sixth field-effect transistor M5 is electrically connected to the output port OUT of the negative voltage charge pump unit, its gate is electrically connected to the drain of the fourth field-effect transistor M4, and its drain is electrically connected to the drain DR3 of the third field-effect transistor M3.

[0067] Optionally, the MOS transistors used in the first field-effect transistor M1, the second field-effect transistor M2, the third field-effect transistor M3, and the fourth field-effect transistor M4 can be of the opposite type to those used in the fifth field-effect transistor M5 and the sixth field-effect transistor M6. Schematic, the first field-effect transistor M1, the second field-effect transistor M2, the third field-effect transistor M3, and the fourth field-effect transistor M4 can be implemented using PMOS transistors. The fifth field-effect transistor M5 and the sixth field-effect transistor M6 can be implemented using NMOS transistors. Furthermore, to reduce the on-chip capacitor area, the first capacitor C0, the second capacitor C1, the third capacitor C2, the fourth capacitor C3, and the fifth capacitor C4 can be implemented using stackable capacitors such as MOS capacitors, DTC (Deep Trench Capacitor) capacitors, or MIM (Metal-Insulator-Metal Capacitor) capacitors; this application does not impose any limitations on this.

[0068] Timing generator 101 is configured to provide control level signals to each field-effect transistor in the negative charge pump unit to control the negative charge pump unit to output corresponding negative level signals. The control level signals can include low-level signals or high-level signals. Low-level signals are zero-level signals, and high-level signals are reference voltages.

[0069] Figure 11 This is a timing diagram of the control level signals according to an embodiment of the present invention. Figure 11 As shown, at time T1, the timing generator 101 can control the control level signal PH2 output to the second field-effect transistor M2 from a low level signal to a high level signal (e.g., from 0V to 3V). At this time, the drain potential DR2 of the second field-effect transistor M2 will become 0V (the reference voltage value needs to be set to be the same as the full charge voltage drop of the third capacitor C2). This drain potential DR2 will turn off the first field-effect transistor M1 and the fourth field-effect transistor M4.

[0070] At time T2, timing generator 101 can control the control level signal PH4 output to the fourth field-effect transistor M4 from a high level signal to a low level signal (e.g., from 3V to 0V). At this time, the drain potential DR4 of the fourth field-effect transistor M4 will become -3V (specifically, it is the superposition of the input voltage received by the negative charge pump unit and the full charge voltage drop of the fifth capacitor C4; for example, if the input voltage received by the negative charge pump unit is 0V and the full charge voltage drop of the fifth capacitor C4 is 3V, then the drain potential DR4 is -3V). This drain potential DR4 will turn off the sixth field-effect transistor M6.

[0071] At time T3, timing generator 101 can control the control level signal PH3 output to the third field-effect transistor M3 from a low level to a high level (e.g., from 0V to 3V). At this time, the drain DR3 potential of the third field-effect transistor M3 will become 0V (the reference voltage value must be set to be the same as the full charge voltage drop of the fourth capacitor C3). This drain DR3 potential will turn on the fifth field-effect transistor M5. The conduction of the fifth field-effect transistor M5 will cause the drain DR4 potential to be output by the output port OUT. It should be understood that since the control level signal PH1 output by timing generator 101 to the first field-effect transistor M1 is maintained at a high level at this time, the third field-effect transistor M3 is in the off state, and the charge stored in the third capacitor C2 will not leak from the input port IN. At the same time, since the sixth field-effect transistor M6 has been turned off at time T2, the charge stored in the third capacitor C2 will not leak from the output port OUT.

[0072] At time T4, the timing generator 101 can control the control level signal PH1 output to the first field-effect transistor M1 to change from a high level signal to a low level signal (e.g., from 3V to 0V). At this time, the drain potential DR1 of the first field-effect transistor M1 will become -3V (specifically, it is the superposition of the input voltage received by the negative charge pump unit and the full charge voltage drop of the second capacitor C1; for example, if the input voltage received by the negative charge pump unit is 0V and the full charge voltage drop of the second capacitor C1 is 3V, then the drain potential DR3 will be -3V). This drain potential DR1 will turn on the second field-effect transistor M2 and the third field-effect transistor M3, thereby replenishing the charge of the third capacitor C2 and the fourth capacitor C3.

[0073] Furthermore, at time T1', the timing generator 101 can control the control level signal PH1 output to the first field-effect transistor M1 from a low level signal to a high level signal (e.g., from 0V to 3V). At this time, the drain DR1 potential of the first field-effect transistor M1 will become 0V (the reference voltage value needs to be set to be the same as the full charge voltage drop of the second capacitor C1). This drain DR1 potential will turn off the second field-effect transistor M2 and the third field-effect transistor M3.

[0074] At time T2', the timing generator 101 can control the control level signal PH3 output to the third field-effect transistor M3 from a high level signal to a low level signal (e.g., from 3V to 0V). At this time, the drain potential DR3 of the third field-effect transistor M3 will become -3V (specifically, it is the superposition of the input voltage received by the negative charge pump unit and the full charge voltage drop of the fourth capacitor C3; for example, if the input voltage received by the negative charge pump unit is 0V and the full charge voltage drop of the fourth capacitor C3 is 3V, then the drain potential DR3 is -3V). This drain potential DR3 will turn off the fifth field-effect transistor M5.

[0075] At time T3', timing generator 101 can control the control level signal PH4 output to the fourth field-effect transistor M4 from a low level to a high level (e.g., from 0V to 3V). At this time, the drain DR4 potential of the fourth field-effect transistor M4 will become 0V (the reference voltage value must be set to be the same as the full charge voltage drop of the fifth capacitor C4). This drain DR4 potential will turn on the sixth field-effect transistor M6. The conduction of the sixth field-effect transistor M6 will cause the drain DR3 potential to be output by the output port OUT. It should be understood that since the control level signal PH2 output by timing generator 101 to the second field-effect transistor M2 is maintained at a high level at this time, the fourth field-effect transistor M4 is in the off state, and the charge stored in the fifth capacitor C4 will not leak from the input port IN. At the same time, since the fifth field-effect transistor M5 has been turned off at time T2', the charge stored in the fifth capacitor C4 will not leak from the output port OUT.

[0076] At time T4', the timing generator 101 can control the control level signal PH2 output to the second field-effect transistor M2 from a high level signal to a low level signal (e.g., from 3V to 0V). At this time, the drain potential DR2 of the second field-effect transistor M2 will become -3V (specifically, the superposition of the input voltage received by the negative charge pump unit and the full charge voltage drop of the third capacitor C2; for example, if the input voltage received by the negative charge pump unit is 0V and the full charge voltage drop of the third capacitor C2 is 3V, then the drain potential DR2 is -3V). This drain potential DR2 will turn on the first field-effect transistor M1 and the fourth field-effect transistor M4, thereby replenishing the charge of the second capacitor C1 and the fifth capacitor C4. Thus, by continuously executing the above process, the negative charge pump unit can input a stable negative level signal. The specific value of this negative level signal is the superposition of the input voltage received by the negative charge pump unit and the full charge voltage drop of the fourth capacitor C3 or the fifth capacitor C4.

[0077] The integrated circuit of this invention includes a semiconductor substrate, multiple isolation island structures, and an amplifier circuit. The semiconductor substrate has a first doping type. The isolation island structures are spaced apart, and each isolation island structure includes at least a first doped region located above the semiconductor substrate, the first doped region having a second doping type. The amplifier circuit includes multiple functional circuits, each including at least one transistor, each transistor being formed within a corresponding isolation island structure. Furthermore, the semiconductor substrate is biased to a first negative potential to enable the amplifier circuit to support negative common-mode input, the first negative potential matching the circuit structure of the amplifier circuit. Therefore, this invention allows the amplifier circuit in the integrated circuit to simultaneously withstand high-voltage and negative common-mode inputs without significantly increasing cost, without adding additional voltage offset and noise, and without affecting dynamic response.

[0078] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. An integrated circuit, characterized in that, The integrated circuit includes: A semiconductor substrate having a first type of doping; Multiple isolation island structures are spaced apart from each other, and each isolation island structure includes at least a first doped region located above the semiconductor substrate, the first doped region having a second doping type; The amplifier circuit includes multiple functional circuits, each including at least one transistor, and each transistor is formed within a corresponding isolation island structure. The semiconductor substrate is biased to a first negative potential so that the amplifier circuit supports negative common-mode input, and the first negative potential matches the circuit structure of the amplifier circuit.

2. The integrated circuit according to claim 1, characterized in that, The integrated circuit also includes: Multiple high-voltage isolation trap regions are formed on a semiconductor substrate where the isolation island structure is not formed, and the multiple high-voltage isolation trap regions are used to isolate each of the isolation island structures.

3. The integrated circuit according to claim 1, characterized in that, The first negative potential is configured as the lowest negative voltage potential of the integrated circuit.

4. The integrated circuit according to claim 1, characterized in that, The plurality of isolation island structures include at least one first isolation island structure, the at least one transistor includes a first high-voltage transistor, the first high-voltage transistor is configured as a high-voltage transistor with a drain-source voltage difference greater than a preset voltage threshold, the first high-voltage transistor is formed in a first doped region of the first isolation island structure, and the drain-source voltage difference is configured as the absolute value of the voltage difference between the drain voltage and the source voltage.

5. The integrated circuit according to claim 4, characterized in that, The first doped region of the first isolation island structure is a high-voltage well region. The first isolation island structure also includes a buried layer located in the semiconductor substrate. The buried layer is located below the first doped region and has a second doping type.

6. The integrated circuit according to claim 4, characterized in that, Each of the first high-voltage transistors corresponds to a separate first isolation island structure.

7. The integrated circuit according to claim 4, characterized in that, At least two of the first high-voltage transistors correspond to a single first isolation island structure.

8. The integrated circuit according to claim 4, characterized in that, The number of the first isolation island structures is multiple, and the first high voltage transistors of different device types are respectively formed in the first doped region of the first isolation island structure.

9. The integrated circuit according to claim 1, characterized in that, The plurality of isolation island structures include a plurality of second isolation island structures, the at least one transistor includes a second transistor, the second transistor is configured as a transistor with a drain-source voltage difference less than a preset voltage threshold, the second transistor is formed in a first doped region of the second isolation island structure, and the drain-source voltage difference is configured as the absolute value of the voltage difference between the drain voltage and the source voltage.

10. The integrated circuit according to claim 9, characterized in that, The first doped regions of the plurality of second isolation island structures are respectively used as different power supply domains. The plurality of power supply domains include a negative power supply domain, a low-voltage power supply domain, and a high-voltage power supply domain. The negative power supply domain is electrically connected to the ground potential of the integrated circuit, the low-voltage power supply domain is configured with a first voltage, and the high-voltage power supply domain is electrically connected to the highest potential.

11. The integrated circuit according to claim 10, characterized in that, Each of the second transistors is formed within the negative voltage power domain, the low voltage power domain, or the high voltage power domain, respectively, based on the voltage operating range of its back gate.

12. The integrated circuit according to claim 10, characterized in that, The first doped region of the second isolation island structure further includes a second doped region having a first doping type, the second doped region having the opposite doping type to the first doped region. The second doped region of the negative voltage power supply domain is configured with a second voltage, the second voltage being less than the lowest common-mode voltage. The second doped region of the low voltage power supply domain is electrically connected to the ground potential of the integrated circuit. The second doped region of the high voltage power supply domain is configured with a third voltage, the third voltage being the difference between the highest potential and the first threshold.

13. The integrated circuit according to claim 10 or 12, characterized in that, The highest potential is configured to be the higher of the common-mode input potential of the integrated circuit and the first voltage.

14. The integrated circuit according to claim 9, characterized in that, The second transistor includes a CMOS transistor, wherein the CMOS transistor is formed using a BCD process.

15. The integrated circuit according to claim 1, characterized in that, The plurality of isolation island structures includes a third isolation island structure; The integrated circuit also includes: An electrostatic discharge circuit is formed within the first doped region of the third isolation island structure.

16. The integrated circuit according to claim 15, characterized in that, The first doped region of the third isolation island structure is a high-voltage well region. The third isolation island structure also includes a buried layer located in the semiconductor substrate. The buried layer is located below the first doped region and has a second doping type.

17. The integrated circuit according to claim 15, characterized in that, The electrostatic discharge circuit includes a first high-voltage electrostatic discharge device, a second high-voltage electrostatic discharge device, and a low-voltage electrostatic discharge device. The first high-voltage electrostatic discharge device is reverse-connected between the non-inverting input port of the integrated circuit and the semiconductor substrate. The second high-voltage electrostatic discharge device is reverse-connected between the inverting input port of the integrated circuit and the semiconductor substrate. The low-voltage electrostatic discharge device is positively connected between the ground potential of the integrated circuit and the semiconductor substrate.

18. The integrated circuit according to claim 1, characterized in that, The first negative potential is configured to be generated by a negative charge pump circuit, the negative charge pump circuit comprising: A multi-stage negative pressure charge pump, comprising a multi-stage negative pressure charge pump connected in series, wherein the multi-stage negative pressure charge pump is used to generate a first negative pressure, and the potential of the first negative pressure is used as the first negative potential; Each stage of the negative pressure charge pump includes one negative pressure charge pump unit or multiple negative pressure charge pump units connected in parallel.

19. The integrated circuit according to claim 18, characterized in that, The multi-stage negative pressure charge pump directly generates the first negative pressure.

20. The integrated circuit according to claim 18, characterized in that, The multi-stage negative pressure charge pump also includes: A ripple suppression field-effect transistor is used to generate a second negative voltage, wherein the first negative voltage is less than the second negative voltage.

21. The integrated circuit according to claim 20, characterized in that, The multi-stage negative pressure charge pump includes a first-stage negative pressure charge pump, a second-stage negative pressure charge pump, and a third-stage negative pressure charge pump connected in series. The first-stage negative pressure charge pump and the second-stage negative pressure charge pump each include a negative pressure charge pump unit. The third-stage negative pressure charge pump includes two negative pressure charge pump units connected in parallel. The output ports of the two negative pressure charge pump units of the third-stage negative pressure charge pump are respectively used as the first output port and the second output port of the multi-stage negative pressure charge pump. The drain of the ripple suppression field-effect transistor is electrically connected to the first output port, and the first output port generates the first negative voltage. The gate of the ripple suppression field-effect transistor is electrically connected to the second output port, and the source of the ripple suppression field-effect transistor generates the second negative voltage.

22. The integrated circuit according to claim 18, characterized in that, The multi-stage negative pressure charge pump also includes a ripple suppression field-effect transistor to generate a first negative pressure and a second negative pressure, wherein the first negative pressure is less than the second negative pressure.

23. The integrated circuit according to claim 22, characterized in that, The multi-stage negative pressure charge pump includes a first-stage negative pressure charge pump, a second-stage negative pressure charge pump, and a third-stage negative pressure charge pump connected in series. The first-stage negative pressure charge pump and the second-stage negative pressure charge pump each include a negative pressure charge pump unit. The third-stage negative pressure charge pump includes two negative pressure charge pump units connected in parallel. The output ports of the two negative pressure charge pump units of the third-stage negative pressure charge pump are respectively used as the first output port and the second output port of the multi-stage negative pressure charge pump. The drain of the ripple suppression field-effect transistor is electrically connected to the first output port, and the gate of the ripple suppression field-effect transistor is electrically connected to the second output port. The source of the ripple suppression field-effect transistor generates the second negative voltage and the first negative voltage.

24. The integrated circuit according to claim 18, characterized in that, The multi-stage negative pressure charge pump also includes a first ripple suppression field-effect transistor and a second ripple suppression field-effect transistor to generate a first negative pressure and a second negative pressure, respectively, wherein the first negative pressure is less than the second negative pressure.

25. The integrated circuit according to claim 24, characterized in that, The ripple suppression field-effect transistor includes a first ripple suppression field-effect transistor and a second ripple suppression field-effect transistor. The multi-stage negative voltage charge pump includes a first-stage negative voltage charge pump, a second-stage negative voltage charge pump, and a third-stage negative voltage charge pump connected in series. The first-stage negative voltage charge pump and the second-stage negative voltage charge pump each include a negative voltage charge pump unit. The third-stage negative voltage charge pump includes two negative voltage charge pump units connected in parallel. The output ports of the two negative voltage charge pump units of the third-stage negative voltage charge pump are respectively used as the first output port and the second output port of the multi-stage negative voltage charge pump. The drain of the first ripple suppression field-effect transistor is electrically connected to the first output port, and the gate of the first ripple suppression field-effect transistor is electrically connected to the second output port. The source of the first ripple suppression field-effect transistor generates the second negative voltage. The drain of the second ripple suppression field-effect transistor is electrically connected to the first output port, and the gate of the second ripple suppression field-effect transistor is electrically connected to the second output port. The source of the second ripple suppression field-effect transistor generates the first negative voltage.

26. The integrated circuit according to claim 20, 22 or 24, characterized in that, The second negative voltage is configured as the voltage of the negative power rail.

27. The integrated circuit according to claim 18, characterized in that, The negative pressure charge pump circuit also includes: A clock oscillator is used to provide a clock signal for the multi-stage negative pressure charge pump; A low-dropout regulator is used to provide power support for the clock oscillator and to provide a reference voltage for the multi-stage negative pressure charge pump.

28. The integrated circuit according to claim 20, 22 or 24, characterized in that, The ripple suppression field-effect transistor is a PMOS transistor.

29. The integrated circuit according to claim 27, characterized in that, The negative voltage charge pump unit includes a first field-effect transistor (FET), a second field-effect transistor (FET), a third field-effect transistor (FET), a fourth field-effect transistor (FET), a fifth field-effect transistor (FET), a sixth field-effect transistor (FET), a first capacitor, a second capacitor, a third capacitor, a fourth capacitor, a fifth capacitor, and a timing generator. The sources of the first, second, third, and fourth FETs are all electrically connected to a common node. The common node is electrically connected to the ground potential of the integrated circuit and to the output port of the negative voltage charge pump unit through the first capacitor. The drains of the first, second, third, and fourth FETs are respectively connected to the second capacitor, a second capacitor, a third capacitor, a fourth capacitor, and a fifth capacitor. The third, fourth, and fifth capacitors are electrically connected to the timing generator. The gates of the second and third field-effect transistors are electrically connected to the drain of the first field-effect transistor. The gates of the first and fourth field-effect transistors are electrically connected to the drain of the second field-effect transistor. The source of the fifth field-effect transistor is electrically connected to the output port of the negative voltage charge pump unit, its gate is electrically connected to the drain of the third field-effect transistor, and its drain is electrically connected to the drain of the fourth field-effect transistor. The source of the sixth field-effect transistor is electrically connected to the output port of the negative voltage charge pump unit, its gate is electrically connected to the drain of the fourth field-effect transistor, and its drain is electrically connected to the drain of the third field-effect transistor.

30. The integrated circuit according to claim 29, characterized in that, The timing generator is configured to provide control level signals to each field-effect transistor in the negative charge pump unit to control the negative charge pump unit to output a corresponding negative level signal. The control level signal includes a low level signal or a high level signal, the low level signal is a zero level signal, and the high level signal is the reference voltage.

31. An electronic device, characterized in that, The device includes an integrated circuit as described in any one of claims 1-30.

32. A negative pressure charge pump circuit, characterized in that, The negative pressure charge pump circuit includes: A multi-stage negative pressure charge pump, comprising a multi-stage negative pressure charge pump connected in series, the multi-stage negative pressure charge pump being used to generate a first negative pressure; Each stage of the negative pressure charge pump includes one negative pressure charge pump unit or multiple negative pressure charge pump units connected in parallel.

33. The negative pressure charge pump circuit according to claim 32, characterized in that, The negative voltage charge pump circuit is integrated on the integrated circuit as described in any one of claims 1-30, wherein the potential of the first negative voltage is a first negative potential, the semiconductor substrate of the integrated circuit is biased to the first negative potential, such that the amplifier circuit on the integrated circuit supports negative voltage common-mode input, and the first negative potential matches the circuit structure of the amplifier circuit.

34. The negative pressure charge pump circuit according to claim 32, characterized in that, The multi-stage negative pressure charge pump directly generates the first negative pressure.

35. The negative voltage charge pump circuit according to claim 34, characterized in that, The multi-stage negative pressure charge pump also includes: A ripple suppression field-effect transistor is used to generate a second negative voltage, wherein the first negative voltage is less than the second negative voltage.

36. The negative pressure charge pump circuit according to claim 35, characterized in that, The multi-stage negative pressure charge pump includes a first-stage negative pressure charge pump, a second-stage negative pressure charge pump, and a third-stage negative pressure charge pump connected in series. The first-stage negative pressure charge pump and the second-stage negative pressure charge pump each include a negative pressure charge pump unit. The third-stage negative pressure charge pump includes two negative pressure charge pump units connected in parallel. The output ports of the two negative pressure charge pump units of the third-stage negative pressure charge pump are respectively used as the first output port and the second output port of the multi-stage negative pressure charge pump. The drain of the ripple suppression field-effect transistor is electrically connected to the first output port, and the first output port generates the first negative voltage. The gate of the ripple suppression field-effect transistor is electrically connected to the second output port, and the source of the ripple suppression field-effect transistor generates the second negative voltage.

37. The negative pressure charge pump circuit according to claim 32, characterized in that, The multi-stage negative pressure charge pump also includes a ripple suppression field-effect transistor to generate a first negative pressure and a second negative pressure, wherein the first negative pressure is less than the second negative pressure.

38. The negative pressure charge pump circuit according to claim 37, characterized in that, The multi-stage negative pressure charge pump includes a first-stage negative pressure charge pump, a second-stage negative pressure charge pump, and a third-stage negative pressure charge pump connected in series. The first-stage negative pressure charge pump and the second-stage negative pressure charge pump each include a negative pressure charge pump unit. The third-stage negative pressure charge pump includes two negative pressure charge pump units connected in parallel. The output ports of the two negative pressure charge pump units of the third-stage negative pressure charge pump are respectively used as the first output port and the second output port of the multi-stage negative pressure charge pump. The drain of the ripple suppression field-effect transistor is electrically connected to the first output port, and the gate of the ripple suppression field-effect transistor is electrically connected to the second output port. The source of the ripple suppression field-effect transistor generates the second negative voltage and the first negative voltage.

39. The negative pressure charge pump circuit according to claim 32, characterized in that, The multi-stage negative pressure charge pump also includes a first ripple suppression field-effect transistor and a second ripple suppression field-effect transistor to generate a first negative pressure and a second negative pressure, respectively, wherein the first negative pressure is less than the second negative pressure.

40. The negative pressure charge pump circuit according to claim 39, characterized in that, The ripple suppression field-effect transistor includes a first ripple suppression field-effect transistor and a second ripple suppression field-effect transistor. The multi-stage negative voltage charge pump includes a first-stage negative voltage charge pump, a second-stage negative voltage charge pump, and a third-stage negative voltage charge pump connected in series. The first-stage negative voltage charge pump and the second-stage negative voltage charge pump each include a negative voltage charge pump unit. The third-stage negative voltage charge pump includes two negative voltage charge pump units connected in parallel. The output ports of the two negative voltage charge pump units of the third-stage negative voltage charge pump are respectively used as the first output port and the second output port of the multi-stage negative voltage charge pump. The drain of the first ripple suppression field-effect transistor is electrically connected to the first output port, and the gate of the first ripple suppression field-effect transistor is electrically connected to the second output port. The source of the first ripple suppression field-effect transistor generates the second negative voltage. The drain of the second ripple suppression field-effect transistor is electrically connected to the first output port, and the gate of the second ripple suppression field-effect transistor is electrically connected to the second output port. The source of the second ripple suppression field-effect transistor generates the first negative voltage.

41. The negative pressure charge pump circuit according to claim 35, 37 or 39, characterized in that, The second negative voltage is configured as the voltage of the negative power rail.

42. The negative pressure charge pump circuit according to claim 32, characterized in that, The negative pressure charge pump circuit also includes: A clock oscillator is used to provide a clock signal for the multi-stage negative pressure charge pump; A low-dropout regulator is used to provide power support for the clock oscillator and to provide a reference voltage for the multi-stage negative pressure charge pump.

43. The negative pressure charge pump circuit according to claim 35, 37 or 39, characterized in that, The ripple suppression field-effect transistor is a PMOS transistor.

44. The negative voltage charge pump circuit according to claim 42, characterized in that, The negative voltage charge pump unit includes a first field-effect transistor (FET), a second field-effect transistor (FET), a third field-effect transistor (FET), a fourth field-effect transistor (FET), a fifth field-effect transistor (FET), a sixth field-effect transistor (FET), a first capacitor, a second capacitor, a third capacitor, a fourth capacitor, a fifth capacitor, and a timing generator. The sources of the first, second, third, and fourth FETs are all electrically connected to a common node. The common node is electrically connected to the ground potential of the integrated circuit and, through the first capacitor, to the output port of the negative voltage charge pump unit. The drains of the first, second, third, and fourth FETs are respectively connected through the second capacitor, the second capacitor, the third capacitor, and the fourth capacitor. The third, fourth, and fifth capacitors are electrically connected to the timing generator. The gates of the second and third field-effect transistors are electrically connected to the drain of the first field-effect transistor. The gates of the first and fourth field-effect transistors are electrically connected to the drain of the second field-effect transistor. The source of the fifth field-effect transistor is electrically connected to the output port of the negative voltage charge pump unit, its gate is electrically connected to the drain of the third field-effect transistor, and its drain is electrically connected to the drain of the fourth field-effect transistor. The source of the sixth field-effect transistor is electrically connected to the output port of the negative voltage charge pump unit, its gate is electrically connected to the drain of the fourth field-effect transistor, and its drain is electrically connected to the drain of the third field-effect transistor.

45. The negative pressure charge pump circuit according to claim 44, characterized in that, The timing generator is configured to provide control level signals to each field-effect transistor in the negative charge pump unit to control the negative charge pump unit to output a corresponding negative level signal. The control level signal includes a low level signal or a high level signal, the low level signal is a zero level signal, and the high level signal is the reference voltage.

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