Balanced amplifier circuit and electronic device comprising a balanced amplifier circuit

Abstract

A balanced amplifier circuit includes a first conversion circuit configured to output a first first signal, a first second signal, a second first signal, and a second second signal based on an input signal having an input impedance, a first amplifier circuit configured to output a first third signal and a first fourth signal, a second amplifier circuit configured to output a second third signal and a second fourth signal, and a second conversion circuit configured to output an output signal having an output impedance based on the first third signal, the first fourth signal, the second third signal, and the second fourth signal. Each of the first first signal, the first second signal, the second first signal, and the second second signal has a target input impedance. The first first signal has a 90-degree phase difference from the second first signal. The first second signal has a differential relationship with the first first signal. The second second signal has a differential relationship with the second first signal.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2025-0055609, filed on April 28, 2025, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] This disclosure relates generally to amplifier circuits, and more specifically to balanced amplifier circuits and electronic devices including balanced amplifier circuits. Background Technology

[0004] The satisfaction may be achieved by the fourth generation (4) th The growing demand for wireless data services driven by the commercialization of fifth-generation (4G) communication systems could lead to attempts to develop improved fifth-generation (5G) systems. th Efforts are underway to develop 5G and / or near-5G communication systems. Therefore, 5G and / or near-5G communication systems can be referred to as super 4G networks and / or post-Long Term Evolution (LTE) systems.

[0005] The use of millimeter-wave (mmWave) bands (e.g., 28 GHz and 60 GHz bands) in 5G communication systems could be considered to potentially achieve relatively high data transmission rates. Alternatively or additionally, techniques such as, but not limited to, beamforming, massive multiple-input multiple-output (massive MIMO), full-dimensional MIMO (FD-MIMO), array antennas, analog beamforming, and / or massive MIMO antennas may be discussed for potential use in 5G communication systems to potentially mitigate path loss and / or increase propagation distance of radio waves in the millimeter-wave band.

[0006] For example, when transmitting signals in relatively high frequency bands, the demand for amplifier circuits that can operate with relatively low sensitivity to changes in load impedance and / or enhanced output power may increase. In such examples, balanced amplifier circuits can be utilized. A balanced amplifier circuit can refer to an amplifier circuit that separates an input signal into in-phase (I) and quadrature (Q) signals (e.g., I / Q signals) that are orthogonal to each other, amplifies each of the separated signals, and combines the amplified signals for use as the output. Summary of the Invention

[0007] One or more exemplary embodiments of this disclosure provide a balanced amplifier circuit including circuitry for outputting signals having target input impedances and differential relationships, and signals having a 90-degree phase difference from each other, from input signals having input impedances.

[0008] Furthermore, one or more exemplary embodiments of this disclosure provide a balanced amplifier circuit that, when compared with associated amplifier circuits, reduces the area of ​​the circuitry that may be required to implement an electronic device.

[0009] According to one aspect of this disclosure, a balanced amplifier circuit includes a first conversion circuit, a first amplifier circuit, a second amplifier circuit, and a second conversion circuit. The first conversion circuit is configured to output a first first signal, a first second signal, a second first signal, and a second second signal based on an input signal having an input impedance. The first amplifier circuit is configured to amplify the first first signal to output a first third signal and amplify the first second signal to output a first fourth signal. The second amplifier circuit is configured to amplify the second first signal to output a second third signal and amplify the second second signal to output a second fourth signal. The second conversion circuit is configured to output an output signal having an output impedance based on the first third signal, the first fourth signal, the second third signal, and the second fourth signal. Each of the first first signal, the first second signal, the second first signal, and the second second signal has a target input impedance. The first first signal and the second first signal have a 90-degree phase difference. The first second signal and the first first signal have a first differential relationship. The second second signal and the second first signal have a second differential relationship.

[0010] According to one aspect of this disclosure, an electronic device includes a balanced amplifier circuit and a processor configured to control the balanced amplifier circuit. The balanced amplifier circuit is configured to amplify an input signal having an input impedance and output an output signal having an output impedance. The balanced amplifier circuit includes a first conversion circuit, a first amplifier circuit, a second amplifier circuit, and a second conversion circuit. The first conversion circuit is configured to output a first first signal, a first second signal, a second first signal, and a second second signal based on an input signal provided by the processor. The first amplifier circuit is configured to amplify the first first signal to output a first third signal and amplify the first second signal to output a first fourth signal. The second amplifier circuit is configured to amplify the second first signal to output a second third signal and amplify the second second signal to output a second fourth signal. The second conversion circuit is configured to output an output signal via an output node based on the first third signal, the first fourth signal, the second third signal, and the second fourth signal. Each of the first first signal, the first second signal, the second first signal, and the second second signal has a target input impedance. The first first signal and the second first signal have a 90-degree phase difference. The first second signal and the first first signal have a first differential relationship. The second second signal and the second first signal have a second differential relationship.

[0011] According to one aspect of this disclosure, a conversion circuit for outputting a plurality of output signals based on an input signal having an input impedance includes: a first capacitor coupled between an input node configured to receive the input signal and ground; a first inductor coupled between the input node and a first node; a first transformer coupled between the input node and a second node and between the input node and a third node; a second transformer coupled between the first node and a fourth node and between the first node and a fifth node; a third transformer coupled between the second node and the fourth node and between the third node and the fifth node; and a second capacitor coupled between the first node and ground. Each of the plurality of output signals has a target input impedance and a 90-degree phase difference relative to each other. A first first output signal of the plurality of output signals is output from the second node. A first second output signal of the plurality of output signals is output from the third node. A second first output signal of the plurality of output signals is output from the fourth node. A second second output signal of the plurality of output signals is output from the fifth node. The first second output signal has a first differential relationship with the first first output signal. The second first output signal has a second differential relationship with the second second output signal.

[0012] Other aspects may be set forth in part in the description which follows, and in part may be apparent from the description and / or may be learned by practice of the presented embodiments. Attached Figure Description

[0013] The above and other aspects, features, and advantages of certain embodiments of the present disclosure will become more apparent from the following description taken in conjunction with the accompanying drawings, in which:

[0014] Figure 1 This is a block diagram illustrating an electronic device according to an embodiment of the present disclosure;

[0015] Figure 2A This is a block diagram illustrating a balanced amplifier circuit according to an embodiment of the present disclosure;

[0016] Figure 2B This is a block diagram illustrating a balanced amplifier circuit that further includes an input resistor and an output resistor according to an embodiment of the present disclosure;

[0017] Figure 3 This is a circuit diagram illustrating a balanced amplifier circuit according to an embodiment of the present disclosure;

[0018] Figure 4 It is shown Figure 3 The circuit diagram of the equivalent circuit of the first conversion circuit of the balanced amplifier circuit;

[0019] Figure 5 This is a circuit diagram illustrating a balanced amplifier circuit including an amplifier in each of the first amplifier circuit and the second amplifier circuit according to an embodiment of the present disclosure.

[0020] Figure 6 This is a circuit diagram illustrating a balanced amplifier circuit including a first conversion circuit according to an embodiment of the present disclosure;

[0021] Figure 7 This is a circuit diagram illustrating a balanced amplifier circuit including a first conversion circuit according to an embodiment of the present disclosure;

[0022] Figure 8 This is a circuit diagram illustrating a balanced amplifier circuit including a first conversion circuit according to an embodiment of the present disclosure;

[0023] Figure 9A This is a circuit diagram illustrating a balanced amplifier circuit that also includes a third amplifier circuit according to an embodiment of the present disclosure;

[0024] Figure 9B This is a circuit diagram illustrating a balanced amplifier circuit that further includes a third amplifier circuit for receiving differential signals, according to an embodiment of the present disclosure.

[0025] Figure 10A This is a flowchart illustrating a method for controlling an input signal based on a first power consumption at an input node, according to an embodiment of the present disclosure;

[0026] Figure 10BThis is a flowchart illustrating a method for controlling an input signal based on a second power consumption at the output node, according to an embodiment of the present disclosure;

[0027] Figure 11 This is a block diagram illustrating an electronic device according to an embodiment of the present disclosure;

[0028] Figure 12 This is a block diagram illustrating an Internet of Things (IoT) device including an electronic device according to embodiments of the present disclosure; and

[0029] Figure 13 This is a block diagram illustrating a mobile terminal using an electronic device according to an embodiment of the present disclosure. Detailed Implementation

[0030] The following description with reference to the accompanying drawings is intended to aid in a full understanding of the embodiments of this disclosure as defined by the claims and their equivalents. Various specific details are included to aid understanding, but these details are to be considered exemplary only. Therefore, those skilled in the art will recognize that various changes and modifications can be made to the embodiments described herein without departing from the scope and spirit of this disclosure. Furthermore, for clarity and brevity, descriptions of well-known functions and structures have been omitted.

[0031] Regarding the description of the accompanying drawings, similar reference numerals may be used to refer to similar or related elements. It will be understood that, unless the relevant context explicitly states otherwise, the singular form of a noun corresponding to an item may include one or more things. As used herein, each of the phrases such as “A or B,” “at least one of A and B,” “at least one of A or B,” “A, B or C,” “at least one of A, B and C,” and “at least one of A, B or C” may include any one or all possible combinations of items enumerated together in the corresponding phrase. As used herein, terms such as “first” and “second” or “first” and “second” may be used simply to distinguish corresponding components from one other component and do not limit the components in other respects (e.g., in terms of importance or order). It will be understood that, in the presence of the terms “operably” or “communically” or in the absence of the terms “operably” or “communically”, if an element (e.g., a first element) is referred to as “coupled to another element (e.g., a second element),” “coupled to another element (e.g., a second element),” “connected to another element (e.g., a second element),” or “connected to another element (e.g., a second element)”, it means that the element can be directly (e.g., wiredly) coupled to the other element, wirelessly coupled to the other element, or coupled to the other element via a third element.

[0032] References throughout this disclosure to “an embodiment,” “an embodiment,” “an exemplary embodiment,” or similar language may indicate that a particular feature, structure, or characteristic described in connection with the indicated embodiment is included in at least one embodiment of the solution. Therefore, the phrases “in an embodiment,” “in an embodiment,” “in an exemplary embodiment,” and similar language throughout this disclosure may, but not necessarily, refer to the same embodiment. The embodiments described herein are exemplary embodiments, and therefore, this disclosure is not limited thereto and may be implemented in various other forms.

[0033] It will be understood that the specific order or hierarchy of the boxes in the disclosed process / flowcharts is an illustration of exemplary methods. Based on design preferences, it should be understood that the specific order or hierarchy of the boxes in these process / flowcharts may be rearranged. Furthermore, some boxes may be combined or omitted. The appended claims present the elements of the various boxes in an exemplary order, but this does not imply limitation to the specific order or hierarchy presented.

[0034] As shown in the accompanying drawings, embodiments of this document can be described and illustrated according to blocks that perform one or more of the described functions. These blocks may be referred to herein as units or modules, or given names such as devices, logic, circuits, controllers, counters, comparators, generators, converters, etc., and may be physically implemented by analog and / or digital circuits including one or more of logic gates, integrated circuits, microprocessors, microcontrollers, memory circuits, passive electronic components, active electronic components, optical components, etc.

[0035] In this disclosure, the articles “a” and “an” are intended to include one or more items and may be used interchangeably with “one or more.” The term “an” or similar language is used when referring to only one item. For example, the term “processor” can refer to a single processor or multiple processors. When a processor is described as performing operations and the processor is referred to as performing additional operations, multiple operations can be performed by a single processor or any one or a combination of multiple processors.

[0036] Various embodiments of the present disclosure are described below with reference to the accompanying drawings.

[0037] Figure 1 This is a block diagram illustrating an electronic device according to an embodiment of the present disclosure. Figure 2A This is a block diagram illustrating a balanced amplifier circuit according to an embodiment of the present disclosure. Figure 2B This is a block diagram illustrating a balanced amplifier circuit that also includes an input resistor and an output resistor according to an embodiment of the present disclosure.

[0038] refer to Figure 1The electronic device 10 may include a processor 110, a radio frequency frontend (RFFE) 120, and an antenna 130.

[0039] The electronic device 10 according to various embodiments of the present disclosure may be and / or may include various types of devices. For example, the electronic device 10 may include portable communication devices (e.g., smartphones), computer devices, portable multimedia devices, portable medical devices, cameras, or wearable devices. However, embodiments of the present disclosure are not limited thereto, and the electronic device 10 may be and / or may include various other devices.

[0040] Electronic device 10 may include an antenna 130 for transmitting and / or receiving radio frequency (RF) signals at a specified frequency. Therefore, electronic device 10 according to this disclosure may also be referred to as an antenna device including antenna 130, a wireless communication device, or a wireless transceiver.

[0041] The electronic device 10 may include a processor 110 for controlling the operation of the electronic device 10.

[0042] Processor 110 may execute software and / or programs to control at least one other component of electronic device 10 (e.g., RFFE 120) and may perform various data processing and / or operations. Processor 110 may be and / or may include a central processing unit (CPU), microprocessor, etc., and may control the overall operation of electronic device 10. Therefore, the operations performed by electronic device 10 as described below can be understood as being performed under the control of processor 110.

[0043] According to an embodiment, processor 110 may include an algorithm for controlling RFFE 120 and / or balanced amplifier circuit 100. For example, the algorithm may be and / or may include software code programmed in processor 110. As another example, the algorithm may be and / or may include hard code that can be hardcoded in processor 110. However, embodiments of this disclosure are not limited thereto.

[0044] The processor 110 can control the RFFE 120 to provide signals and / or power to the antenna 130 for transmitting RF signals according to an algorithm. For example, the processor 110 can provide transmission power to the antenna 130 via the RFFE 120.

[0045] In this way, the processor 110 can transmit and / or receive signals in a specified frequency band via the antenna 130.

[0046] Therefore, the processor 110 according to this disclosure can be referred to as a communication processor (CP).

[0047] Furthermore, the electronic device 10 may include an RFFE 120 connected between the processor 110 and the antenna 130. In this disclosure, the RFFE 120 may include at least one of a phase shifter, a bandpass filter, and a mixer.

[0048] According to an embodiment, RFFE 120 may include balanced amplifier circuitry 100. For example, RFFE 120 may include balanced amplifier circuitry 100 connected to antenna 130.

[0049] According to an embodiment, the electronic device 10 may further include a radio frequency integrated circuit (RFIC) connected between the RFFE 120 and the processor 110. Furthermore, the RFIC may include a balanced amplifier circuit 100 electrically connected to the antenna 130 via the RFFE 120.

[0050] In other words, referring to the above configuration, the balanced amplifier circuit 100 can be included in the RFFE 120 or the RFIC. However, for the sake of explanation below, it is assumed that the balanced amplifier circuit 100 is included in the RFFE 120.

[0051] refer to Figure 1 , Figure 2A and Figure 2B The balanced amplifier circuits 100, 100A, and 100B amplify the input signal IS and output the amplified input signal IS as the output signal OS. In this disclosure, as... Figure 2A The balanced amplifier circuit 100A shown is as follows: Figure 2B The balanced amplifier circuit 100B shown may include and / or may be similar in many respects to Figure 1 The balanced amplifier circuit 100 shown may include additional features. Therefore, for the sake of brevity, repeated descriptions of balanced amplifier circuits 100A and 100B described with reference to balanced amplifier circuit 100 may be omitted.

[0052] For example, balanced amplifier circuits 100, 100A, and 100B can amplify the amplitude of the input signal IS, which can be input through the input node IN, with a pre-specified gain, and can output the amplified input signal IS as the output signal OS through the output node ON.

[0053] refer to Figure 2AThe balanced amplifier circuit 100A may include a first conversion circuit 111, a first amplifier circuit AC1, a second amplifier circuit AC2, and a second conversion circuit 112.

[0054] For example, the balanced amplifier circuit 100A may include a first conversion circuit 111 that outputs multiple signals (e.g., a first-first signal S11, a first-second signal S12, a second-first signal S21, and a second-second signal S22) from an input signal IS having an input impedance Z0. Each of the multiple signals S11 to S22 may have a target input impedance Z1 and may have different phases.

[0055] In this disclosure, the target input impedance Z1 can be the impedance that minimizes the signal reflected when the signal is sent to the first amplifier circuit AC1 and the second amplifier circuit AC2. For example, the target input impedance Z1 can be approximately 50 ohms (Ω).

[0056] In other words, the first conversion circuit 111 can perform impedance matching to output multiple signals S11 to S22, each with a target input impedance Z1, from the input signal IS with an input impedance Z0.

[0057] Furthermore, the first conversion circuit 111 can output signals that are differentially related to each other from the single-phase input signal IS. For example, the first conversion circuit 111 can output a first signal S11 and a second signal S12 that are differentially related from the single-phase input signal IS.

[0058] Furthermore, the first conversion circuit 111 can output a signal with a 90-degree phase difference from each of the signals having a differential relationship. For example, the first conversion circuit 111 can output a second first signal S21 with a 90-degree phase difference from the first first signal S11. Furthermore, the first conversion circuit 111 can output a second second signal S22 with a 90-degree phase difference from the first second signal S12.

[0059] Referring to the above configuration, the first conversion circuit 111 can output multiple signals S11 to S22 that are orthogonal to each other from the input signal IS. The input signal IS can have an input impedance Z0, and each of the multiple signals S11 to S22 can have a target input impedance Z1.

[0060] In other words, the first conversion circuit 111 can perform the operation of converting the impedance of the input signal IS, outputting signals S11 and S12 that are in a differential relationship from the single-phase input signal IS, and outputting signals S11 and S21 that have a 90-degree phase difference with each other.

[0061] Therefore, compared to the case where separate circuits are provided for impedance conversion, for generating differential signals, and for generating signals with a 90-degree phase difference, the balanced amplifier circuit 100A according to this disclosure can be implemented with a relatively small area.

[0062] In other words, with the above configuration, the balanced amplifier circuit 100A according to this disclosure can reduce the area that may be required to implement the electronic device 10 compared to related amplifier circuits.

[0063] In addition, the balanced amplifier circuit 100A may include a first amplifier circuit AC1 and a second amplifier circuit AC2.

[0064] In other words, the balanced amplifier circuit 100A may include a first amplifier circuit AC1 that amplifies the first signal S11 and the first second signal S12.

[0065] According to an embodiment, the first amplifier circuit AC1 can amplify the first signal S11 and the first second signal S12 with a specified gain. For example, the first amplifier circuit AC1 can amplify the first signal S11 and output the amplified first signal S11 as a first-third signal S13. Furthermore, the first amplifier circuit AC1 can amplify the first second signal S12 and output the amplified first second signal S12 as a first-fourth signal S14.

[0066] The balanced amplifier circuit 100A may include a second amplifier circuit AC2 that amplifies the second first signal S21 and the second second signal S22.

[0067] According to an embodiment, the second amplifier circuit AC2 can amplify the second first signal S21 and the second second signal S22 with a specified gain. For example, the second amplifier circuit AC2 can amplify the second first signal S21 and output the amplified second first signal S21 as a second-third signal S23. Furthermore, the second amplifier circuit AC2 can amplify the second second signal S22 and output the amplified second second signal S22 as a second-fourth signal S24.

[0068] In this disclosure, each of the first amplifier circuit AC1 and the second amplifier circuit AC2 may include at least one amplifier transistor for amplifying the signal input thereto. Therefore, each of the first amplifier circuit AC1 and the second amplifier circuit AC2 may be referred to as a transistor amplifier.

[0069] Furthermore, each of the first amplifier circuit AC1 and the second amplifier circuit AC2 can be referred to as a differential amplifier, which amplifies signals that are in a differential relationship (e.g., first signal S11 and first signal S12).

[0070] Each of the first and third signals S13, the first and fourth signals S14, the second and third signals S23, and the second and fourth signals S24 may have a target output impedance Z2. In this disclosure, the target output impedance Z2 may be the impedance that minimizes the signal reflected when the signal is sent from the first amplifier circuit AC1 and the second amplifier circuit AC2 to the second conversion circuit 112. For example, the target output impedance Z2 may be approximately 50 Ω.

[0071] Furthermore, for example, the target output impedance Z2 and the target input impedance Z1 may have substantially similar and / or identical values. However, embodiments of this disclosure are not limited thereto.

[0072] The balanced amplifier circuit 100A may include a second conversion circuit 112, which outputs an output signal OS with an output impedance Z3 from a first third signal S13 to a second fourth signal S24, each having a target output impedance Z2 and a 90-degree phase difference from the other.

[0073] According to an embodiment, the second conversion circuit 112 can perform an impedance matching function to output an output signal OS with an output impedance Z3 from a first third signal S13 to a second fourth signal S24, each having a target output impedance Z2.

[0074] Furthermore, the second conversion circuit 112 can output a single-phase output signal OS from signals that are differentially related to each other and from signals that have a 90-degree phase difference with each of the signals that are differentially related.

[0075] In other words, the second conversion circuit 112 can perform the operation of converting the impedance of the signal input to it and outputting a single-phase signal from a signal with different phases.

[0076] Therefore, compared to the case where separate circuits are provided for impedance conversion and for generating single-phase signals from signals that are differentially related and signals that have a 90-degree phase difference with the signals that are differentially related, the balanced amplifier circuit 100A according to this disclosure can be implemented with a relatively small area.

[0077] In other words, with the above configuration, the balanced amplifier circuit 100A according to this disclosure can reduce the area that may be required to implement the electronic device 10 compared to related amplifier circuits.

[0078] Furthermore, compared to the case where separate circuits are provided for impedance conversion and for generating single-phase signals from signals that are differentially related and signals that have a 90-degree phase difference with the signals that are differentially related, the balanced amplifier circuit 100A according to this disclosure may include a relatively small number of passive components.

[0079] Therefore, compared with related amplifier circuits, the balanced amplifier circuit 100A according to this disclosure can reduce power consumption due to passive components. Furthermore, compared with related amplifier circuits, the balanced amplifier circuit 100A can improve output power and gain.

[0080] Furthermore, referring to the above configuration, the balanced amplifier circuit 100A can use different first amplifier circuits AC1 and second amplifier circuits AC2 to amplify signals that have a 90-degree phase difference with each other.

[0081] Furthermore, the balanced amplifier circuit 100A can output a single-phase output signal OS with an output impedance Z3 from the first third signal S13 to the second fourth signal S24, which are output from different first amplifier circuits AC1 and AC2.

[0082] Therefore, when compared with related amplifier circuits, the electronic device 10 or balanced amplifier circuit 100A according to this disclosure can improve the output power.

[0083] Furthermore, the electronic device 10 or balanced amplifier circuit 100A according to this disclosure can operate with less sensitivity to changes in load impedance by individually amplifying signals with a 90-degree phase difference.

[0084] In other words, compared with related amplifier circuits, the balanced amplifier circuit 100A according to this disclosure can improve the performance of the RF signal transmission operation of the electronic device 10.

[0085] refer to Figure 2B The balanced amplifier circuit 100B may include a first conversion circuit 111, a first amplifier circuit AC1, a second amplifier circuit AC2, and a second conversion circuit 112. The balanced amplifier circuit 100B may also include an input resistor RI and an output resistor RO.

[0086] Figure 2B The balanced amplifier circuit 100B shown may include and / or may be similar in many respects to Figure 2AThe balanced amplifier circuit 100A shown may include additional features not mentioned above. For example, the balanced amplifier circuit 100B may include an input resistor RI and an output resistor RO. Therefore, for the sake of brevity, the references above can be omitted. Figure 2A The description is a repetition of the description of the balanced amplifier circuit 100B.

[0087] The balanced amplifier circuit 100B may include an input resistor RI connected between the first conversion circuit 111 and ground. In this disclosure, the input resistor RI may have a resistance value equal to approximately half of the target input impedance Z1. For example, the input resistor RI may have a resistance value of approximately 25 Ω.

[0088] Furthermore, the balanced amplifier circuit 100B may include an output resistor RO connected between the second conversion circuit 112 and ground. In this disclosure, the output resistor RO may have a resistance value equal to approximately half of the target output impedance Z2. For example, the output resistor RO may have a resistance value of approximately 25 Ω.

[0089] Figure 3 This is a circuit diagram illustrating a balanced amplifier circuit according to an embodiment of the present disclosure. Figure 4 It is shown Figure 3 The circuit diagram of the equivalent circuit of the first conversion circuit of the balanced amplifier circuit. Figure 5 This is a circuit diagram illustrating a balanced amplifier circuit comprising an amplifier in each of the first amplifier circuit and the second amplifier circuit according to an embodiment of the present disclosure.

[0090] refer to Figure 3 The balanced amplifier circuit 100B1 may include a first conversion circuit 111A, a first amplifier circuit AC1a, a second amplifier circuit AC2a, and a second conversion circuit 112A. In this disclosure, as... Figure 3 The balanced amplifier circuit 100B1 and its components shown may include and / or may be similar in many respects to Figure 2B The balanced amplifier circuit 100B shown may include additional features not mentioned above. Therefore, for the sake of brevity, the references above can be omitted. Figure 2B The description is a repetitive description of the balanced amplifier circuit 100B1.

[0091] For example, the balanced amplifier circuit 100B1 may include a first conversion circuit 111A, which can output multiple signals S11 to S22 from an input signal IS having an input impedance Z0. The multiple signals S11 to S22 may have a target input impedance Z1 and may have different phases. In this disclosure, Figure 3 The first conversion circuit 111A shown may include and / or may be similar in many respects to Figure 2B The first conversion circuit 111 shown may include additional features not mentioned above. Therefore, for the sake of brevity, the references above can be omitted. Figure 2B The description is a repetition of the description of the first conversion circuit 111A.

[0092] In this disclosure, the target input impedance Z1 can be the impedance that minimizes the signal reflected when the signal is sent to the first amplifier circuit AC1a and the second amplifier circuit AC2a. For example, the target input impedance Z1 can be approximately 50 Ω.

[0093] According to an embodiment, the first conversion circuit 111A may include a first transformer T1, a second transformer T2, a third transformer T3, a first capacitor C1, a second capacitor C2, and a first inductor L1.

[0094] For example, the first conversion circuit 111A may include a first transformer T1 connected between the input node IN and the first amplifier circuit AC1a.

[0095] In addition, the first conversion circuit 111A may include a second transformer T2 connected between the input resistor RI and the second amplifier circuit AC2a.

[0096] In addition, the first conversion circuit 111A may include a first capacitor C1 connected between the input node IN and ground.

[0097] In addition, the first conversion circuit 111A may include a first inductor L1 connected between a first node N1 and an input node IN, with the first node N1 between an input resistor RI and a second transformer T2.

[0098] In addition, the first conversion circuit 111A may include a second capacitor C2 connected between the first node N1 and ground.

[0099] Furthermore, the first conversion circuit 111A may include a third transformer T3 connected between a second node N2 from which it outputs a first signal S11 and a fourth node N4 from which it outputs a second signal S21, and connected between a third node N3 from which it outputs a first signal S12 and a fifth node N5 from which it outputs a second signal S22. In this disclosure, the third transformer T3 may include an inductor connected between the second node N2 and the fourth node N4, and an inductor connected between the third node N3 and the fifth node N5.

[0100] refer to Figure 4 The first conversion circuit 511 may include multiple transmission lines (e.g., first transmission line TL1, second transmission line TL2, third transmission line TL3 and fourth transmission line TL4), a first matching circuit 521 and a second matching circuit 522.

[0101] For example, the first conversion circuit 511 may include a first transmission line TL1 connected between the input node IN and the input resistor RI. Furthermore, the first conversion circuit 511 may include a second transmission line TL2 connected between the input node IN and the first matching circuit 521. Additionally, the first conversion circuit 511 may include a third transmission line TL3 connected between the input resistor RI and the second matching circuit 522. Furthermore, the first conversion circuit 511 may include a fourth transmission line TL4 connected between the first matching circuit 521 and the second matching circuit 522.

[0102] The first conversion circuit 511 can generate an I signal I1 and a Q signal Q1 with a 90-degree phase difference from a single-phase input signal IS via multiple first transmission lines TL1 to a fourth transmission line TL4. In this disclosure, each of the I signal I1 and the Q signal Q1 can have an input impedance Z0 that is substantially similar to and / or the same as that of the input signal IS.

[0103] Therefore, at least a portion of the first conversion circuit 511, which includes multiple first transmission lines TL1 to fourth transmission line TL4, can be referred to as a coupler circuit.

[0104] In addition, the first conversion circuit 511 may include a first matching circuit 521, which outputs a first first signal S11 and a first second signal S12 from the I signal I1, each having a target input impedance Z1 and a differential relationship.

[0105] In other words, the first matching circuit 521 can perform impedance matching to change the impedance of the input signal. Furthermore, the first matching circuit 521 can output a first signal S11 and a second signal S12 that are differentially related from the input signal I1.

[0106] Therefore, for example, the first matching circuit 521 can be referred to as an impedance matching circuit and / or a balun circuit.

[0107] In addition, the first conversion circuit 511 may include a second matching circuit 522 that outputs a second first signal S21 and a second second signal S22, each having a target input impedance Z1 and in a differential relationship, from the Q signal Q1.

[0108] In other words, the second matching circuit 522 can perform impedance matching to change the impedance of the input signal. Furthermore, the second matching circuit 522 can output a second first signal S21 and a second second signal S22 that are differentially related from the input signal I1.

[0109] Therefore, for example, the second matching circuit 522 can be referred to as an impedance matching circuit and / or a balun circuit.

[0110] refer to Figure 3 and Figure 4 , Figure 3 The first conversion circuit 111A shown and Figure 4 The first conversion circuit 511 shown can be equivalent.

[0111] For example, Figure 4 The first transmission line TL1 shown may include and / or may be similar in many respects to Figure 3 The first inductor L1, the first capacitor C1, and the second capacitor C2 shown are at least a portion thereof, and may include additional features not mentioned above. Therefore, for the sake of brevity, the references above can be omitted. Figure 3 The description is a repetition of the description of the first transmission line TL1.

[0112] For example, Figure 4 The first transmission line TL1 shown can be equivalently represented as two capacitors and an inductor connected between the two capacitors. That is, the first transmission line TL1 can be equivalently represented as a line that can... Configure the connection of one inductor and two capacitors.

[0113] also, Figure 4 At least a portion of the second transmission line TL2 and the first matching circuit 521 shown may include and / or may be similar in many respects to Figure 3 The first transformer T1 and the first capacitor C1 shown are at least a portion thereof, and may include additional features not mentioned above. Therefore, for the sake of brevity, the references above can be omitted. Figure 3 The description is a repetition of the description of the second transmission line TL2.

[0114] For example, Figure 4 The second transmission line TL2 shown can be coupled to the first matching circuit 521 and can be equivalently represented as the first transformer T1 and a capacitor connected in parallel across the two ends of the first transformer T1. In this disclosure, the capacitor connected to one end of the first transformer T1 can be referred to as... Figure 3 The first capacitor C1 in the circuit. However, the capacitor connected to the other end of the first transformer T1 can be understood as being included in the first input parasitic capacitor IPC1 of the first amplifier circuit AC1a.

[0115] therefore, Figure 3 The first capacitor C1 shown can be understood as a combination of capacitors included in the equivalent circuit of the first transmission line TL1 and the second transmission line TL2.

[0116] also, Figure 4At least a portion of the third transmission line TL3 and the second matching circuit 522 shown may include and / or may be similar in many respects to Figure 3 The second transformer T2 and the second capacitor C2 shown herein are at least a portion thereof, and may include additional features not mentioned above. Therefore, for the sake of brevity, the references above can be omitted. Figure 3 The description is a repetition of the description of the third transmission line TL3 and the second matching circuit 522.

[0117] For example, Figure 4 The third transmission line TL3 shown can be coupled to the second matching circuit 522 and can be equivalently represented as the second transformer T2 and a capacitor connected in parallel across the two ends of the second transformer T2. In this disclosure, the capacitor connected to one end of the second transformer T2 can be... Figure 3 The second capacitor C2 is connected to the other end of the second transformer T2. However, the capacitor connected to the other end of the second transformer T2 can be understood as being included in the second input parasitic capacitor IPC2 of the second amplifier circuit AC2a.

[0118] therefore, Figure 3 The second capacitor C2 shown can be understood as a combination of capacitors included in the equivalent circuit of the first transmission line TL1 and the third transmission line TL3.

[0119] also, Figure 4 At least a portion of the fourth transmission line TL4, the first matching circuit 521, and the second matching circuit 522 shown can be understood as equivalent to Figure 3 The third transformer T3 shown may include additional features not mentioned above. Therefore, for the sake of brevity, the references above can be omitted. Figure 3 The description repeats the description of the fourth transmission line TL4, the first matching circuit 521, and the second matching circuit 522.

[0120] For example, Figure 4 The fourth transmission line TL4 shown can be coupled to the first matching circuit 521 and the second matching circuit 522, and can be equivalently represented as the third transformer T3 and a capacitor connected in parallel across the two ends of the third transformer T3. However, the capacitor connected across the two ends of the third transformer T3 can be understood as being included in the first input parasitic capacitor IPC1 of the first amplifier circuit AC1a and the second input parasitic capacitor IPC2 of the second amplifier circuit AC2a, respectively.

[0121] As described above, the first conversion circuit 111A can perform the operation of converting the impedance of the input signal IS, outputting signals S11 and S12 that are in a differential relationship from the single-phase input signal IS, and outputting signals S11 and S21 that have a 90-degree phase difference with each other.

[0122] In other words, the first conversion circuit 111A can perform impedance matching to output multiple signals S11 to S22 from an input signal IS having an input impedance Z0. Each of the multiple signals S11 to S22 has a target input impedance Z1.

[0123] Furthermore, the first conversion circuit 111A can output signals that are in a differential relationship from the single-phase input signal IS. For example, the first conversion circuit 111A can output a first signal S11 and a second signal S12 that are in a differential relationship from the single-phase input signal IS.

[0124] Furthermore, the first conversion circuit 111A can output a signal orthogonal to each of the signals in a differential relationship. For example, the first conversion circuit 111A can output a second first signal S21 orthogonal to the first first signal S11. Additionally, the first conversion circuit 111A can output a second second signal S22 orthogonal to the first second signal S12.

[0125] Therefore, compared to the case where separate circuits are set up for impedance transformation, for generating differential signals, and for generating signals with a 90-degree phase difference (e.g., Figure 4 Compared to the first conversion circuit 511), the first conversion circuit 111A can be implemented with a relatively small area.

[0126] When compared with related amplifier circuits, the balanced amplifier circuit 100B1 according to embodiments of the present disclosure can reduce the circuit area that may be required to output multiple signals S11 to S22 from the input signal IS.

[0127] In other words, with the above configuration, the balanced amplifier circuit 100B1 according to the embodiments of this disclosure can reduce the area that may be required to implement the electronic device 10 compared to the associated amplifier circuit.

[0128] refer to Figure 3 The balanced amplifier circuit 100B1 may include a first amplifier circuit AC1a and a second amplifier circuit AC2a.

[0129] For example, the balanced amplifier circuit 100B1 may include a first amplifier circuit AC1a that amplifies the first signal S11 and the first second signal S12.

[0130] The first amplifier circuit AC1a may include a first amplifier transistor ATR1 that amplifies the input signal (e.g., a first signal S11). Furthermore, the first amplifier circuit AC1a may include a first input parasitic capacitor IPC1 and a first output parasitic capacitor OPC1 connected in parallel across the first amplifier transistor ATR1.

[0131] The first amplifier circuit AC1a can amplify the first signal S11 and the first second signal S12 with a specified gain. For example, the first amplifier circuit AC1a can amplify the first signal S11 through the first amplifier transistor ATR1, and can output the amplified first signal S11 as the first third signal S13. In addition, the first amplifier circuit AC1a can amplify the first second signal S12 through the first amplifier transistor ATR1, and can output the amplified first second signal S12 as the first fourth signal S14.

[0132] In addition, the balanced amplifier circuit 100B1 may include a second amplifier circuit AC2a that amplifies the second first signal S21 and the second second signal S22.

[0133] The second amplifier circuit AC2a may include a second amplifier transistor ATR2 that amplifies the input signal (e.g., the second first signal S21). Furthermore, the second amplifier circuit AC2a may include a second input parasitic capacitor IPC2 and a second output parasitic capacitor OPC2 connected in parallel across the two terminals of the second amplifier transistor ATR2.

[0134] The second amplifier circuit AC2a can amplify the second first signal S21 and the second second signal S22 with a specified gain. For example, the second amplifier circuit AC2a can amplify the second first signal S21 through the second amplifier transistor ATR2, and can output the amplified second first signal S21 as the second third signal S23. Furthermore, the second amplifier circuit AC2a can amplify the second second signal S22 through the second amplifier transistor ATR2, and can output the amplified second second signal S22 as the second fourth signal S24.

[0135] In this disclosure, the first amplifier circuit AC1a and the second amplifier circuit AC2a, which respectively include a first amplifier transistor ATR1 and a second amplifier transistor ATR2, can be referred to as transistor amplifiers.

[0136] Furthermore, for example, the first amplifier circuit AC1a and the second amplifier circuit AC2a can amplify signals that are in a differential relationship (e.g., the first signal S11 and the second signal S12). Therefore, each of the first amplifier circuit AC1a and the second amplifier circuit AC2a can be referred to as a differential amplifier.

[0137] refer to Figure 5 According to an embodiment, the balanced amplifier circuit 100B2 may include a first amplifier circuit AC1b and a second amplifier circuit AC2b, each of which includes multiple amplifiers.

[0138] For example, the first amplifier circuit AC1b may include a first amplifier A1 that amplifies the first signal S11. Furthermore, the first amplifier circuit AC1b may include a second amplifier A2 that amplifies the first second signal S12.

[0139] Furthermore, the second amplifier circuit AC2b may include a third amplifier A3 that amplifies the second first signal S21. The second amplifier circuit AC2b may also include a fourth amplifier A4 that amplifies the second second signal S22.

[0140] In embodiments where each of the first amplifier circuit AC1b and the second amplifier circuit AC2b is implemented with multiple amplifiers, the first conversion circuit 111A1 and the second conversion circuit 112A1 may further include equivalent capacitors EC1, EC2, EC3 and EC4.

[0141] For example, when the first amplifier circuit AC1b is implemented using multiple amplifiers A1 and A2, the first conversion circuit 111A1 may include a first equivalent capacitor EC1 connected between the second node N2 and the third node N3. In this disclosure, the first equivalent capacitor EC1 can be understood as being connected through… Figure 4 The capacitor is obtained by combining the capacitors included in the equivalent circuit of the second transmission line TL2 and the fourth transmission line TL4 shown.

[0142] Furthermore, when the second amplifier circuit AC2b is implemented using multiple amplifiers A3 and A4, the first conversion circuit 111A1 may include a second equivalent capacitor EC2 connected between the fourth node N4 and the fifth node N5. In this disclosure, the second equivalent capacitor EC2 can be understood as being connected through… Figure 4 The capacitor is obtained by combining the capacitors included in the equivalent circuit of the third transmission line TL3 and the fourth transmission line TL4 shown.

[0143] Therefore, in addition to Figure 3 Apart from the configuration of the first conversion circuit 111A shown, Figure 5 The first conversion circuit 111A1 shown can be understood as including a first equivalent capacitor EC1 and a second equivalent capacitor EC2.

[0144] When the first amplifier circuit AC1b is implemented using multiple amplifiers A1 and A2, the second conversion circuit 112A1 may include a third equivalent capacitor EC3 connected between the sixth node N6 and the seventh node N7.

[0145] When the second amplifier circuit AC2b is implemented using multiple amplifiers A3 and A4, the second conversion circuit 112A1 may include a fourth equivalent capacitor EC4 connected between the eighth node N8 and the ninth node N9.

[0146] Therefore, in addition to Figure 3 In addition to the configuration of the second conversion circuit 112A shown, Figure 5 The second conversion circuit 112A1 shown can be understood as including a third equivalent capacitor EC3 and a fourth equivalent capacitor EC4.

[0147] However, for ease of explanation, in the following description, it is assumed that each of the first amplifier circuit AC1a and the second amplifier circuit AC2a included in the balanced amplifier circuit 100B1 is a transistor amplifier that includes an amplifier transistor.

[0148] In addition, refer to Figure 3 The balanced amplifier circuit 100B1 may include a second conversion circuit 112A, which outputs an output signal OS with an output impedance Z3 from a first third signal S13 to a second fourth signal S24, each having a target output impedance Z2 and a 90-degree phase difference relative to each other.

[0149] In this disclosure, Figure 3 The second conversion circuit 112A shown may include and / or may be similar in many respects to Figure 2B The second conversion circuit 112 shown may include additional features not mentioned above. Therefore, for the sake of brevity, the references above can be omitted. Figure 2B The description is a repetition of the description of the second conversion circuit 112A.

[0150] The second conversion circuit 112A may include a fourth transformer T4, a fifth transformer T5, a sixth transformer T6, a third capacitor C3, a fourth capacitor C4, and a second inductor L2.

[0151] For example, the second conversion circuit 112A may include a fourth transformer T4 connected between the first amplifier circuit AC1a and the output resistor RO. Furthermore, the second conversion circuit 112A may include a fifth transformer T5 connected between the second amplifier circuit AC2a and the output node ON.

[0152] Furthermore, the second conversion circuit 112A may include a sixth transformer T6 connected between a sixth node N6 from which it outputs the first and third signals S13 and an eighth node N8 from which it outputs the second and third signals S23, and connected between a seventh node N7 from which it outputs the first and fourth signals S14 and a ninth node N9 from which it outputs the second and fourth signals S24. In this disclosure, the sixth transformer T6 may include an inductor connected between the sixth node N6 and the eighth node N8, and an inductor connected between the seventh node N7 and the ninth node N9.

[0153] Furthermore, the second conversion circuit 112A may include a third capacitor C3 connected between the tenth node N10 and ground, with the tenth node N10 located between the fourth transformer T4 and the output resistor RO. The second conversion circuit 112A may also include a second inductor L2 connected between the output node ON and the tenth node N10. Additionally, the second conversion circuit 112A may include a fourth capacitor C4 connected between the output node ON and ground.

[0154] The second conversion circuit 112A can perform impedance matching to output an output signal OS with an output impedance Z3 from the first and third signals S13 to the second and fourth signals S24, each with a target input impedance Z2.

[0155] Furthermore, the second conversion circuit 112A can output a single-phase output signal OS from signals that are in a differential relationship and from signals that have a 90-degree phase difference with each of the differential signals.

[0156] In other words, the second conversion circuit 112A can perform the operation of converting the impedance of the signal input to it and outputting a single-phase signal from signals that have a phase difference with each other.

[0157] Therefore, compared to the case where separate circuits are provided for impedance conversion, for generating differential signals, and for generating signals with a 90-degree phase difference from each of the differential signals, the balanced amplifier circuit 100B1 according to this disclosure can be implemented with a relatively small area.

[0158] In other words, with the above structure, the balanced amplifier circuit 100B1 according to this disclosure can reduce the area that may be required to implement the electronic device 10 when compared with the associated amplifier circuit.

[0159] Furthermore, compared to the case where separate circuits are provided for impedance conversion and for generating single-phase signals from signals that are differentially related and signals that have a 90-degree phase difference with the signals that are differentially related, the balanced amplifier circuit 100B1 according to this disclosure may include a relatively small number of passive components.

[0160] Therefore, compared with related amplifier circuits, the balanced amplifier circuit 100B1 according to this disclosure can reduce power consumption due to passive components. Furthermore, compared with related amplifier circuits, the balanced amplifier circuit 100B1 can improve output power and gain.

[0161] Furthermore, referring to the above structure, the balanced amplifier circuit 100B1 can use different amplifier circuits AC1a and AC2a to amplify signals that have a 90-degree phase difference with each other.

[0162] Furthermore, the balanced amplifier circuit 100B1 can output a single-phase output signal OS with an output impedance Z3 from the first and third signals S13 to the second and fourth signals S24 output through different amplifier circuits AC1a and AC2a.

[0163] Therefore, when compared with a related amplifier circuit, the electronic device 10 (or balanced amplifier circuit 100B1) according to this disclosure can improve the output power.

[0164] Furthermore, the electronic device 10 (or balanced amplifier circuit 100B1) according to this disclosure can operate with less sensitivity to changes in load impedance by individually amplifying signals that have a 90-degree phase difference with each other.

[0165] In other words, compared with related amplifier circuits, the balanced amplifier circuit 100B1 according to this disclosure can improve the performance of the RF signal transmission operation of the electronic device 10.

[0166] Figure 6 This is a circuit diagram illustrating a balanced amplifier circuit including a first conversion circuit according to an embodiment of the present disclosure.

[0167] refer to Figure 6 The balanced amplifier circuit 100C1 may include a first conversion circuit 111B, a first amplifier circuit AC1, a second amplifier circuit AC2, and a second conversion circuit 112B.

[0168] Figure 6 The balanced amplifier circuit 100C1 shown may include and / or may be similar in many respects to Figure 2B The balanced amplifier circuit 100B shown may include additional features not mentioned above. Therefore, for the sake of brevity, the references above can be omitted. Figure 2B The description is a repetitive description of the balanced amplifier circuit 100C1.

[0169] The balanced amplifier circuit 100C1 may include a first conversion circuit 111B, which outputs multiple signals S11, S12, and S2, each having a target input impedance Z1 and different phases, from an input signal IS having an input impedance Z0. In this disclosure, Figure 6 The first conversion circuit 111B shown may include and / or may be similar in many respects to Figure 2B The first conversion circuit 111 shown may include additional features not mentioned above. Therefore, for the sake of brevity, the references above can be omitted. Figure 2B The description is a repetition of the description of the first conversion circuit 111B.

[0170] In this disclosure, the first signal S11 and the second signal S12 can be differentially related to each other. Furthermore, the first signal S11 and the second signal S2 can have a 90-degree phase difference.

[0171] According to an embodiment, the first conversion circuit 111B may include a first transformer T1, a second transformer T2, a first inductor L1, a second inductor L2, a first capacitor C1, and a second capacitor C2.

[0172] For example, the first conversion circuit 111B may include a first transformer T1 connected between the input node IN and the first amplifier circuit AC1. Furthermore, the first conversion circuit 111B may include a first capacitor C1 connected between the input node IN and ground.

[0173] Furthermore, the first conversion circuit 111B may include a first inductor L1 connected between the input node IN and the first node N1. The first conversion circuit 111B may also include a second capacitor C2 connected between the first node N1 and ground.

[0174] Furthermore, the first conversion circuit 111B may include a second transformer T2 connected between a fourth node N4 from which it outputs the second signal S2 and a second node N2 from which it outputs the first signal S11, and connected between the fourth node N4 and a third node N3 from which it outputs the first second signal S12. For example, the second transformer T2 may include an inductor connected between the second node N2 and the third node N3, and an inductor connected between the fourth node N4 and ground.

[0175] The first conversion circuit 111B may include a second inductor L2 connected between the first node N1 and the fourth node N4.

[0176] The first conversion circuit 111B can perform the operation of converting the impedance of the input signal IS and outputting signals S11, S12 and S2 that have different phases from each other from the single-phase input signal IS.

[0177] In other words, the first conversion circuit 111B can perform impedance matching to output signals S11, S12 and S2, each with a target input impedance Z1, from an input signal IS with an input impedance Z0.

[0178] The first conversion circuit 111B can output signals that are in a differential relationship from the single-phase input signal IS. For example, the first conversion circuit 111B can output a first signal S11 and a second signal S12 that are in a differential relationship from the single-phase input signal IS.

[0179] The first conversion circuit 111B can output signals with a 90-degree phase difference from each other. For example, the first conversion circuit 111B can output a second signal S2 that is orthogonal to the first signal S11.

[0180] Therefore, compared to the case where separate circuits are provided for impedance conversion, for generating differential signals, and for generating signals with a 90-degree phase difference, the first conversion circuit 111B can be implemented with a relatively small area.

[0181] Compared to related amplifier circuits, the balanced amplifier circuit 100C1 according to this disclosure can reduce the circuit area that may be required for output signals S11, S12 and S2 from the input signal IS.

[0182] In other words, according to the above configuration, the balanced amplifier circuit 100C1 can reduce the area that the electronic device 10 may require compared to the associated amplifier circuit.

[0183] The balanced amplifier circuit 100C1 may include a first amplifier circuit AC1 and a second amplifier circuit AC2.

[0184] For example, the balanced amplifier circuit 100C1 may include a first amplifier circuit AC1 that amplifies the first signal S11 and the first second signal S12.

[0185] The first amplifier circuit AC1 can amplify the first signal S11 and the first second signal S12 with a specified gain. For example, the first amplifier circuit AC1 can amplify the first signal S11 and output the amplified first signal S11 as the first third signal S13. In addition, the first amplifier circuit AC1 can amplify the first second signal S12 and output the amplified first second signal S12 as the first fourth signal S14.

[0186] In addition, the balanced amplifier circuit 100C1 may include a second amplifier circuit AC2 that amplifies the second signal S2.

[0187] The second amplifier circuit AC2 can amplify the second signal S2 with a specified gain. For example, the second amplifier circuit AC2 can amplify the second signal S2 and output the amplified second signal S2 as the third signal S3.

[0188] In this disclosure, the first amplifier circuit AC1 can amplify signals that are in a differential relationship (e.g., a first signal S11 and a second signal S12). Therefore, the first amplifier circuit AC1 can be referred to as a differential amplifier. Furthermore, for example, the second amplifier circuit AC2 can be understood as an amplifier that amplifies single-phase signals.

[0189] In addition, the balanced amplifier circuit 100C1 may include a second conversion circuit 112B, which outputs an output signal OS with an output impedance Z3 from a first third signal S13, a first fourth signal S14 and a third signal S3, each having a target output impedance Z2 and a 90-degree phase difference relative to each other.

[0190] In this disclosure, Figure 6 The second conversion circuit 112B shown may include and / or may be similar in many respects to Figure 2B The second conversion circuit 112 shown may include additional features not mentioned above. Therefore, for the sake of brevity, the references above can be omitted. Figure 2B The description is a repetition of the description of the second conversion circuit 112B.

[0191] The second conversion circuit 112B may include a third transformer T3, a fourth transformer T4, a third capacitor C3, a fourth capacitor C4, a third inductor L3, and a fourth inductor L4.

[0192] For example, the second conversion circuit 112B may include a third transformer T3 connected between the first amplifier circuit AC1 and the output resistor RO.

[0193] Furthermore, the second conversion circuit 112B may include a fourth transformer T4 connected between a fifth node N5, from which it outputs the first and third signals S13, and a seventh node N7, from which it outputs the third signal S3, and connected between a sixth node N6, from which it outputs the first and fourth signals S14, and a seventh node N7, from which it outputs the third signal S3. That is, the fourth transformer T4 may include an inductor connected between the fifth node N5 and the sixth node N6, and an inductor connected between the seventh node N7 and ground.

[0194] Furthermore, the second conversion circuit 112B may include a third inductor L3 connected between the seventh node N7 and the output node ON. The second conversion circuit 112B may also include a third capacitor C3 connected between the eighth node N8 and ground, with the eighth node N8 located between the third transformer T3 and the output resistor RO. The second conversion circuit 112B may also include a fourth inductor L4 connected between the output node ON and the eighth node N8. Additionally, the second conversion circuit 112B may also include a fourth capacitor C4 connected between the output node ON and ground.

[0195] The second conversion circuit 112B can perform impedance matching to output an output signal OS with an output impedance Z3 from the first third signal S13, the first fourth signal S14, and the third signal S3, each with a target output impedance Z2.

[0196] Furthermore, the second conversion circuit 112B can output a single-phase output signal OS from signals that are in a differential relationship and signals that have a 90-degree phase difference with each other. For example, the second conversion circuit 112B can output a single-phase output signal OS from a first and a third signal S13 and a first and a fourth signal S14 that are in a differential relationship, as well as a third signal S3 that has a 90-degree phase difference with the first and third signal S13.

[0197] In other words, the second conversion circuit 112B can perform the operation of converting the impedance of the signal input to it and outputting a single-phase signal from signals that have a phase difference with each other.

[0198] Therefore, compared to the case where separate circuits are provided for impedance conversion and for generating single-phase signals from signals in a differential relationship and signals with a 90-degree phase difference, the balanced amplifier circuit 100C1 according to this disclosure can be implemented with a relatively small area.

[0199] In other words, according to the above configuration, the balanced amplifier circuit 100C1 can reduce the area that the electronic device 10 may require compared to the associated amplifier circuit.

[0200] Furthermore, compared to the case where separate circuits are provided for impedance conversion and for generating single-phase signals from signals in a differential relationship and signals with a 90-degree phase difference, the balanced amplifier circuit 100C1 according to this disclosure may include a relatively small number of passive components.

[0201] Therefore, compared with related amplifier circuits, the balanced amplifier circuit 100C1 according to this disclosure can reduce power consumption due to passive components. Furthermore, compared with related amplifier circuits, the balanced amplifier circuit 100C1 can improve output power and gain.

[0202] Furthermore, referring to the above configuration, the balanced amplifier circuit 100C1 can use different first amplifier circuits AC1 and second amplifier circuits AC2 to amplify signals that have a 90-degree phase difference with each other.

[0203] Furthermore, the balanced amplifier circuit 100C1 can output a single-phase output signal OS with an output impedance Z3 from the first third signal S13, the first fourth signal S14, and the third signal S3 output from the first amplifier circuit AC1 and the second amplifier circuit AC2 respectively.

[0204] Therefore, when compared with a related amplifier circuit, the electronic device 10 (or balanced amplifier circuit 100C1) according to this disclosure can improve the output power.

[0205] Furthermore, the electronic device 10 (or balanced amplifier circuit 100C1) according to this disclosure can operate with less sensitivity to changes in load impedance by individually amplifying signals that have a 90-degree phase difference with each other.

[0206] In other words, compared with related amplifier circuits, the balanced amplifier circuit 100C1 according to this disclosure can improve the performance of the RF signal transmission operation of the electronic device 10.

[0207] Figure 7 This is a circuit diagram illustrating a balanced amplifier circuit including a first conversion circuit according to an embodiment of the present disclosure.

[0208] refer to Figure 7 The balanced amplifier circuit 100C2 may include a first conversion circuit 111C, a first amplifier circuit AC1, a second amplifier circuit AC2, and a second conversion circuit 112C.

[0209] Figure 7 The balanced amplifier circuit 100C2 shown may include and / or may be similar in many respects to Figure 2B The balanced amplifier circuit 100B shown may include additional features not mentioned above. Therefore, for the sake of brevity, the references above can be omitted. Figure 2B The description is a repetition of the description of the balanced amplifier circuit 100C2.

[0210] The balanced amplifier circuit 100C2 can receive a first input signal ISP with an input impedance ZO through the first input node INP. Furthermore, the balanced amplifier circuit 100C2 can receive a second input signal ISN with an input impedance ZO through the second input node INN. In this disclosure, the first input signal ISP and the second input signal ISN can have a differential relationship with each other.

[0211] The balanced amplifier circuit 100C2 may include a first conversion circuit 111C, which can output multiple signals S11 to S22 from a first input signal ISP and a second input signal ISN. Each of the first input signal ISP and the second input signal ISN may have an input impedance ZO. Each of the multiple signals S11 to S22 may have a target input impedance Z1 and a different phase. In this disclosure, Figure 7 The first conversion circuit 111C shown may include and / or may be similar in many respects to Figure 2B The first conversion circuit 111 shown may include additional features not mentioned above. Therefore, for the sake of brevity, the references above can be omitted. Figure 2B The description is a repetition of the description of the first conversion circuit 111C.

[0212] In this disclosure, for example, the first signal S11 and the first second signal S12 may be differentially related to each other. Furthermore, the second first signal S21 and the second second signal S22 may be differentially related to each other. Additionally, the first first signal S11 and the second first signal S21 may have a 90-degree phase difference. The first second signal S12 and the second second signal S22 may also have a 90-degree phase difference.

[0213] The first conversion circuit 111C may include a first transformer T1, a second transformer T2, a third transformer T3, a fourth transformer T4, a first capacitor C1, and a second capacitor C2.

[0214] In other words, the first conversion circuit 111C may include a first transformer T1 connected between the first amplifier circuit AC1 and the first input node INP, and connected between the first amplifier circuit AC1 and the second input node INN. Furthermore, the first conversion circuit 111C may include a first capacitor C1 connected between the first input node INP and the second input node INN.

[0215] In addition, the first conversion circuit 111C may include a second transformer T2 connected between the input resistor RI and the second amplifier circuit AC2.

[0216] In addition, the first conversion circuit 111C may include a second capacitor C2 connected between the first node N1 and ground, the first node N1 being between the input resistor RI and the second transformer T2.

[0217] The first conversion circuit 111C may include a third transformer T3 connected between a second node N2 from which it outputs a first signal S11 and a fourth node N4 from which it outputs a second signal S21, and connected between a third node N3 from which it outputs a first signal S12 and a fifth node N5 from which it outputs a second signal S22. In this disclosure, the third transformer T3 may include an inductor connected between the second node N2 and the fourth node N4, and an inductor connected between the third node N3 and the fifth node N5.

[0218] Furthermore, the first conversion circuit 111C may include a fourth transformer T4 connected between the first input node INP and the first node N1 and between the second input node INN and the first node N1. In this disclosure, the fourth transformer T4 may include an inductor connected between the first input node INP and the second input node INN, and an inductor connected between the first node N1 and ground.

[0219] The first conversion circuit 111C can perform the operation of converting the impedance of the first input signal ISP and the second input signal ISN, outputting a first signal S11 and a first signal S12 that are in a differential relationship from the first input signal ISP and the second input signal ISN, and outputting a first signal S11 and a second signal S21 that have a 90-degree phase difference with each other.

[0220] In other words, the first conversion circuit 111C can perform impedance matching to output multiple signals S11 to S22 from the first input signal ISP and the second input signal ISN. Each of the first input signal ISP and the second input signal ISN can have an input impedance ZO. Each of the multiple signals S11 to S22 can have a target input impedance Z1.

[0221] The first conversion circuit 111C can output signals that are in a differential relationship. For example, the first conversion circuit 111C can output a first signal S11 and a second signal S21 that are in a differential relationship.

[0222] The first conversion circuit 111C can output signals that have a 90-degree phase difference with each other. For example, the first conversion circuit 111C can output a second first signal S21 that has a 90-degree phase difference with the first first signal S11.

[0223] Therefore, compared to the case where separate circuits are provided for impedance conversion, for generating signals in a differential relationship, and for generating signals with a 90-degree phase difference from each other, the first conversion circuit 111C can be implemented with a relatively small area.

[0224] Compared to related amplifier circuits, the balanced amplifier circuit 100C2 according to this disclosure can reduce the circuit area that may be required to output multiple signals S11 to S22 from the first input signal ISP and the second input signal ISN.

[0225] In other words, according to the above configuration, the balanced amplifier circuit 100C2 can reduce the area that the electronic device 10 may require compared to the associated amplifier circuit.

[0226] Furthermore, the balanced amplifier circuit 100C2 may include a first amplifier circuit AC1 and a second amplifier circuit AC2. In this disclosure, the first amplifier circuit AC1 can be understood as having the same characteristics as... Figure 3 The first amplifier circuit AC1a shown has a substantially similar and / or identical configuration, and may include additional features not mentioned above. Furthermore, the second amplifier circuit AC2 can be understood to have the same configuration as... Figure 3The second amplifier circuit AC2a shown has a substantially similar and / or identical configuration, and may include additional features not mentioned above. Therefore, for the sake of brevity, the references above can be omitted. Figure 3 The description is a repetition of the description of the balanced amplifier circuit 100C2.

[0227] Furthermore, the balanced amplifier circuit 100C2 may include a second conversion circuit 112C, which outputs an output signal OS having an output impedance Z3 from first and third signals S13 to second and fourth signals S24, each having a target output impedance Z2 and a 90-degree phase difference relative to each other. In this disclosure, Figure 7 The second conversion circuit 112C shown may include and / or may be similar in many respects to Figure 2B The second conversion circuit 112 shown may include additional features not mentioned above. Therefore, for the sake of brevity, the references above can be omitted. Figure 2B The description is a repetition of the description of the second conversion circuit 112C.

[0228] The second conversion circuit 112C may include a fifth transformer T5, a sixth transformer T6, a seventh transformer T7, a third capacitor C3, a fourth capacitor C4, and a second inductor L2.

[0229] For example, the second conversion circuit 112C may include a fifth transformer T5 connected between the first amplifier circuit AC1 and the output resistor RO. Furthermore, the second conversion circuit 112C may include a sixth transformer T6 connected between the second amplifier circuit AC2 and the output node ON.

[0230] Furthermore, the second conversion circuit 112C may include a seventh transformer T7 connected between a sixth node N6, from which it outputs the first and third signals S13, and an eighth node N8, from which it outputs the second and third signals S23, and between a seventh node N7, from which it outputs the first and fourth signals S14, and a ninth node N9, from which it outputs the second and fourth signals S24. In this disclosure, the seventh transformer T7 may include an inductor connected between the sixth node N6 and the eighth node N8, and an inductor connected between the seventh node N7 and the ninth node N9.

[0231] The second conversion circuit 112C may include a third capacitor C3 connected between the tenth node N10 and ground, the tenth node N10 being between the fifth transformer T5 and the output resistor RO. Furthermore, the second conversion circuit 112C may include a fourth capacitor C4 connected between the output node ON and ground.

[0232] The second conversion circuit 112C may include a second inductor L2 connected between the tenth node N10 and the output node ON.

[0233] The second conversion circuit 112C can perform impedance matching to output an output signal OS with an output impedance Z3 from the first and third signals S13 to the second and fourth signals S24, each with a target output impedance Z2.

[0234] Furthermore, the second conversion circuit 112C can output a single-phase output signal OS from signals that are differentially related and signals that have a 90-degree phase difference with each other. For example, the second conversion circuit 112C can output a single-phase output signal OS from a first third signal S13 and a first fourth signal S14 that are differentially related, a second third signal S23 that has a 90-degree phase difference with the first third signal S13, and a second fourth signal S24 that has a 90-degree phase difference with the first fourth signal S14.

[0235] In other words, the second conversion circuit 112C can perform the operation of converting the impedance of the input signal and outputting a single-phase signal from signals that have a phase difference with each other.

[0236] Therefore, compared to the case where separate circuits are provided for impedance conversion and for generating single-phase signals from signals that are in a differential relationship and signals that have a 90-degree phase difference from each other, the balanced amplifier circuit 100C2 according to this disclosure can be implemented with a relatively small area.

[0237] In other words, according to the above configuration, the balanced amplifier circuit 100C2 can reduce the area that the electronic device 10 may require compared to the associated amplifier circuit.

[0238] Furthermore, compared to the case where separate circuits are provided for impedance conversion, for generating single-phase signals from signals in a differential relationship, and for generating signals with a 90-degree phase difference relative to each of the signals in a differential relationship, the balanced amplifier circuit 100C2 according to this disclosure may include a relatively small number of passive components.

[0239] Therefore, compared with related amplifier circuits, the balanced amplifier circuit 100C2 according to this disclosure can reduce power consumption due to passive components. Furthermore, compared with related amplifier circuits, the balanced amplifier circuit 100C2 can improve output power and gain.

[0240] Figure 8 This is a circuit diagram illustrating a balanced amplifier circuit including a first conversion circuit according to an embodiment of the present disclosure.

[0241] refer to Figure 8 The balanced amplifier circuit 100C3 may include a first conversion circuit 111D, a first amplifier circuit AC1, a second amplifier circuit AC2, and a second conversion circuit 112D.

[0242] Figure 8 The balanced amplifier circuit 100C3 shown may include and / or may be similar in many respects to Figure 2B The balanced amplifier circuit 100B shown may include additional features not mentioned above. Therefore, for the sake of brevity, the references above can be omitted. Figure 2B The description is a repetition of the description of the balanced amplifier circuit 100C3.

[0243] The balanced amplifier circuit 100C3 can receive a first input signal ISP with an input impedance ZO through the first input node INP. The balanced amplifier circuit 100C3 can receive a second input signal ISN with an input impedance ZO through the second input node INN. In this disclosure, the first input signal ISP and the second input signal ISN can have a differential relationship with each other.

[0244] The balanced amplifier circuit 100C3 may include a first conversion circuit 111D, which outputs multiple signals S11, S12, and S2, each having a target input impedance Z1 and different phases, from a first input signal ISP and a second input signal ISN, each having an input impedance Z0. In this disclosure, Figure 8 The first conversion circuit 111D shown may include and / or may be similar in many respects to Figure 2B The first conversion circuit 111 shown may include additional features not mentioned above. Therefore, for the sake of brevity, the references above can be omitted. Figure 2B The description is a repetition of the description of the first conversion circuit 111D.

[0245] The first signal S11 and the second signal S12 can be in a differential relationship. Furthermore, the first signal S11 and the second signal S2 can have a 90-degree phase difference relative to each other.

[0246] The first conversion circuit 111D may include a first transformer T1, a second transformer T2, a third transformer T3, a first inductor L1, a first capacitor C1, and a second capacitor C2.

[0247] For example, the first conversion circuit 111D may include a first transformer T1 connected between the first input node INP and the first amplifier circuit AC1, and connected between the second input node INN and the first amplifier circuit AC1. Furthermore, the first conversion circuit 111D may include a first capacitor C1 connected between the first input node INP and the second input node INN.

[0248] The first conversion circuit 111D may include a first inductor L1 connected between the input resistor RI and the second amplifier circuit AC2. Furthermore, the first conversion circuit 111D may include a second capacitor C2 connected between a first node N1 and ground, the first node N1 being between the input resistor RI and the first inductor L1.

[0249] Furthermore, the first conversion circuit 111D may include a second transformer T2 connected between a fourth node N4 from which it outputs the second signal S2 and a second node N2 from which it outputs the first signal S11, and connected between the fourth node N4 from which it outputs the second signal S2 and a third node N3 from which it outputs the first signal S12. In this disclosure, the second transformer T2 may include an inductor connected between the second node N2 and the third node N3, and an inductor connected between the fourth node N4 and ground.

[0250] The first conversion circuit 111D may include a third transformer T3 connected between the first input node INP and the first node N1 and between the second input node INN and the first node N1. In this disclosure, the third transformer T3 may include an inductor connected between the first input node INP and the second input node INN, and an inductor connected between the first node N1 and ground.

[0251] The first conversion circuit 111D can perform the operation of converting the impedance of the first input signal ISP and the second input signal ISN, and outputting signals S11, S12 and S2 with different phases from the first input signal ISP and the second input signal ISN which are in a differential relationship.

[0252] For example, the first conversion circuit 111D can perform an impedance matching function to output signals S11, S12 and S2, each having a target input impedance Z1, from a first input signal ISP and a second input signal ISN, each having an input impedance Z0.

[0253] Furthermore, the first conversion circuit 111D can output signals S11, S12, and S2 with different phases from the first input signal ISP and the second input signal ISN, which are in a differential relationship. For example, the first conversion circuit 111D can output a first signal S11 and a first second signal S12 that are in a differential relationship with each other. Additionally, for example, the first conversion circuit 111D can output a second signal S2 that has a 90-degree phase difference with the first signal S11.

[0254] Therefore, compared to the case where separate circuits are provided for impedance conversion, for generating signals in a differential relationship, and for generating signals with a 90-degree phase difference, the first conversion circuit 111D can be implemented with a relatively small area.

[0255] When compared with related amplifier circuits, the balanced amplifier circuit 100C3 according to this disclosure can reduce the circuit area that may be required for output signals S11, S12 and S2 from the first input signal ISP and the second input signal ISN.

[0256] In other words, according to the above configuration, the balanced amplifier circuit 100C3 can reduce the area that the electronic device 10 may require compared to the associated amplifier circuit.

[0257] The balanced amplifier circuit 100C3 may include a first amplifier circuit AC1 and a second amplifier circuit AC2.

[0258] For example, the balanced amplifier circuit 100C3 may include a first amplifier circuit AC1 that amplifies the first signal S11 and the first second signal S12.

[0259] The first amplifier circuit AC1 can amplify the first signal S11 and the first second signal S12 with a specified gain. For example, the first amplifier circuit AC1 can amplify the first signal S11 and output the amplified first signal S11 as the first third signal S13. In addition, the first amplifier circuit AC1 can amplify the first second signal S12 and output the amplified first second signal S12 as the first fourth signal S14.

[0260] The balanced amplifier circuit 100C3 may include a second amplifier circuit AC2 that amplifies the second signal S2.

[0261] The second amplifier circuit AC2 can amplify the second signal S2 with a specified gain. For example, the second amplifier circuit AC2 can amplify the second signal S2 and output the amplified second signal S2 as the third signal S3.

[0262] In this disclosure, the first amplifier circuit AC1 can amplify signals that are in a differential relationship (e.g., a first signal S11 and a second signal S12). Therefore, the first amplifier circuit AC1 can be referred to as a differential amplifier. Furthermore, the second amplifier circuit AC2 can be understood as an amplifier that amplifies single-phase signals.

[0263] In addition, the balanced amplifier circuit 100C3 may include a second conversion circuit 112D, which outputs an output signal OS having an output impedance Z3 from a first third signal S13, a first fourth signal S14, and a third signal S3, each having a target output impedance Z2 and a 90-degree phase difference relative to each other.

[0264] In this disclosure, Figure 8The second conversion circuit 112D shown may include and / or may be similar in many respects to Figure 2B The second conversion circuit 112 shown may include additional features not mentioned above. Therefore, for the sake of brevity, the references above can be omitted. Figure 2B The description is a repetition of the description of the second conversion circuit 112D.

[0265] In an embodiment, the second conversion circuit 112D may include a fourth transformer T4, a fifth transformer T5, a third capacitor C3, a fourth capacitor C4, a second inductor L2, and a third inductor L3.

[0266] In other words, the second conversion circuit 112D may include a fourth transformer T4 connected between the first amplifier circuit AC1 and the output resistor RO.

[0267] Furthermore, the second conversion circuit 112D may include a fifth transformer T5 connected between a fifth node N5, from which it outputs the first and third signals S13, and a seventh node N7, from which it outputs the third signal S3, and connected between a sixth node N6, from which it outputs the first and fourth signals S14, and a seventh node N7. In this disclosure, the fifth transformer T5 may include an inductor connected between the fifth node N5 and the sixth node N6, and an inductor connected between the seventh node N7 and ground.

[0268] The second conversion circuit 112D may include a third capacitor C3 connected between the eighth node N8 and ground, the eighth node N8 being between the fourth transformer T4 and the output resistor RO. Additionally, the second conversion circuit 112D may include a fourth capacitor C4 connected between the output node ON and ground.

[0269] The second conversion circuit 112D may include a second inductor L2 connected between the output node ON and the eighth node N8. Furthermore, the second conversion circuit 112D may include a third inductor L3 connected between the seventh node N7 and the output node ON.

[0270] The second conversion circuit 112D can perform impedance matching to output an output signal OS with an output impedance Z3 from the first third signal S13, the first fourth signal S14, and the third signal S3, each with a target output impedance Z2.

[0271] The second conversion circuit 112D can output a single-phase output signal OS from signals that are in a differential relationship and signals that have a 90-degree phase difference with each other. For example, the second conversion circuit 112D can output a single-phase output signal OS from a first and a third signal S13 and a first and a fourth signal S14 that are in a differential relationship, as well as a third signal S3 that has a 90-degree phase difference with the first and third signal S13.

[0272] In other words, the second conversion circuit 112D can perform the operation of converting the impedance of the input signal and outputting a single-phase signal from signals that have a phase difference with each other.

[0273] Therefore, compared to the case where separate circuits are provided for impedance conversion and for generating single-phase signals from signals that are in a differential relationship and signals that have a 90-degree phase difference from each other, the balanced amplifier circuit 100C3 according to this disclosure can be implemented with a relatively small area.

[0274] In other words, according to the above configuration, the balanced amplifier circuit 100C3 can reduce the area that the electronic device 10 may require compared to the associated amplifier circuit.

[0275] Furthermore, compared to the case where separate circuits are provided for impedance conversion, for generating single-phase signals from signals in a differential relationship, and for generating signals with a 90-degree phase difference from each other, the balanced amplifier circuit 100C3 according to this disclosure may include a relatively small number of passive components.

[0276] Therefore, compared with related amplifier circuits, the balanced amplifier circuit 100C3 according to this disclosure can reduce power consumption due to passive components. Furthermore, compared with related amplifier circuits, the balanced amplifier circuit 100C3 can improve output power and gain.

[0277] Figure 9A This is a circuit diagram illustrating a balanced amplifier circuit that also includes a third amplifier circuit according to an embodiment of the present disclosure. Figure 9B This is a circuit diagram illustrating a balanced amplifier circuit that also includes a third amplifier circuit for receiving differential signals, according to an embodiment of the present disclosure.

[0278] refer to Figure 9A and Figure 9B The balanced amplifier circuits 100D1 and 100D2 can each include a third amplifier circuit AC3a and a third amplifier circuit AC3b, respectively.

[0279] refer to Figure 9A The balanced amplifier circuit 100D1 may include a first conversion circuit 111A, a first amplifier circuit AC1, a second amplifier circuit AC2, and a second conversion circuit 112A.

[0280] Figure 9A The balanced amplifier circuit 100D1 shown may include and / or may be similar in many respects to Figure 2BThe balanced amplifier circuit 100B shown may include additional features not mentioned above. For example, the output resistor RO may be omitted from the balanced amplifier circuit 100D1. Therefore, for the sake of brevity, the references above may be omitted. Figure 2B The description is a repetitive description of the balanced amplifier circuit 100D1.

[0281] The first conversion circuit 111A can output multiple signals S11 to S22 from the first portion of the input signal PIS1 received via the input node IN. Each of the multiple signals S11 to S22 has a target input impedance Z1 and a different phase.

[0282] In this disclosure, the first part of the input signal PIS1 can be referred to as such Figure 3 At least a portion of the input signal IS shown.

[0283] In other words, the first conversion circuit 111A can perform impedance matching to output multiple signals S11 to S22, each with a target input impedance Z1, from the first part of the input signal PIS1.

[0284] Furthermore, the first conversion circuit 111A can output signals that are differentially related to each other from the single-phase first part input signal PIS1. For example, the first conversion circuit 111A can output a first signal S11 and a first second signal S12 that are differentially related to each other from the single-phase first part input signal PIS1.

[0285] Furthermore, the first conversion circuit 111A can output a signal orthogonal to each of the signals in a differential relationship. For example, the first conversion circuit 111A can output a second first signal S21 orthogonal to the first first signal S11. The first conversion circuit 111A can output a second second signal S22 orthogonal to the first second signal S12.

[0286] According to an embodiment, the balanced amplifier circuit 100D1 may further include a third amplifier circuit AC3a connected to the second conversion circuit 112A.

[0287] In other words, the balanced amplifier circuit 100D1 may include a third amplifier circuit AC3a, which amplifies the second part of the input signal PIS2 received via the additional input node AIN and outputs the amplified second part of the input signal PIS2 as the amplified signal AS.

[0288] In this disclosure, the second part of the input signal PIS2 can be referred to as Figure 3 The input signal IS shown is at least a portion of the input signal IS. Therefore, the first portion of the input signal PIS1 and the second portion of the input signal PIS2 can be referred to as being from... Figure 3The input signal IS shown is a separated signal. Furthermore, the first part of the input signal PIS1 and the second part of the input signal PIS2 can be distinguished from each other in at least one of phase and amplitude.

[0289] The second input signal PIS2 can be understood as a single-phase signal.

[0290] According to an embodiment, the third amplifier circuit AC3a may include a third transistor amplifier ATR3 that amplifies the second part of the input signal PIS2.

[0291] In addition, the third amplifier circuit AC3a may include a first additional capacitor CP1 connected in parallel between the tenth node N10 and ground to the third transistor amplifier ATR3.

[0292] In this disclosure, the first additional capacitor CP1 may include the parasitic capacitor of the third transistor amplifier ATR3. The first additional capacitor CP1 may include... Figure 3 The third capacitor C3 is shown. That is, the first additional capacitor CP1 can be referred to as the parasitic capacitor connected to the third transistor amplifier ATR3. Figure 3 The configuration is equivalent to that obtained by the third capacitor C3 shown.

[0293] The balanced amplifier circuit 100D1 may include a second conversion circuit 112A, which outputs an output signal OS from the first and third signals S13, the first and fourth signals S14, the second and third signals S23, the second and fourth signals S24 and the amplified signal AS.

[0294] For example, the second conversion circuit 112A can output an output signal OS with an output impedance Z3 from the amplified signal AS and the first third signal S13 to the second fourth signal S24, each having a target output impedance Z2 and a 90-degree phase difference relative to each other.

[0295] In this disclosure, when the amplified signal AS is input to the second conversion circuit 112A, the load impedance in the direction from the first amplifier circuit AC1 and the second amplifier circuit AC2 toward the second conversion circuit 112A may change.

[0296] In other words, the balanced amplifier circuit 100D1 can generate load modulation by amplifying a portion of the input signal through the third amplifier circuit AC3a.

[0297] Therefore, compared with related amplifier circuits, the balanced amplifier circuit 100D1 according to this disclosure can improve the power efficiency of amplifying and outputting input signals.

[0298] refer to Figure 9BThe balanced amplifier circuit 100D2 may also include a third amplifier circuit AC3b connected to the second conversion circuit 112E.

[0299] For example, the balanced amplifier circuit 100D2 may include a third amplifier circuit AC3b, which amplifies the second first portion input signal PIS2P received via the first additional input node AINP and the second second portion input signal PIS2N received via the second additional input node AINP. In this disclosure, the second first portion input signal PIS2P and the second second portion input signal PIS2N may have a differential relationship with each other.

[0300] According to the embodiment, the third amplifier circuit AC3b can amplify the second first part of the input signal PIS2P and output the amplified second first part of the input signal PIS2P as the first amplified signal AS1. Furthermore, the third amplifier circuit AC3b can amplify the second second part of the input signal PIS2N and output the amplified second second part of the input signal PIS2N as the second amplified signal AS2.

[0301] In other words, the third amplifier circuit AC3b can amplify the second first part input signal PIS2P and the second second part input signal PIS2N, which are in a differential relationship, and can output the amplified second first part input signal PIS2P and the amplified second second part input signal PIS2N as the first amplified signal AS1 and the second amplified signal AS2.

[0302] According to an embodiment, the third amplifier circuit AC3b may include a third transistor amplifier ATR3 that amplifies the second first part input signal PIS2P and the second second part input signal PIS2N.

[0303] The third amplifier circuit AC3a may include a first additional capacitor CP1 connected in parallel between the tenth node N10 and the eleventh node N11 to the third transistor amplifier ATR3.

[0304] In this disclosure, the first additional capacitor CP1 may include a parasitic capacitor of the third transistor amplifier ATR3. Furthermore, the first additional capacitor CP1 may include... Figure 3 The third capacitor C3 is shown. That is, the first additional capacitor CP1 can be referred to as the parasitic capacitor connected to the third transistor amplifier ATR3. Figure 3 The configuration is equivalent to that obtained by the third capacitor C3 shown.

[0305] The balanced amplifier circuit 100D2 may include a second conversion circuit 112E, which outputs an output signal OS from the first third signal S13, the first fourth signal S14, the second third signal S23, the second fourth signal S24, the first amplified signal AS1, and the second amplified signal AS2.

[0306] The second conversion circuit 112E may include a fourth transformer T4, a fifth transformer T5, a sixth transformer T6, a seventh transformer T7, and a fourth capacitor C4.

[0307] For example, the second conversion circuit 112E may include a fourth transformer T4 connected between the first amplifier circuit AC1 and the third amplifier circuit AC3b. Furthermore, the second conversion circuit 112E may include a fifth transformer T5 connected between the second amplifier circuit AC2 and the output node ON.

[0308] Furthermore, the second conversion circuit 112E may include a sixth transformer T6 connected between a sixth node N6 from which it outputs the first and third signals S13 and an eighth node N8 from which it outputs the second and third signals S23, and connected between a seventh node N7 from which it outputs the first and fourth signals S14 and a ninth node N9 from which it outputs the second and fourth signals S24. In this disclosure, the sixth transformer T6 may include an inductor connected between the sixth node N6 and the eighth node N8, and an inductor connected between the seventh node N7 and the ninth node N9.

[0309] The second conversion circuit 112E may include a seventh transformer T7 connected between the tenth node N10 and the output node ON, and between the eleventh node N11 and the output node ON. For example, the seventh transformer T7 may include an inductor connected between the tenth node N10 and the eleventh node N11, and an inductor connected between the output node ON and ground.

[0310] The second conversion circuit 112E may include a fourth capacitor C4 connected between the output node ON and ground.

[0311] The second conversion circuit 112E can output an output signal OS with an output impedance Z3 from the first amplified signal AS1, the second amplified signal AS2, and the first third signal S13 to the second fourth signal S24, each with a target output impedance Z2 and a 90-degree phase difference relative to each other.

[0312] In this disclosure, when the first amplified signal AS1 and the second amplified signal AS2 are input to the second conversion circuit 112E, the load impedance in the direction from the first amplifier circuit AC1 and the second amplifier circuit AC2 toward the second conversion circuit 112E may change.

[0313] In other words, according to the embodiment, the balanced amplifier circuit 100D2 can generate load modulation by using the third amplifier circuit AC3b, which amplifies a portion of the input signal.

[0314] Therefore, compared with related amplifier circuits, the balanced amplifier circuit 100D2 according to this disclosure can improve the power efficiency of amplifying and outputting input signals.

[0315] According to the above configuration, compared to the case where separate circuits are set up for impedance conversion, for generating single-phase signals from signals that are in a differential relationship and from signals that have a 90-degree phase difference with each of the signals in a differential relationship, the balanced amplifier circuit 100D2 can be implemented with a relatively small area.

[0316] In other words, according to the above configuration, the balanced amplifier circuit 100D2 can reduce the area that the electronic device 10 may require compared to the associated amplifier circuit.

[0317] Furthermore, compared to the case where separate circuits are provided for impedance conversion, for generating single-phase signals from signals that are differentially related and from signals that have a 90-degree phase difference with each of the signals that are differentially related, the balanced amplifier circuit 100D2 according to this disclosure may include a relatively small number of passive components.

[0318] Therefore, compared with related amplifier circuits, the balanced amplifier circuit 100D2 according to this disclosure can reduce power consumption due to passive components. Furthermore, compared with related amplifier circuits, the balanced amplifier circuit 100D2 can improve output power and gain.

[0319] Figure 10A This is a flowchart illustrating a method for controlling an input signal based on a first power consumption at an input node, according to an embodiment of the present disclosure. Figure 10B This is a flowchart illustrating a method for controlling an input signal based on a second power consumption at the output node, according to an embodiment of the present disclosure.

[0320] refer to Figure 10A and Figure 10B The processor 110 (or electronic device 10) can control the signals input to the balanced amplifier circuit 100 based on power consumption.

[0321] refer to Figure 10A The processor 110 can control the signal input to the balanced amplifier circuit 100 based on the first power consumption PC1 consumed at the input node IN.

[0322] In operation S10, the processor 110 can detect the first power consumption PC1 consumed at the input node IN.

[0323] For example, processor 110 can detect the first power consumption PC1 consumed at input node IN when balanced amplifier circuit 100 amplifies input signal IS and outputs the amplified input signal IS as output signal OS.

[0324] In this disclosure, the electronic device 10 may further include a detection circuit that detects the power consumption consumed at at least one node of the balanced amplifier circuit 100. Furthermore, the detection circuit may be electrically connected to the processor 110.

[0325] In operation S20, the processor 110 may determine whether the first power consumption PC1 is less than a first threshold TH1. In this disclosure, the first threshold TH1 may be understood as a predetermined value relative to the first power consumption PC1.

[0326] When the first power consumption PC1 is greater than or equal to the first threshold TH1 (No in operation S20), in operation S31, the processor 110 can input the input signal IS to the input node IN.

[0327] For example, when the first power consumption PC1 is greater than or equal to the first threshold TH1, the processor 110 may input the input signal IS that may be needed to transmit an RF signal with a specified frequency through the antenna 130 to the input node IN.

[0328] When the first power consumption PC1 is less than the first threshold TH1 (yes in operation S20), in operation S33, the processor 110 can input the first part of the input signal PIS1 to the input node IN.

[0329] In this disclosure, the first portion of the input signal PIS1 can be understood as at least a portion of the signal (e.g., input signal IS) input to the balanced amplifier circuit 100 to transmit an RF signal of a specified frequency via the antenna 130.

[0330] Furthermore, in operation S40, the processor 110 can input the second part of the input signal PIS2 to the third amplifier circuits AC3a and AC3b.

[0331] For example, when the first power consumption PC1 is less than the first threshold TH1, the processor 110 can input the second part of the input signal PIS2 to the additional input node AIN of the third amplifier circuits AC3a and AC3b.

[0332] In this disclosure, the second portion of the input signal PIS2 can be understood as at least a portion of the signal (e.g., the input signal IS) input to the balanced amplifier circuit 100 to transmit an RF signal of a specified frequency via the antenna 130.

[0333] Furthermore, the second part of the input signal PIS2 can be distinguished from the first part of the input signal PIS1 by at least one of its amplitude and phase. That is, the first part of the input signal PIS1 and the second part of the input signal PIS2 can constitute the input signal IS that may be needed to transmit an RF signal of a specified frequency through the antenna 130.

[0334] In this disclosure, the order in which operations S33 and S40 are performed should not be limited to Figure 10A The order shown is such that at least a portion of operations S33 and S40 can be executed simultaneously.

[0335] In other words, when the first power consumption PC1 is less than the first threshold TH1, the processor 110 can input a portion of the signal that may be needed to transmit an RF signal with a specified frequency through the antenna 130 to the input node IN, and can input another portion of the signal to the additional input node AIN.

[0336] refer to Figure 10B The processor 110 can control the signal input to the balanced amplifier circuit 100 based on the second power consumption PC2 consumed at the output node ON.

[0337] In operation S11, the processor 110 can detect the second power consumption PC2 consumed at the output node ON.

[0338] For example, processor 110 can detect a second power consumption PC2 consumed at output node ON during the process in which balanced amplifier circuit 100 amplifies input signal IS and outputs the amplified input signal IS as output signal OS.

[0339] In operation S21, the processor 110 may determine whether the second power consumption PC2 is less than the second threshold TH2. In this disclosure, the second threshold TH2 may be a predetermined value relative to the second power consumption PC2.

[0340] When the second power consumption PC2 is greater than or equal to the second threshold TH2 (No in operation S21), in operation S32, the processor 110 can input the input signal IS to the input node IN.

[0341] For example, when the second power consumption PC2 is greater than or equal to the second threshold TH2, the processor 110 may input the input signal IS, which may be required to transmit an RF signal with a specified frequency through the antenna 130, to the input node IN.

[0342] When the second power consumption PC2 is less than the second threshold TH2 (yes in operation S21), in operation S34, the processor 110 can input the first part of the input signal PIS1 to the input node IN.

[0343] In operation S41, the processor 110 can input the second part of the input signal PIS2 to the third amplifier circuits AC3a and AC3b.

[0344] For example, when the second power consumption PC2 is less than the second threshold TH2, the processor 110 can input the second part of the input signal PIS2 to the additional input node AIN of the third amplifier circuits AC3a and AC3b.

[0345] In this disclosure, the second part of the input signal PIS2 can be understood as a portion of the signal input to the balanced amplifier circuit 100 to transmit an RF signal with a specified frequency via the antenna 130.

[0346] Furthermore, the second part of the input signal PIS2 can be distinguished from the first part of the input signal PIS1 by at least one of its amplitude and phase. That is, the first part of the input signal PIS1 and the second part of the input signal PIS2 can constitute the input signal IS that may be needed to transmit an RF signal of a specified frequency through the antenna 130.

[0347] In this disclosure, the order in which operations S34 and S41 are performed should not be limited to Figure 10B The order shown is such that at least a portion of operations S34 and S41 can be executed simultaneously.

[0348] In other words, when the second power consumption PC2 is less than the second threshold TH2, the processor 110 can input a portion of the signal that may be needed to transmit an RF signal with a specified frequency through the antenna 130 to the input node IN, and can input another portion of the signal to the additional input node AIN.

[0349] In addition, the third amplifier circuits AC3a and AC3b can amplify the second part of the input signal PIS2, and output the amplified second part of the input signal PIS2 as the amplified signal AS.

[0350] In addition, the second conversion circuit 112 can output the output signal OS from the first and third signals S13, the first and fourth signals S14, the second and third signals S23, the second and fourth signals S24 and the amplified signal AS.

[0351] In this disclosure, as the amplified signal AS is input to the second conversion circuit 112, the load impedance in the direction from the first amplifier circuit AC1 and the second amplifier circuit AC2 toward the second conversion circuit 112 may change.

[0352] In other words, when the first power consumption PC1 is less than the first threshold TH1, the processor 110 can input a portion of the signal (e.g., the input signal IS) that may be needed to transmit the RF signal to the third amplifier circuits AC3a and AC3b, thereby generating load modulation.

[0353] Therefore, compared with the associated amplifier circuit, the electronic device 10 can improve the power efficiency of the operation of transmitting RF signals.

[0354] Figure 11 This is a block diagram illustrating a wireless communication device according to an embodiment of the present disclosure.

[0355] refer to Figure 11 The wireless communication device 900 may include a communication processor 910, an RFIC 200, a power modulator 300, a duplexer 115, a power amplifier PA, and an antenna 130.

[0356] like Figure 11 The wireless communication device 900 and its components shown may include and / or may be similar in many respects to Figure 1 The electronic device 10 and its components are shown, and may include additional features not mentioned above. Therefore, for the sake of brevity, references to the above are omitted. Figure 1 The description is a repetitive description of the wireless communication device 900.

[0357] The communication processor 910 can process the transmitted baseband signal BB_T according to the established communication method via the internal digital transmission processor 810. Furthermore, the communication processor 910 can process the received baseband signal BB_R according to the established communication method via the digital reception processor 820. In an embodiment, the communication processor 910 may have... Figure 1 The processor 110 shown has a substantially similar and / or identical configuration.

[0358] For example, the communication processor 910 can process the signal to be transmitted or received according to communication methods such as, but not limited to, Orthogonal Frequency Division Multiplexing (OFDM), Orthogonal Frequency Division Multiple Access (OFDMA), Wideband Code Division Multiple Access (WCDMA), and High Speed ​​Packet Access+ (HSPA+). Furthermore, the communication processor 910 can process the transmitted baseband signal BB_T or the received baseband signal BB_R according to various types of communication methods (i.e., various communication methods that apply techniques for modulating or demodulating the amplitude and frequency of the transmitted baseband signal BB_T or the received baseband signal BB_R).

[0359] The communication processor 910 can extract the envelope of the baseband signal BB_T via the digital transmission processor 810, and can generate a digital envelope signal D_ENV based on the extracted envelope. Furthermore, the communication processor 910 can generate an average power signal D_REF based on an average power tracking table stored in memory. In this disclosure, the extracted envelope can correspond to the amplitude components of the transmitted baseband signal BB_T, i.e., the amplitudes of the I and Q signals.

[0360] In this disclosure, the communication processor 910 can use multiple internal digital-to-analog converters DAC1 and DAC2 to perform digital-to-analog conversion on the transmitted baseband signal BB_T and the digital envelope signal D_ENV to generate a transmitted signal TX and an analog envelope signal A_ENV as analog signals. That is, the average power signal D_REF output from the communication processor 910 can be a digital signal. Therefore, the average power signal D_REF can be provided to the digital-to-analog converter included in the power modulator 300 via the MIPI 830, and can be converted into an analog signal, such as a reference voltage signal, by the digital-to-analog converter included in the power modulator 300. The digital-to-analog converters DAC1 and DAC2 included in the communication processor 910 can operate at a relatively higher speed than the digital-to-analog converter included in the power modulator 300.

[0361] However, this disclosure should not be limited to or construed as such, and the communication processor 910 may convert the average power signal D_REF into an analog signal via an internal digital-to-analog converter. In such an embodiment, the communication processor 910 may provide the average power signal, converted into an analog signal, to the power modulator 300 as a reference voltage signal.

[0362] For ease of explanation, the communication processor 910 can be described as providing the average power signal D_REF to the digital-to-analog converter included in the power modulator 300 via the MIPI 830. However, embodiments of this disclosure are not limited thereto.

[0363] The transmitted signal TX and the analog envelope signal A_ENV can be differential signals, each including a positive signal and a negative signal, respectively.

[0364] Furthermore, the communication processor 910 can receive a received signal RX as an analog signal from the RFIC 200. The communication processor 910 can extract a received baseband signal BB_R as a digital signal by performing analog-to-digital conversion on the received signal RX via an internal analog-to-digital converter (ADC). In such an embodiment, the received signal RX can be a differential signal including both positive and negative signals.

[0365] RFIC 200 can generate an RF input signal RF_IN by up-converting the transmitted signal TX, or it can generate a received signal RX by down-converting the RF received signal RF_R. For example, RFIC 200 may include a transmitted circuit TXC for up-conversion, a received circuit RXC for down-conversion, and a local oscillator LO.

[0366] In this disclosure, the transmitting circuit TXC may include a first analog baseband filter ABF1, a first mixer MX1, and an amplifier 210. For example, the first analog baseband filter ABF1 may include a low-pass filter.

[0367] The first analog baseband filter ABF1 filters the transmit signal TX received from the communication processor 910 and provides the filtered transmit signal TX to the first mixer MX1. Furthermore, the first mixer MX1 ​​performs up-conversion, responding to a frequency signal provided by the local oscillator LO to convert the frequency of the transmit signal TX from baseband to a higher frequency band. Through up-conversion, the transmit signal TX can be provided to amplifier 210 as the RF input signal RF_IN, and amplifier 210 performs primary power amplification of the RF input signal RF_IN, providing the amplified RF input signal RF_IN to the power amplifier PA.

[0368] According to an embodiment, Figure 11 The amplifier 210 shown may include Figure 1 The balanced amplifier circuit 100 shown is illustrated.

[0369] Therefore, the balanced amplifier circuit 100 (or amplifier 210) may include a first conversion circuit 111, which outputs signals S11 and S12 with a target input impedance Z1 and differential relationship with each other, and signals S11 and S21 with a 90-degree phase difference with each other from the single-phase input signal IS.

[0370] In other words, compared to the case where separate circuits are provided for impedance conversion, for generating signals in a differential relationship, and for generating signals with a 90-degree phase difference, the balanced amplifier circuit 100 according to this disclosure can be implemented with a relatively small area.

[0371] In other words, according to the above configuration, the balanced amplifier circuit 100 can reduce the area that may be needed to implement the wireless communication device 900 compared to the associated amplifier circuit.

[0372] In addition, the balanced amplifier circuit 100 may include a first amplifier circuit AC1 and a second amplifier circuit AC2 that amplify at least a portion of the plurality of signals S11 to S22.

[0373] In addition, the balanced amplifier circuit 100 may include a second conversion circuit 112, which outputs a single-phase output signal OS with an output impedance Z3 from the first third signal S13 to the second fourth signal S24 amplified by the first amplifier circuit AC1 and the second amplifier circuit AC2.

[0374] In other words, compared to the case where separate circuits are provided for impedance conversion, for generating signals in a differential relationship, and for generating single-phase signals from signals in a differential relationship and signals having a 90-degree phase difference with each of the signals in a differential relationship, the balanced amplifier circuit 100 according to this disclosure may include a relatively small number of passive components.

[0375] Therefore, compared with related amplifier circuits, the balanced amplifier circuit 100 according to this disclosure can reduce power consumption due to passive components. Furthermore, compared with related amplifier circuits, the balanced amplifier circuit 100 can increase output power and gain.

[0376] The power amplifier PA can receive a power supply voltage (i.e., a dynamically variable output voltage) from the power modulator 300 and can perform secondary power amplification of the RF input signal RF_IN based on the received power supply voltage to generate an RF output signal RF_OUT. The power amplifier PA can then provide the generated RF output signal RF_OUT to the duplexer 115.

[0377] According to an embodiment, Figure 1The balanced amplifier circuit 100 can be included Figure 11 The power amplifier PA shown is shown.

[0378] The receiver circuit RXC may include a second analog baseband filter ABF2, a second mixer MX2, and a low-noise amplifier (LNA) 220. For example, the second analog baseband filter ABF2 may include a low-pass filter.

[0379] The low-noise amplifier 220 amplifies the RF received signal RF_R received from the duplexer 115 and provides the amplified RF received signal RF_R to the second mixer MX2. The second mixer MX2 can perform down-conversion using a frequency signal provided by the local oscillator LO to convert the frequency of the RF received signal RF_R from the high-frequency band to the baseband. Through down-conversion, the RF received signal RF_R can be provided to the second analog baseband filter ABF2 as the received signal RX, and the second analog baseband filter ABF2 can filter the received signal RX and provide the filtered received signal RX to the communication processor 910.

[0380] The power modulator 300 can generate a modulated output voltage whose level changes dynamically based on the analog envelope signal A_ENV and the average power signal D_REF, and can provide the modulated output voltage to the power amplifier PA as a power supply voltage.

[0381] For example, the power modulator 300 can receive an average power signal D_REF and an analog envelope signal A_ENV from the communication processor 910. The power modulator 300 can be driven in either ET mode or APT mode based on the received average power signal D_REF and analog envelope signal A_ENV to generate a dynamically variable output voltage. Furthermore, the power modulator 300 can provide the generated output voltage to the power amplifier PA as a power supply voltage.

[0382] When a power amplifier PA with a fixed supply voltage is applied, the power efficiency of the power amplifier PA may decrease. Therefore, for efficient power management of the power amplifier PA, the power modulator 300 can modulate the input voltage (e.g., power supplied from a battery) based on at least one of the analog envelope signal A_ENV and the average power signal D_REF, and can provide the modulated input voltage to the power amplifier PA as a supply voltage.

[0383] The wireless communication device 900 may include a duplexer 115 capable of separating the transmit frequency and the receive frequency. For example, the duplexer 115 may separate the RF output signal RF_OUT provided from the power amplifier PA for each frequency band, and may provide the RF output signal RF_OUT to the corresponding antenna 130. Furthermore, the duplexer 115 may provide external signals provided from the antenna 130 to the low-noise amplifier 220 of the receiver circuit RXC of the RFIC 200. For example, the duplexer 115 may include a front-end module with an integrated duplexer (FEMiD).

[0384] Antenna 130 can transmit an RF output signal RF_OUT to the outside, or it can provide an RF receive signal RF_R from an external source to RFIC 200. For example, antenna 130 can be referred to as a 1T1R antenna, but it should not be limited to or restricted by this.

[0385] Each of the communication processor 910, power modulator 300, RFIC 200, power amplifier PA, and duplexer 115 can be individually implemented as an IC, chip, or module. Furthermore, the communication processor 910, power modulator 300, RFIC 200, power amplifier PA, and duplexer 115 can be mounted together on a printed circuit board (PCB). However, the spirit of this disclosure is not limited thereto, and in some embodiments, at least some of the communication processor 910, power modulator 300, RFIC 200, power amplifier PA, and duplexer 115 can be implemented as a single communication chip.

[0386] also, Figure 11 The wireless communication device 900 shown may be included in a wireless communication system using cellular networks such as, but not limited to, fifth generation (5G), Long Term Evolution (LTE), etc., and / or may be included in a wireless local area network (WLAN) system or any other arbitrary wireless communication system. Figure 11 The configuration of the wireless communication device 900 shown is merely an example and can be configured differently depending on the communication protocol or communication method.

[0387] Figure 12 This is a block diagram illustrating an Internet of Things (IoT) device including electronic devices according to an embodiment of the present disclosure.

[0388] refer to Figure 12The term IoT can refer to a network between objects using wired or wireless communication. IoT device 1000 may have accessible wired or wireless interfaces and may include devices that communicate with at least one other device via these wired or wireless interfaces to send or receive data. The accessible interfaces of IoT device 1000 may include wired local area networks (LANs), wireless local area networks (WLANs) (such as, but not limited to, wireless fidelity (Wi-Fi)), wireless personal area networks (WPANs) (such as, but not limited to, Bluetooth™, universal serial bus (USB)), ZigBee, near field communication (NFC), radio-frequency identification (RFID), power line communication (PLC), or modem communication interfaces that can access mobile cellular networks (e.g., third-generation (3G), LTE, fourth-generation (4G), or fifth-generation (5G)). The Bluetooth interface may support Bluetooth Low Energy (BLE) communication.

[0389] Specifically, the IoT device 1000 may include a communication interface 1020 for communicating with external devices. The communication interface 1020 may be, for example, a wired local area network (LAN), a wireless local area communication interface (such as, but not limited to, Bluetooth™, Wi-Fi), ZigBee, or a modem communication interface that can access a PLC or mobile cellular network, such as, but not limited to, 3G, LTE, 4G, 5G, etc.

[0390] According to an embodiment, the IoT device 1000 may include and / or may be similar in many respects to Figure 1 The electronic device 10 shown may include additional features not mentioned above. Therefore, for the sake of brevity, the references above can be omitted. Figure 1 The description is a repetitive description of IoT device 1000.

[0391] The communication interface 1020 may include a transmitter and / or a receiver. Here, Figure 12 The communication interface 1020 shown can be understood to include Figure 1 The RFFE 120 and antenna 130 are shown.

[0392] For example, the communication interface 1020 may include a balanced amplifier circuit 100 that amplifies the signal to transmit RF signals through the antenna 130.

[0393] In this disclosure, the balanced amplifier circuit 100 may include a first conversion circuit 111, which outputs signals S11 and S12, each having a target input impedance Z1 and a differential relationship, and signals S11 and S21 having a 90-degree phase difference from each other, from the single-phase input signal IS.

[0394] In other words, compared to the case where separate circuits are provided for impedance conversion, for generating differential signals, and for generating signals with a 90-degree phase difference, the balanced amplifier circuit 100 according to this disclosure can be implemented with a relatively small area.

[0395] In other words, according to the above configuration, the balanced amplifier circuit 100 can reduce the area that may be needed to implement the IoT device 1000 compared to the associated amplifier circuit.

[0396] In addition, the balanced amplifier circuit 100 may include a first amplifier circuit AC1 and a second amplifier circuit AC2 that amplify at least a portion of the plurality of signals S11 to S22.

[0397] In addition, the balanced amplifier circuit 100 may include a second conversion circuit 112, which outputs a single-phase output signal OS with an output impedance Z3 from the first third signal S13 to the second fourth signal S24 amplified by the first amplifier circuit AC1 and the second amplifier circuit AC2.

[0398] In other words, compared to the case where separate circuits are provided for impedance conversion, for generating differential signals, and for generating single-phase signals from each of the differential signals having a 90-degree phase difference, the balanced amplifier circuit 100 according to this disclosure may include a relatively small number of passive components.

[0399] Therefore, compared with related amplifier circuits, the balanced amplifier circuit 100 according to this disclosure can reduce power consumption due to passive components. Compared with related amplifier circuits, the balanced amplifier circuit 100 can increase output power and gain.

[0400] The IoT device 1000 can send information to an access point or gateway via a transmitter and / or receive information from an access point or gateway via a receiver. Furthermore, the IoT device 1000 can communicate with a user device or another IoT device to send and / or receive control information or data from the IoT device 1000.

[0401] The IoT device 1000 may include a processor 1010 for performing operations. In this disclosure, Figure 12 The processor 1010 shown can have the same Figure 1 The processor 110 shown has a substantially similar and / or identical configuration, and may include additional features not mentioned above. Therefore, for the sake of brevity, the references above can be omitted. Figure 1 The description is a repetitive description of processor 1010.

[0402] The IoT device 1000 may also include a power supply unit, which includes a built-in battery for internal power supply or receives power from an external source. Additionally, the IoT device 1000 may include a display 1040 to display internal status or data. Users can control the IoT device 1000 through the user interface (UI) of the display 1040. The IoT device 1000 can transmit internal status and / or data to the outside via a transmitter and can receive control commands and / or data from an external source via a receiver.

[0403] The memory 1030 can store control command codes, control data, or user data for controlling the IoT device 1000. The memory 1030 may include at least one of volatile memory or non-volatile memory. Non-volatile memory may include at least one of various types of memory, including but not limited to: read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable and programmable ROM (EEPROM), flash memory, phase-change RAM (PRAM), magnetic RAM (MRAM), resistive RAM (ReRAM), or ferroelectric RAM (FRAM). Volatile memory may include at least one of various types of memory, including but not limited to: dynamic RAM (DRAM), static RAM (SRAM), or synchronous DRAM (SDRAM).

[0404] The IoT device 1000 may also include a storage device. The storage device may include at least one of the following non-volatile media: hard disk drive (HDD), solid-state drive (SSD), embedded multimedia card (eMMC), or universal flash storage (UFS). The storage device may store user information provided via input / output unit (I / O) 1050 and sensed information collected via sensor 1060.

[0405] Figure 13 This is a block diagram illustrating a mobile terminal using an electronic device according to an embodiment of the present disclosure.

[0406] refer to Figure 13 The mobile terminal 1100 may include a processor 1200, a memory 1300, a display 1400, and a radio frequency (RF) module 1510. Furthermore, the mobile terminal 1100 may include various components, such as, but not limited to, a lens, a sensor, and an audio module.

[0407] Processor 1200 can be implemented as a system-on-chip (SoC) and may include a central processing unit (CPU) 1210, RAM 1220, a power management unit (PMU) 1230, a memory interface (memory I / F) 1240, a display controller (DCON) 1250, a modem 1260, and a bus 1270. Processor 1200 may also include various other IPs. Processor 1200 may be referred to as ModAP because the functionality of the modem chip is integrated into processor 1200, but it should not be limited to or restricted by this.

[0408] In this disclosure, Figure 13 The processor 1200 shown may include and / or may be similar in many respects to Figure 1 The processor 110 shown may include additional features not mentioned above. Therefore, for the sake of brevity, the references above can be omitted. Figure 1 The description is a repetitive description of processor 1200.

[0409] The CPU 1210 can control the overall operation of the processor 1200 and the mobile terminal 1100. The CPU 1210 can control the operation of each component of the processor 1200. Furthermore, the CPU 1210 can be implemented as a multi-core processor. A multi-core processor can be a single computing component with two or more independent cores.

[0410] RAM 1220 can temporarily store programs, data, or instructions. For example, programs and / or data stored in memory 1300 can be temporarily stored in RAM 1220 according to the control or boot code of CPU 1210. RAM 1220 can be implemented as DRAM or SRAM.

[0411] The PMU 1230 can manage the power of each component of the processor 1200. The PMU 1230 can determine the operating status of each component of the processor 1200 and can control the operation of each component of the processor 1200.

[0412] The memory interface 1240 can control the overall operation of the memory 1300 and can control the data exchange between each component of the processor 1200 and the memory 1300. The memory interface 1240 can write data to or read data from the memory 1300 according to requests from the CPU 1210.

[0413] The display controller 1250 can send image data to the display 1400 to be displayed. The display 1400 can be implemented as a flat panel display or a flexible display, such as, but not limited to, a liquid crystal display (LCD) or an organic light emitting diode (OLED) display.

[0414] The modem 1260 for wireless communication can modulate data to be transmitted to be suitable for the wireless environment and can recover received data. The modem 1260 can perform digital communication with the RF module 1510.

[0415] According to an embodiment, the RF module 1510 can be electrically connected to Figure 1 The antenna 130 is shown. Additionally, the modem 1260 may include... Figure 1 The balanced amplifier circuit 100 shown is illustrated.

[0416] In such an embodiment, the balanced amplifier circuit 100 may include a first conversion circuit 111, which outputs signals S11 and S12 with a target input impedance Z1 and differentially related to each other, and signals S11 and S21 with a 90-degree phase difference from each other, from the single-phase input signal IS.

[0417] In other words, compared to the case where separate circuits are provided for impedance conversion, for generating signals in a differential relationship, and for generating signals with a 90-degree phase difference, the balanced amplifier circuit 100 according to this disclosure can be implemented with a relatively small area.

[0418] In other words, according to the above configuration, the balanced amplifier circuit 100 can reduce the area that may be needed to implement the mobile terminal 1100 compared to the associated amplifier circuit.

[0419] In addition, the balanced amplifier circuit 100 may include a first amplifier circuit AC1 and a second amplifier circuit AC2 that amplify at least a portion of the plurality of signals S11 to S22.

[0420] In addition, the balanced amplifier circuit 100 may include a second conversion circuit 112, which outputs a single-phase output signal OS with an output impedance Z3 from a first third signal S13 to a second fourth signal S24 having a target output impedance Z2 and different phases from each other.

[0421] In other words, compared to the case where a separate circuit is provided for impedance conversion, or for generating a single-phase signal from a signal that is differentially related to a signal that has a 90-degree phase difference with respect to each of the signals that are differentially related, the balanced amplifier circuit 100 according to this disclosure may include a relatively small number of passive components.

[0422] Therefore, compared with related amplifier circuits, the balanced amplifier circuit 100 according to this disclosure can reduce power consumption due to passive components. Furthermore, compared with related amplifier circuits, the balanced amplifier circuit 100 can increase output power and gain.

[0423] Therefore, RF module 1510 can convert high-frequency signals received via antenna 130 into low-frequency signals, and can transmit the converted low-frequency signals to modem 1260. Furthermore, RF module 1510 can convert low-frequency signals received from modem 1260 into high-frequency signals, and can transmit the converted high-frequency signals to the outside of mobile terminal 1100 via antenna 130. RF module 1510 can amplify or filter signals.

[0424] As described above, the balanced amplifier circuit 100 according to the present disclosure may include a first conversion circuit 111, which outputs multiple signals S11 to S22, each having a target input impedance Z1 and different phases, from a single-phase input signal IS.

[0425] In other words, compared to the case where separate circuits are provided for impedance conversion, for generating differential signals, and for generating signals with a 90-degree phase difference, the balanced amplifier circuit 100 according to this disclosure can be implemented with a relatively small area.

[0426] In other words, according to the above configuration, the balanced amplifier circuit 100 can reduce the area that may be needed to implement the mobile terminal 1100 compared to the associated amplifier circuit.

[0427] In addition, the balanced amplifier circuit 100 may include a first amplifier circuit AC1 and a second amplifier circuit AC2 that amplify at least a portion of the plurality of signals S11 to S22.

[0428] In addition, the balanced amplifier circuit 100 may include a second conversion circuit 112, which outputs a single-phase output signal OS with an output impedance Z3 from a first third signal S13 to a second fourth signal S24, each having a target output impedance Z2 and different phases.

[0429] In other words, compared to the case where separate circuitry is provided for impedance conversion and for generating single-phase signals from signals in a differential relationship and signals having a 90-degree phase difference with respect to each of the differential signals, the balanced amplifier circuit 100 according to this disclosure may include a relatively small number of passive components.

[0430] Therefore, compared with related amplifier circuits, the balanced amplifier circuit 100 according to this disclosure can reduce power consumption due to passive components. Furthermore, compared with related amplifier circuits, the balanced amplifier circuit 100 can increase output power and gain.

[0431] Although embodiments of this disclosure have been described, it should be understood that this disclosure is not intended to be limited to these embodiments, and various changes and modifications can be made by those skilled in the art within the spirit and scope of this disclosure. Therefore, the subject matter disclosed should not be limited to any single embodiment described herein, and the scope of this disclosure can be determined by the appended claims.

Claims

1. A balanced amplifier circuit, comprising: A first conversion circuit is configured to output a first first signal, a first second signal, a second first signal, and a second second signal based on an input signal having an input impedance, wherein the first first signal and the second first signal have a 90-degree phase difference, the first second signal and the first first signal have a first differential relationship, and the second second signal and the second first signal have a second differential relationship. The first amplifier circuit is configured as follows: Amplify the first signal to output the first and third signals, and Amplify the first and second signals to output the first and fourth signals; The second amplifier circuit is configured as follows: Amplify the second first signal to output the second and third signals, and Amplify the second signal to output the second fourth signal; and The second conversion circuit is configured to output an output signal with output impedance based on the first third signal, the first fourth signal, the second third signal, and the second fourth signal. Each of the first first signal, the first second signal, the second first signal, and the second second signal has a target input impedance.

2. The balanced amplifier circuit according to claim 1 further includes: An input resistor is coupled between the first conversion circuit and ground; and An output resistor is coupled between the second conversion circuit and the ground.

3. The balanced amplifier circuit according to claim 2, wherein, The first conversion circuit further includes: A first transformer is coupled between the input node to which the input signal is input and the first amplifier circuit; A second transformer is coupled between the input resistor and the second amplifier circuit; A first capacitor is coupled between the input node and the ground; A second capacitor is coupled between a first node and the ground, the first node being between the input resistor and the second transformer; A first inductor is coupled between the input node and the first node; and The third transformer is coupled between the second and fourth nodes, and between the third and fifth nodes. The first signal is output from the second node. The second first signal is output from the fourth node. Wherein, the first and second signals are output from the third node, and The second signal is output from the fifth node.

4. The balanced amplifier circuit according to claim 3, wherein, The second conversion circuit further includes: A fourth transformer is coupled between the first amplifier circuit and the output resistor; The fifth transformer is coupled between the second amplifier circuit and the output node; The sixth transformer is coupled between the sixth and eighth nodes and between the seventh and ninth nodes; The third capacitor is coupled between the tenth node and the ground; A fourth capacitor is coupled between the output node and the ground; and A second inductor is coupled between the tenth node and the output node. The output signal is output from the output node. The first and third signals are output from the sixth node. The first and fourth signals are output from the seventh node. The second and third signals are output from the eighth node. The second and fourth signals are output from the ninth node, and The tenth node is located between the fourth transformer and the output resistor.

5. The balanced amplifier circuit according to claim 4, wherein, The first amplifier circuit also includes: A first amplifier transistor is configured to amplify the first first signal and the first second signal; A first input parasitic capacitor is coupled in parallel with the first amplifier transistor between the second node and the third node; and A first output parasitic capacitor is coupled in parallel with the first amplifier transistor between the sixth node and the seventh node.

6. The balanced amplifier circuit according to claim 4, wherein, The first amplifier circuit also includes: A first amplifier is configured to amplify the first signal; and The second amplifier is configured to amplify the first and second signals.

7. The balanced amplifier circuit according to claim 6, wherein, The first conversion circuit further includes: A first equivalent capacitor is coupled between the second node and the third node; and A second equivalent capacitor is coupled between the fourth node and the fifth node.

8. The balanced amplifier circuit according to claim 1, further comprising: The third amplifier circuit is coupled to the second conversion circuit. The third amplifier circuit is configured to amplify the signal input to the third amplifier circuit via the additional input node and output an amplified signal. The second conversion circuit is configured to output the output signal based on the first third signal, the first fourth signal, the second third signal, the second fourth signal, and the amplified signal.

9. The balanced amplifier circuit according to claim 2, wherein, Each of the first third signal, the first fourth signal, the second third signal, and the second fourth signal has a target output impedance. The input resistor has an input resistance value corresponding to half of the target input impedance, and The output resistor has an output resistance value corresponding to half of the target output impedance.

10. An electronic device, comprising: A balanced amplifier circuit is configured to amplify an input signal with input impedance and output an output signal with output impedance. and The processor is configured to control the balanced amplifier circuit. The balanced amplifier circuit includes: A first conversion circuit is configured to output a first first signal, a first second signal, a second first signal, and a second second signal based on the input signal provided by the processor, wherein the first first signal and the second first signal have a 90-degree phase difference, the first second signal and the first first signal have a first differential relationship, and the second second signal and the second first signal have a second differential relationship. A first amplifier circuit is configured to amplify the first first signal to output a first third signal, and to amplify the first second signal to output a first fourth signal; A second amplifier circuit is configured to amplify the second first signal to output a second third signal, and to amplify the second second signal to output a second fourth signal; and The second conversion circuit is configured to output the output signal via an output node based on the first third signal, the first fourth signal, the second third signal, and the second fourth signal. Each of the first first signal, the first second signal, the second first signal, and the second second signal has a target input impedance.

11. The electronic device according to claim 10, wherein, The balanced amplifier circuit also includes: An input resistor is coupled between the first conversion circuit and ground; and The third amplifier circuit is coupled to the second conversion circuit.

12. The electronic device according to claim 11, wherein, The processor is configured to: input a first portion of the input signal to the input node based on a first power consumption at the input node being less than a first threshold, and input a second portion of the input signal to the third amplifier circuit. The balanced amplifier circuit is configured to input the input signal at the input node, and The second part of the input signal differs from the first part of the input signal in at least one aspect, either phase or amplitude.

13. The electronic device according to claim 12, wherein, The processor is configured to input the first portion of the input signal to the input node and the second portion of the input signal to the third amplifier circuit based on the second power consumption consumed at the output node being less than a second threshold.

14. The electronic device according to claim 12, wherein, The first conversion circuit further includes: A first transformer is coupled between the input node and the first amplifier circuit; A second transformer is coupled between the input resistor and the second amplifier circuit; A first capacitor is coupled between the input node and the ground; A second capacitor is coupled between the first node and the ground; A first inductor is coupled between the input node and the first node; and The third transformer is coupled between the second and fourth nodes, and between the third and fifth nodes. The first node is located between the input resistor and the second transformer. The first signal is output from the second node. The first and second signals are output from the third node. Wherein, the second first signal is output from the fourth node, and The second signal is output from the fifth node.

15. The electronic device according to claim 14, wherein, The second conversion circuit further includes: A fourth transformer is coupled between the first amplifier circuit and the third amplifier circuit; The fifth transformer is coupled between the second amplifier circuit and the output node; The sixth transformer is coupled between the sixth and eighth nodes and between the seventh and ninth nodes; The third capacitor is coupled between the tenth node and the ground; A fourth capacitor is coupled between the output node and the ground; and A second inductor is coupled between the tenth node and the output node. The output signal is output from the output node. The first and third signals are output from the sixth node. The first and fourth signals are output from the seventh node. The second and third signals are output from the eighth node. The second and fourth signals are output from the ninth node, and The tenth node is located between the fourth transformer and the output resistor.

16. The electronic device according to claim 15, wherein, The first amplifier circuit also includes: First amplifier transistor; A first input parasitic capacitor is coupled in parallel with the first amplifier transistor between the second node and the third node; and A first output parasitic capacitor is coupled in parallel with the first amplifier transistor between the sixth node and the seventh node.

17. The electronic device of claim 10, further comprising: The antenna is configured to transmit a radio frequency (RF) signal of a predetermined frequency band based on the output signal output by the balanced amplifier circuit.

18. A conversion circuit for outputting multiple output signals based on an input signal having an input impedance, comprising: A first capacitor is coupled between an input node configured to receive the input signal and ground; A first inductor is coupled between the input node and the first node; A first transformer is coupled between the input node and the second node, and between the input node and the third node; The second transformer is coupled between the first node and the fourth node, and between the first node and the fifth node; A third transformer is coupled between the second node and the fourth node, and between the third node and the fifth node; and A second capacitor is coupled between the first node and the ground. Each of the plurality of output signals has a target input impedance and a 90-degree phase difference relative to each other. Among the plurality of output signals, the first output signal is output from the second node. Among the plurality of output signals, the first and second output signals are output from the third node. Among the plurality of output signals, the second first output signal is output from the fourth node. Among the plurality of output signals, the second output signal is output from the fifth node. Wherein, the first and second output signals have a first differential relationship with the first and first output signals, and The second first output signal and the second second output signal have a second differential relationship.

19. The conversion circuit according to claim 18, further comprising: A first equivalent capacitor is coupled between the second node and the third node; and A second equivalent capacitor is coupled between the fourth node and the fifth node.

20. The conversion circuit according to claim 18, further comprising: An input resistor is coupled between the first node and the ground. The input resistor has a resistance value corresponding to half of the target input impedance.

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