High-power multi-channel digital power amplifier and frequency resonance suppression method thereof

Abstract

The present application relates to the field of digital audio power amplifier, discloses a high-power multi-channel digital power amplifier and its frequency resonance suppression method, including power management, network communication, digital signal processing, multi-channel power amplifier and intelligent control unit;Intelligent control unit calculates initial static impedance by using diagnostic current source;Call prime number sequence to calculate independent initial switching frequency reference value for activated channel, generate pulse width modulation driving signal;Extract the output waveform spectrum, reset the pulse width modulation center frequency when the crosstalk amplitude is out of limit;Calculate transient power determination reverse energy backflow, use energy routing module to temporarily store reverse energy and reuse for power supply of other channels;Digital signal processing unit superimposes ultrasonic pilot frequency to calculate real-time impedance and execute overrun protection;The method sequentially executes frequency allocation, crosstalk fine tuning and energy scheduling based on the above structure. The present application avoids frequency crosstalk and resonance phenomenon, and ensures operation stability.

Description

Technical Field

[0001] This invention relates to the field of digital audio power amplification technology, and in particular to a high-power multi-channel digital power amplifier and a method for suppressing frequency resonance. Background Technology

[0002] High-power multi-channel digital power amplifiers are widely used due to their high conversion efficiency and good integration. However, they have structural stability defects when multiple channels output concurrently. Existing multi-channel power amplifiers use a fixed and unified switching frequency. When multiple channels share a DC bus for synchronous operation, the switching ripples will crosstalk each other, causing frequency resonance and low-frequency beat interference. In severe cases, it can lead to phase-locked loop traction loss and damage to device control timing. At the same time, the speaker, as an inductive load, will generate back electromotive force when playing high dynamic range audio. Traditional power amplifiers lack a reverse energy dispatch mechanism. The bus pumping effect caused by reverse current backflow will directly interfere with the power supply stability of other channels and result in serious energy waste.

[0003] In addition, traditional impedance safety monitoring relies on a single measurement at the moment of power-on or passive disconnection after overload. It cannot continuously detect the dynamic impedance drift of the speaker without interfering with the audio output. This lagging protection mechanism with blind spots cannot cope with sudden load changes or poor contact that may occur at any time during operation, and it is difficult to ensure the long-term stable operation of the equipment under complex high-load conditions. Summary of the Invention

[0004] The purpose of this invention is to provide a high-power multi-channel digital power amplifier and its frequency resonance suppression method, which solves the problems of inter-channel frequency resonance, power supply fluctuations caused by reverse energy backflow, and dynamic impedance protection lag in existing digital power amplifiers.

[0005] To achieve the above objectives, the present invention provides the following technical solution:

[0006] Firstly, a high-power multi-channel digital power amplifier is provided, including: a power management unit, a network communication unit, a digital signal processing unit, a multi-channel power amplification unit, and an intelligent control unit; the power management unit outputs low-voltage DC power and high-voltage DC power respectively; the network communication unit parses network audio data packets into digital audio bitstreams and transmits them to the digital signal processing unit; the digital signal processing unit outputs pulse width modulation drive signals to the multi-channel power amplification unit;

[0007] The multi-channel power amplifier unit includes multiple switching amplifier topologies corresponding to each power amplifier channel. Each switching amplifier topology includes a power switch and a low-pass filter at the output. The intelligent control unit has an analog-to-digital conversion sampling interface. The intelligent control unit integrates a diagnostic current source and a high-voltage isolation electronic switch controlled by the intelligent control unit. The diagnostic current source is electrically connected to the output of each switching amplifier topology through the high-voltage isolation electronic switch. The analog-to-digital conversion sampling interface of the intelligent control unit is connected to the output of the power switch and the output of the low-pass filter of each switching amplifier topology.

[0008] The aforementioned high-power multi-channel digital power amplifier utilizes the bidirectional connection between the intelligent control unit and each switching amplification topology circuit to detect the physical operating status of each power amplifier channel and adjust the pulse width modulation drive signal.

[0009] Preferably, the intelligent control unit controls the high-voltage isolation electronic switch to turn on, and injects DC test current into the output terminal of each switch amplification topology circuit using a diagnostic current source; the intelligent control unit obtains the static test voltage value through the analog-to-digital conversion sampling interface to calculate the initial static DC impedance of each power amplifier channel; when the initial static DC impedance of all power amplifier channels is between the preset safe short-circuit threshold and the safe open-circuit threshold, the intelligent control unit sends a command to the power management unit to turn on the high-voltage DC output and controls the high-voltage isolation electronic switch to turn off to achieve physical isolation.

[0010] The above structure uses injected DC test current to obtain the initial static DC impedance, and turns on the high voltage DC output when the impedance is within a safe range, thus avoiding hardware damage caused by external load short circuit at the moment of power-on.

[0011] Preferably, the intelligent control unit is configured to obtain the number of power amplifier channels currently in the active state and call the internally stored prime number sequence to calculate an independent initial target switching frequency reference value for each active power amplifier channel. The initial target switching frequency reference value is calculated by adding the product of the system-set base switching frequency, the frequency fine-tuning step size coefficient, and the prime number values ​​selected sequentially from the prime number sequence according to the active power amplifier channel number. The intelligent control unit converts the initial target switching frequency reference value into a digital frequency division control word and sends it to the phase-locked loop circuit configured in the multi-channel power amplifier unit to set the carrier frequency of each switching amplifier topology circuit.

[0012] The above structure avoids harmonic superposition caused by multiple power amplifier channels operating synchronously at the same switching frequency by assigning independent initial target switching frequency reference values ​​to each active power amplifier channel, and suppresses electromagnetic crosstalk and frequency resonance phenomena inside the digital power amplifier.

[0013] Preferably, the digital signal processing unit performs dynamic range compression logic on the digital audio bitstream and calculates the root mean square voltage amplitude of the digital audio data within the time window; when the calculated root mean square voltage amplitude is greater than the preset digital domain limiting threshold, the digital signal processing unit triggers a gain attenuation operation to suppress the output signal level using a dynamic gain coefficient; after performing oversampling interpolation on the processed digital audio bitstream, the digital signal processing unit compares the processed digital audio bitstream with a reference carrier sequence generated by the multi-channel pulse width modulation generator built into the digital signal processing unit on a cycle-by-cycle basis to generate a pulse width modulation drive signal.

[0014] The aforementioned digital signal processing unit triggers gain attenuation operation by monitoring the root mean square voltage amplitude to prevent peak clipping distortion of the output waveform caused by large transient audio signals.

[0015] Preferably, the intelligent control unit acquires the continuous output voltage waveforms of the power switching transistors of each switching amplifier topology circuit through an analog-to-digital conversion sampling interface; the intelligent control unit superimposes a window function on the continuous output voltage waveforms and performs a fast Fourier transform to extract spectrum data; when the crosstalk amplitude extracted at the discrete frequency point corresponding to the current actual operating pulse width modulation center frequency of the adjacent power amplifier channel that is subject to interference in the spectrum data is greater than the preset interference threshold, the intelligent control unit triggers a closed-loop fine-tuning mechanism based on gradient descent logic; the intelligent control unit dynamically determines the adjustment amplitude by using the deviation between the crosstalk amplitude and the interference threshold to calculate and update the pulse width modulation center frequency, and resets the pulse width modulation center frequency of the power amplifier channel that has lost traction by sending a frequency reset command to the phase-locked loop circuit configured in the multi-channel power amplifier unit.

[0016] The aforementioned intelligent control unit extracts the spectral data of the continuous output voltage waveform through fast Fourier transform, and resets the pulse width modulation center frequency through a closed-loop fine-tuning mechanism when the crosstalk amplitude exceeds the limit, thereby eliminating signal coupling interference between adjacent power amplifier channels.

[0017] Preferably, the intelligent control unit acquires the instantaneous output voltage and instantaneous output current of each power amplifier channel at the current moment, and calculates the transient power using a moving average model based on a discrete time window; when the calculated transient power is negative and the duration of the negative state or the accumulated negative energy in the current detection cycle exceeds the preset judgment threshold, the intelligent control unit determines that the power amplifier channel that generates negative power is in a reverse energy feedback state.

[0018] The aforementioned intelligent control unit calculates transient power by combining the output instantaneous voltage and output instantaneous current. By determining the negative state and duration of the transient power, it identifies the reverse energy backflow condition caused by the back electromotive force of the external speaker load.

[0019] Preferably, the multi-channel power amplifier unit has a power distribution branch unit, which integrates a bidirectional switching network. The high-power multi-channel digital power amplifier is also equipped with an energy storage buffer array and an energy routing module. After confirming that a specific power amplifier channel is in a reverse energy feedback state, the intelligent control unit controls the bidirectional switching network to redirect the power supply path of the power amplifier channel in the feedback state to the energy storage buffer array to temporarily store the reverse energy. The intelligent control unit selects candidate power amplifier channels whose transient power is greater than the preset forward power demand setting value, and controls the energy routing module to enter the buck chopper working mode to convert the reverse energy temporarily stored in the energy storage buffer array into a matching DC voltage and inject it into the power supply rail of the candidate power amplifier channel.

[0020] The aforementioned high-power multi-channel digital power amplifier utilizes a bidirectional switching network and energy routing module to transfer the reverse energy of the power amplifier channel in the feedback state to the energy storage buffer array for temporary storage, and converts the temporary energy into DC voltage to inject into the power supply rail of the power amplifier channel with a large forward power demand, thereby improving the system power supply stability and energy utilization.

[0021] Preferably, the digital signal processing unit generates a high-frequency ultrasonic pilot signal with a frequency set outside the range of human hearing, and mixes the high-frequency ultrasonic pilot signal with the input digital audio bitstream by digital addition; the digital signal processing unit uses a digital bandpass filter to separate the voltage amplitude and current amplitude at the high-frequency ultrasonic pilot frequency point from the acquired output voltage and output current, and obtains the real-time load impedance magnitude through division operation; when the real-time load impedance magnitude exceeds the preset impedance safety range, the intelligent control unit controls the digital signal processing unit to perform amplitude limiting and attenuation operation.

[0022] The above structure superimposes the high-frequency ultrasonic pilot signal onto the digital audio bitstream, and uses a digital bandpass filter to separate the voltage amplitude and current amplitude to calculate the real-time load impedance magnitude, thereby realizing dynamic impedance monitoring and over-limit protection during equipment operation.

[0023] Preferably, the multi-channel power amplifier unit is also equipped with a temperature sensor; the intelligent control unit integrates the real-time load impedance modulus of each power amplifier channel, the detected temperature of the power switch tube surface obtained by the temperature sensor, and the current operation protection status flag bit to generate a standard network data packet; the data frame structure of the standard network data packet, from high to low, includes: a fixed frame header, a channel identification field, an impedance data load, a temperature data load, a protection status flag bit field, and a cyclic redundancy check code; the network communication unit sends the standard network data packet to the remote monitoring terminal through the Ethernet physical interface.

[0024] The aforementioned high-power multi-channel digital power amplifier packages impedance, temperature, and protection status flags into standard network data packets and sends them through an Ethernet physical interface, enabling remote communication of the device's underlying operating status parameters.

[0025] Secondly, the present invention also provides a method for suppressing frequency resonance of a high-power multi-channel digital power amplifier, the method comprising the following steps: the intelligent control unit acquires the impedance state of the output terminal of the multi-channel power amplifier unit, and when the impedance state is within a preset safe impedance range, sends a command to the power management unit to enable high-voltage DC output.

[0026] The intelligent control unit obtains the number of active power amplifier channels and calculates the initial target switching frequency reference value in order to set the carrier frequency of each switching amplifier topology circuit.

[0027] The digital signal processing unit compares the digital audio bitstream with the carrier corresponding to the initial target switching frequency reference value to generate a pulse width modulation drive signal, which drives the power switching transistors in each switching amplifier topology to operate.

[0028] The intelligent control unit acquires the continuous output voltage waveforms of each switching amplifier topology circuit and extracts the spectrum data. When the crosstalk amplitude extracted from the spectrum data is greater than the preset interference threshold, the pulse width modulation center frequency of the corresponding power amplifier channel is calculated, updated, and reset.

[0029] The intelligent control unit calculates the transient power of each switching amplifier topology circuit. When the transient power of a specific power amplifier channel is negative and exceeds the preset judgment threshold, it determines that the power amplifier channel is in a reverse energy backflow state and controls the digital signal processing unit to adjust the pulse width modulation drive signal of the power amplifier channel to suppress the reverse energy backflow.

[0030] The digital signal processing unit generates an ultrasonic pilot signal outside the audio band and superimposes it onto the pulse width modulation drive signal. The intelligent control unit calculates the real-time load impedance based on the pilot signal. When the real-time load impedance exceeds the preset impedance safety range or triggers the operation protection condition, it performs a limiting attenuation operation and sends a status data packet through the network communication unit.

[0031] The above method sequentially performs static impedance detection, switching frequency reference value allocation, spectrum crosstalk monitoring, transient power calculation, and ultrasonic pilot impedance monitoring steps to avoid frequency crosstalk and resonance when multiple power amplifier channels are working in parallel, and to suppress the impact of reverse energy backflow on the system, thus ensuring the operational stability of the digital power amplifier under dynamic load conditions.

[0032] In summary, the present invention has at least one of the following beneficial technical effects:

[0033] 1. Before system startup, this invention utilizes an intelligent control unit to control a diagnostic current source to inject DC test current into the output terminals of each switching amplification topology circuit to calculate the initial static DC impedance. During dynamic operation, a high-frequency ultrasonic pilot signal is superimposed by a digital signal processing unit to calculate the real-time load impedance modulus. The above control logic can intercept external physical short-circuit conditions before high-voltage DC power is turned on, and continuously monitor the external impedance status without interfering with the main audio signal output, preventing hardware damage caused by sudden changes in load wiring.

[0034] 2. This invention calculates independent initial target switching frequency reference values ​​for the active power amplifier channels by calling a prime number sequence, and uses Fast Fourier Transform to extract the spectrum data of the continuous output voltage waveform to monitor crosstalk amplitude. When crosstalk exceeds the limit, a closed-loop fine-tuning mechanism is triggered to reset the pulse width modulation center frequency. The above frequency allocation and closed-loop adjustment mechanism avoids harmonic superposition caused by multiple power amplifier channels operating synchronously at a fixed frequency, decouples electromagnetic interference between adjacent channels, and suppresses frequency resonance phenomena inside the device.

[0035] 3. This invention continuously calculates the transient power of each power amplifier channel by using a moving average model based on a discrete time window. After determining that a reverse energy backflow state has occurred, the bidirectional switching network is controlled to redirect the reverse energy to the energy storage buffer array for temporary storage. The energy routing module is then used to convert the temporarily stored energy into DC voltage and inject it into the power supply rail of the candidate power amplifier channel with positive power demand. The above energy scheduling process isolates the impact of the speaker back electromotive force on the main power supply network, realizes the transfer of power between multiple channels and cross-channel multiplexing, and maintains the voltage stability of the underlying power supply node of the system. Attached Figure Description

[0036] Figure 1 This is a schematic diagram of the system architecture of the present invention;

[0037] Figure 2 This is a schematic diagram of the method flow of the present invention;

[0038] Figure 3 This is a flowchart illustrating the specific implementation steps of the initial target switching frequency reference value calculation and carrier frequency setting steps of the present invention;

[0039] Figure 4 This is a flowchart illustrating the specific implementation steps of the spectrum data extraction and frequency traction loss fine-tuning reset steps of the present invention.

[0040] Figure 5 This is a flowchart illustrating the specific implementation steps of the reverse energy reinjection detection and energy routing reuse of the present invention.

[0041] Figure 6 This is a flowchart illustrating the specific implementation steps of the ultrasonic pilot impedance monitoring and thermal protection early warning system of the present invention.

[0042] Figure 7 This is a comparison diagram of the FFT spectrum of the high-frequency residual signal at the power amplifier output terminal of the present invention.

[0043] Among them, 10 is the power management unit; 20 is the network communication unit; 30 is the digital signal processing unit; 40 is the multi-channel power amplification unit; and 50 is the intelligent control unit. Detailed Implementation

[0044] The following is in conjunction with the appendix Figure 1 - Appendix Figure 7 The present invention will be further described in detail below.

[0045] See attached document Figure 1 The present invention provides a high-power multi-channel digital power amplifier, which may include: a power management unit 10, a network communication unit 20, a digital signal processing unit 30, a multi-channel power amplification unit 40, and an intelligent control unit 50.

[0046] The input terminal of the power management unit 10 is connected to the external AC power grid. The power management unit 10 integrates an active power factor correction circuit and a switching power supply. The power management unit 10 is equipped with two DC bus output terminals, which provide low-voltage DC power with a voltage range of 3.3V to 12V to the control logic unit and high-voltage DC power with a voltage range of 100V to 400V to the multi-channel power amplifier unit 40.

[0047] The network communication unit 20 includes an Ethernet physical interface and a network protocol processor. The network communication unit 20 supports network audio stream protocols and network control protocols. The data output end of the network communication unit 20 is connected to the digital signal processing unit 30 through an audio data bus, and is used to parse the received network audio data packets into digital audio bitstreams and transmit them to the digital signal processing unit 30.

[0048] The input terminal of the digital signal processing unit 30 receives the digital audio bitstream. The digital signal processing unit 30 is built based on a digital signal processor. The output terminal of the digital signal processing unit 30 is connected to a multi-channel pulse width modulation generator. The multi-channel pulse width modulation generator is electrically connected to the input terminal of the multi-channel power amplifier unit 40 and is used to output pulse width modulation drive signals to the multi-channel power amplifier unit 40.

[0049] The multi-channel power amplifier unit 40 includes multiple independent switching amplifier topologies. Each switching amplifier topology includes a power switch and a low-pass filter at the output. The output of each switching amplifier topology is connected to an external speaker load. Each switching amplifier topology in the multi-channel power amplifier unit 40 shares the high-voltage DC power output from the power management unit 10 through a controlled power distribution branch unit. The power distribution branch unit integrates an electronic switch switching array, which is used to physically and independently connect, disconnect, or redirect the high-voltage power supply path of a specific power amplifier channel according to the instructions of the intelligent control unit 50.

[0050] The intelligent control unit 50 is built on a microcontroller and has an analog-to-digital conversion sampling interface and a communication bus. The intelligent control unit 50 also integrates a diagnostic current source and a high-voltage isolation electronic switch controlled by the intelligent control unit 50. The diagnostic current source is electrically connected to the output terminal of each switching amplification topology circuit in the multi-channel power amplifier unit 40 through the high-voltage isolation electronic switch for offline impedance diagnosis. The analog-to-digital conversion sampling interface of the intelligent control unit 50 is connected to the power switch output terminal and the low-pass filter output terminal of each switching amplification topology circuit in the multi-channel power amplifier unit 40, respectively, for acquiring the high-frequency carrier drive signal waveform of the switching node of the power switch, the output voltage waveform and the output current waveform of the low-pass filter. The communication bus of the intelligent control unit 50 is connected to the digital signal processing unit 30, the multi-channel power amplifier unit 40 and the power management unit 10, respectively, for transmitting control commands.

[0051] See attached document Figure 2 This invention provides a method for suppressing frequency resonance in high-power multi-channel digital power amplifiers, the method comprising the following steps:

[0052] S10, the intelligent control unit 50 controls the power management unit 10 to establish a low-voltage control power supply. The digital signal processing unit 30 and the network communication unit 20 receive the low-voltage control power supply and complete the register configuration. The intelligent control unit 50 obtains the impedance status of the output terminal of the multi-channel power amplifier unit 40 through the analog-to-digital conversion sampling interface. When the impedance status is within the safe impedance range of 1.5Ω to 40Ω, the intelligent control unit 50 sends a command to the power management unit 10 to turn on the high-voltage DC power output.

[0053] S20, the network communication unit 20 receives the input audio signal, the intelligent control unit 50 obtains the number of power amplifier channels in the current active state and calculates the initial target switching frequency reference value that conforms to the prime number distribution law, and the intelligent control unit 50 sends the initial target switching frequency reference value to the phase-locked loop circuit in the multi-channel power amplifier unit 40 through the communication bus to set the carrier frequency of each switching amplifier topology circuit.

[0054] S30, the digital signal processing unit 30 performs parametric equalization, dynamic range compression and frequency division processing on the digital audio bitstream, compares the processed digital audio bitstream with the carrier corresponding to the initial target switching frequency reference value to generate a pulse width modulation waveform, and drives the power switching transistor in the multi-channel power amplifier unit 40 to operate and is demodulated and output through a low-pass filter.

[0055] S40, the intelligent control unit 50 obtains the continuous output voltage waveforms of the power switch output terminals of each switching amplification topology circuit in the multi-channel power amplifier unit 40, i.e. the front-end switching nodes of the low-pass filter, through the analog-to-digital conversion sampling interface, and performs fast Fourier transform to extract spectrum data. When the amplitude at the frequency difference between the two channels in the spectrum data exceeds the interference threshold, the intelligent control unit 50 calculates the frequency fine-tuning step size and resets the pulse width modulation center frequency of the corresponding channel.

[0056] S50, the intelligent control unit 50 calculates the product and phase difference of the instantaneous output voltage and instantaneous output current of each switching amplification topology circuit in the multi-channel power amplification unit 40. When the product is negative and the phase difference exceeds the set range, the intelligent control unit 50 controls the bidirectional switching network to introduce the reverse current into the energy storage buffer array, and controls the energy routing module to inject the electrical energy in the energy storage buffer array into the power supply rail of the switching amplification topology circuit with a forward power greater than the set value.

[0057] S60, the digital signal processing unit 30 generates an ultrasonic pilot signal outside the audio band and superimposes it onto the pulse width modulation waveform. The intelligent control unit 50 calculates the real-time load impedance based on the voltage and current values ​​of the acquired ultrasonic pilot signal. When the real-time load impedance exceeds the safe impedance range or the system temperature reaches the temperature threshold, the intelligent control unit 50 controls the digital signal processing unit 30 to perform a limiting attenuation operation and sends a status data packet through the network communication unit 20.

[0058] In specific implementations, step S10 provided by the present invention may include the following steps:

[0059] S101, after the system is connected to the external AC power grid, the intelligent control unit 50 is in the auxiliary power supply wake-up state and sends a low-voltage enable level signal to the power management unit 10. The auxiliary step-down circuit inside the power management unit 10 receives the low-voltage enable level signal and starts the low-voltage DC power output. In a practical design architecture, the low-voltage DC power is configured as the core voltage for digital logic operations and the driving voltage for peripheral analog interfaces. The power management unit 10 distributes the low-voltage DC power from 3.3V to 12V to the power input terminals of the digital signal processing unit 30 and the network communication unit 20.

[0060] S102, after the digital signal processing unit 30 and the network communication unit 20 establish basic power supply, they perform initialization and reset operations. The digital signal processing unit 30 reads the boot program stored in its internal non-volatile memory, loads the initial state of each control register, and controls the multi-channel pulse width modulation generator pin at the output of the digital signal processing unit 30 to remain at a low level, cutting off the drive signal to the power switching transistor in the multi-channel power amplifier unit 40. In the actual circuit, this control mechanism can prevent uncontrolled pulse width modulation disorder pulses from causing the subsequent switching transistor to shoot-through short circuit before the high-voltage bus of the system is established. The network communication unit 20 synchronously starts the hardware protocol stack, initializes the Ethernet physical layer link, and enters the network audio stream listening state. The specific operations of addressing the underlying registers and reading and writing initial data are performed according to the existing microcontroller serial communication bus methods.

[0061] S103, the intelligent control unit 50 first detects the residual voltage of each channel output terminal or high-voltage bus through the analog-to-digital conversion sampling interface. When it is confirmed that the residual voltage is lower than the set safe voltage threshold of 5V to 12V, it controls the internal diagnostic current source to inject DC test current into the output terminal of each switching amplification topology circuit of the multi-channel power amplifier unit 40. The injected DC test current value of the diagnostic current source is set to 1mA to 10mA. The diagnostic current source is connected to the output terminal through a high-voltage isolation electronic switch.

[0062] Before performing impedance detection, the intelligent control unit 50 controls the high-voltage isolation electronic switch to be turned on; before determining that the impedance is normal and preparing to turn on the high-voltage DC output, it first controls the high-voltage isolation electronic switch to be turned off, so as to physically isolate the diagnostic current source from the high-power output circuit and prevent the high-voltage bus voltage from flowing back into the intelligent control unit 50. The intelligent control unit 50 calculates the initial static DC impedance of the external speaker load of the multi-channel power amplifier unit 40 based on the collected voltage and current parameters. The calculation model of the static DC impedance is as follows:

[0063] ;

[0064] In the formula, For the first The initial static DC impedance of the power amplifier channel; For the analog-to-digital conversion sampling interface in the first The static test voltage values ​​obtained from each power amplifier channel; To diagnose the current source to the first The DC test current value injected into each power amplifier channel; This is the channel number for the power amplifier.

[0065] The intelligent control unit 50 compares the calculated initial static DC impedance with the system-set safe short-circuit threshold and safe open-circuit threshold. The safe short-circuit threshold is set according to the minimum nominal impedance of the adapted speaker and can be 0.5Ω to 1.5Ω. The safe open-circuit threshold is set according to the maximum equivalent DC resistance of the speaker voice coil and cable and can be 50Ω to 100Ω. When the initial static DC impedance of any channel is less than the safe short-circuit threshold or greater than the safe open-circuit threshold, the intelligent control unit 50 determines that there is a short-circuit or open-circuit fault in the external speaker load or physical wiring. At this time, the intelligent control unit 50 restricts the high-voltage control interface of the power management unit 10 to close, maintains the zero-voltage isolation state of the multi-channel power amplifier unit 40, and sends an alarm data packet containing the fault channel number to the peripheral control device through the network communication unit 20.

[0066] S104, when the initial static DC impedance of all power amplifier channels is between the safe short-circuit threshold and the safe open-circuit threshold, the intelligent control unit 50 determines that the external physical connection is normal. The intelligent control unit 50 sends a high-voltage DC output command to the power management unit 10, triggering the soft-start control of the high-voltage DC bus. A large-capacity energy storage capacitor directly connected to the AC rectifier output in a fully discharged state will generate a high surge current. Therefore, it is necessary to limit the initial charging current to protect the upstream power grid and the rectifier bridge within the system. The power management unit 10 closes its internal pre-charge relay. After passing through the active power factor correction circuit, the AC grid power is connected to the high-voltage DC bus terminal via a series current-limiting resistor. The energy storage capacitor array is charged with constant current. The intelligent control unit 50 monitors the bus voltage across the energy storage capacitor array. When the bus voltage rises and reaches the preset safety ratio of the rated operating voltage, the intelligent control unit 50 controls the main power bypass relay to close, shorting the current limiting resistor. The preset safety ratio can be set to 85% to 95% of the rated operating voltage according to the capacitor charging and discharging time constant, to ensure that cutting off the current limiting resistor in the 85% to 95% range will not cause a destructive current step in the main circuit. Subsequently, the energy storage capacitor array is directly connected to the rectifier bus, and the multi-channel power amplifier unit 40 obtains full high-voltage DC power supply. The high-power multi-channel digital power amplifier system enters the audio amplification standby state.

[0067] See attached document Figure 3 In specific implementations, step S20 provided by the present invention may include the following steps:

[0068] S201, the network communication unit 20 receives the input audio signal and transmits it to the system. The intelligent control unit 50 monitors the audio signal input level of each power amplifier channel in real time. When the input signal level of a certain power amplifier channel is detected to be greater than the preset mute threshold, the intelligent control unit 50 determines that the power amplifier channel in the signal input state is in the active state. The mute threshold is set to a range of -80dBFS to -100dBFS. The intelligent control unit 50 counts the total number of power amplifier channels in the active state and sequentially numbers these active power amplifier channels. During this process, the mute threshold is set according to the system hardware noise floor level to filter background random noise when there is no effective audio input and prevent non-signal channels from participating in frequency resource allocation.

[0069] S202, the intelligent control unit 50, based on the number of active power amplifier channels, calls the internally stored prime number sequence to calculate an independent initial target switching frequency reference value for each active power amplifier channel. In a conventional multi-channel digital power amplifier architecture, if the pulse width modulation switching frequencies of each channel are exactly the same or differ very little, the switching ripples of each channel will crosstalk due to the shared DC bus and grounding network, resulting in low-frequency beat frequency interference. To avoid this phenomenon, the mathematical model for prime number distribution frequency allocation is set as follows:

[0070] ;

[0071] In the formula, To be assigned to the The initial target switching frequency reference value for each activated power amplifier channel; The base switching frequency set for the system; This is the frequency fine-tuning step size coefficient; For the set of prime number sequences, sorted by channel number Selected in sequence A prime number value; To activate the power amplifier channel number.

[0072] The base switching frequency is determined by combining the switching loss tolerance of the internal power switching transistors of the multi-channel power amplifier unit 40 with the cutoff frequency of the output low-pass filter, and is set in the range of 300kHz to 500kHz. The frequency fine-tuning step size coefficient is set according to the hearing masking characteristics of the human ear and the frequency resolution of the phase-locked loop circuit, and the value range is set to 500Hz to 1000Hz. The upper boundary of the product of the frequency fine-tuning step size coefficient and the prime number sequence is set to 10% to 15% of the base switching frequency. This is limited by the thermal balance constraints of the power switching transistors of each channel and the in-band group delay consistency boundary of the output low-pass filter to ensure that the switching loss and signal phase shift of the high-frequency off-channel are within a safe and controllable range.

[0073] S203, the intelligent control unit 50 completes the frequency reference allocation of each channel based on the above prime number allocation algorithm. According to the mathematical property that prime numbers can only be divided by 1 and themselves, the above algorithm makes it difficult for the difference between the initial target switching frequency reference values ​​of any two activated power amplifier channels and the harmonic frequencies generated by the switching action to form a simple integer multiple relationship. This frequency staggered configuration method causes the difference frequency component generated by parasitic parameter coupling between different power amplifier channels to be frequency shifted, guiding it to outside the range of human hearing frequency band, or falling into the stopband attenuation frequency range of the low-pass filter at the output end, thereby reducing the probability of cross-frequency resonance when multiple channels output high power concurrently in physical implementation.

[0074] S204, the intelligent control unit 50 converts the calculated initial target switching frequency reference values ​​into corresponding digital frequency division control words. In a specific embodiment, the intelligent control unit 50 sends these digital frequency division control words to the phase-locked loop circuit register in the multi-channel power amplifier unit 40 through the internal communication bus.

[0075] The multi-channel power amplifier unit 40 contains multiple independent phase-locked loop (PLL) modules. Each PLL module receives the corresponding digital frequency division control word and smoothly adjusts the output frequency of the internal voltage-controlled oscillator based on a preset frequency change slope. It independently sets and locks the pulse width modulation carrier frequency of the corresponding switching amplifier topology circuit. Through progressive frequency division adjustment, it avoids carrier phase tearing caused by frequency abrupt changes and the resulting audible out-of-band noise interference. The mapping addressing of the data frame encapsulation format of the communication bus and the address of the PLL register is based on existing microcontroller digital control and communication methods.

[0076] In specific implementations, step S30 provided by the present invention may include the following steps:

[0077] S301, after receiving the digital audio bitstream, the digital signal processing unit 30 performs multi-band parametric equalization processing. In a specific embodiment, the digital signal processing unit 30 uses a cascaded dual second-order infinite impulse response filter to adjust the frequency domain amplitude response of the digital audio bitstream. This type of digital filter can achieve precise gain control of a specific audio frequency band by performing discrete convolution operations on the input signal and historical states. The time-domain difference calculation model of a single dual second-order infinite impulse response filter is as follows:

[0078] ;

[0079] In the formula, The output digital audio data for the current sampling point; These are the first feedforward filter coefficients of the dual second-order infinite impulse response filter; This refers to the original input digital audio data at the current sampling point; These are the second feedforward filter coefficients of the dual second-order infinite impulse response filter; The original input digital audio data from the previous sampling period; For the third feedforward filter coefficient of the dual second-order infinite impulse response filter; This refers to the raw input digital audio data from the first two sampling cycles; These are the first feedback filter coefficients of the dual second-order infinite impulse response filter; This is the output digital audio data of the previous sampling period; These are the second feedback filter coefficients of the dual second-order infinite impulse response filter; This is the output digital audio data for the first two sampling cycles; This is the index of the current discrete sampling point in the time domain.

[0080] In practical applications, the feedforward filter coefficients and feedback filter coefficients are jointly calculated and determined by the target center frequency, quality factor, and frequency band gain. Specifically, the set analog filter transfer function can be discretized and mapped to the digital domain using the bilinear transformation method to obtain the corresponding coefficient values. The digital signal processing unit 30 executes the above time-domain difference equation through its internal hardware multiply-accumulate arithmetic unit to achieve amplitude enhancement or attenuation of signals in a specific audio frequency band.

[0081] S302, the digital signal processing unit 30 performs dynamic range compression logic on the digital audio data after parametric equalization. To prevent transient large signal overload from burning out the downstream speaker equipment, the digital signal processing unit 30 calculates the root mean square voltage amplitude of the audio data in real time within a time window of 10ms to 50ms. The calculated root mean square value can more accurately reflect the true acoustic energy density of the audio signal and avoid false triggering of amplitude limiting for occasional harmless narrow pulses. The calculation model of the root mean square voltage amplitude is as follows:

[0082] ;

[0083] In the formula, The root mean square voltage amplitude calculated at the current moment; This represents the total number of discrete sampling points contained within the time window. The variable is accumulated cyclically for discrete sampling points within the time window; For the first time window The digital audio voltage amplitude corresponding to each discrete sampling point, specifically refers to the digital audio data after parametric equalization processing; This is the index of the current discrete sampling point in the time domain.

[0084] The length of the time window is determined based on the lower limit of the low-frequency response set by the system to ensure accurate extraction of the envelope of long-period audio signals.

[0085] The digital signal processing unit 30 compares the calculated root mean square voltage amplitude with a preset limiting threshold. The limiting threshold is set according to the upper limit of the rated output power of the multi-channel power amplifier unit 40 or the upper limit of the allowable long-term heat dissipation power of the external speaker load. The digital signal processing unit 30 stores a mapping conversion coefficient established based on the system hardware amplification gain in advance, and uses the mapping conversion coefficient to convert the preset 40V to 150V physical voltage limiting threshold into the corresponding digital domain full-scale reference value.

[0086] When the calculated root mean square voltage amplitude is greater than the digital domain limiting threshold after conversion, the digital signal processing unit 30 triggers a gain attenuation operation and multiplies the dynamic gain coefficient with the current digital audio data to suppress the output signal level within a safe range. When the root mean square voltage amplitude falls back below the limiting threshold, the digital signal processing unit 30 gradually restores the dynamic gain coefficient to a constant of 1 according to the set release time constant, thereby ensuring the continuity of the audio dynamic envelope and avoiding abrupt changes in sound.

[0087] In step S303, the digital signal processing unit 30 converts the digital audio bitstream after dynamic range compression into a pulse width modulation waveform. Since the sampling rate of the input digital audio bitstream is much lower than the set pulse width modulation carrier frequency, before performing the comparison conversion, the digital signal processing unit 30 performs oversampling interpolation processing on the digital audio bitstream through an internal multi-stage half-band filter or a cascaded integrator comb filter to improve the time domain resolution of the signal and suppress aliasing image spectrum. Subsequently, the digital signal processing unit 30 uses an internal multi-channel pulse width modulation generator to generate a reference carrier sequence. The center frequency of the reference carrier sequence is controlled by the initial target switching frequency reference value issued in step S20. In the digital domain mapping conversion logic, the reference carrier sequence is represented as a high-frequency digital triangular wave or sawtooth wave. The digital signal processing unit 30 performs a cycle-by-cycle numerical comparison between the instantaneous amplitude of the oversampled digital audio bitstream and the instantaneous amplitude of the reference carrier sequence.

[0088] When the instantaneous amplitude of the digital audio bitstream is greater than the instantaneous amplitude of the reference carrier sequence, the corresponding pin of the pulse width modulation generator outputs a high-level state; when the instantaneous amplitude of the digital audio bitstream is less than or equal to the instantaneous amplitude of the reference carrier sequence, the corresponding pin of the pulse width modulation generator outputs a low-level state. This numerical comparison process converts the digital audio bitstream carrying continuous waveform information into a high-frequency pulse width modulation waveform with different duty cycles.

[0089] S304, the multi-channel power amplifier unit 40 receives the pulse width modulation waveform. The multi-channel power amplifier unit 40 contains power switching transistors with a half-bridge or full-bridge topology. To prevent common-mode conduction short circuits when the upper and lower power switching transistors of the same bridge arm alternate in state, the gate drive circuit of the multi-channel power amplifier unit 40 forcibly inserts a dead time of 50ns to 200ns between the high and low level transition edges of the complementary drive signal. After the dead time control, the gate drive circuit controls the power switching transistors to switch rapidly between the conduction and cutoff regions according to the high and low level transition states of the pulse width modulation waveform. This controls the high voltage DC current to form an amplified high-frequency pulse voltage sequence. The high-frequency pulse voltage sequence is input to the low-pass filter at the output of the multi-channel power amplifier unit 40. The low-pass filter blocks and filters out the high-frequency switching carrier component, demodulates the pulse width modulation waveform to restore it to an amplified analog audio signal, and transmits it to the external speaker load for sound generation.

[0090] See attached document Figure 4 In specific implementations, step S40 provided by the present invention may include the following steps:

[0091] S401, the intelligent control unit 50 acquires the continuous output voltage waveforms of each switching amplification topology circuit in the multi-channel power amplifier unit 40 located at the power switch output terminal through the analog-to-digital conversion sampling interface at a preset sampling frequency. The analog-to-digital conversion sampling interface is internally configured with multiple independent sampling channels or a switchable signal conditioning network. Among them, the sampling channel used for frequency resonance suppression is equipped with a high-gain active high-frequency bandpass filter in the pre-stage, which is used to selectively isolate and amplify the resonance crosstalk component in the high-frequency carrier drive signal of the switching node to ensure that the crosstalk amplitude can be effectively extracted from the spectrum data. The sampling channel used for energy reinjection detection and online impedance monitoring is equipped with full-band voltage divider and current shunt sampling circuits to introduce complete full-band voltage and current signals.

[0092] The dedicated hardware mathematical accelerator integrated within the intelligent control unit 50 superimposes a window function onto the discrete sampling points of the acquired output voltage to suppress spectral leakage caused by non-integer period truncation. In a specific embodiment, a Hanning window or a flat-top window is used to ensure the measurement accuracy of the interference frequency amplitude. Subsequently, the intelligent control unit 50 uses the dedicated hardware mathematical accelerator to perform a fast Fourier transform on the windowed data to extract the frequency domain data. The mathematical operation process of the windowed fast Fourier transform is as follows:

[0093] ;

[0094] In the formula, The first of the 40 multi-channel power amplifier units Each power amplifier channel at discrete frequency points Complex spectral data at the location; Number the power amplifier channels; For discrete frequency points in the frequency domain; This is the cyclically accumulated variable for the discrete sampling points in the time domain of the Fast Fourier Transform. This represents the number of processing points for the Fast Fourier Transform. For the first Each power amplifier channel at discrete sampling points in the time domain The output voltage discrete sampling point values ​​at the location; The window function is set at discrete sampling points in the time domain. The weight value at the location; It is the imaginary unit.

[0095] In practical engineering implementation, the sampling frequency of the analog-to-digital conversion sampling interface is set according to the Nyquist sampling theorem and must be greater than twice the highest switching frequency of the system. The number of processing points for the fast Fourier transform is determined according to the required frequency resolution. In order to balance the system's computing resources and the accuracy of difference frequency extraction, the number of processing points is configured to be 1024 or 2048.

[0096] S402, after acquiring the spectrum data of each channel, the intelligent control unit 50 maps the current actual operating pulse width modulation center frequency of the neighboring power amplifier channel that is causing the interference to the corresponding discrete frequency index. This is to accurately extract the high-frequency crosstalk component coupled from the neighboring channel from the high-frequency carrier residual signal of the current channel. The lookup and location model of the discrete frequency index is as follows:

[0097] ;

[0098] In the formula, The discrete frequency index corresponding to the center frequency of the adjacent power amplifier channel that is causing the interference; The pulse width modulation center frequency currently in operation of the adjacent power amplifier channel that is causing the interference; The sampling frequency of the analog-to-digital conversion sampling interface; This represents the number of processing points for the Fast Fourier Transform. The neighboring power amplifier channel that is causing the interference is numbered. Based on the calculated discrete frequency index, the intelligent control unit 50 extracts the crosstalk amplitude at that specific frequency point from the spectrum data of the target power amplifier channel being compared.

[0099] S403, the intelligent control unit 50 compares the extracted crosstalk amplitude with the preset interference threshold. The interference threshold is set according to the signal-to-noise ratio requirements of the audio system, and the value is between -60dB and -80dB of the fundamental amplitude. When the crosstalk amplitude is greater than the interference threshold, the intelligent control unit 50 determines that the corresponding channel has a frequency pull-out state and triggers a closed-loop fine-tuning mechanism based on gradient descent logic. When multiple power amplifier channels operate under high load for a long time and the DC bus voltage fluctuates, the phase-locked loop of some channels will experience frequency drift, causing the originally staggered switching frequencies to approach each other, generating a frequency pull phenomenon, which in turn causes resonance.

[0100] The intelligent control unit 50 calculates the target frequency fine-tuning step size for the traction loss-lock channel, and the closed-loop feedback mathematical formula is as follows:

[0101] ;

[0102] In the formula, For the calculated first The update pulse width modulation center frequency of each power amplifier channel in the next adjustment cycle; The index is used to mark the iteration for the next adjustment cycle; For the first The pulse width modulation center frequency of each power amplifier channel in the current adjustment cycle; This is the iteration index for the current adjustment period; The convergence step size gain coefficient is set, and the initial value range of the convergence step size gain coefficient is set to 0.01 to 0.1; This represents the actual extracted crosstalk amplitude. The preset interference threshold; The first resonant interference The pulse width modulation center frequency of each power amplifier channel in the current adjustment cycle; The target power amplifier channel number that needs to be adjusted; Number the neighboring power amplifier channel that caused the interference.

[0103] This closed-loop feedback logic dynamically determines the adjustment range by utilizing the deviation between the difference frequency amplitude and the interference threshold. Simultaneously, it uses a sign function to determine the relative position of the two frequencies, controlling the updated center frequency to move away from the interference source. Furthermore, the convergence step size gain coefficient determines the response speed and stability of frequency fine-tuning. To prevent excessive adjustment range from causing frequency overshoot or positive feedback oscillation, the convergence step size gain coefficient is configured as a nonlinear attenuation factor, whose value decreases proportionally with the increase of the closed-loop iteration number, ensuring smooth frequency convergence.

[0104] S404, the intelligent control unit 50 performs a safety boundary constraint detection on the calculated updated pulse width modulation center frequency. The intelligent control unit 50 determines whether the updated pulse width modulation center frequency falls within the set hardware safety operating range, and simultaneously checks whether the frequency overlaps with the frequency band of other operating channels in the system. After passing the constraint detection, the intelligent control unit 50 sends a frequency reset command to the phase-locked loop circuit in the multi-channel power amplifier unit 40 through the communication bus. The phase-locked loop circuit receives the command and updates the division ratio parameter of the internal voltage-controlled oscillator, completing the smooth transition switching of the channel carrier center frequency and eliminating the difference frequency resonance energy from a physical level.

[0105] See attached document Figure 5 In specific implementations, step S50 provided by the present invention may include the following steps:

[0106] S501, the intelligent control unit 50 collects the output voltage and output current of each power amplifier channel in the multi-channel power amplifier unit 40 in real time. The intelligent control unit 50 obtains the instantaneous output voltage and output current of each power amplifier channel at the current moment through its internally integrated dedicated hardware mathematical accelerator, and performs multiplication within a single hardware cycle to obtain the current transient power. From a physical mechanism perspective, when the power amplifier channel drives an inductive speaker load and the audio signal undergoes rapid changes, the change in magnetic flux in the load voice coil will impede the change in current, thereby inducing a reverse induced current, causing electrical energy to flow back from the load end to the source end. In order to filter out the interference of high-frequency switching ripple and avoid noise-induced misjudgment, the transient power calculation adopts a moving average model based on a discrete time window. The specific mathematical conditions are as follows:

[0107] ;

[0108] In the formula, The first of the 40 multi-channel power amplifier units The current transient power of each power amplifier channel; This represents the total number of sampling points within the moving average time window. A variable that is accumulated cyclically with a delay within the moving average time window; For the first Each power amplifier channel at discrete sampling points in the time domain The instantaneous output voltage at the location; For the first Each power amplifier channel at discrete sampling points in the time domain The instantaneous output current at the location; This is the index of the current discrete sampling point in the time domain; This is the channel number for the power amplifier.

[0109] The intelligent control unit 50 determines the sign of the calculated transient power value. When the output instantaneous voltage and output instantaneous current are opposite in direction, resulting in a negative transient power value, and the duration of the negative value state or the accumulated negative energy in the current detection cycle exceeds the set judgment threshold, the intelligent control unit 50 identifies that the power amplifier channel generating negative power is in a reverse energy feedback state. In specific implementation, the judgment threshold is set according to the lowest fundamental period of the audio signal, and the value range is configured to be from 2ms to 10ms to prevent the normal high-frequency transient phase shift component from being misjudged as large energy feedback.

[0110] S502, after confirming that a specific power amplifier channel is in a reverse energy feedback state, the intelligent control unit 50 triggers the bidirectional switching network in the internal hardware architecture of the system. The bidirectional switching network, as the specific implementation of the electronic switch switching array in the power distribution branch unit, is electrically connected between the power supply rail of each switch amplifier topology circuit and the common high-voltage DC bus. It is used to perform topology reconstruction at the power supply level without disconnecting the speaker load. In the specific hardware implementation, the bidirectional switching network adopts a back-to-back series metal oxide semiconductor field-effect transistor structure, and uses its controlled conduction characteristics to realize bidirectional current shutdown and selective conduction.

[0111] The intelligent control unit 50 outputs control timing to control the operation of electronic switches in the power distribution branch unit, redirecting the power supply path of the power amplifier channel in the backfeed state to a high-speed low equivalent series resistance buffer array. During the switching process, the intelligent control unit 50 controls the power switch of the power amplifier channel to briefly enter a safe dead zone high impedance state for a set duration, and performs zero-current soft switching in conjunction with the electronic switch switching array. The energy routing module executes closed-loop voltage compensation logic to suppress transient voltage steps caused by power rail switching, minimizing transient interference to the continuity of the output audio waveform caused by power rail topology switching. The reverse backfeed current generated by the speaker flows back to the corresponding power rail through the reverse body diode of the power switch and is introduced into the buffer array for transient storage through the bidirectional switch network.

[0112] The buffer array is composed of high-frequency thin-film capacitors and supercapacitors connected in parallel. It can absorb transient large current pulses. During the charging process, the intelligent control unit 50 monitors the terminal voltage across the buffer array in real time. When the terminal voltage reaches the set safe withstand voltage overvoltage threshold, the energy storage path of the bidirectional switching network is forcibly cut off to execute the overvoltage protection logic. Excess energy is dissipated through the bleed resistor. The safe withstand voltage overvoltage threshold is set according to the rated withstand voltage of the capacitors in the buffer array. It can be set to 110% to 120% of the rated voltage of the high-voltage DC bus, thereby avoiding capacitor overvoltage breakdown.

[0113] S503, while the buffer array collects and temporarily stores reverse energy, the intelligent control unit 50 simultaneously traverses the remaining active power amplifier channels in the multi-channel power amplifier unit 40. The intelligent control unit 50 extracts data from all power amplifier channels with positive transient power values, determines that these channels are in a positive work state of obtaining power from the power supply, introduces a preset positive power demand setting value, and compares the transient power of each extracted positive work channel with the positive power demand setting value one by one, and filters out candidate power amplifier channels whose current transient power is greater than the positive power demand setting value; wherein, the value range of the positive power demand setting value is configured to be from 50W to 200W. Subsequently, the intelligent control unit 50 determines whether there is a large dynamic work channel in the current system that is greater than the positive power demand setting value, in order to decide whether to trigger the transient current auxiliary supply mechanism of the main power network.

[0114] S504, the intelligent control unit 50 activates the energy routing module in the system based on the power demand determination result. The energy routing module includes a bidirectional DC-DC converter topology circuit. In the specific hardware implementation, the bidirectional DC-DC converter topology circuit adopts a non-isolated bidirectional synchronous buck-boost converter architecture. By adjusting the complementary drive pulse width modulation duty cycle of the internal switching transistors, the bidirectional reversible flow of energy is achieved.

[0115] The intelligent control unit 50 acquires the current terminal voltage of the buffer array and the current voltage value of the common high-voltage DC bus. The intelligent control unit 50 compares the voltage difference between the two and makes a judgment: when the terminal voltage of the buffer array is higher than the set voltage regulation threshold of the common high-voltage DC bus due to the absorption of reverse energy, the intelligent control unit 50 controls the energy routing module to enter the step-down chopper working mode, converts the reverse reinjection energy temporarily stored in the buffer array into a matching DC voltage and injects it into the common high-voltage DC bus, thereby indirectly supplementing the power supply for the forward power channel with high power demand, realizing energy reuse and bus voltage regulation at the system level; when the terminal voltage of the buffer array does not increase due to reinjection and is equal to or lower than the voltage of the common high-voltage DC bus, the energy routing module stops injecting energy into the common high-voltage DC bus and maintains a standby monitoring state.

[0116] If, at a specific moment, the optimization algorithm fails to find a target power amplifier channel with positive power requirements within the system, the intelligent control unit 50 controls the energy routing module to smoothly feed the energy in the buffer array back to the main energy storage capacitor array of the power management unit 10 in a set low-current constant current mode. The current value range of the low-current constant current mode is set to 0.1A to 0.5A. The specific pulse drive and closed-loop voltage regulation feedback of the bidirectional DC-DC converter circuit are based on existing switching power supply control methods.

[0117] See attached document Figure 6To address the risks of abnormal load changes and thermal runaway in high-power multi-channel digital power amplifier systems under long-term high-load operation, step S60 provided by this invention may include the following steps in specific implementation:

[0118] S601, the digital sine wave generator inside the digital signal processing unit 30 generates a high-frequency ultrasonic pilot signal. The frequency of the high-frequency ultrasonic pilot signal is set outside the range of human hearing, specifically 22kHz to 24kHz. The amplitude of the high-frequency ultrasonic pilot signal is controlled at a low level, set to -30dB to -40dB of the full scale, so as to perform background monitoring without occupying the dynamic margin of the main audio signal and without causing signal clipping. Subsequently, the digital signal processing unit 30 uses a digital adder to digitally add and mix the high-frequency ultrasonic pilot signal with the input digital audio bitstream to generate a mixed digital audio bitstream containing the pilot component. This bitstream is then input into the pulse width modulation generation pipeline. By mixing in the digital domain pre-stage, it can be ensured that the pilot signal and the audio signal are synchronously processed by subsequent power amplification, achieving lossless online load detection.

[0119] S602, the mixed digital audio stream, after pulse width modulation and power amplification, drives the external speaker load. During this period, the analog-to-digital conversion sampling interface acquires the instantaneous voltage and instantaneous current at the power amplifier output in real time. The digital signal processing unit 30 uses a digital bandpass filter for a specific pilot frequency. In a specific embodiment, a second-order infinite impulse response bandpass filter with a specific center frequency or a Gossel algorithm filter with high selectivity can be used to separate the voltage amplitude and current amplitude at the high-frequency ultrasonic pilot frequency point from the acquired output voltage and output current. The digital signal processing unit 30 performs a division operation on the voltage amplitude and current amplitude to obtain the real-time load impedance magnitude. To avoid a calculation dead zone when the current amplitude approaches zero due to an open circuit or disconnection of the external load, the impedance calculation logic introduces a conditional segmentation discrimination mechanism. The calculation formula for the real-time load impedance magnitude is as follows:

[0120] ;

[0121] In the formula, The real-time load impedance magnitude obtained for the current calculation cycle; This is the index of the current discrete sampling point in the time domain; The voltage amplitude at the extracted high-frequency ultrasonic pilot frequency point; The current amplitude at the extracted high-frequency ultrasonic pilot frequency point; The preset minimum effective current threshold; Replace the upper limit value with the preset open-circuit impedance.

[0122] In the actual system configuration, the minimum effective current threshold is set according to the system sampling electromagnetic noise floor, and the value is between 1mA and 5mA; the upper limit of the open circuit impedance substitution is set to 100Ω to ensure the stability of the divider operation. After the real-time load impedance modulus is calculated, the digital signal processing unit 30 uploads the real-time load impedance modulus of each channel to the intelligent control unit 50 at regular intervals through the internal serial communication bus.

[0123] S603, the intelligent control unit 50 synchronously reads the detection temperature of the thermistor installed on the surface of the key heat-generating power device in the power amplifier circuit, and synchronously receives the real-time load impedance magnitude value uploaded by the digital signal processing unit 30. The intelligent control unit 50 compares the calculated real-time load impedance magnitude value with the preset impedance safety range, and at the same time compares the detected temperature with the preset temperature alarm threshold and temperature protection threshold. The lower limit of the impedance safety range is set to 1.5Ω to 2Ω, and the upper limit is set to 40Ω to 60Ω; the temperature alarm threshold is set to 85℃ to 95℃, and the temperature protection threshold is set to 105℃ to 115℃, until the detected temperature falls below the temperature alarm threshold minus a hysteresis margin of 5℃ to 10℃, and the impedance abnormality disappears. In order to prevent the system from frequently triggering and releasing the protection intermittent oscillation state due to signal fluctuations at the threshold critical point, a temperature hysteresis loop and an impedance continuous filtering counter are embedded in the control logic.

[0124] When the real-time load impedance magnitude exceeds the impedance safety range, or the detected temperature exceeds the temperature alarm threshold but does not reach the temperature protection threshold, the intelligent control unit 50 sends a linkage control command to the digital signal processing unit 30. The digital signal processing unit 30 reduces the digital gain of the corresponding channel through the internal digital attenuator, gradually attenuating the audio output power in a step manner until the detected temperature stops rising. If the detected temperature continues to rise and exceeds the temperature protection threshold, or the impedance triggers a severe short circuit, the intelligent control unit 50 shuts down the drive output of the pulse width modulation generator, putting the system into a fully protected isolation state. The system is only allowed to smoothly resume output after the detected temperature drops below the temperature alarm threshold minus a hysteresis margin of five to ten degrees Celsius, and the impedance abnormality disappears and is maintained for ten filter cycles. This is used to suppress or prevent control blind spots.

[0125] S604, the intelligent control unit 50 integrates the real-time load impedance modulus of each channel, the detection temperature of the thermistor, and the current operating protection status flag, and encapsulates it according to the data frame format of the network audio management protocol. The above monitoring data is packaged into a standard network data packet. In a preferred embodiment, the data frame structure of the standard network data packet, from high to low, includes: a fixed frame header for synchronous listening and parsing, a channel identifier field for distinguishing physical channels, an impedance data payload for carrying real-time impedance demodulation values, a temperature data payload for carrying temperature acquisition values, a protection status flag field representing the current hardware integrity, and a cyclic redundancy check code for tail verification. Subsequently, the intelligent control unit 50 transmits the standard network data packet to the network communication unit 20. The network communication unit 20 uses the user datagram protocol or transmission control protocol of the network layer to periodically send the standard network data packet to the remote monitoring terminal through the Ethernet physical interface, realizing networked centralized online monitoring and fault early warning. The underlying driver of the network protocol stack, the verification and calculation of data packets, and the transmission operation of the physical layer network link are performed according to existing network communication management methods.

[0126] To aid in understanding the technical solution of this invention, an application example of a distributed battery management system for megawatt-level energy storage power stations is provided below.

[0127] The energy storage system in this embodiment is configured with four independent battery clusters, namely Cluster 1, Cluster 2, Cluster 3 and Cluster 4, which are connected in parallel to a 1500-volt DC bus. Each battery cluster consists of 384 280 Ah lithium iron phosphate cells connected in series. The supporting hardware includes a distributed voltage acquisition module, a Hall current sensor, a surface-mount NTC temperature sensor array, and a bidirectional DC active balancing module with a maximum balancing current set to 5 Amperes. The main control unit embeds a multivariate state estimation algorithm and a thermally coupled balancing control logic program.

[0128] When the system receives an external dynamic frequency modulation command and enters a high-rate charging and discharging alternating state, the system performs dynamic frequency conversion state feature sampling: During the normal constant power charging and discharging stage, the voltage and temperature sampling interface frequency is configured to 1 Hz by default. The main control unit acquires the bus current change rate in real time. When the Hall current sensor measures that the change rate exceeds the set threshold of 50 amps / second, the main control unit triggers the dynamic frequency conversion sampling mechanism, controls the sampling interface frequency to be increased to 50 Hz, and the main control unit extracts the discrete data of terminal voltage and operating current collected at high frequency, substitutes them into the algorithm model to calculate the transient polarization internal resistance change of each individual cell, and combines the ampere-hour integral reference value and internal resistance compensation parameters to output the corrected state of charge estimation value, thereby completing the extraction of the underlying state features.

[0129] After the system has been running at full load for 2 hours, if the temperature sensor array feedback data indicates a temperature distribution difference, the system will execute thermal coupling cross-cluster active equalization control. Assuming the current system state is: the surface temperature of battery module 45 in cluster 2 is 41.2℃ and the terminal voltage is 3.38 volts; the surface temperature of battery module 112 in cluster 3 is 30.4℃ and the terminal voltage is 3.29 volts, the main control unit extracts the current maximum temperature difference of the system as 10.8℃ based on the global temperature matrix and voltage matrix calculation. Since this value is greater than the preset temperature gradient threshold of 8℃, the system determines that the cross-cluster thermal coupling equalization mechanism is triggered.

[0130] During the equalization path establishment and energy transfer phase, the main control unit uses the temperature difference as a weight parameter in the voltage difference calculation through the equalization calculation model. It matches module 45 of cluster 2 as the energy output end and module 112 of cluster 3 as the energy receiving end, and sends control commands to the corresponding bidirectional DC active equalization circuit. The equalization circuit corresponding to module 45 of cluster 2 enters the discharge mode and discharges with a constant current of 4.3 amps. The extracted electrical energy is boosted to the bus voltage by the isolated DC converter and then injected into the charging circuit corresponding to module 112 of cluster 3.

[0131] During the energy transfer process, the internal heat generation power of module 45 in cluster 2 decreases due to the release of electrical energy, while the heat generation of module 112 in cluster 3 increases due to the reception of electrical energy. The main control unit collects the temperature and voltage data of the target modules at a 10-second cycle. When it is determined that the voltage difference between the two ends is less than 15 millivolts and the temperature difference is less than 3°C, the main control unit issues a stop command to disconnect the cross-cluster energy transfer path.

[0132] To verify the technical effect of this embodiment, a battery management system with traditional passive dissipation equalization control was used as a comparison in the same megawatt-level energy storage test chamber environment. The system was tested for 15 consecutive days under the automatic power generation control dynamic frequency regulation condition. The obtained system operation index data are shown in Table 1.

[0133] Table 1: Operational Test Data of Battery Management System for Megawatt-Level Energy Storage Power Station under Different Control Strategies

[0134] Test metrics Traditional passive equilibrium management group (comparative ratio) Active thermal coupling management group (in this embodiment) Maximum differential pressure at the end of the cycle (mV) 142.6 27.4 Maximum temperature difference within the battery cluster (°C) 13.9 4.2 Overall charge-discharge energy conversion efficiency (%) 88.7 95.1 Maximum absolute error (%) in state of charge (SOC) estimation 5.82 1.43 Daily energy consumption of external cooling system (kWh) 47.5 31.2

[0135] Combined with Table 1 Figure 7The technical effects of the embodiments of the present invention can be analyzed as follows: In terms of individual cell voltage difference control and system energy conversion efficiency, the passive balancing strategy of the proportional system relies on resistors to dissipate excess power of high-voltage cells, resulting in unintended power loss. The maximum voltage difference at the end of the cycle reaches 142.6 mV, and the charging and discharging efficiency is only 88.7%. This embodiment is based on a cross-module isolated energy transmission path, which directly injects the power of high-voltage cells into low-voltage cells, avoiding dissipation losses. The data in Table 1 show that the individual cell voltage difference at the end of the cycle in this embodiment converges to 27.4 mV, and the overall energy conversion efficiency of charging and discharging is improved to 95.1%, verifying the substantial improvement of the overall power utilization rate of the active energy routing mechanism.

[0136] Regarding thermodynamic consistency and auxiliary energy consumption of the heat dissipation system, the proportional balance control lacks a temperature state variable, and the passive resistance energy consumption increases the local thermal load, causing the maximum temperature difference of the battery cluster to expand to 13.9℃. This forces the external heat dissipation system to operate at high load for a long time, with an average daily power consumption of 47.5 kWh. In this embodiment, thermal coupling weights are introduced into the balance control, which prioritizes the pumping of high-temperature and high-voltage cells to reduce their heat generation rate and transfers energy to low-temperature regions to supplement heat. Tests show that the maximum temperature difference of the battery cluster in this embodiment is stabilized at 4.2℃, achieving thermal state self-balance at the physical level of the battery array. This reduces the average daily energy consumption of the external heat dissipation system to 31.2 kWh, thereby reducing the auxiliary operating cost of the system.

[0137] Regarding the accuracy of the estimation algorithm data, the comparative example, under transient large dynamic current jump conditions, caused the effective characteristic parameters to be truncated due to the fixed sampling frequency, resulting in an accumulated error in the ampere-hour integral, and the maximum absolute error of the state of charge estimation reached 5.82%. In this embodiment, dynamic frequency conversion sampling is triggered based on the current change rate to obtain complete transient response curve characteristics, and combined with a multivariate state estimation algorithm, the maximum absolute error of the state of charge estimation is limited to 1.43%, improving the reliability and accuracy of the underlying state data output.

[0138] Although embodiments of the invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the appended claims and their equivalents.

Claims

1. A high-power multi-channel digital power amplifier, comprising a power management unit, a network communication unit, a digital signal processing unit, a multi-channel power amplification unit, and an intelligent control unit, characterized in that: The power management unit outputs low-voltage DC power and high-voltage DC power respectively; The network communication unit parses network audio data packets into digital audio streams and transmits them to the digital signal processing unit; The digital signal processing unit outputs a pulse width modulation drive signal to the multi-channel power amplifier unit; The multi-channel power amplifier unit includes multiple switching amplifier topologies corresponding to each power amplifier channel. Each switching amplifier topology includes a power switch transistor and a low-pass filter located at the output terminal. The intelligent control unit has an analog-to-digital conversion sampling interface. The intelligent control unit integrates a diagnostic current source and a high-voltage isolation electronic switch controlled by the intelligent control unit. The diagnostic current source is electrically connected to the output terminal of each switching amplification topology circuit through the high-voltage isolation electronic switch. The analog-to-digital conversion sampling interface of the intelligent control unit is connected to the output terminal of the power switch tube and the output terminal of the low-pass filter of each switching amplification topology circuit.

2. The high-power multi-channel digital power amplifier according to claim 1, characterized in that, The intelligent control unit controls the high-voltage isolation electronic switch to be turned on, and uses the diagnostic current source to inject DC test current into the output terminal of each switch amplification topology circuit. The intelligent control unit obtains the static test voltage value through the analog-to-digital conversion sampling interface to calculate the initial static DC impedance of each power amplifier channel; When the initial static DC impedance of all power amplifier channels is between the preset safe short-circuit threshold and the safe open-circuit threshold, the intelligent control unit sends a command to the power management unit to turn on the high-voltage DC output and controls the high-voltage isolation electronic switch to open to achieve physical isolation.

3. The high-power multi-channel digital power amplifier according to claim 1, characterized in that, The intelligent control unit is configured to obtain the number of power amplifier channels that are currently active, and call the internally stored prime number sequence to calculate an independent initial target switching frequency reference value for each active power amplifier channel. The initial target switching frequency reference value is calculated as follows: the system-set basic switching frequency is added to the product of the frequency fine-tuning step size coefficient and the prime number values ​​selected sequentially from the prime number sequence set according to the activated power amplifier channel number. The intelligent control unit converts the initial target switching frequency reference value into a digital frequency division control word and sends it to the phase-locked loop circuit configured in the multi-channel power amplifier unit to set the carrier frequency of each switching amplifier topology circuit.

4. The high-power multi-channel digital power amplifier according to claim 1, characterized in that, The digital signal processing unit performs dynamic range compression logic on the digital audio bitstream and calculates the root mean square voltage amplitude of the digital audio data within the time window. When the calculated root mean square voltage amplitude is greater than the preset digital domain limiting threshold, the digital signal processing unit triggers a gain attenuation operation to suppress the output signal level using a dynamic gain coefficient. The digital signal processing unit performs oversampling interpolation on the processed digital audio bitstream and then compares it with a reference carrier sequence generated by the multi-channel pulse width modulation generator built into the digital signal processing unit on a cycle-by-cycle basis to generate the pulse width modulation drive signal.

5. The high-power multi-channel digital power amplifier according to claim 1, characterized in that, The intelligent control unit obtains the continuous output voltage waveforms of the power switching transistors of each switching amplifier topology through the analog-to-digital conversion sampling interface. The intelligent control unit superimposes a window function onto the continuous output voltage waveform and performs a fast Fourier transform to extract spectral data; When the crosstalk amplitude extracted at the discrete frequency point corresponding to the current actual operating pulse width modulation center frequency of the adjacent power amplifier channel that is subject to interference in the spectrum data is greater than the preset interference threshold, the intelligent control unit triggers a closed-loop fine-tuning mechanism based on gradient descent logic. The intelligent control unit dynamically determines the adjustment range by using the deviation between the crosstalk amplitude and the interference threshold to calculate and update the pulse width modulation center frequency, and resets the pulse width modulation center frequency of the power amplifier channel in the traction loss state by sending a frequency reset command to the phase-locked loop circuit configured in the multi-channel power amplifier unit.

6. The high-power multi-channel digital power amplifier according to claim 1, characterized in that, The intelligent control unit acquires the instantaneous output voltage and instantaneous output current of each power amplifier channel at the current moment, and calculates the transient power using a moving average model based on a discrete time window. When the calculated transient power is negative and the duration of the negative state or the accumulated negative energy in the current detection cycle exceeds the preset judgment threshold, the intelligent control unit determines that the power amplifier channel that generates negative power is in a reverse energy feedback state.

7. The high-power multi-channel digital power amplifier according to claim 1, characterized in that, The multi-channel power amplifier unit has a power distribution branch unit, which integrates a bidirectional switching network, and the high-power multi-channel digital power amplifier is equipped with an energy storage buffer array and an energy routing module. After confirming that a specific power amplifier channel is in a reverse energy feedback state, the intelligent control unit controls the bidirectional switching network to redirect and switch the power supply path of the power amplifier channel in the feedback state to the energy storage buffer array to temporarily store the reverse energy. The intelligent control unit filters out candidate power amplifier channels whose transient power is greater than the preset forward power demand setting value, and controls the energy routing module to enter the buck chopper working mode to convert the reverse energy temporarily stored in the energy storage buffer array into a matching DC voltage and inject it into the power supply rail of the candidate power amplifier channel.

8. The high-power multi-channel digital power amplifier according to claim 1, characterized in that, The digital signal processing unit generates a high-frequency ultrasonic pilot signal with a frequency set outside the range of human hearing, and mixes the high-frequency ultrasonic pilot signal with the input digital audio bitstream by digital addition. The digital signal processing unit uses a digital bandpass filter to separate the voltage amplitude and current amplitude at the high-frequency ultrasonic pilot frequency point from the acquired output voltage and output current, and obtains the real-time load impedance magnitude through division operation; When the real-time load impedance magnitude exceeds the preset impedance safety range, the intelligent control unit controls the digital signal processing unit to perform a limiting attenuation operation.

9. The high-power multi-channel digital power amplifier according to claim 1, characterized in that, The multi-channel power amplifier unit is also equipped with a temperature sensor; The intelligent control unit integrates the real-time load impedance modulus of each power amplifier channel, the detected temperature of the power switch tube surface obtained by the temperature sensor, and the current operation protection status flag to generate a standard network data packet. The data frame structure of the standard network data packet, from high to low, includes: a fixed frame header, a channel identifier field, an impedance data payload, a temperature data payload, a protection status flag field, and a cyclic redundancy check code. The network communication unit sends the standard network data packets to the remote monitoring terminal via the Ethernet physical interface.

10. A method for suppressing frequency resonance in a high-power multi-channel digital power amplifier, using the high-power multi-channel digital power amplifier described in any one of claims 1 to 9, characterized in that, The method includes the following steps: The intelligent control unit acquires the impedance status of the output terminal of the multi-channel power amplifier unit. When the impedance status is within the preset safe impedance range, it sends a command to the power management unit to enable high-voltage DC output. The intelligent control unit obtains the number of power amplifier channels in the active state and calculates the initial target switching frequency reference value in order to set the carrier frequency of each switching amplification topology circuit. The digital signal processing unit compares the digital audio bitstream with the carrier corresponding to the initial target switching frequency reference value to generate a pulse width modulation drive signal, which drives the power switching transistors in each switching amplifier topology to operate. The intelligent control unit acquires the continuous output voltage waveforms of each switching amplifier topology circuit and extracts the spectrum data. When the crosstalk amplitude extracted from the spectrum data is greater than the preset interference threshold, the pulse width modulation center frequency of the corresponding power amplifier channel is calculated, updated, and reset. The intelligent control unit calculates the transient power of each switching amplifier topology circuit. When the transient power of a specific power amplifier channel is negative and exceeds the preset judgment threshold, it determines that the power amplifier channel is in a reverse energy backflow state and controls the digital signal processing unit to adjust the pulse width modulation drive signal of the power amplifier channel to suppress the reverse energy backflow. The digital signal processing unit generates an ultrasonic pilot signal outside the audio band and superimposes it onto the pulse width modulation drive signal. The intelligent control unit calculates the real-time load impedance based on the pilot signal. When the real-time load impedance exceeds the preset impedance safety range or triggers the operation protection condition, it performs a limiting attenuation operation and sends a status data packet through the network communication unit.

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