A rail-to-rail high voltage operational amplifier with high slew rate
Patent Information
- Application Number
- CN202611173540.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2026-08-04
- Publication Date
- 2026-10-30
AI Technical Summary
[0003]传统单一差分输入级难以覆盖轨对轨输入共模范围，互补输入对结构又容易在P型MOS输入对和N型MOS输入对的交接区产生跨导变化；传统跨导线性环式Class AB结构的动态电流能力有限，高压器件较大的寄生电容会进一步降低压摆率；传统共漏级Class AB输出还存在阈值电压压降，限制输出摆幅
1.P型MOS输入级和N型MOS输入级共同实现轨对轨输入，覆盖轨对轨输入共模范围；
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Figure CN123019638A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of integrated circuit design technology, and in particular to a rail-to-rail high-voltage operational amplifier with a high slew rate. Background Technology
[0002] High-voltage operational amplifiers are widely used in industrial control, power drives, automotive electronics, sensor interfaces, and high-voltage signal conditioning. To fully utilize the dynamic range provided by the high-voltage power supply, the operational amplifier needs to maintain normal operation when the input common-mode voltage is close to the two power rails, and the output terminal needs to be close to the two power rails. At the same time, it also needs to quickly complete the charging and discharging of internal nodes and load capacitors under large-signal conditions.
[0003] Traditional single differential input stages struggle to cover the rail-to-rail common-mode range, while complementary input pair structures are prone to transconductance variations at the junction of P-type and N-type MOS input pairs. Traditional transconductance linear loop Class AB structures have limited dynamic current capability, and the large parasitic capacitance of high-voltage devices further reduces slew rate. Traditional common-drain Class AB outputs also suffer from threshold voltage drop, limiting output swing. Therefore, a high-voltage operational amplifier is needed that combines rail-to-rail input / output, transconductance compensation, and high dynamic current capability. Summary of the Invention
[0004] The present invention was made in view of the above-mentioned problems, and its object is to provide a rail-to-rail high voltage operational amplifier with high voltage slew rate.
[0005] The objective of this invention is achieved through the following technical solution: This invention provides a rail-to-rail high-voltage operational amplifier with high slew rate, comprising: a self-biased current source, a Class AB P-type MOS input stage, a Class AB N-type MOS input stage, a triple current mirror, and a common-source output stage; The self-biased current source provides bias signals to each Class AB P-type MOS input stage and Class AB N-type MOS input stage; The Class AB P-type MOS input stage and the Class AB N-type MOS input stage are complementary and jointly receive the differential input signal; Both the Class AB P-type MOS input stage and the Class AB N-type MOS input stage employ a cross-coupling structure to construct the Class AB input. The triple current mirror is connected to the output terminals of the Class AB P-type MOS input stage and the Class AB N-type MOS input stage; The common source stage output is connected to the output terminal of the triple current mirror.
[0006] Further: The self-biased current source includes: P-type MOS transistors MP8 and MP14, and resistors R1 and R3; the source of MP8 and one end of R1 are connected to the positive power rail, the other end of R1 is connected to the gate of MP8 and the source of MP14, the drain of MP8 is connected to the gate of MP14, and the drain of MP14 serves as the upper bias signal output node; one end of R3 is connected to the drain of MP8 and the gate of MP14, and the other end is connected to ground.
[0007] Further: The Class AB P-type MOS input stage includes P-type MOS transistors MP21, MP24, MP25, and MP26, and N-type MOS transistors NM9, NM10, NM11, and NM12; MP21 and MP26 have their gates connected to the inverting input terminal VIN-, and MP24 and MP25 have their gates connected to the non-inverting input terminal VIN+, forming a pair of P-type MOS input stage transistors for the operational amplifier; The source of MP21 is connected to the source of MN11, the source of MP24 is connected to the source of MN9, the source of MP25 is connected to the source of MN12, the source of MP26 is connected to the source of MN10, the gate and drain of MN9 are connected to the gate of MN10, and the gate and drain of MN11 are connected to the gate of MN12, forming a cross-coupled structure. The drains of MP21 and MP24 are grounded, and the drains of MN6 and MN7 serve as the output ports for differential current.
[0008] Furthermore: the Class AB N-type MOS input stage includes P-type MOS transistors MP15, MP16, MP18, and MP19, and N-type MOS transistors NM2, NM5, NM6, and NM7. The gates of MN5 and MN6 are connected to the inverting input terminal VIN-, and the gates of MN2 and MN7 are connected to the non-inverting input terminal VIN+, forming the N-type MOS input stage pair of the operational amplifier; The source of MN2 is connected to the source of MP15, the source of MN5 is connected to the source of MP18, the source of MN6 is connected to the source of MP16, the source of MN7 is connected to the source of MP19, the gate and drain of MP15 are connected to the gate of MP16, and the gate and drain of MP18 are connected to the gate of MP19, forming a cross-coupled structure. The drains of MN2 and MN5 are grounded, and the drains of MN6 and MN7 serve as the output ports for differential current.
[0009] Furthermore: the triple current mirror includes an upper P-type MOS triple current mirror and a lower N-type MOS triple current mirror; The upper P-type MOS triple current mirror includes MP1-MP2, MP9-MP13, MN1, MN3-MN4, and MN8. The gate and drain of MP1 and the source of MP9 are connected to the gate of MP2. The gate and drain of MP9 are connected to the gate of MP10. The drain of MP2 and the source of MP10 are connected. The sources of MP1 and MP2 are both connected to the power supply. The lower N-type MOS triple current mirror includes MP17, MP20, MP22-MP23, and MN13-MN21; the gate and drain of MN19 and the source of MN13 are connected to the gates of MN20 and MN21, the gate and drain of MN13 are connected to the gates of MN14 and MN15, the drain of MN20 is connected to the source of MN14, the drains of MN21 and MN15 are connected to the source of MN14, and the sources of MN19-MN21 are all grounded.
[0010] Furthermore: the common-source stage output includes a P-type MOS transistor MP7, an N-type MOS transistor MN26, resistors R2 and R4, and capacitors C1 and C2; The source of MP7 is connected to the positive power rail, one end of R2 is connected to the gate of MP7, the other end of R2 is connected to one end of C1, and the other end of C1 is connected to the drain of MP7. One end of R2 and the gate of MP7 are connected to the pull-up drive current mirror, and one end of R4 and the gate of MN26 are connected to the pull-down drive current mirror. The drain of MP7 is connected to the drain of MN26 to form the output terminal VO.
[0011] In summary, the beneficial effects of the present invention are as follows: 1. The P-type MOS input stage and the N-type MOS input stage work together to achieve rail-to-rail input, covering the rail-to-rail input common-mode range; 2. The triple current mirror activates transconductance compensation when a pair of input transistors is turned off due to common-mode voltage changes, suppressing the influence of the input common-mode voltage on the overall transconductance of the operational amplifier and reducing the transconductance change in the junction region of the complementary input stage; 3. Compared with the traditional transconducting linear loop Class AB structure, the cross-coupled Class AB structure can provide larger dynamic current and higher slew rate; 4. The common-source stage output avoids the threshold voltage loss of the common-drain stage output, achieving a larger output swing, and the high and low levels of the output can be close to the positive power rail and ground, respectively. Attached Figure Description
[0012] To more clearly illustrate the technical solutions in the embodiments of this drawing or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this drawing. For those skilled in the art, other drawings can be obtained based on the structures shown in these drawings without creative effort.
[0013] Figure 1 This is the overall circuit diagram of the present invention; Figure 2 This is a schematic diagram of the circuit structure of the present invention; Figure 3 This is a circuit diagram of the self-biased current source of the present invention; Figure 4 This is a circuit diagram of the Class AB P-type MOS input stage of the present invention; Figure 5 This is a circuit diagram of the Class AB N-type MOS input stage of the present invention; Figure 6 This is the circuit diagram of the triple current mirror of the present invention; Figure 7 This is a common-source stage output circuit diagram of the present invention; Figure 8 This is a transient simulation diagram of the present invention.
[0014] The purpose, features, and advantages of this accompanying drawing will be further explained in conjunction with the embodiments and with reference to the accompanying drawing. Detailed Implementation
[0015] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be described and illustrated below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention. All other embodiments obtained by those skilled in the art based on the embodiments provided by this invention without inventive effort are within the scope of protection of this invention.
[0016] Obviously, the accompanying drawings described below are merely some examples or embodiments of the present invention. Those skilled in the art can apply the present invention to other similar scenarios based on these drawings without any inventive effort. Furthermore, it is understood that although the efforts made in this development process may be complex and lengthy, for those skilled in the art related to the content disclosed in this invention, modifications to design, manufacturing, or production based on the technical content disclosed in this invention are merely conventional technical means and should not be construed as insufficient disclosure of the present invention.
[0017] Unless otherwise specified, all embodiments and optional embodiments of the present invention can be combined with each other to form new technical solutions.
[0018] Unless otherwise specified, all technical features and optional technical features of this invention can be combined to form new technical solutions.
[0019] Unless otherwise specified, all steps of the present invention may be performed sequentially or randomly, preferably sequentially. For example, the method includes steps (a) and (b), indicating that the method may include steps (a) and (b) performed sequentially, or it may include steps (b) and (a) performed sequentially. For example, the mention that the method may also include step (c) indicates that step (c) may be added to the method in any order. For example, the method may include steps (a), (b), and (c), or it may include steps (a), (c), and (b), or it may include steps (c), (a), and (b), etc.
[0020] Unless otherwise specified, the terms "comprising" and "including" as used in this invention can be open-ended or closed-ended. For example, "comprising" and "including" can mean that other components not listed may also be included, or that only the listed components may be included.
[0021] Unless otherwise specified, the term "or" is inclusive in this invention. For example, the phrase "A or B" means "A, B, or both A and B". More specifically, the condition "A or B" is satisfied by any of the following conditions: A is true (or exists) and B is false (or does not exist); A is false (or does not exist) and B is true (or exists); or both A and B are true (or exist).
[0022] Please see Figure 1 and Figure 2This system includes: a self-biased current source, a Class AB P-type MOS input stage, a Class AB N-type MOS input stage, a triple current mirror, and a common-source output stage. The self-biased current source provides bias signals to the Class AB P-type and Class AB N-type MOS input stages. The Class AB P-type and Class AB N-type MOS input stages are complementary, jointly receiving differential input signals to achieve rail-to-rail common-mode range. Both the Class AB P-type and Class AB N-type MOS input stages employ cross-coupling structures to construct the Class AB input stage, maintaining a low quiescent current and providing a larger dynamic current when the differential input signal changes, thereby improving the slew rate. The triple current mirror is connected to the outputs of the Class AB P-type and Class AB N-type MOS input stages, used to adjust the output of the Class AB P-type or Class AB N-type MOS input stage. When the input pairs of N-type MOS input stage transistors (input pairs refer to transistors such as MN2, MN5, MN6, and MN7, which appear in pairs and whose gates are directly connected to the differential input port) are turned off due to common-mode voltage changes, transconductance compensation is activated to suppress the influence of the input common-mode voltage on the overall transconductance of the op-amp. The triple current mirror output is connected to Class AB P-type MOS and Class AB N-type MOS and controls the common-source stage output through pull-up and pull-down current mirrors to provide rail-to-rail output voltage and output current. The built-in compensation network establishes the dominant poles and zeros to ensure system stability.
[0023] Specifically: The main function of the self-biased current source (10) is to form a closed bias loop between the positive power rail and ground. After power-on, it can establish the working current without external bias and provide bias signals to the complementary input stage, current mirror and output drive stage. The specific circuit structure is as follows: Figure 3 As shown, it includes: P-type MOS transistors MP8 and MP14, and resistors R1 and R3; the source of MP8 and one end of R1 are connected to the positive power rail, the other end of R1 is connected to the gate of MP8 and the source of MP14, the drain of MP8 is connected to the gate of MP14, and the drain of MP14 serves as the upper bias signal output node; one end of R3 is connected to the drain of MP8 and the gate of MP14, and the other end is connected to ground.
[0024] The circuit structure of the Class AB P-type MOS input stage (20) is as follows: Figure 4As shown, the amplifier includes P-type MOS transistors MP21, MP24, MP25, and MP26, and N-type MOS transistors NM9, NM10, NM11, and NM12. The gates of MP21 and MP26 are connected to the inverting input terminal VIN-, and the gates of MP24 and MP25 are connected to the non-inverting input terminal VIN+, forming a pair of P-type MOS input stage transistors for the operational amplifier. The source of MP21 is connected to the source of MN11, the source of MP24 is connected to the source of MN9, the source of MP25 is connected to the source of MN12, and the source of MP26 is connected to the source of MN10. The gate and drain of MN9 are connected to the gate of MN10, and the gate and drain of MN11 are connected to the gate of MN12, forming a cross-coupling structure to improve dynamic current. The drains of MP21 and MP24 are grounded, and the drains of MN6 and MN7 serve as output ports for differential current, aiming to output higher dynamic current. In summary, combining... Figure 1 The contents of the Class AB P-type MOS input stage (20) use MP24, MP25 and MP21, MP26 as complementary input pairs. The gates of MP21 and MP26 are connected to VIN-, and the gates of MP24 and MP25 are connected to VIN+. MN9-MN12 form a cross-coupled bias branch on both sides. When a differential voltage signal is applied to the input terminal, a certain positive feedback will be generated due to the cross-coupled structure, thereby forming a large dynamic differential current.
[0025] The circuit diagram of Class AB N-type MOS input stage (30) is as follows: Figure 5 As shown: The system includes P-type MOS transistors MP15, MP16, MP18, and MP19, and N-type MOS transistors NM2, NM5, NM6, and NM7. The gates of MN5 and MN6 are connected to the inverting input terminal VIN-, and the gates of MN2 and MN7 are connected to the non-inverting input terminal VIN+. This forms the N-type MOS input stage of the operational amplifier. The source of transistor MN2 is connected to the source of MP15, the source of MN5 to the source of MP18, the source of MN6 to the source of MP16, and the source of MN7 to the source of MP19. The gate and drain of MP15 are connected to the gate of MP16, and the gate and drain of MP18 are connected to the gate of MP19, forming a cross-coupling structure to improve dynamic current. The drains of MN2 and MN5 are grounded, and the drains of MN6 and MN7 serve as the output ports for differential current, resulting in higher dynamic current output. In summary, combining... Figure 1The contents of the Class AB N-type MOS input stage (30) use MN5, MN6 and MN2, MN7 as complementary input pairs. The gates of MN5 and MN6 are connected to VIN-, and the gates of MN2 and MN7 are connected to VIN+. MP15-MP16 and MP18-MP19 form a cross-coupled bias branch on both sides. When a differential voltage signal is applied to the input terminal, a certain positive feedback will be generated due to the cross-coupled structure, thereby forming a large dynamic differential current.
[0026] The circuit diagram of the triple current mirror (40) is as follows: Figure 6 As shown, it includes a triple current mirror for the upper P-type MOS and a triple current mirror for the lower N-type MOS; The upper P-type MOS triple current mirror includes MP1-MP2, MP9-MP13, MN1, MN3-MN4, and MN8. The gate and drain of MP1 and the source of MP9 are connected to the gate of MP2. The gate and drain of MP9 are connected to the gate of MP10. The drain of MP2 and the source of MP10 are connected. The sources of MP1 and MP2 are both connected to the power supply, forming a common-source, common-gate current mirror to accurately replicate the current. Figure 1 The contents are as follows: the source of MN8 is grounded, the gate and drain of MN8 are connected to the source of MN1, the gate and drain of MN1 are connected to the drain of MP10, the current after the current mirror is copied is converted into a bias voltage and connected to the gates of MN3 and MN4 to control the turn-on or turn-off of the upper P-type MOS triple current mirror; the sources of MN3 and MN4 serve as the input terminals of the differential current of the upper P-type MOS triple current mirror, the drains of MN3 and MN4 are connected to the gate and drain of MP13, the differential current is summed and converted into a bias voltage and connected to the gates of MP11 and MP12, the sources of MP11-MP13 are grounded, and the drains of MP11 and MP12 serve as the output of the differential current, used to compensate the triple current to the Class AB N-type MOS input stage; The lower-side N-type MOS triple current mirror includes MP17, MP20, MP22-MP23, and MN13-MN21; the gate and drain of MN19 and the source of MN13 are connected to the gates of MN20 and MN21; the gate and drain of MN13 are connected to the gates of MN14 and MN15; the drain of MN20 is connected to the source of MN14; the drains of MN21 and MN15 are connected to the source of MN14; and the sources of MN19-MN21 are all grounded, forming a common-source, common-gate current mirror to accurately replicate the current; combined with Figure 1The contents are as follows: the source of MP17 is connected to the power supply; the gate and drain of MP17 are connected to the source of MP20; the gate and drain of MP20 are connected to the drain of MN15; the current copied by the current mirror is converted into a bias voltage and connected to the gates of MP22 and MP23 to control the on or off of the upper P-type MOS triple current mirror; the sources of MP22 and MP23 serve as the input terminals of the differential current of the lower N-type MOS triple current mirror; the drains of MP22 and MP23 are connected to the gate and drain of MN18; the differential current is summed and converted into a bias voltage and connected to the gates of MN16 and MN17; the sources of MN16-MN18 are grounded; the drains of MN16 and MN17 serve as the output of the differential current, used to compensate the triple current to the Class AB P-type MOS input stage; The current replication ratio of the triple current mirror is 3:1, and it is set as an upper and lower complementary structure. The principle is that when one pair of input transistors in the P-type MOS input stage or N-type MOS input stage gradually turns off due to the change of input common mode voltage, the corresponding triple current mirror increases the equivalent current contribution of the other input stage to reduce the amplitude of the total transconductance changing with the input common mode voltage.
[0027] The common-source output (50) circuit structure is as follows: Figure 7 As shown, it includes a P-type MOS transistor MP7, an N-type MOS transistor MN26, resistors R2 and R4, and capacitors C1 and C2; combined with Figure 1In this configuration, the source of MP7 is connected to the positive power rail; one end of R2 is connected to the gate of MP7; the other end of R2 is connected to one end of C1; and the other end of C1 is connected to the drain of MP7. MP5 and MP6 form a pull-up drive current mirror, MP7 forms a common-source pull-up output transistor, and R2 and C1 form a compensation branch from the pull-up drive node to the output terminal. The sources of MN24-MN26 are connected to ground; the gate and drain of MN24 are connected and connected to the gate of MN25; the drain of MN25 is connected to the gate of MN26; one end of R4 is connected; the other end of R4 is connected to one end of C2; and the other end of C2 is connected to the drain of MN26. MN24 and MN25 form a pull-down drive current mirror, MN26 forms a common-source pull-down output transistor, and R4 and C2 form a compensation branch from the pull-down drive node to the output terminal. The drain of MP7 is connected to the drain of MN26 to form the output terminal VO, thereby achieving rail-to-rail voltage output. The common-source stage output consists of a P-type MOS pull-up transistor connected to the positive power rail and an N-type MOS pull-down transistor connected to ground. The common drain node of the two transistors serves as the output terminal VO. Since the output devices are connected from the same source, the high and low output levels can be close to the positive power rail and ground, respectively, while providing a large source current and sink current. The pull-up channel of the common-source stage output is equipped with a compensation network consisting of R2 and C1 connected in series, and the pull-down channel is equipped with a compensation network consisting of R4 and C2 connected in series. The two compensation networks form frequency compensation paths between the corresponding drive nodes and the output terminal VO, respectively, to improve the phase margin and take into account the large signal response.
[0028] Transient simulation diagram as follows Figure 8 As shown, the yellow line represents the input voltage change at the VIN terminal, and the red line represents the output voltage change at the VO terminal. The switching range of the input voltage is shown on the vertical axis (0-15V). It can be seen that when VIN is switched quickly within the same time period, VO can follow the change within a range close to the two power rails. The slew rate dx of the rising and falling edges is shown by the data S: 125MV / s, which is approximately 125V / μs, indicating that it can meet the large signal response requirements under high-voltage rail-to-rail working conditions.
[0029] It should be noted that the present invention is not limited to the above-described embodiments. The above embodiments are merely examples, and any embodiments that have the same structure and perform the same effects as the technical concept within the scope of the present invention are included within the scope of the present invention. Furthermore, various modifications that can be conceived by those skilled in the art to the embodiments, and other ways of constructing by combining some of the constituent elements of the embodiments, without departing from the spirit of the present invention, are also included within the scope of the present invention.
Claims
1. A rail-to-rail high-voltage operational amplifier with high slew rate, characterized in that, include: Self-biased current source, Class AB P-type MOS input stage, Class AB N-type MOS input stage, triple current mirror and common-source output; The self-biased current source provides bias signals to each Class AB P-type MOS input stage and Class AB N-type MOS input stage; The Class AB P-type MOS input stage and the Class AB N-type MOS input stage are complementary and jointly receive the differential input signal; Both the Class AB P-type MOS input stage and the Class AB N-type MOS input stage employ a cross-coupling structure to construct the Class AB input. The triple current mirror is connected to the output terminals of the Class AB P-type MOS input stage and the Class AB N-type MOS input stage; The common source stage output is connected to the output terminal of the triple current mirror.
2. The rail-to-rail high-voltage operational amplifier with high slew rate according to claim 1, characterized in that, The self-biased current source includes: P-type MOS transistors MP8 and MP14, and resistors R1 and R3; the source of MP8 and one end of R1 are connected to the positive power rail, the other end of R1 is connected to the gate of MP8 and the source of MP14, the drain of MP8 is connected to the gate of MP14, and the drain of MP14 serves as the upper bias signal output node; one end of R3 is connected to the drain of MP8 and the gate of MP14, and the other end is connected to ground.
3. The rail-to-rail high-voltage operational amplifier with high slew rate according to claim 1, characterized in that, The Class AB P-type MOS input stage includes P-type MOS transistors MP21, MP24, MP25, and MP26, and N-type MOS transistors NM9, NM10, NM11, and NM12; MP21 and MP26 have their gates connected to the inverting input terminal VIN-, and MP24 and MP25 have their gates connected to the non-inverting input terminal VIN+, forming a pair of P-type MOS input stage transistors for the operational amplifier; The source of MP21 is connected to the source of MN11, the source of MP24 is connected to the source of MN9, the source of MP25 is connected to the source of MN12, the source of MP26 is connected to the source of MN10, the gate and drain of MN9 are connected to the gate of MN10, and the gate and drain of MN11 are connected to the gate of MN12, forming a cross-coupled structure. The drains of MP21 and MP24 are grounded, and the drains of MN6 and MN7 serve as the output ports for differential current.
4. A rail-to-rail high-voltage operational amplifier with high slew rate according to claim 1, characterized in that, The Class AB N-type MOS input stage includes P-type MOS transistors MP15, MP16, MP18, and MP19, and N-type MOS transistors MN2, MN5, MN6, and MN7. The gates of MN5 and MN6 are connected to the inverting input terminal VIN-, and the gates of MN2 and MN7 are connected to the non-inverting input terminal VIN+, forming the N-type MOS input stage pair of the operational amplifier; The source of MN2 is connected to the source of MP15, the source of MN5 is connected to the source of MP18, the source of MN6 is connected to the source of MP16, the source of MN7 is connected to the source of MP19, the gate and drain of MP15 are connected to the gate of MP16, and the gate and drain of MP18 are connected to the gate of MP19, forming a cross-coupled structure. The drains of MN2 and MN5 are grounded, and the drains of MN6 and MN7 serve as the output ports for differential current.
5. A rail-to-rail high-voltage operational amplifier with high slew rate according to claim 1, characterized in that, The triple current mirror includes an upper P-type MOS triple current mirror and a lower N-type MOS triple current mirror; The upper P-type MOS triple current mirror includes MP1-MP2, MP9-MP13, MN1, MN3-MN4, and MN8. The gate and drain of MP1 and the source of MP9 are connected to the gate of MP2. The gate and drain of MP9 are connected to the gate of MP10. The drain of MP2 and the source of MP10 are connected. The sources of MP1 and MP2 are both connected to the power supply. The lower N-type MOS triple current mirror includes MP17, MP20, MP22-MP23, and MN13-MN21; the gate and drain of MN19 and the source of MN13 are connected to the gates of MN20 and MN21, the gate and drain of MN13 are connected to the gates of MN14 and MN15, the drain of MN20 is connected to the source of MN14, the drains of MN21 and MN15 are connected to the source of MN14, and the sources of MN19-MN21 are all grounded.
6. A rail-to-rail high-voltage operational amplifier with high slew rate according to claim 1, characterized in that, The common-source stage output includes a P-type MOS transistor MP7, an N-type MOS transistor MN26, resistors R2 and R4, and capacitors C1 and C2; The source of MP7 is connected to the positive power rail, one end of R2 is connected to the gate of MP7, the other end of R2 is connected to one end of C1, and the other end of C1 is connected to the drain of MP7. One end of R2 and the gate of MP7 are connected to the pull-up drive current mirror, and one end of R4 and the gate of MN26 are connected to the pull-down drive current mirror. The drain of MP7 is connected to the drain of MN26 to form the output terminal VO.