Dry sensing interface mismatch suppression circuit for wearable electrocardiogram acquisition devices

Abstract

The present application relates to a kind of dry sensing interface mismatch inhibition circuit for wearable electrocardio acquisition device, comprising: electrocardio signal amplification unit, for receiving and amplifying the input electric signal containing useful electrocardio signal, obtain differential amplification electric signal;Direct current servo loop, for receiving differential amplification electric signal, according to the relationship between the amplitude of differential amplification electric signal and preset voltage threshold value adaptively switches between first mode and second mode, and the compensation voltage opposite to the polarity of dry interface misadjustment voltage is fed back to the input end of electrocardio signal amplification unit, to offset dry interface misadjustment voltage.The present application has the characteristics such as simple circuit structure, PVT characteristics stable, can realize the fast misadjustment inhibition in millisecond level time.

Description

Technical Field

[0001] This invention relates to the interdisciplinary field of biomedical engineering and microelectronics, specifically to a dry sensing interface mismatch suppression circuit for wearable ECG acquisition devices. Background Technology

[0002] Wearable ECG acquisition devices are crucial tools for daily monitoring and early warning of cardiovascular diseases. To improve comfort during long-term wear, the industry generally uses dry electrodes instead of traditional Ag / AgCl wet electrodes, thus avoiding skin irritation and allergy problems caused by conductive gel. However, the application of dry electrodes also introduces new technical challenges: due to the inevitable differences in the physical and electrical properties of the two electrodes in differential mode sampling and their contact surfaces with the skin, an extremely low-frequency (typically below 0.05Hz) differential mode interference voltage, much larger than the amplitude of the useful ECG signal, is superimposed at the input of the signal amplification unit—this is the dry interface offset voltage. After high-gain amplification, this dry interface offset voltage can easily cause the amplifier output stage to saturate, rendering ECG signal acquisition completely ineffective and severely affecting the amplifier's linearity and output swing.

[0003] Traditional solutions typically employ AC coupling or high-order high-pass filters to suppress DC offset voltage, but these methods require extremely large capacitors or resistors, making them difficult to implement in miniaturized wearable ECG acquisition devices. Furthermore, filters with fixed time constants cannot simultaneously meet the requirements of rapid setup and steady-state maintenance.

[0004] Therefore, there is an urgent need for a circuit scheme that can simultaneously achieve rapid suppression and steady-state maintenance of dry interface offset voltage under the conditions of miniaturization and low power consumption. Summary of the Invention

[0005] To address the aforementioned problems in the prior art, this invention provides a dry sensing interface mismatch suppression circuit for wearable ECG acquisition devices. The technical problem to be solved by this invention is achieved through the following technical solution: This invention provides a dry sensing interface mismatch suppression circuit for wearable ECG acquisition devices, comprising: The electrocardiogram signal amplification unit is used to amplify the input electrical signal containing the useful electrocardiogram signal to obtain a differential amplified electrical signal; A DC servo loop is used to adaptively switch between a first mode and a second mode according to the relationship between the amplitude of the differential amplified electrical signal and a preset voltage threshold, and to feed back a compensation voltage with the opposite polarity to the dry interface offset voltage to the input of the ECG signal amplification unit to counteract the dry interface offset voltage. In the first mode, the DC servo loop operates with a first time constant to establish the compensation voltage to suppress the dry interface offset voltage. In the second mode, the DC servo loop operates with a second time constant to make the ECG signal amplification unit have a lower cutoff frequency lower than the lowest frequency component of the useful ECG signal to maintain the steady state after the dry interface offset voltage is canceled. The first time constant is smaller than the second time constant.

[0006] Compared with the prior art, the beneficial effects of the present invention are as follows: The dry interface mismatch suppression circuit provided by this invention achieves adaptive and rapid suppression and steady-state maintenance of dry interface offset voltage through a closed-loop negative feedback architecture of an ECG signal amplification unit and a DC servo loop. The DC servo loop of this invention can automatically switch between a first mode and a second mode based on the relationship between the amplitude of the differential amplified electrical signal and a preset voltage threshold: when the dry interface offset voltage is large, the DC servo loop operates with a small first time constant to quickly establish a compensation voltage, suppressing the dry interface offset voltage to a normal level within milliseconds; when the dry interface offset voltage is canceled out, the DC servo loop automatically switches to a very large second time constant, ensuring that the ECG signal amplification unit has a lower cutoff frequency below the lowest frequency component of the useful ECG signal, maintaining steady state while ensuring that the useful ECG signal is not affected. This adaptive dual-mode switching mechanism overcomes the shortcomings of traditional fixed-time-constant schemes that cannot simultaneously meet the requirements of rapid establishment and steady-state maintenance. Under the conditions of miniaturization and low power consumption, it achieves both rapid suppression and steady-state maintenance of dry interface offset voltage, significantly improving the signal quality and user experience of wearable ECG acquisition devices. Compared with the dry sensor interface mismatch suppression circuit of traditional wearable ECG acquisition devices, the present invention has the advantages of simple circuit structure, stable PVT (process-voltage-temperature) characteristics, and the ability to achieve rapid mismatch suppression in milliseconds.

[0007] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description

[0008] Figure 1 This is an overall structural diagram of a dry sensing interface mismatch suppression circuit for wearable ECG acquisition devices provided by the present invention. Figure 2 This is a circuit-level schematic diagram of a dry sensing interface mismatch suppression circuit for wearable ECG acquisition devices provided by the present invention; Figure 3 This is a circuit-level schematic diagram of a threshold-controlled two-state pseudo-resistor provided by the present invention; Figure 4 This is a circuit-level schematic diagram of an adaptive control module provided by the present invention; Figure 5 This is a circuit schematic diagram of a threshold offset hysteresis comparator provided by the present invention; Figure 6 This is a clock signal waveform diagram of a threshold offset hysteresis comparator provided by the present invention; Figure 7 This is a circuit-level schematic diagram of a common pseudo-resistor provided by the present invention. Detailed Implementation

[0009] The present invention will be further described in detail below with reference to specific embodiments, but the implementation of the present invention is not limited thereto.

[0010] Please see Figure 1 , Figure 1 This is an overall structural diagram of a dry sensor interface mismatch suppression circuit for wearable ECG acquisition devices provided by the present invention. The present invention provides a dry sensor interface mismatch suppression circuit for wearable ECG acquisition devices, the dry sensor interface mismatch suppression circuit comprising: The electrocardiogram signal amplification unit is used to amplify the input electrical signal containing the useful electrocardiogram signal to obtain a differential amplified electrical signal; The DC servo loop is used to adaptively switch between the first mode and the second mode according to the relationship between the amplitude of the differential amplified electrical signal and the preset voltage threshold, and to feed back the compensation voltage with the opposite polarity to the dry interface offset voltage to the input of the ECG signal amplification unit to cancel the dry interface offset voltage. In the first mode, the DC servo loop operates with a first time constant to establish a compensation voltage to suppress the dry interface offset voltage. In the second mode, the DC servo loop operates with a second time constant to enable the ECG signal amplification unit to have a lower cutoff frequency below the lowest frequency component of the useful ECG signal, so as to maintain the steady state after the dry interface offset voltage is canceled. The first time constant is smaller than the second time constant.

[0011] Specifically, useful electrocardiogram (ECG) signals refer to the weak bioelectrical signals generated by the human heartbeat, with a frequency range typically between 0.05 Hz and 100 Hz. These are the target signals that ECG acquisition equipment needs to accurately record and measure.

[0012] The dry interface mismatch suppression circuit provided in this embodiment includes an ECG signal amplification unit and a DC servo loop. The ECG signal amplification unit amplifies the input electrical signal containing the useful ECG signal and outputs a differential amplified electrical signal. The DC servo loop forms a closed-loop structure. This DC servo loop determines the current suppression state of the dry interface mismatch voltage by detecting the amplitude (i.e., the absolute value of the differential amplified electrical signal) of the differential amplified electrical signal, and adaptively switches between a first mode and a second mode according to the relationship between the amplitude of the differential amplified electrical signal and a preset voltage threshold. Simultaneously, the DC servo loop also generates a compensation voltage with the opposite polarity to the dry interface mismatch voltage and feeds it back to the input of the ECG signal amplification unit, thereby achieving cancellation of the dry interface mismatch voltage at the input.

[0013] The first mode corresponds to the stage where the dry interface offset voltage has not yet been effectively suppressed; this mode is also called the setup mode. In the first mode, the differential amplified electrical signal includes not only the amplified useful ECG signal but also the amplified dry interface offset voltage. The amplitude of the differential amplified electrical signal is relatively large, indicating that there is a significant residual dry interface offset voltage at the output of the ECG signal amplification unit. The DC servo loop responds to this state, operating with a first time constant (a smaller time constant), enabling the DC servo loop to have a fast response speed and quickly establish a compensation voltage sufficient to offset the dry interface offset voltage. This process achieves rapid suppression of the dry interface offset voltage, preventing the ECG signal amplification unit from entering saturation due to excessive dry interface offset voltage, thereby ensuring that the useful ECG signal can be amplified normally.

[0014] The second mode corresponds to the steady-state stage after the dry interface offset voltage has been effectively suppressed; this mode is also called the integral mode. In the second mode, the dry interface offset voltage has been essentially canceled out, and the amplitude of the differential amplified electrical signal has returned to normal levels. The DC servo loop responds to this state, operating with a second time constant (an extremely large time constant), resulting in a very slow response speed. This causes the overall amplitude-frequency characteristic of the ECG signal amplification unit to exhibit a lower cutoff frequency below the lowest frequency component of the useful ECG signal (typically 0.05Hz). This lower cutoff frequency is the lowest frequency point corresponding to when the gain of the ECG signal amplification unit begins to decrease significantly in its overall amplitude-frequency characteristic in the second mode. This means that useful ECG signals with frequencies higher than this lower cutoff frequency can pass through and be amplified normally, while residual dry interface offset voltage components with frequencies lower than this lower cutoff frequency are effectively suppressed. This design maintains the steady state after the dry interface offset voltage is canceled out while ensuring normal acquisition of the useful ECG signal, meeting the relevant national standards requirements for ECG signal acquisition equipment.

[0015] In a specific embodiment, such as Figure 1As shown, the DC servo loop includes a dry sensor interface mismatch suppression module. The first input terminal of the dry sensor interface mismatch suppression module is connected to the positive output terminal of the ECG signal amplification unit, and the second input terminal is connected to the inverted output terminal of the ECG signal amplification unit. The dry interface mismatch suppression module is used to extract the amplified dry interface mismatch voltage from the differential amplified electrical signal, process the amplified dry interface mismatch voltage to generate a compensation voltage with the opposite polarity to the dry interface mismatch voltage, modulate the compensation voltage to a preset frequency to obtain the modulated compensation voltage, and couple the modulated compensation voltage to the ECG signal amplification unit to cancel the dry interface mismatch voltage.

[0016] Specifically, the dry interface mismatch suppression module in the DC servo loop first extracts the amplified dry interface mismatch voltage from the differential amplified electrical signal, and then performs integration and other processing operations on it to generate a compensation voltage that is related to the amplitude of the dry interface mismatch voltage but has the opposite polarity. Next, the compensation voltage is modulated to a preset chopping frequency (i.e., preset frequency) to form a modulated compensation voltage, so that the modulated compensation voltage can be aligned with the signal in the input ECG signal amplification unit in frequency. Finally, the modulated compensation voltage is coupled back to the positive and negative input terminals of the ECG signal amplification unit to form negative feedback cancellation with the dry interface mismatch voltage in the input electrical signal at the input terminal of the ECG signal amplification unit, thereby achieving effective suppression of the dry interface mismatch voltage.

[0017] In an optional embodiment, such as Figure 2 As shown, the dry sensing interface mismatch suppression module includes: The integrator has its positive input connected to the positive output of the ECG signal amplification unit and its inverting input connected to the inverting output of the ECG signal amplification unit. It is used to extract the amplified dry interface offset voltage from the differential amplified electrical signal and to integrate the amplified dry interface offset voltage to generate an integrated voltage that is related to the amplitude of the amplified dry interface offset voltage, which serves as a compensation voltage. The first and second input terminals of the chopper switch CH4 are connected to the positive and negative output terminals of the integrator, respectively, to modulate the compensation voltage to a preset frequency and obtain the modulated compensation voltage. Differential capacitor C DSL1 and differential capacitor C DSL2 Differential capacitor C DSL1 and differential capacitor C DSL2 The input terminals are connected to the first and second output terminals of the chopper switch CH4, respectively, and the differential capacitor C DSL1 The output terminal is connected to the inverting input terminal of the ECG signal amplification unit, and the differential capacitor C... DSL2The output terminal is connected to the positive input terminal of the ECG signal amplification unit to couple the modulated compensation voltage to the positive and negative input terminals of the ECG signal amplification unit to cancel the dry interface offset voltage.

[0018] Specifically, the integrator in the dry interface mismatch suppression module is the core processing unit of the module. The integrator's positive and negative inputs serve as the first and second inputs of the dry interface mismatch suppression module, respectively, and are connected to the positive and negative outputs of the ECG signal amplification unit. Because the integrator has an extremely low cutoff frequency (with a frequency component lower than the useful ECG signal), it can isolate the useful ECG signal in the frequency domain and selectively extract the amplified dry interface mismatch voltage from the differential amplified electrical signal. The integrator integrates the extracted amplified dry interface mismatch voltage, and as the integration time progresses, it eventually generates an integrated voltage related to the amplitude of the amplified dry interface mismatch voltage. This integrated voltage is the compensation voltage, and its polarity is opposite to that of the dry interface mismatch voltage.

[0019] The compensation voltage output from the integrator cannot be directly superimposed on the input electrical signal to the ECG signal amplification unit. Therefore, the first and second input terminals of the chopper switch CH4 are connected to the positive and negative output terminals of the integrator, respectively, to modulate the compensation voltage to a preset chopping frequency (i.e., the preset frequency). After modulation, the frequency of the compensation voltage is shifted to near the chopping frequency, thus aligning it with the signal in the ECG signal amplification unit that is also at the chopping frequency, creating conditions for subsequent cancellation. The modulated compensation voltage is output from the first and second output terminals of the chopper switch CH4.

[0020] The modulated compensation voltage needs to pass through the differential capacitor C DSL1 and C DSL2 The coupling is applied to the positive and negative input terminals of the ECG signal amplification unit. Differential capacitor C DSL1 and C DSL2 The input terminals are connected to the first and second output terminals of chopper switch CH4, respectively. DSL1 The output terminal serves as the first output terminal of the dry sensor interface mismatch suppression module, connected to the inverting input terminal of the ECG signal amplification unit. DSL2 The output terminal serves as the second output terminal of the dry interface mismatch suppression module, connected to the positive input terminal of the ECG signal amplification unit. This cross-connection ensures that the modulated compensation voltage is injected differentially into the input terminal of the ECG signal amplification unit, forming negative feedback to cancel out the dry interface mismatch voltage in the input signal. Through this mechanism, the dry interface mismatch voltage is effectively suppressed, enabling the ECG signal amplification unit to amplify the useful ECG signal normally without being affected by the dry interface mismatch voltage.

[0021] In an optional embodiment, such as Figure 2 As shown, the integrator includes: The variable impedance module has its first and second input terminals connected to the positive and negative output terminals of the ECG signal amplification unit, respectively. It is used to adjust the impedance value of the variable impedance module according to the relationship between the amplitude of the differential amplified electrical signal and the preset voltage threshold, and to convert the received amplified dry interface offset voltage into an integral current. Includes operational amplifier G mD1 Integrating capacitor C INTD1 and integrating capacitor C INTD2 The integration module, operational amplifier G mD1 The positive and negative input terminals are connected to the first and second output terminals of the variable impedance module, respectively. Operational amplifier G... mD1 The positive and negative output terminals are connected to the input terminals of chopper switch CH4, and the integrating capacitor C... INTD1 The two ends are respectively connected to operational amplifier G mD1 The positive input terminal and the inverting output terminal, the integrating capacitor C INTD2 The two ends are respectively connected to operational amplifier G mD1 The inverting input and the non-inverting output are used to accumulate charge on the integral current to generate an integral voltage as a compensation voltage. Among them, based on the impedance value of the variable impedance module and the integrating capacitor C INTD1 and integrating capacitor C INTD2 The relationship between the capacitance values ​​causes the integrator's time constant to switch between a first time constant and a second time constant, thereby controlling the DC servo loop to switch between the first mode and the second mode.

[0022] Specifically, the variable impedance module in the integrator is the component that determines the integrator's time constant. The variable impedance module automatically adjusts its impedance value based on the relationship between the amplitude of the differential amplified signal and a preset voltage threshold. When the amplitude of the differential amplified signal is large (indicating that the interfacial offset voltage has not been effectively suppressed), the variable impedance module exhibits a low impedance value; when the amplitude of the differential amplified signal is small (indicating that the interfacial offset voltage has been largely canceled), the variable impedance module exhibits a very high impedance value. This dynamic adjustment of the impedance value is the basis for achieving the switching of the integrator's time constant.

[0023] The amplified dry interface offset voltage is converted into an integrating current by a variable impedance module. This integrating current then passes through the operational amplifier G. mD1 Integrating capacitor C INTD1 and integrating capacitor C INTD2 The two are connected across operational amplifier G in a cross-connect manner. mD1Between the input and output terminals, this differential structure makes the integrating capacitor C... INTD1 and integrating capacitor C INTD2 It can simultaneously accumulate charge on the integrating current. As the integrating current continues to flow in, the voltage across the integrating capacitor gradually increases. This integrating voltage is the compensation voltage, and its polarity is opposite to that of the dry interface offset voltage.

[0024] The integrator's time constant is determined by the impedance value of the variable impedance module and the integrating capacitor C. INTD1 and integrating capacitor C INTD2 The capacitance value is jointly determined by the integrator, i.e., τ = R × C. When the variable impedance module is in a low impedance state, the integrator has a small first time constant, and the integrating capacitor can quickly accumulate charge, causing the DC servo loop to enter the first mode (fast suppression state), establishing a compensation voltage within milliseconds to suppress the dry interface offset voltage. When the variable impedance module is in a high impedance state, the integrator has a very large second time constant, causing the DC servo loop to enter the second mode (steady-state holding state). The ECG signal amplification unit exhibits a lower cutoff frequency below the lowest frequency component of the useful ECG signal, thus maintaining a steady state after the dry interface offset voltage is canceled while ensuring that the useful ECG signal is not affected.

[0025] In an optional embodiment, such as Figure 2 The variable impedance module includes a threshold-controlled two-state pseudo-resistor R with the same structure. T1 and threshold-controlled two-state pseudo-resistance R T2 Threshold-controlled two-state pseudo-resistance R T1 The input terminal is connected to the positive output terminal of the ECG signal amplification unit, and the output terminal is connected to the operational amplifier G. mD1 The positive input terminal, threshold-controlled two-state pseudo-resistor R T2 The input terminal is connected to the inverting output terminal of the ECG signal amplification unit, and the output terminal is connected to the operational amplifier G. mD1 The inverting input terminal.

[0026] Specifically, the variable impedance module consists of a threshold-controlled two-state pseudo-resistor R with an identical structure. T1 and threshold-controlled two-state pseudo-resistance R T2 The two components are connected differentially and symmetrically at the input of the integrator. Threshold-controlled two-state pseudo-resistor R T1 The input terminal is the first input terminal of the variable impedance module, and also the first input terminal of the dry sensing interface mismatch suppression module. The output terminal is the first output terminal of the variable impedance module. The threshold-controlled dual-state pseudo-resistance R T2The input terminal is also the second input terminal of the variable impedance module and the second input terminal of the dry sensing interface mismatch suppression module; the output terminal is the second output terminal of the variable impedance module. This symmetrical structure of the variable impedance module ensures that the impedance characteristics of the two branches are completely identical, thus maintaining balance in the differential signal path. Each threshold-controlled two-state pseudo-resistor can be controlled by the signal φ. ctrl Under the influence of [the system], it switches between low impedance and high impedance states, thereby changing the time constant of the integrator and realizing the adaptive switching of the DC servo loop between the first mode and the second mode.

[0027] Furthermore, such as Figure 3 As shown, the threshold-controlled two-state pseudo-resistor R T1 and threshold-controlled two-state pseudo-resistance R T2 Each includes transistor M1, transistor M2, and single-pole double-throw switch K1, wherein: The sources of transistors M1 and M2 serve as the input and output terminals, respectively. The source of transistor M1 is shorted to its substrate, and the source of transistor M2 is shorted to its substrate. The drain of transistor M1 is connected to the drain of transistor M2. The gates of transistors M1 and M2 are interconnected and controlled by a control signal φ via a single-pole double-throw switch K1. ctrl ; When the control signal φ ctrl When the voltage is high, the gates of transistors M1 and M2 are connected to a fixed voltage V. R Terminal, so that the threshold-controlled two-state pseudo-resistance R T1 and threshold-controlled two-state pseudo-resistance R T2 In the first impedance state; when the control signal φ ctrl When the voltage is low, the gates of transistor M1 and M2 are connected to the power supply voltage V. DD Terminal, so that the threshold-controlled two-state pseudo-resistance R T1 and threshold-controlled two-state pseudo-resistance R T2 In the second impedance state, where the fixed voltage V R Less than the power supply voltage V DD The impedance value in the first impedance state is less than the impedance value in the second impedance state.

[0028] Specifically, the threshold-controlled two-state pseudo-resistor is composed of transistors M1 and M2. The gates and drains of transistors M1 and M2 are interconnected, and their sources serve as the two ports of the threshold-controlled two-state pseudo-resistor, connected in the circuit as resistive electronic components. Both transistors M1 and M2 employ a source-to-substrate short circuit, thereby providing a defined voltage to the substrate, ensuring that the source-substrate voltage V of transistors M1 and M2 operates within this voltage range. BSThe value is always zero, thus ensuring that the PN junctions formed between the drains of transistors M1 and M2 and the substrate will not break down. The gates of transistors M1 and M2 are controlled by a single-pole double-throw switch K1 via a control signal φ. ctrl When φ ctrl When the voltage is high, the gates of transistors M1 and M2 are connected to a fixed voltage V. R Terminal, through a fixed voltage V R Terminal transmission of fixed voltage V R Fixed voltage V R It can be set as needed, but a fixed voltage V must be ensured. R Much smaller than the power supply voltage V DD At this point, the threshold-controlled two-state pseudo-resistor exhibits a small resistance value, typically in the range of hundreds to thousands of ohms; when the control signal φ ctrl When the voltage is low, the gates of transistors M1 and M2 are connected to the power supply voltage V. DD Terminal, through power supply voltage V DD Terminal transmission power supply voltage V DD At this point, the pseudo-resistor exhibits an extremely high resistance, typically on the order of gigahertz. This can be achieved by adjusting the control signal φ. ctrl By adjusting the voltage level, the pseudo-resistor can switch between two impedance states, thereby changing the time constant of the integrator and controlling the DC servo loop to adaptively switch between the first and second modes.

[0029] Furthermore, both transistor M1 and transistor M2 are P-type transistors.

[0030] In an optional embodiment, such as Figure 1 As shown, the DC servo loop also includes an adaptive control module. The A port of the adaptive control module is connected to the inverted output of the ECG signal amplification unit and the second input of the dry sensor interface mismatch suppression module. The B port of the adaptive control module is connected to the forward output of the ECG signal amplification unit and the first input of the dry sensor interface mismatch suppression module. The adaptive control module is used to detect the amplitude of the differential amplified electrical signal and compare the amplitude of the differential amplified electrical signal with a preset voltage threshold. When the amplitude of the differential amplifier signal is greater than or equal to the preset voltage threshold, a high-level control signal φ is output. ctrl To the dry sensing interface mismatch suppression module, to control the DC servo loop to enter the first mode; When the amplitude of the differential amplifier signal is less than the preset voltage threshold, a low-level control signal φ is output. ctrl The dry sensing interface mismatch suppression module is used to control the DC servo loop to enter the second mode.

[0031] Specifically, the adaptive control module is the decision-making unit in the DC servo loop, used to monitor the output status of the ECG signal amplification unit in real time and switch the loop's operating mode accordingly. Port A of the adaptive control module is connected to the inverting output of the ECG signal amplification unit and the second input of the dry sensor interface mismatch suppression module, while port B is connected to the forward output of the ECG signal amplification unit and the first input of the dry sensor interface mismatch suppression module, thus enabling direct acquisition of the differential amplified electrical signal. The adaptive control module controls the amplitude of the differential amplified electrical signal (i.e., V output from the forward output of the ECG signal amplification unit). OUT+ V output from the inverting output terminal OUT- The absolute value of the difference, that is, the amplitude of the differential amplified electrical signal, is |V. OUT+ -V OUT- |) Perform real-time detection and compare the amplitude with a preset voltage threshold, and generate a corresponding control signal φ based on the comparison result. ctrl This drives the dry sensing interface mismatch suppression module to switch between two operating modes.

[0032] When the amplitude of the differential amplified electrical signal is greater than or equal to the preset voltage threshold, it indicates that the dry interface offset voltage has not been effectively suppressed, and a large offset component still exists at the output of the ECG signal amplification unit. At this time, the adaptive control module outputs a high-level control signal φ. ctrl The dry interface mismatch suppression module controls the DC servo loop to enter the first mode. When the amplitude of the differential amplified electrical signal is less than the preset voltage threshold, it indicates that the dry interface mismatch voltage has been basically canceled, and the output of the ECG signal amplification unit is considered to have returned to normal. At this time, the adaptive control module outputs a low-level control signal DC servo, controlling the DC servo loop to enter the second mode.

[0033] In an optional embodiment, such as Figure 4 As shown, the adaptive control module includes: Comparator U1 and comparator U2, the positive input terminal of comparator U1 is connected to port A and the negative input terminal is connected to port B, the positive input terminal of comparator U2 is connected to port B and the negative input terminal is connected to port A; The input of the NOR gate is connected to the output of comparator U1 and comparator U2. The inverter INV has its input connected to the output of a NOR gate, and its output connected to a dry sensing interface mismatch suppression module.

[0034] Specifically, the adaptive control module consists of comparator U1, comparator U2, a NOR gate, and an inverter INV. The positive input of comparator U1 is connected to port A, and the negative input is connected to port B, used to detect whether the differential amplified signal exceeds the negative limit. The positive input of comparator U2 is connected to port B, and the negative input is connected to port A, used to detect whether the differential amplified signal exceeds the positive limit. The outputs of comparators U1 and U2 are respectively connected to the two inputs of the NOR gate. The NOR gate performs a logical OR-NOT operation on the outputs of comparators U1 and U2. When either comparator detects an over-limit, the NOR gate outputs a low level. The output of the NOR gate is connected to the input of the inverter INV. The inverter INV inverts the output signal of the NOR gate and uses it as the control signal φ. ctrl The output is sent to the dry sensing interface mismatch suppression module. Through this circuit structure, regardless of whether the differential amplified electrical signal exceeds the limit in the positive or negative direction, the adaptive control module can output the corresponding control signal to realize the adaptive switching of the DC servo loop between the first mode and the second mode.

[0035] Furthermore, comparators U1 and U2 have the same structure; both are threshold-offset hysteresis comparators, such as... Figure 5 As shown, comparators U1 and U2 both include switches K2, K3, K4, K5, K6, K7, and capacitor C. a1 Capacitor C a2 Fully differential operational amplifier G c and a D flip-flop, where: In comparator U1, one end of switch K2 is connected to the inverting output of the ECG signal amplification unit, and one end of switch K5 is connected to the positive output of the ECG signal amplification unit; in comparator U2, one end of switch K2 is connected to the positive output of the ECG signal amplification unit, and one end of switch K5 is connected to the inverting output of the ECG signal amplification unit. One end of switch K3 is connected to the positive reference voltage V. refp Terminal, to receive positive reference voltage V refp One end of switch K4 is connected to the negative reference voltage V. refn Terminal, to receive negative reference voltage V refn The other ends of switches K2 and K3 are connected to capacitor C. a1 One end of switch K4 and the other end of switch K5 are connected to capacitor C. a2 One end of the capacitor C a1 The other end is connected to the fully differential operational amplifier G. c The positive input terminal, capacitor C a2 The other end is connected to the fully differential operational amplifier G. cThe inverting input terminal of the amplifier is connected to switch K6, which is connected to the fully differential operational amplifier G. c Switch K7 is connected between the positive input and the inverting output of the fully differential operational amplifier G. c Between the inverting input and the non-inverting output of the fully differential operational amplifier G c The positive output terminal is connected to the input terminal of the D flip-flop. The clock terminal of the D flip-flop receives the latched phase signal φ after a delay from the compared phase signal φ1. 1d The output of the D flip-flop is connected to a NOR gate, where the positive reference voltage V is... refp and negative reference voltage V refn Satisfying relation: V refp = -V refn =1 / 2V ref V ref The threshold offset voltages of comparators U1 and U2 are given; therefore, the preset voltage threshold is equal to the threshold offset voltage V. ref V ref =V refp -V refn .

[0036] Specifically, such as Figure 6 As shown, the comparison phase signal φ1 is the clock phase signal that controls the comparator to enter the comparison / sampling stage. Specifically, it is achieved by closing switches K2 and K5 and opening switches K6 and K7, thereby enabling the fully differential operational amplifier G... c Enter open-loop comparison mode. Latch the phase signal φ. 1d The clock phase signal φ1 is delayed by τ d The clock phase signal after that. φ2 is the reset / sampling phase signal, used to control the fully differential operational amplifier G. c Entering the reset / sampling state closes switches K3, K4, K6, and K7, while opening switches K2 and K5, thereby transferring the positive reference voltage V. refp and negative reference voltage V refn Sampled to capacitor C a1 and capacitor C a2 The clock phase signal.

[0037] When the clock phase signal φ2 is high (reset phase), the adaptive control module is in a reset state. At this time, switches K6 and K7 are closed, and the fully differential operational amplifier G... c In the buffer connection mode of negative feedback, the positive input terminal is shorted to the inverting output terminal, and the inverting input terminal is shorted to the positive output terminal, forming a negative feedback closed loop. At this time, the fully differential operational amplifier G... cBoth the positive and negative input terminals are at AC ground potential, meaning these two terminals are grounded in the small-signal model. Simultaneously, switches K3 and K4 are closed, while switches K2 and K5 are open, causing capacitor C to... a1 Charged to positive reference voltage V refp Capacitor C a2 Charged to negative reference voltage V refn The D flip-flop latches the phase signal φ. 1d The output V of the D flip-flop is not yet triggered (or is low). Dout Maintaining the latched state from the previous cycle ensures that subsequent logic circuits are not affected by the current reset phase. This stage establishes the comparator input signals and prepares the charge for accurate comparison in the next cycle. When the comparison phase signal φ1 is high (comparison phase), the adaptive control module is in the comparison state, and the fully differential operational amplifier G... c When the fully differential operational amplifier G is in open-loop operation, c When the positive input terminal is greater than or equal to the inverting input terminal, the positive output terminal outputs a high level, which is sent to the D terminal (data input terminal) of the D flip-flop. The fully differential operational amplifier G... c When the positive input terminal is smaller than the negative input terminal, the positive output terminal outputs a low level, and the D flip-flop samples a low level. At the instant of switching between the comparison phase signal φ1 and the clock phase signal φ2, because the voltage across the capacitor cannot change abruptly, the capacitor C... a1 Capacitor C a2 The voltage across the capacitor C remains constant. a1 The voltage on it is still the positive reference voltage V. refp Capacitor C a2 The voltage on it is still the negative reference voltage V. refn At the same time, the switch states change: switches K2 and K5 are closed, while switches K3 and K4 are open, causing capacitor C to... a1 The left plate is connected to the positive input voltage V. in+ Capacitor C a2 The left plate is connected to the reverse input voltage V. in- Based on the characteristic of maintaining the voltage across a capacitor, the fully differential operational amplifier G... c The positive input voltage becomes V in+ -V refp The voltage at the inverting input terminal becomes V. in- -V refn Therefore, the comparator's decision condition is: when V in+ -V refp ≥V in- -V refn When V is high, the comparator outputs a high level; when V is high, the comparator outputs a high level. in+ -V refp <Vin- -V refn When the threshold offset voltage satisfies the relationship V, the comparator outputs a low level. refp =-V refn =1 / 2V ref Therefore, when V in+ -V in- ≥V ref When V is high, the comparator outputs a high level; when V is high, the comparator outputs a high level. in+ -V in- <V ref When the comparator outputs a low level, the comparator outputs a low level. Therefore, this comparator achieves ±V... ref For the threshold offset comparison function, its equivalent hysteresis window width is 2V. ref The comparator's output is fed into the D terminal of the D flip-flop. The comparison phase signal φ1 is delayed by τ. d Then a latched phase signal φ is generated. 1d This delay ensures that after the comparison phase signal φ1 is pulled high, the fully differential operational amplifier G... c Sufficient time is allowed to establish a stable comparison result, which is then latched by the D flip-flop to the phase signal φ. 1d The result is latched on the rising edge, thereby preventing metastability or glitches from interfering with subsequent logic. The threshold offset voltage V in this embodiment... ref This is set by external circuitry to control the allowable equivalent dry interface residual dry interface offset voltage. The absolute value of this residual dry interface offset voltage is equal to V. ref / (C IN / C FB ), where C IN For the input capacitor, C FB As a feedback capacitor, by adjusting V ref Alternatively, the capacitance ratio can be used to flexibly configure the circuit's tolerance to dry interface offset voltage. In one optional embodiment, such as Figure 2 As shown, the ECG signal amplification unit includes a first-stage amplification module and a second-stage amplification module for sequentially performing first-stage and second-stage amplification of the input electrical signal, as well as an inter-stage coupling module, a common-mode bias module, and a chopper switch CH2, wherein: The first-stage amplification module includes a first-stage transconductance amplifier G. m1 Pseudo-resistance R p1 and pseudo resistor R p2 First-stage transconductance amplifier G m1 The positive and negative input terminals are respectively connected to differential capacitors C. DSL2 The output terminal and differential capacitor C DSL1 The output terminal, pseudo resistor R p1 Connected to the first-stage transconductance amplifier G m1The pseudo resistor R is located between the positive input terminal and the inverting output terminal. p2 Connected to the first-stage transconductance amplifier G m1 Between the inverting input and the positive output; Interstage coupling module includes coupling capacitor C RR1 and coupling capacitor C RR2 Coupling capacitor C RR1 Connected to the first-stage transconductance amplifier G m1 The coupling capacitor C is located between the inverting output terminal and the first input terminal of the chopper switch CH2. RR2 Connected to the first-stage transconductance amplifier G m1 Between the positive output terminal and the second input terminal of the chopper switch CH2; The common-mode bias module includes a pseudo-resistor R. p3 and pseudo resistor R p4 pseudo-resistance R p3 Connected to the first input terminal of chopper switch CH2 and common-mode level V CM Between the terminals, the pseudo-resistance R p4 Connected to the second input terminal of chopper switch CH2 and common-mode level V CM Between ends; The second-stage amplification module includes a second-stage transconductance amplifier G. m2 First RC Miller compensation module and second RC Miller compensation module, second-stage transconductance amplifier G m2 The positive input terminal is connected to the first output terminal of chopper switch CH2, and the negative input terminal is connected to the second output terminal of chopper switch CH2. The first RC Miller compensation module is connected to the second stage transconductance amplifier G. m2 The second RC Miller compensation module is connected between the positive input and the inverting output terminals of the second-stage transconductance amplifier G. m2 Between the inverting input and the non-inverting output, the second-stage transconductance amplifier G... m2 The positive output terminal is connected to a threshold-controlled two-state pseudo resistor R. T1 The input terminal of the second-stage transconductance amplifier G m2 The inverting output terminal is connected to a threshold-controlled two-state pseudo resistor R. T2 The input terminal, and the second-stage transconductance amplifier G m2 The positive and negative output terminals output differential amplified electrical signals.

[0038] Specifically, the ECG signal amplification unit adopts a two-stage amplification architecture, consisting of a first-stage amplification module, an interstage coupling module, a chopper switch CH2, a common-mode bias module, and a second-stage amplification module connected sequentially. The first-stage amplification module amplifies the input electrical signal, and its output signal is transmitted to the chopper switch CH2 via the interstage coupling module. The chopper switch CH2 operates at the chopping clock signal φ. chUnder the control of [unclear], the signal is demodulated, restoring the signal modulated to the chopper frequency to the baseband frequency. The common-mode bias module provides a stable DC operating point for the input node of the chopper switch CH2, ensuring that the input common-mode level of the second-stage amplifier module is within a reasonable range. The demodulated signal is finally input to the second-stage amplifier module for second-stage amplification, and differential amplified electrical signals are output from the positive and negative output terminals of the second-stage amplifier module.

[0039] Furthermore, the pseudo-resistance R p1 Pseudo-resistance R p2 Pseudo-resistance R p3 and pseudo resistor R p4 They all have the same structure and are ordinary pseudo-resistors, such as Figure 7 As shown, the pseudo resistor R p1 Pseudo-resistance R p2 Pseudo-resistance R p3 and pseudo resistor R p4 Both transistors include transistors M3 and M4. The sources of transistors M3 and M4 are shorted to their respective substrates, thus providing a defined voltage to the substrates. During operation, the source-substrate voltage V of transistors M3 and M4... BS The value is always 0 to ensure that the drain-substrate PN junction of transistors M3 and M4 will not be broken down. The gates of transistors M3 and M4 are connected and no longer have any electrical connection with other components. The drains of transistors M3 and M4 are connected. The sources of transistors M3 and M4 serve as the two ports of a pseudo-resistor, connected in the circuit as resistive electronic components.

[0040] Furthermore, both transistors M3 and M4 are P-type transistors.

[0041] Furthermore, the first RC Miller compensation module and the second RC Miller compensation module form a symmetrical RC frequency compensation network. For example... Figure 2 As shown, the first RC Miller compensation module includes resistors R connected in series. m1 and capacitor C m1 The second RC Miller compensation module includes resistors R connected in series. m2 and capacitor C m2 .

[0042] In an optional embodiment, such as Figure 1 and Figure 2 As shown, the dry sensing interface mismatch suppression circuit in this embodiment further includes a modulation coupling unit, which includes a chopper switch CH1. The ECG signal amplification unit also includes a capacitor C. IN1 and capacitor C IN2 The first and second output terminals of the chopper switch CH1 are respectively connected to capacitor C. IN1 The input terminal and capacitor CIN2 The input terminal, capacitor C IN1 The output terminal and capacitor C IN2 The output terminals are respectively connected to the first-stage transconductance amplifier G. m1 The positive and negative input terminals.

[0043] Specifically, the input terminal of the chopper switch CH1 receives a superimposed dry interface offset voltage V. EDO The bioelectrical signal, and in the chopper clock signal φ ch Under the control of [unclear], the signal is modulated to the chopping frequency, shifting the dry interface offset voltage and ECG signal, originally in the low-frequency range, to a higher frequency range, thus avoiding interference from low-frequency flicker noise and intrinsic offset voltage of components. The modulated signal is output from the first and second output terminals of chopper switch CH1 to capacitor C respectively. IN1 and capacitor C IN2 The input terminal. Capacitor C IN1 and capacitor C IN2 The output terminals are respectively connected to the first-stage transconductance amplifier G. m1 The positive and negative input terminals transmit the input electrical signal to the first-stage amplifier module via AC coupling.

[0044] In an optional embodiment, such as Figure 2 As shown, the ECG signal amplification unit includes a capacitor C that provides negative feedback. FB1 Capacitor C FB2 The first and second input terminals of chopper switch CH3 are respectively connected to the second-stage transconductance amplifier G. m2 The positive and negative output terminals of the chopper switch CH3 are connected to capacitor C respectively. FB1 The input terminal and capacitor C FB2 The input terminal, capacitor C FB1 The output terminal and capacitor C FB2 The output terminals are respectively connected to the first-stage transconductance amplifier G. m1 The positive and negative input terminals.

[0045] The DC servo loop in this invention achieves adaptive and rapid suppression and steady-state maintenance of dry interface offset voltage through the coordinated operation of the dry interface mismatch suppression module and the adaptive control module. The dry interface mismatch suppression module, as the core processing unit of the DC servo loop, extracts, processes, and cancels the dry interface offset voltage. The integrator in this module utilizes its extremely low cutoff frequency to selectively extract the amplified dry interface offset voltage from the differential amplified electrical signal, while effectively suppressing useful ECG signals. Through integration processing, it generates a compensation voltage with amplitude related to but opposite polarity to the dry interface offset voltage, aligning the compensation voltage with the main path signal in frequency. The modulated compensation voltage is then fed back to the input of the ECG signal amplification unit via cross-coupling, forming negative feedback cancellation. Through this complete signal processing link, the dry interface mismatch suppression module can establish an effective compensation voltage within milliseconds, quickly suppress the dry interface mismatch voltage, and maintain extremely low residual mismatch in the steady state phase. This ensures that the ECG signal amplification unit can amplify the useful ECG signal normally without being affected by the dry interface mismatch voltage, significantly improving the signal quality and reliability of wearable ECG acquisition devices.

[0046] This invention utilizes an adaptive control module in a DC servo loop to detect the amplitude of the differential amplified electrical signal in real time and automatically switch operating modes based on the relationship between the amplitude and a preset voltage threshold. When the dry interface offset voltage is large, the DC servo loop operates with a first time constant, and the integrator rapidly accumulates charge, establishing a compensation voltage within milliseconds to quickly suppress the dry interface offset voltage. Once the dry interface offset voltage is suppressed, the DC servo loop switches to a second time constant, ensuring that the ECG signal amplification unit has a lower cutoff frequency below the lowest frequency component of the useful ECG signal. This maintains a steady state after the dry interface offset voltage is canceled while ensuring that the useful ECG signal remains unaffected. This adaptive dual-mode switching mechanism overcomes the shortcomings of traditional fixed-time-constant schemes, which cannot simultaneously meet the requirements of rapid establishment and steady-state maintenance.

[0047] This invention employs a threshold-controlled dual-state pseudo-resistor to switch impedance between hundreds of ohms and gigahertz. Combined with chopper modulation feedback and a threshold offset hysteresis comparator, it achieves an ultra-wide time constant range, precise feedback cancellation, and reliable bidirectional mode switching. This effectively overcomes the shortcomings of traditional fixed-time-constant schemes, which cannot simultaneously meet the requirements of rapid setup and steady-state maintenance, significantly improving the signal quality of wearable ECG acquisition devices. A threshold-controlled dual-state pseudo-resistor composed of two P-type transistors is used as a variable impedance element. By controlling the gate voltage to switch between low and high impedance states, a very large impedance dynamic range is achieved. Combined with a differential integrating capacitor, the integrator's time constant can switch between milliseconds and tens of seconds, enabling rapid establishment of the compensation voltage in the first mode and achieving a lower cutoff frequency below 0.05Hz in the second mode, meeting the national standard requirements for ECG signal acquisition. Furthermore, the pseudo-resistor structure is simple and occupies a small chip area, making it suitable for the miniaturization requirements of wearable ECG acquisition devices.

[0048] The adaptive control module of this invention employs two identical threshold offset hysteresis comparators, cross-connected to achieve bidirectional detection. This ensures accurate mode switching regardless of whether the differential amplified electrical signal exceeds the limit in the positive or negative direction. The comparators' built-in hysteresis effectively prevents frequent mode switching near the threshold due to noise interference, improving system stability. Furthermore, the use of switched capacitor technology for threshold offset eliminates the need for an additional resistor divider network, saving chip area.

[0049] The ECG signal amplification unit in this invention employs a two-stage fully differential amplification architecture. Through the coordinated operation of the first-stage amplification module, inter-stage coupling module, chopper switch CH2, common-mode bias module, and second-stage amplification module, high-quality amplification of the input electrical signal is achieved. The chopper switch CH2 in this ECG signal amplification unit demodulates the signal amplified by the first stage, restoring the signal modulated to the chopper frequency to the baseband frequency. Simultaneously, it demodulates the signal from the first-stage transconductance amplifier G... m1 The intrinsic offset voltage and flicker noise are modulated to the chopping frequency for subsequent filtering, effectively suppressing the impact of the amplifier circuit's own low-frequency noise and offset on signal quality. The common-mode bias module provides a stable DC operating point for the second-stage amplifier module, ensuring the amplifier maintains linear operation over a wide dynamic range. The frequency compensation network, composed of the first and second RC Miller compensation modules, is used in the second-stage transconductance amplifier G... m2 Introducing a zero into the closed-loop frequency response cancels out the phase lag caused by the dominant poles of the amplifier in the high-frequency range, effectively extending the bandwidth of the amplifier and improving the closed-loop stability.

[0050] The ECG signal amplification unit, dry sensor interface mismatch suppression module, and adaptive control module of this invention all adopt a fully differential symmetrical structure design. Key components (such as the threshold-controlled dual-state pseudo-resistor R in the variable impedance module) are designed with a fully differential symmetrical structure. T1 and threshold-controlled two-state pseudo-resistance R T2 Integrating capacitor C INTD1 and integrating capacitor C INTD2 Differential capacitor C DSL1 and differential capacitor C DSL2 The first and second RC Miller compensation modules, among others, appear in pairs and are structurally symmetrical. This symmetrical design effectively suppresses common-mode interference, improves the common-mode rejection ratio of the circuit, and ensures the quality of ECG signal acquisition.

[0051] In the description of this invention, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0052] Although the invention has been described herein in conjunction with various embodiments, those skilled in the art will understand and implement other variations of the disclosed embodiments by reviewing the accompanying drawings, disclosure, and appended claims in carrying out the claimed invention. In the claims, the word "comprising" does not exclude other components or steps, and "a" or "an" does not exclude a plurality. A single processor or other unit can implement several functions listed in the claims. While different dependent claims may recite certain measures, this does not mean that these measures cannot be combined to produce good results.

[0053] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, any modifications made without departing from the inventive concept should be considered within the scope of protection of the present invention.

Claims

1. A dry sensing interface mismatch suppression circuit for wearable ECG acquisition devices, characterized in that, include: The electrocardiogram signal amplification unit is used to amplify the input electrical signal containing the useful electrocardiogram signal to obtain a differential amplified electrical signal; A DC servo loop is used to adaptively switch between a first mode and a second mode according to the relationship between the amplitude of the differential amplified electrical signal and a preset voltage threshold, and to feed back a compensation voltage with the opposite polarity to the dry interface offset voltage to the input of the ECG signal amplification unit to counteract the dry interface offset voltage. In the first mode, the DC servo loop operates with a first time constant to establish the compensation voltage to suppress the dry interface offset voltage. In the second mode, the DC servo loop operates with a second time constant to make the ECG signal amplification unit have a lower cutoff frequency lower than the lowest frequency component of the useful ECG signal to maintain the steady state after the dry interface offset voltage is canceled. The first time constant is smaller than the second time constant.

2. The dry sensing interface mismatch suppression circuit according to claim 1, characterized in that, The DC servo loop includes a dry sensor interface mismatch suppression module. The first input terminal of the dry sensor interface mismatch suppression module is connected to the positive output terminal of the ECG signal amplification unit, and the second input terminal is connected to the negative output terminal of the ECG signal amplification unit. The dry interface mismatch suppression module is used to extract the amplified dry interface mismatch voltage from the differential amplified electrical signal, process the amplified dry interface mismatch voltage to generate a compensation voltage with opposite polarity to the dry interface mismatch voltage, modulate the compensation voltage to a preset frequency to obtain a modulated compensation voltage, and couple the modulated compensation voltage to the ECG signal amplification unit to cancel the dry interface mismatch voltage.

3. The dry sensing interface mismatch suppression circuit according to claim 2, characterized in that, The dry sensing interface mismatch suppression module includes: An integrator, the positive input of which is connected to the positive output of the ECG signal amplification unit, and the negative input of which is connected to the negative output of the ECG signal amplification unit, is used to extract the amplified dry interface offset voltage from the differential amplified electrical signal, and to integrate the amplified dry interface offset voltage to generate an integrated voltage related to the amplitude of the amplified dry interface offset voltage, which serves as the compensation voltage. Chopper switch CH4, the first input terminal and the second input terminal of chopper switch CH4 are respectively connected to the positive output terminal and the negative output terminal of the integrator, and are used to modulate the compensation voltage to a preset frequency to obtain the modulated compensation voltage; Differential capacitor C DSL1 and differential capacitor C DSL2 The differential capacitor C DSL1 and the differential capacitor C DSL2 The input terminals are respectively connected to the first and second output terminals of the chopper switch CH4, and the differential capacitor C DSL1 The output terminal is connected to the inverting input terminal of the ECG signal amplification unit, and the differential capacitor C DSL2 The output terminal is connected to the positive input terminal of the ECG signal amplification unit, and is used to couple the modulated compensation voltage to the positive and negative input terminals of the ECG signal amplification unit to cancel the dry interface offset voltage.

4. The dry sensing interface mismatch suppression circuit according to claim 3, characterized in that, The integrator includes: A variable impedance module, wherein the first input terminal and the second input terminal of the variable impedance module are respectively connected to the positive output terminal and the reverse output terminal of the ECG signal amplification unit, and are used to adjust the impedance value of the variable impedance module according to the relationship between the amplitude of the differential amplified electrical signal and the preset voltage threshold, and convert the received amplified dry interface offset voltage into an integral current. Includes operational amplifier G mD1 Integrating capacitor C INTD1 and integrating capacitor C INTD2 The integration module, the operational amplifier G mD1 The positive and negative input terminals are respectively connected to the first and second output terminals of the variable impedance module, and the operational amplifier G... mD1 The positive and negative output terminals are connected to the input terminals of the chopper switch CH4, and the integrating capacitor C INTD1 The two ends are respectively connected to the operational amplifier G mD1 The positive input terminal and the negative output terminal, the integrating capacitor C INTD2 The two ends are respectively connected to the operational amplifier G mD1 The inverting input terminal and the positive output terminal are used to accumulate charge on the integral current to generate an integral voltage as the compensation voltage. Among them, based on the impedance value of the variable impedance module and the integrating capacitor C INTD1 and the integrating capacitor C INTD2 The relationship between the capacitance values ​​causes the time constant of the integrator to switch between the first time constant and the second time constant, thereby controlling the DC servo loop to switch between the first mode and the second mode.

5. The dry sensing interface mismatch suppression circuit according to claim 4, characterized in that, The variable impedance module includes a threshold-controlled two-state pseudo-resistor R with the same structure. T1 and threshold-controlled two-state pseudo-resistance R T2 The threshold-controlled two-state pseudo-resistor R T1 The input terminal is connected to the positive output terminal of the ECG signal amplification unit, and the output terminal is connected to the operational amplifier G. mD1 The positive input terminal of the threshold-controlled two-state pseudo-resistor R T2 The input terminal is connected to the inverting output terminal of the ECG signal amplification unit, and the output terminal is connected to the operational amplifier G. mD1 The inverting input terminal; The threshold-controlled dual-state pseudo-resistor R T1 and the threshold-controlled two-state pseudo-resistor R T2 Each includes transistor M1, transistor M2, and single-pole double-throw switch K1, wherein: The sources of transistors M1 and M2 serve as input and output terminals, respectively. The source of transistor M1 is shorted to its substrate, and the source of transistor M2 is shorted to its substrate. The drain of transistor M1 is connected to the drain of transistor M2. The gates of transistors M1 and M2 are interconnected and controlled by a control signal φ via a single-pole double-throw switch K1. ctrl ; When the control signal φ ctrl When the voltage is high, the gates of transistors M1 and M2 are connected to a fixed voltage V. R Terminal, so that the threshold-controlled two-state pseudo-resistor R T1 and the threshold-controlled two-state pseudo-resistor R T2 In the first impedance state; when the control signal φ ctrl When the voltage is low, the gates of transistor M1 and M2 are connected to the power supply voltage, so that the threshold-controlled dual-state pseudo-resistor R... T1 and the threshold-controlled two-state pseudo-resistor R T2 In the second impedance state, where the fixed voltage V R Less than the power supply voltage V DD The impedance value of the first impedance state is less than the impedance value of the second impedance state.

6. The dry sensing interface mismatch suppression circuit according to claim 2, characterized in that, The DC servo loop also includes an adaptive control module. Port A of the adaptive control module is connected to the inverted output of the ECG signal amplification unit and the second input of the dry sensor interface mismatch suppression module. Port B of the adaptive control module is connected to the forward output of the ECG signal amplification unit and the first input of the dry sensor interface mismatch suppression module. The adaptive control module is used to detect the amplitude of the differential amplified electrical signal and compare the amplitude of the differential amplified electrical signal with the preset voltage threshold. When the amplitude of the differential amplified electrical signal is greater than or equal to the preset voltage threshold, a high-level control signal φ is output. ctrl The dry sensing interface mismatch suppression module is used to control the DC servo loop to enter the first mode. When the amplitude of the differential amplified electrical signal is less than the preset voltage threshold, a low-level control signal φ is output. ctrl The dry sensing interface mismatch suppression module is then used to control the DC servo loop to enter the second mode.

7. The dry sensing interface mismatch suppression circuit according to claim 6, characterized in that, The adaptive control module includes: Comparator U1 and comparator U2, wherein the positive input terminal of comparator U1 is connected to port A and the inverting input terminal is connected to port B, and the positive input terminal of comparator U2 is connected to port B and the inverting input terminal is connected to port A; A logic NOR gate, the input of which is connected to the output of comparator U1 and comparator U2; Inverter INV, the input of which is connected to the output of the logic NOR gate, and the output is connected to the dry sensing interface mismatch suppression module.

8. The dry sensing interface mismatch suppression circuit according to claim 7, characterized in that, The comparator U1 and the comparator U2 have the same structure, both including switches K2, K3, K4, K5, K6, K7, and capacitor C. a1 Capacitor C a2 Fully differential operational amplifier G c and a D flip-flop, where: In comparator U1, one end of switch K2 is connected to the inverting output of the ECG signal amplification unit, and one end of switch K5 is connected to the positive output of the ECG signal amplification unit; in comparator U2, one end of switch K2 is connected to the positive output of the ECG signal amplification unit, and one end of switch K5 is connected to the inverting output of the ECG signal amplification unit. One end of the switch K3 is connected to a positive reference voltage V. refp One end of the switch K4 is connected to the negative reference voltage V. refn One end of switch K2 and the other end of switch K3 are connected to capacitor C. a1 One end of the switch K4 and the other end of the switch K5 are connected to the capacitor C. a2 One end of the capacitor C a1 The other end is connected to the fully differential operational amplifier G. c The positive input terminal of the capacitor C a2 The other end is connected to the fully differential operational amplifier G. c The inverting input terminal of the fully differential operational amplifier G is connected to the switch K6. c The switch K7 is connected between the positive input terminal and the inverting output terminal of the fully differential operational amplifier G. c Between the inverting input and the non-inverting output of the fully differential operational amplifier G c The positive output terminal is connected to the input terminal of the D flip-flop, and the clock terminal of the D flip-flop receives the latched phase signal φ after a delay of the compared phase signal φ1. 1d The output of the D flip-flop is connected to the NOR gate, where the positive reference voltage V... refp and negative reference voltage V refn Satisfying relation: V refp = -V refn =1 / 2V ref V ref The threshold offset voltages of the comparator U1 and the comparator U2.

9. The dry sensing interface mismatch suppression circuit according to claim 1, characterized in that, The ECG signal amplification unit includes a first-stage amplification module and a second-stage amplification module for sequentially performing first-stage and second-stage amplification of the input electrical signal, as well as an inter-stage coupling module, a common-mode bias module, and a chopper switch CH2, wherein: The first-stage amplification module includes a first-stage transconductance amplifier G. m1 Pseudo-resistance R p1 and pseudo-resistance R p2 The pseudo resistor R p1 Connected to the first stage transconductance amplifier G m1 The pseudo resistor R is located between the positive input terminal and the negative output terminal. p2 Connected to the first stage transconductance amplifier G m1 Between the inverting input and the positive output; The interstage coupling module includes a coupling capacitor C. RR1 and coupling capacitor C RR2 The coupling capacitor C RR1 Connected to the first stage transconductance amplifier G m1 Between the inverting output terminal and the first input terminal of the chopper switch CH2, the coupling capacitor C RR2 Connected to the first stage transconductance amplifier G m1 Between the positive output terminal and the second input terminal of the chopper switch CH2; The common-mode bias module includes a pseudo-resistor R. p3 and pseudo-resistance R p4 The pseudo resistor R p3 The pseudo-resistor R is connected between the first input terminal and the common-mode level terminal of the chopper switch CH2. p4 Connected between the second input terminal and the common-mode level terminal of the chopper switch CH2; The second-stage amplification module includes a second-stage transconductance amplifier G. m2 The first RC Miller compensation module and the second RC Miller compensation module, and the second stage transconductance amplifier G m2 The positive input terminal is connected to the first output terminal of the chopper switch CH2, and the negative input terminal is connected to the second output terminal of the chopper switch CH2. The first RC Miller compensation module is connected to the second stage transconductance amplifier G. m2 The second RC Miller compensation module is connected between the positive input terminal and the inverting output terminal of the second-stage transconductance amplifier G. m2 Between the inverting input and the non-inverting output, the second-stage transconductance amplifier G... m2 The differential amplified electrical signal is output from the positive and negative output terminals.

10. The dry sensing interface mismatch suppression circuit according to claim 9, characterized in that, It also includes a modulation coupling unit, which includes a chopper switch CH1, and the ECG signal amplification unit also includes a capacitor C. IN1 and capacitor C IN2 The first and second output terminals of the chopper switch CH1 are respectively connected to the capacitor C. IN1 The input terminal and the capacitor C IN2 The input terminal of the capacitor C IN1 The output terminal and the capacitor C IN2 The output terminals are respectively connected to the first stage transconductance amplifier G. m1 The positive and negative input terminals; The electrocardiogram signal amplification unit includes capacitor C. FB1 Capacitor C FB2 The chopper switch CH3, wherein the first and second input terminals of the chopper switch CH3 are respectively connected to the second stage transconductance amplifier G. m2 The positive and negative output terminals of the chopper switch CH3 are respectively connected to the capacitor C. FB1 The input terminal and the capacitor C FB2 The input terminal of the capacitor C FB1 The output terminal and the capacitor C FB2 The output terminals are respectively connected to the first stage transconductance amplifier G. m1 The positive and negative input terminals.

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