A radio frequency power supply sampling and control circuit

Abstract

The application provides a kind of radio frequency power supply sampling and control circuit, it is related to radio frequency sampling technical field, including directional coupler sampling module and control module, directional coupler sampling module includes nickel zinc magnetic ring current transformer, multistage capacitor voltage division voltage sampling network and sampling signal processing unit, nickel zinc magnetic ring current transformer is used to collect two-way differential current sampling signal, multistage capacitor voltage division voltage sampling network is used to collect radio frequency high voltage working voltage sampling signal, sampling signal processing unit is used to carry out phase calibration compensation, load effect elimination, high-frequency peak detection and low-pass smooth filtering respectively to two-way differential current sampling signal and radio frequency high voltage working voltage sampling signal, obtain two-way standard differential sampling signal, control module is used to compare given reference value and two-way standard differential sampling signal, carry out proportional integral adjustment by PI control, and carry out cross limiting amplitude interlock, obtain control signal.The application can stably carry out sampling and control.

Description

Technical Field

[0001] This invention relates to the field of radio frequency sampling technology, and more specifically, to a radio frequency power supply sampling and control circuit. Background Technology

[0002] Radio frequency (RF) power supplies are specialized industrial power supply devices that convert industrial frequency AC power into high-frequency alternating current power ranging from 1MHz to 30MHz. The mainstream industrial frequency is 13.56MHz, and they are widely used in precision processes such as semiconductor etching, thin film sputtering, plasma treatment, and industrial RF heating. During RF operation, the load impedance is highly susceptible to sudden changes due to process variations, arcing, and dielectric fluctuations, which can generate significant reflected voltages. These voltages can easily damage the core components of the power amplifier and disrupt production. Therefore, it is essential to collect incident and reflected RF voltage / current signals in real time through RF sampling, accurately calculate the output power and reflected power, and then construct a closed-loop control system based on the control circuit.

[0003] In related technologies, RF power supplies generally adopt a digital sampling control scheme with high-speed AD chips and embedded main controllers, relying on analog-to-digital conversion and software PID algorithms to complete power acquisition, closed-loop regulation, and stepped waveform output. However, this scheme has many links and large signal conversion delays, achieving only millisecond-level response and a control bandwidth of less than 100 Hz, making it difficult to quickly suppress reflected high voltages caused by load changes. At the same time, digital circuits are susceptible to noise interference in the complex electromagnetic environment of RF, resulting in distorted sampling data and waveform jitter. Traditional directional couplers lack temperature control and calibration structures, and the temperature drift of magnetic rings and capacitors will reduce sampling accuracy over a long period. Furthermore, the single-loop independent control architecture separates steady-state power control from overload protection, easily causing power oscillations when the load is mismatched, requiring the power amplifier to be shut down for protection. In addition, the entire set of digital hardware components is numerous and the circuits are complex, resulting in high equipment costs and subsequent maintenance pressure. A few simple analog control schemes have low filter cutoff frequencies and poor dynamic response performance, which also cannot meet the stringent requirements of plasma and semiconductor processes for high-speed, high-precision, and continuous production. Summary of the Invention

[0004] The present invention aims to solve at least one of the above-mentioned problems.

[0005] To address the aforementioned problems, this invention provides an RF power supply sampling and control circuit, comprising a directional coupler sampling module and a control module. The directional coupler sampling module includes a nickel-zinc magnetic ring current transformer, a multi-stage capacitive voltage divider sampling network, and a sampling signal processing unit. Both the nickel-zinc magnetic ring current transformer and the multi-stage capacitive voltage divider sampling network are connected to the sampling signal processing unit. The nickel-zinc magnetic ring current transformer is used to acquire two differential current sampling signals from the main output circuit of the RF power amplifier. The multi-stage capacitor voltage divider sampling network is used to acquire the RF high voltage operating voltage sampling signal from the main output circuit of the power amplifier. The sampling signal processing unit is used to perform phase calibration compensation, load effect elimination, high-frequency peak detection, and low-pass smoothing filtering on the two differential current sampling signals and the RF high voltage operating voltage sampling signals according to the built-in circuit, so as to obtain two standard differential sampling signals. The control module is used to compare the given reference value with the two standard differential sampling signals, perform proportional-integral adjustment through PI control, and perform cross-limiting interlocking to obtain the control signal.

[0006] Optionally, the built-in circuit of the sampling signal processing unit includes a phase lead compensation capacitor, two processing branches, an incident voltage differential amplifier unit, and a reflected voltage differential amplifier unit. The two ends of the phase lead compensation capacitor are respectively connected to the input terminals of the two processing branches. The output terminals of the two processing branches are respectively connected to the input terminals of the incident voltage differential amplifier unit and the reflected voltage differential amplifier unit. The output terminals of the incident voltage differential amplifier unit and the reflected voltage differential amplifier unit are respectively connected to the input terminal of the control module. The two processing branches are used to receive the corresponding two differential current sampling signals and the radio frequency high voltage operating voltage sampling signal. Each processing branch includes a phase lag calibration network, a high-frequency Schottky diode, and a low-pass smoothing filter network connected in sequence. The phase lag calibration network includes a fixed capacitor, an adjustable phase lag calibration capacitor, and a fixed resistor. One end of each of the fixed capacitor, the adjustable phase lag calibration capacitor, and the fixed resistor is connected to the processing branch, and the other end is grounded at a common point.

[0007] Optionally, the low-pass smoothing filter network includes a filter inductor, a first conditioning resistor, a second conditioning resistor, a third conditioning resistor, a fourth conditioning resistor, and a filter capacitor. The filter inductor, the first conditioning resistor, and the second conditioning resistor are connected in series to the processing branch. One end of the third conditioning resistor and one end of the filter capacitor are connected between the first conditioning resistor and the second conditioning resistor. The other end of the third conditioning resistor, the other end of the filter capacitor, and one end of the fourth conditioning resistor are grounded at the same point. The output of the second conditioning resistor in one of the processing branches is connected to the first pin of the incident voltage differential amplifier unit, and the other end of the fourth conditioning resistor is connected to the second pin of the incident voltage differential amplifier unit. The output of the second conditioning resistor in another processing branch is connected to the first pin of the reflected voltage differential amplifier unit, and the other end of the fourth conditioning resistor is connected to the second pin of the reflected voltage differential amplifier unit.

[0008] Optionally, the multi-stage capacitor voltage divider sampling network includes a first capacitor voltage divider sampling sub-network and a second capacitor voltage divider sampling sub-network, and the first capacitor voltage divider sampling sub-network and the second capacitor voltage divider sampling sub-network are respectively connected to the corresponding processing branches; The first capacitor voltage divider sampling sub-network includes a first voltage divider capacitor and a second voltage divider capacitor. One end of the first voltage divider capacitor is connected to the main output circuit of the power amplifier, and the other end is connected between the corresponding high-frequency Schottky diode and the low-pass smoothing filter network. One end of the second voltage divider capacitor is connected between the corresponding high-frequency Schottky diode and the low-pass smoothing filter network, and the other end is grounded. The second capacitor voltage divider sampling subnetwork includes a third voltage divider capacitor and a fourth voltage divider capacitor. One end of the third voltage divider capacitor is connected to the main output circuit of the power amplifier, and the other end is connected between the corresponding high-frequency Schottky diode and the low-pass smoothing filter network. One end of the fourth voltage divider capacitor is connected between the corresponding high-frequency Schottky diode and the low-pass smoothing filter network, and the other end is grounded.

[0009] Optionally, the sampling signal processing unit further includes a first load effect elimination isolation resistor and a second load effect elimination isolation resistor. The first load effect elimination isolation resistor is connected in parallel across the first voltage divider capacitor, and the second load effect elimination isolation resistor is connected in series between the first voltage divider capacitor and the fourth voltage divider capacitor.

[0010] Optionally, the sampling signal processing unit further includes a first voltage sampling voltage division ratio adjustment capacitor and a second voltage sampling voltage division ratio adjustment capacitor, wherein the first voltage sampling voltage division ratio adjustment capacitor is connected in parallel across the second voltage division capacitor, and the second voltage sampling voltage division ratio adjustment capacitor is connected in parallel across the fourth voltage division capacitor.

[0011] Optionally, the control module includes an incident voltage error adder, an incident voltage PI controller, an incident voltage limiter, a reflected voltage error adder, a reflected voltage PI controller, a reflected voltage limiter, and a dual-loop cross-limiting unit. An incident voltage error adder, an incident voltage PI controller, and an incident voltage limiter are connected in sequence. A reflected voltage error adder, a reflected voltage PI controller, and a reflected voltage limiter are also connected in sequence. The incident voltage error adder receives the incident voltage setpoint from a given reference value and the incident voltage feedback value from two standard differential sampling signals. The reflected voltage error adder receives the reflected voltage setpoint from a given reference value and the reflected voltage feedback value from two standard differential sampling signals. The outputs of both the incident voltage limiter and the reflected voltage limiter are connected to the input of a dual-loop cross-limiting unit. The dual-loop cross-limiting unit outputs a control signal, and the output of the incident voltage limiter is connected to the input of the reflected voltage limiter, and the output of the reflected voltage limiter is connected to the input of the incident voltage limiter.

[0012] Optionally, the control module includes multiple high-speed operational amplifiers, high-speed switching transistors, and Schottky diodes.

[0013] Optionally, the RF power supply sampling and control circuit further includes a multiplier unit, a DDS unit, and a power amplifier unit. The input terminal of the multiplier unit is connected to the control module and the DDS unit, respectively. The output terminal of the multiplier unit is connected to the input terminal of the power amplifier unit, and the output terminal of the power amplifier unit is connected to the directional coupler sampling module.

[0014] Optionally, the RF power supply sampling and control circuit also includes a constant temperature control unit. The constant temperature control unit includes a temperature detection and sensing subunit and a constant temperature drive control subunit. The temperature detection and sensing subunit is used to collect the real-time operating temperature of the directional coupler sampling module, and the constant temperature drive control subunit is used to dynamically adjust the working state of the temperature actuator according to the real-time operating temperature.

[0015] The beneficial effects of the radio frequency power sampling and control circuit of the present invention are: A directional coupler sampling module, comprising a nickel-zinc magnetic ring current transformer, a multi-stage capacitive voltage divider sampling network, and a sampling signal processing unit, is employed. First, the nickel-zinc magnetic ring current transformer acquires two differential current sampling signals from the main output circuit of the power amplifier, while the multi-stage capacitive voltage divider sampling network acquires the RF high-voltage operating voltage sampling signal from the main output circuit. Leveraging the stable high-frequency permeability and low high-frequency loss of the nickel-zinc magnetic ring, high-precision coupling acquisition of the high-frequency RF current is achieved. Simultaneously, the capacitive voltage divider principle ensures the synchronous correspondence between voltage and current sampling, providing an accurate raw sampling basis for subsequent incident and reflected signal processing. Next, the sampling signal processing unit sequentially performs phase calibration compensation, load effect elimination, high-frequency peak detection, and low-pass smoothing filtering on the two differential current sampling signals and the RF high-voltage operating voltage sampling signal. Phase calibration compensation corrects the phase and amplitude deviations between the current and voltage sampling branches, ensuring precise alignment of voltage and current signals during detection. Load effect elimination isolates the sampling branches from the effects of parallel load absorption on the RF main circuit, eliminating inherent system errors caused by sampling amplitude attenuation and phase shift, thus improving the sampling results. For authenticity and accuracy, high-frequency peak detection can quickly convert high-frequency alternating radio frequency signals into DC analog signals. Low-pass smoothing filtering can filter out high-frequency noise and ripple interference superimposed on the signal, ultimately outputting two standard differential sampling signals. Relying on the anti-interference characteristics of differential signals, common-mode interference and signal crosstalk in complex radio frequency electromagnetic environments are suppressed, ensuring stable and distortion-free transmission of sampling signals. Finally, the control module compares the given reference value with the two standard differential sampling signals, completes proportional-integral adjustment through PI control, and obtains the control signal after performing cross-limiting interlocking. The entire process relies on pure analog hardware. Complete closed-loop operation without AD / DA signal conversion and digital algorithm processing. It ensures zero steady-state error and small dynamic response overshoot through PI regulation, and achieves smooth priority switching between steady-state control of incident signal and overload limiting of reflected signal through cross-limiting interlock, avoiding power jumps and oscillations during control switching. The overall control link has extremely low latency, achieving μs-level dynamic response and hundreds of kHz-level control bandwidth. It solves the technical problems of slow response and low bandwidth of existing digital sampling control schemes, as well as unstable switching and protection lag under load mismatch in traditional single-loop control. Attached Figure Description

[0016] Figure 1 This is a schematic diagram of the structure of the radio frequency power supply sampling and control circuit provided in an embodiment of the present invention; Figure 2 This is a schematic diagram of the structure of the directional coupler sampling module provided in an embodiment of the present invention; Figure 3 This is a schematic diagram of the incident voltage signal conditioning and error amplification unit provided in an embodiment of the present invention; Figure 4This is a schematic diagram of the structure of the reflected voltage signal conditioning and error amplification unit provided in an embodiment of the present invention; Figure 5 This is a schematic diagram of the structure of the dual-loop cross-limiting and PI adjustment unit provided in an embodiment of the present invention; Figure 6 This is a schematic diagram of the structure of the PI regulator limiting unit provided in an embodiment of the present invention; Figure 7 This is a schematic diagram of the structure of the loop control signal proportional unit provided in an embodiment of the present invention; Figure 8 This is a schematic diagram of the incident given signal buffer conditioning circuit provided in an embodiment of the present invention; Figure 9 This is a schematic diagram of the structure of the reflection given signal buffer conditioning circuit provided in an embodiment of the present invention.

[0017] Explanation of reference numerals in the attached figures: 101. Incident voltage error adder; 102. Incident voltage PI controller; 103. Incident voltage limiter; 104. Reflected voltage error adder; 105. Reflected voltage PI controller; 106. Reflected voltage limiter; 107. Dual-loop cross-limiting unit; 108. Multiplier unit; 109. Power amplifier unit; 110. Incident voltage differential amplifier unit; 111. Reflected voltage differential amplifier unit. Detailed Implementation

[0018] To make the above-mentioned objects, features, and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings. Although some embodiments of the present invention are shown in the drawings, it should be understood that the present invention can be implemented in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided to provide a more thorough and complete understanding of the present invention. It should be understood that the accompanying drawings and embodiments of the present invention are for illustrative purposes only and are not intended to limit the scope of protection of the present invention.

[0019] The term "comprising" and its variations as used herein are open-ended, meaning "including but not limited to"; the term "based on" means "at least partially based on"; the term "one embodiment" means "at least one embodiment"; the term "another embodiment" means "at least one additional embodiment"; the term "some embodiments" means "at least some embodiments"; and the term "optionally" means "optional embodiments". Definitions of other terms will be given in the following description. It should be noted that the concepts of "first," "second," etc., mentioned in this invention are used only to distinguish different devices, modules, or units, and are not intended to limit the order of functions performed by these devices, modules, or units or their interdependencies.

[0020] It should be noted that the terms "a" and "a plurality of" used in this invention are illustrative rather than restrictive. Those skilled in the art should understand that, unless otherwise expressly indicated in the context, they should be understood as "one or more".

[0021] The names of the messages or information exchanged between the multiple devices in the embodiments of the present invention are for illustrative purposes only and are not intended to limit the scope of these messages or information.

[0022] like Figure 1 As shown in the figure, an embodiment of the present invention provides an RF power supply sampling and control circuit, including a directional coupler sampling module and a control module. The directional coupler sampling module includes a nickel-zinc magnetic ring current transformer, a multi-stage capacitive voltage divider sampling network and a sampling signal processing unit. The nickel-zinc magnetic ring current transformer and the multi-stage capacitive voltage divider sampling network are both connected to the sampling signal processing unit. The nickel-zinc magnetic ring current transformer is used to acquire two differential current sampling signals from the main output circuit of the RF power amplifier. The multi-stage capacitor voltage divider sampling network is used to acquire the RF high voltage operating voltage sampling signal from the main output circuit of the power amplifier. The sampling signal processing unit is used to perform phase calibration compensation, load effect elimination, high-frequency peak detection, and low-pass smoothing filtering on the two differential current sampling signals and the RF high voltage operating voltage sampling signals according to the built-in circuit, so as to obtain two standard differential sampling signals. The control module is used to compare the given reference value with the two standard differential sampling signals, perform proportional-integral adjustment through PI control, and perform cross-limiting interlocking to obtain the control signal.

[0023] Specifically, the system comprises a directional coupler sampling module and a control module. The directional coupler sampling module integrates a nickel-zinc magnetic ring current transformer CT1, a multi-stage capacitive voltage divider sampling network, and a sampling signal processing unit. The outputs of both the nickel-zinc magnetic ring current transformer and the multi-stage capacitive voltage divider sampling network are connected to the input of the sampling signal processing unit, jointly completing the acquisition and preprocessing of the RF power signal. In actual operation, the nickel-zinc magnetic ring current transformer is connected in series within the main output circuit of the RF power supply's amplifier. Leveraging the stable permeability, high coupling accuracy, and low loss characteristics of nickel-zinc material under high-frequency conditions, the RF operating current of the main circuit is acquired in real time via electromagnetic coupling, synchronously outputting two differential current sampling signals. The differential output format can initially suppress common-mode interference during transmission, ensuring the integrity and synchronization of the current sampling signal. A multi-stage capacitor voltage divider sampling network is connected in parallel to the main output circuit of the power amplifier. The RF high voltage operating voltage of the main circuit is proportionally reduced and sampled using the capacitor voltage divider principle to obtain the RF high voltage operating voltage sampling signal. The voltage sampling and current sampling maintain strict time synchronization, providing the original sampling basis with phase and amplitude correspondence for the subsequent calculation of incident and reflected signals. After receiving two differential current sampling signals and an RF high-voltage operating voltage sampling signal, the sampling signal processing unit performs four types of signal processing in sequence: First, phase calibration compensation, adjusting the phase offset between the current branch and the voltage branch to ensure precise phase alignment of the two signals, avoiding system errors in subsequent detection operations caused by phase deviation; Second, load effect elimination, isolating the influence of the sampling branch's own impedance on the parallel load absorption of the power amplifier's output main circuit, avoiding impedance mismatch, sampling amplitude attenuation, and phase distortion caused by the sampling branch connection, thus eliminating inherent system sampling errors at their source; Third, high-frequency peak detection, converting the high-frequency alternating RF AC signal into a DC analog voltage signal, and calculating the corresponding incident and reflected power sampling original signals through hardware calculations; Fourth, low-pass smoothing filtering, filtering out high-frequency noise, ripple, and pulse interference superimposed on the detected signal, outputting a clean DC sampling signal, and converting it into two standard differential sampling signals for transmission to the control module. The control module receives a given reference value from an external input and two standard difference sampling signals obtained from sampling. First, the two are fed into an error comparison stage for difference calculation. The resulting error signal is then controlled by a PI controller to achieve proportional-integral regulation. The proportional stage responds quickly to error changes, while the integral stage eliminates steady-state error, balancing dynamic speed and steady-state accuracy. The two regulated signals then enter a cross-limiting interlock stage to achieve dynamic priority switching between steady-state control of the incident signal and overload limiting of the reflected signal. Under normal operating conditions, the incident control branch dominates, while the reflection branch is on standby for monitoring. When the reflected signal exceeds the limit, the limiting interlock mechanism instantly switches the control authority, forcibly pulling down the output control signal, ultimately outputting a stable control signal for subsequent power amplifier control.This embodiment can achieve RF power sampling and closed-loop control through a pure analog hardware architecture, without the need for digital sampling and software algorithm processing. It features low control link latency, achieving μs-level dynamic response and hundreds of kHz-level control bandwidth. At the same time, it improves sampling accuracy through phase calibration, load effect elimination, and filtering. It achieves smooth switching between steady-state power control and overload protection through dual-loop cross-limiting, avoiding power jumps and oscillations during the regulation process, and improving the stability and reliability of the RF power supply.

[0024] In this embodiment, a directional coupler sampling module comprising a nickel-zinc magnetic ring current transformer, a multi-stage capacitive voltage divider sampling network, and a sampling signal processing unit is employed. First, the nickel-zinc magnetic ring current transformer acquires two differential current sampling signals from the main output circuit of the power amplifier, while the multi-stage capacitive voltage divider sampling network acquires the RF high-voltage operating voltage sampling signal from the main output circuit of the power amplifier. Leveraging the stable high-frequency permeability and low high-frequency loss of the nickel-zinc magnetic ring, high-precision coupling acquisition of the high-frequency RF current is achieved. Simultaneously, the capacitive voltage divider principle ensures the synchronous correspondence between voltage and current sampling, providing an accurate original sampling basis for subsequent incident and reflected signal processing. Then, the sampling signal processing unit sequentially performs phase calibration compensation, load effect elimination, high-frequency peak detection, and low-pass smoothing filtering on the two differential current sampling signals and the RF high-voltage operating voltage sampling signal. Phase calibration compensation corrects the phase and amplitude deviations between the current and voltage sampling branches, ensuring accurate alignment of voltage and current signals during detection. Load effect elimination isolates the sampling branches from the parallel load absorption effect on the RF main circuit, eliminating inherent system errors caused by sampling amplitude attenuation and phase shift, thus improving sampling accuracy. The authenticity and accuracy of the results are ensured by high-frequency peak detection, which can quickly convert high-frequency alternating radio frequency signals into DC analog signals. Low-pass smoothing filtering can remove high-frequency noise and ripple interference superimposed on the signal, ultimately outputting two standard differential sampling signals. Relying on the anti-interference characteristics of differential signals, common-mode interference and signal crosstalk in complex radio frequency electromagnetic environments are suppressed, ensuring stable and distortion-free transmission of the sampling signals. Finally, the control module compares the given reference value with the two standard differential sampling signals, completes proportional-integral adjustment through PI control, and obtains the control signal after cross-limiting interlocking. The entire process relies on pure analog. The hardware completes the closed-loop operation without the need for AD / DA signal conversion and digital algorithm processing. It ensures zero steady-state error and small overshoot in dynamic response through PI regulation, and achieves smooth priority switching between steady-state control of incident signal and overload limiting of reflected signal through cross-limiting interlock, avoiding power jumps and oscillations during control switching. The overall control link has extremely low latency, achieving μs-level dynamic response and hundreds of kHz-level control bandwidth. It solves the technical problems of slow response and low bandwidth of existing digital sampling control schemes, as well as unstable switching and protection lag in traditional single-loop control when load mismatch occurs.

[0025] Optionally, the built-in circuit of the sampling signal processing unit includes a phase lead compensation capacitor, two processing branches, an incident voltage differential amplifier unit, and a reflected voltage differential amplifier unit. The two ends of the phase lead compensation capacitor are respectively connected to the input terminals of the two processing branches. The output terminals of the two processing branches are respectively connected to the input terminals of the incident voltage differential amplifier unit and the reflected voltage differential amplifier unit. The output terminals of the incident voltage differential amplifier unit and the reflected voltage differential amplifier unit are respectively connected to the input terminal of the control module. The two processing branches are used to receive the corresponding two differential current sampling signals and the radio frequency high voltage operating voltage sampling signal. Each processing branch includes a phase lag calibration network, a high-frequency Schottky diode, and a low-pass smoothing filter network connected in sequence. The phase lag calibration network includes a fixed capacitor, an adjustable phase lag calibration capacitor, and a fixed resistor. One end of each of the fixed capacitor, the adjustable phase lag calibration capacitor, and the fixed resistor is connected to the processing branch, and the other end is grounded at a common point.

[0026] Specifically, such as Figure 2 As shown, the built-in circuit of the sampling signal processing unit includes a phase lead compensation capacitor L1, two independent processing branches, an incident voltage differential amplifier unit 110, and a reflected voltage differential amplifier unit 111. The two ends of the phase lead compensation capacitor L1 are connected to the input terminals of the two processing branches, respectively. The output terminals of the two processing branches are connected to the input terminals of the incident voltage differential amplifier unit 110 and the reflected voltage differential amplifier unit 111, respectively. The output terminals of the incident voltage differential amplifier unit 110 and the reflected voltage differential amplifier unit 111 are connected to the input terminals of the control module. The two processing branches respectively receive the two differential current sampling signals output from the nickel-zinc magnetic ring current transformer, namely CT1-P and CT1-N in the two differential current sampling signals, and the RF high-voltage working voltage sampling signal RE-OUT. Each processing branch consists of a phase lag calibration network and a high-frequency Schottky diode (i.e.,...). Figure 2 The current sampling network consists of a fixed capacitor (VD1 or VD2) and a low-pass smoothing filter network connected in series. A phase lead compensation capacitor L1 is connected across the input of the two differential current sampling branches to provide overall phase lead compensation for the current sampling signals. This compensates for the inherent phase lag caused by the current transformer and subsequent circuits, allowing the initial phase of the current signal to initially match the phase reference of the voltage sampling signal, providing a basis for fine-grained phase calibration within the branch. Each processing branch's phase lag calibration network includes a fixed capacitor (i.e., VD1 or VD2). Figure 2 C6 or C9), adjustable phase hysteresis calibration capacitor (i.e. Figure 2 The C2 or C10 of the JZ400 series and the fixed resistor (i.e. Figure 2The three resistors (R4 or R9) are connected in parallel at one end to the signal link of the corresponding processing branch, and the other end is grounded at the same point. This network forms a continuously adjustable phase shift hysteresis network through the combination of resistors and capacitors. The adjustable phase hysteresis calibration capacitor can change the phase hysteresis of a single branch by adjusting its own capacitance value. The staff can calibrate the adjustable capacitor according to the actual sampling phase deviation to accurately correct the phase shift of the current sampling signal in the branch. Together with the phase lead compensation capacitor L1 at the front end, the phase difference between the current sampling branch and the voltage sampling branch is accurately reduced to zero, ensuring that the voltage signal and the current signal are completely aligned during subsequent detection operations, and avoiding errors in the calculation of incident and reflected power due to phase deviation. After phase calibration, the sampled signal is fed into a high-frequency Schottky diode. Leveraging the Schottky diode's fast high-frequency response, low on-state voltage, and low high-frequency loss, the envelope of the high-frequency radio frequency signal is extracted using peak detection. This rapidly converts the high-frequency alternating AC signal into a DC analog voltage signal corresponding to the signal peak value. The original DC sampled signals corresponding to the incident and reflected voltages are directly obtained through hardware calculations, eliminating the need for additional digital computation and ensuring real-time signal conversion. The detected signal is then fed into a low-pass smoothing filter network to remove residual high-frequency carrier components and spurious interference, outputting a stable DC sampled signal. The sampled signals output from the two processing branches are fed into the incident voltage differential amplifier unit 110 and the reflected voltage differential amplifier unit 111, respectively, and converted into standard differential sampled signals RF-F and RF-R. Simultaneously, these signals are transmitted to the input of the control circuit via differential long-line anti-interference transmission. Utilizing the inherent anti-interference characteristics of differential transmission, common-mode interference and high-frequency signal crosstalk in complex radio frequency electromagnetic environments are effectively suppressed, ensuring accurate and stable control signal transmission. This embodiment achieves precise phase alignment of current and voltage sampling signals through a two-stage phase adjustment structure of phase lead compensation and branch phase lag calibration, thereby improving the accuracy of detection and solution. At the same time, it uses high-frequency Schottky diodes for peak detection to ensure the response speed and accuracy of high-frequency signal conversion. Combined with differential amplification output, it enhances the signal's anti-interference capability, further improving the accuracy and stability of the sampling process and providing a reliable sampling basis for subsequent closed-loop control.

[0027] Optionally, the low-pass smoothing filter network includes a filter inductor, a first conditioning resistor, a second conditioning resistor, a third conditioning resistor, a fourth conditioning resistor, and a filter capacitor. The filter inductor, the first conditioning resistor, and the second conditioning resistor are connected in series to the processing branch. One end of the third conditioning resistor and one end of the filter capacitor are connected between the first conditioning resistor and the second conditioning resistor. The other end of the third conditioning resistor, the other end of the filter capacitor, and one end of the fourth conditioning resistor are grounded at the same point. The output of the second conditioning resistor in one of the processing branches is connected to the first pin of the incident voltage differential amplifier unit, and the other end of the fourth conditioning resistor is connected to the second pin of the incident voltage differential amplifier unit. The output of the second conditioning resistor in another processing branch is connected to the first pin of the reflected voltage differential amplifier unit, and the other end of the fourth conditioning resistor is connected to the second pin of the reflected voltage differential amplifier unit.

[0028] Specifically, such as Figure 2 As shown, the low-pass smoothing filter network includes a filter inductor (i.e., Figure 2 L2 or L3), the first conditioning resistor (i.e. Figure 2 R2 or R7), the second conditioning resistor (i.e. Figure 2 R3 or R8), the third conditioning resistor (i.e. Figure 2 R5 or R11), the fourth conditioning resistor (i.e. Figure 2 R6 or R12) and filter capacitors (i.e. Figure 2The filter inductor (C5 or C8), the first conditioning resistor, and the second conditioning resistor are connected in series in the main signal link of the processing branch. One end of the third conditioning resistor and the filter capacitor are connected to the node between the first and second conditioning resistors. The other end of the third conditioning resistor, the other end of the filter capacitor, and one end of the fourth conditioning resistor are grounded at the same point, forming an LC-RC combined cascaded low-pass filter structure. In actual operation, the filter inductor is connected in series at the front end of the signal link. Utilizing the characteristic of the inductor to pass DC and block AC, it firstly suppresses the high-frequency carrier component in the detected signal, forming a first-stage LC low-pass filter, which significantly attenuates the high-frequency noise energy. The signal after inductor filtering enters the voltage divider conditioning link formed by the first and second conditioning resistors. At the same time, it works with the RC filter branch formed by the third conditioning resistor and the filter capacitor to perform secondary filtering of the intermediate frequency ripple and spurious interference in the signal. The filter capacitor can form a low-impedance discharge path for AC noise, further smoothing the DC signal ripple and outputting a stable DC signal with minimal ripple. The fourth conditioning resistor is connected between the ground terminal and the second pin of the differential amplifier unit. It is used to provide a precise reference level for the differential amplifier unit, and at the same time match the impedance of the differential input port to ensure that the differential amplifier circuit operates in the optimal linear range and reduce signal distortion. Regarding the port connections, the output terminal of the second conditioning resistor of one processing branch is connected to the first pin of the incident voltage differential amplifier unit 110, and outputs a signal RF-FFp to the incident voltage differential amplifier unit 110. The other end of the fourth conditioning resistor of this branch is connected to the second pin of the incident voltage differential amplifier unit 110, and outputs a signal RF-FFn to the incident voltage differential amplifier unit 110, so that the incident voltage sampling signal is input to the amplifier unit in a fully differential form. The output terminal of the second conditioning resistor of the other processing branch is connected to the first pin of the reflected voltage differential amplifier unit 111, and outputs a signal RF-RFp to the reflected voltage differential amplifier unit 111. The other end of the fourth conditioning resistor of this branch is connected to the second pin of the reflected voltage differential amplifier unit 111, and outputs a signal RF-RFn to the reflected voltage differential amplifier unit 111, thus realizing the fully differential input of the reflected voltage sampling signal. This LC-RC cascaded low-pass filter structure offers a steeper cutoff characteristic compared to a single RC filter. It maintains a wider effective signal bandwidth while ensuring filtering performance, effectively filtering out high-frequency RF noise, switching pulse interference, and ripple noise to output a clean, stable, and noise-free DC sampling signal. It also avoids excessively lowering the cutoff frequency, which could slow down the dynamic response of the sampling signal, thus balancing filtering effectiveness and response speed. Furthermore, the combination of multiple conditioning resistors allows for flexible adjustment of the filter network's cutoff frequency and signal attenuation ratio, adapting to different sampling signal ranges. The differential input connection ensures precise impedance matching between the filter network and the differential amplifier unit, reducing signal reflection and loss and guaranteeing the accuracy of the sampled signal amplitude.This embodiment can achieve efficient filtering of the post-detection sampled signal through an LC-RC combined low-pass smoothing filter network, effectively filtering out high-frequency noise and ripple interference while maintaining good dynamic response performance. Combined with the precise impedance matching connection with the differential amplifier unit, it further improves the purity and amplitude accuracy of the sampled signal, providing a stable and low-noise sampling feedback signal for subsequent closed-loop control.

[0029] Optionally, the multi-stage capacitor voltage divider sampling network includes a first capacitor voltage divider sampling sub-network and a second capacitor voltage divider sampling sub-network, and the first capacitor voltage divider sampling sub-network and the second capacitor voltage divider sampling sub-network are respectively connected to the corresponding processing branches; The first capacitor voltage divider sampling sub-network includes a first voltage divider capacitor and a second voltage divider capacitor. One end of the first voltage divider capacitor is connected to the main output circuit of the power amplifier, and the other end is connected between the corresponding high-frequency Schottky diode and the low-pass smoothing filter network. One end of the second voltage divider capacitor is connected between the corresponding high-frequency Schottky diode and the low-pass smoothing filter network, and the other end is grounded. The second capacitor voltage divider sampling subnetwork includes a third voltage divider capacitor and a fourth voltage divider capacitor. One end of the third voltage divider capacitor is connected to the main output circuit of the power amplifier, and the other end is connected between the corresponding high-frequency Schottky diode and the low-pass smoothing filter network. One end of the fourth voltage divider capacitor is connected between the corresponding high-frequency Schottky diode and the low-pass smoothing filter network, and the other end is grounded.

[0030] Specifically, such as Figure 2 As shown, the multi-stage capacitive voltage divider sampling network includes a first capacitive voltage divider sampling sub-network and a second capacitive voltage divider sampling sub-network. The first and second capacitive voltage divider sampling sub-networks are respectively connected to their corresponding processing branches, providing independent voltage sampling references for the incident and reflected branches, respectively. The first capacitive voltage divider sampling sub-network includes a first voltage-dividing capacitor (i.e.,...) Figure 2 C1) and the second voltage divider capacitor (i.e. Figure 2 (C4) One end of the first voltage divider capacitor is connected to the main output circuit of the power amplifier to acquire the RF high-voltage operating voltage sampling signal RF-OUT, and the other end is connected to the node between the high-frequency Schottky diode and the low-pass smoothing filter network of the corresponding processing branch. One end of the second voltage divider capacitor is connected to the same node, and the other end is grounded; the second capacitor voltage divider sampling sub-network includes the third voltage divider capacitor (i.e., C4). Figure 2 C7) and the fourth voltage divider capacitor (i.e. Figure 2In the first sub-network, the first capacitor (C12) is connected to the main output circuit of the power amplifier. One end of the third capacitor is connected to the main output circuit to collect the RF high-voltage working voltage sampling signal RF-OUT. The other end is connected to the node between the high-frequency Schottky diode and the low-pass smoothing filter network in the corresponding processing branch. One end of the fourth capacitor is connected to the same node, and the other end is grounded. In actual operation, the RF high-voltage working voltage of the main output circuit of the power amplifier is applied to two sampling sub-networks simultaneously. Taking the first capacitor voltage divider sampling sub-network as an example, the first and second capacitors are connected in series to form a complete voltage divider branch. According to the inverse relationship between capacitance and voltage division, the high-amplitude RF voltage is proportionally reduced, converting the high-voltage RF signal of the main circuit into a low-amplitude voltage sampling signal suitable for processing by the back-end detection circuit. The voltage sampling signal is directly injected into the detection node of the processing branch and participates in the peak detection calculation together with the current sampling signal to solve the sampling signal corresponding to the incident voltage. The working principle of the second capacitor voltage divider sampling sub-network is exactly the same as that of the first sub-network. It provides the corresponding voltage sampling signal for the reflection branch and participates in the detection calculation of the reflected voltage. The structure employing a dual independent capacitor voltage divider sampling sub-network provides precisely matched voltage sampling signals for both the incident and reflected branches, avoiding signal attenuation and phase inconsistency issues caused by single-branch transmission. This ensures high consistency in amplitude and phase between the voltage sampling references of the two processing branches, improving the symmetry and accuracy of incident and reflected signal calculations. Furthermore, the capacitor voltage divider structure offers advantages such as low loss, fast response, and no DC bias at high frequencies, preventing the introduction of additional phase shifts and amplitude losses. It is compatible with high-frequency RF operating bands from 1MHz to 30MHz, enabling precise synchronous acquisition of transient voltage changes in the main circuit. This ensures time synchronization between voltage and current sampling, providing a reliable voltage reference for subsequent phase calibration and power calculation. This embodiment can provide voltage sampling signals for two processing branches through a dual independent capacitor voltage divider sampling sub-network, ensuring the consistency and synchronization of the sampling reference of the incident and reflection branches. At the same time, relying on the high-frequency characteristics of capacitor voltage divider, it can achieve low-loss and high-precision acquisition of high-voltage radio frequency signals, improve the accuracy and frequency band adaptability of voltage sampling, and provide a reliable voltage basis for accurate calculation of incident and reflected power.

[0031] Optionally, the sampling signal processing unit further includes a first load effect elimination isolation resistor and a second load effect elimination isolation resistor. The first load effect elimination isolation resistor is connected in parallel across the first voltage divider capacitor, and the second load effect elimination isolation resistor is connected in series between the first voltage divider capacitor and the fourth voltage divider capacitor.

[0032] Specifically, such as Figure 2 As shown, the sampling signal processing unit also includes a first load effect elimination isolation resistor (i.e., Figure 2 R1) and the second load effect elimination isolation resistor (i.e. Figure 2In this embodiment, a first load effect elimination isolation resistor (R10) is connected in parallel across the first voltage divider capacitor, and a second load effect elimination isolation resistor is connected in series between the third and fourth voltage divider capacitors. Because the high-frequency output main circuit of the RF power supply has stringent requirements for port impedance matching, if the sampling branch is directly connected to the main circuit, the input impedance of the sampling circuit itself will create an additional parallel load suction effect on the main circuit. This directly causes impedance mismatch at the RF output port, passively pulls down the RF voltage and current sampling amplitude, and causes phase distortion of the sampling signal, resulting in inherent sampling system errors. Ultimately, this leads to inaccurate power sampling values ​​and continuous drift in closed-loop control. This embodiment uses two dedicated isolation resistors to specifically suppress the load effects of the two voltage sampling sub-networks. Specifically, the first load effect elimination isolation resistor is connected in parallel across the first voltage divider capacitor, which increases the overall input impedance of the incident voltage sampling sub-network, raises the impedance threshold for the sampling branch to extract signals from the main circuit, weakens the parallel load suction effect of the downstream detection and filtering circuits on the main circuit, reduces the interference of the sampling branch connection on the main circuit's operating state, and avoids amplitude attenuation and phase shift in the incident voltage sampling. The second load effect elimination isolation resistor is connected in series between the third and fourth voltage divider capacitors. Through impedance isolation, it breaks the direct impedance coupling between the reflection branch sampling circuit and the main circuit, blocking the influence path of the downstream circuit impedance on the main circuit. Simultaneously, it works with the voltage divider capacitors to adjust the overall impedance of the sampling branch, matching it with the characteristic impedance of the main circuit, thus eliminating sampling errors caused by the load effect of the reflection branch. The two isolation resistors perform impedance matching and isolation for the incident and reflection sampling sub-networks respectively, specifically eliminating the load effect of the two branches. This ensures that the amplitude and phase of both sampled signals accurately reflect the actual operating state of the main circuit, eliminating system errors introduced by the sampling branches at the hardware level. After load effect elimination processing, the sampled signal can accurately reproduce the voltage and current characteristics of the main circuit, avoiding power calculation deviations caused by sampling load effects, improving the power sampling accuracy across the entire frequency band, and ensuring the stability of closed-loop control during long-term operation of the equipment. This embodiment can effectively isolate the impedance influence of the sampling back-end circuit on the main output circuit of the power amplifier by configuring dedicated load effect elimination isolation resistors in the two capacitor voltage divider sampling sub-networks, thereby eliminating the amplitude attenuation, phase shift and system sampling error caused by the load effect of the sampling branch, improving the authenticity and accuracy of the sampling signal, and ensuring the long-term accuracy and stability of power sampling and closed-loop control.

[0033] Optionally, the sampling signal processing unit further includes a first voltage sampling voltage division ratio adjustment capacitor and a second voltage sampling voltage division ratio adjustment capacitor, wherein the first voltage sampling voltage division ratio adjustment capacitor is connected in parallel across the second voltage division capacitor, and the second voltage sampling voltage division ratio adjustment capacitor is connected in parallel across the fourth voltage division capacitor.

[0034] Specifically, such as Figure 2As shown, the sampling signal processing unit also includes a first voltage sampling division ratio adjustment capacitor (i.e., Figure 2 C3) and the second voltage sampling voltage divider ratio adjustment capacitor (i.e. Figure 2 In the first voltage sampling voltage division ratio adjustment capacitor (C11), the first voltage sampling voltage division ratio adjustment capacitor is connected in parallel across the second voltage division capacitor, and the second voltage sampling voltage division ratio adjustment capacitor is connected in parallel across the fourth voltage division capacitor. The voltage division ratio of the capacitor voltage divider network is determined by the capacitance values ​​of the two capacitors connected in series. In actual production and assembly, capacitor components have inherent production variability, and the distributed capacitance of the circuit wiring also has a slight impact on the actual voltage division ratio, causing a deviation between the actual voltage division ratio of the two sampling sub-networks and the design value. This results in amplitude errors in the incident and reflected voltage sampling, affecting the accuracy of power calculation. This embodiment achieves accurate calibration of the voltage sampling voltage division ratio by configuring an adjustable voltage division ratio adjustment capacitor. In practical operation, the first voltage sampling voltage division ratio adjustment capacitor is connected in parallel across the second voltage division capacitor. This, together with the second voltage division capacitor, forms the total ground capacitance of the voltage division branch. By adjusting the capacitance of this adjustable capacitor, the total ground capacitance of the incident voltage sampling sub-network can be fine-tuned, thereby changing the capacitance ratio between the first voltage division capacitor and the total ground capacitance, achieving precise calibration of the incident branch voltage division ratio. Similarly, the second voltage sampling voltage division ratio adjustment capacitor is connected in parallel across the fourth voltage division capacitor, allowing for independent calibration of the reflected voltage sampling sub-network's voltage division ratio. During equipment debugging, operators can measure the actual output power using a standard power meter and adjust the capacitance of the two adjustable capacitors accordingly, comparing the sampled values ​​to ensure a precise correspondence between the sampled amplitudes of the incident and reflected voltages and the actual values, correcting amplitude deviations caused by device discreteness and distributed parameters. This adjustable voltage divider structure enables amplitude calibration of the sampled signal on top of phase calibration, ensuring amplitude matching between voltage and current sampling. Combined with the phase calibration network, it achieves dual alignment of phase and amplitude for both voltage and current sampling signals, significantly improving the accuracy of peak detection power calculation. Simultaneously, the two adjusting capacitors independently correspond to two branches, allowing for separate calibration of the incident and reflected sampling branches. This avoids mutual interference between the two sampling paths, ensuring consistency in sampling accuracy, improving sampling consistency and control precision during mass production, and reducing the difficulty of batch calibration. This embodiment, by configuring independent voltage divider ratio adjusting capacitors in the two capacitor voltage divider sampling sub-networks, precisely calibrates the voltage division ratio of voltage sampling, corrects amplitude errors caused by device discreteness and distributed parameters, and achieves dual accuracy in amplitude and phase of the sampled signal in conjunction with phase calibration. This improves the accuracy of power calculation and sampling consistency of batch products, ensuring the accuracy and stability of closed-loop control.

[0035] Optionally, the control module includes an incident voltage error adder, an incident voltage PI controller, an incident voltage limiter, a reflected voltage error adder, a reflected voltage PI controller, a reflected voltage limiter, and a dual-loop cross-limiting unit. An incident voltage error adder, an incident voltage PI controller, and an incident voltage limiter are connected in sequence. A reflected voltage error adder, a reflected voltage PI controller, and a reflected voltage limiter are also connected in sequence. The incident voltage error adder receives the incident voltage setpoint from a given reference value and the incident voltage feedback value from two standard differential sampling signals. The reflected voltage error adder receives the reflected voltage setpoint from a given reference value and the reflected voltage feedback value from two standard differential sampling signals. The outputs of both the incident voltage limiter and the reflected voltage limiter are connected to the input of a dual-loop cross-limiting unit. The dual-loop cross-limiting unit outputs a control signal, and the output of the incident voltage limiter is connected to the input of the reflected voltage limiter, and the output of the reflected voltage limiter is connected to the input of the incident voltage limiter.

[0036] Specifically, such as Figure 1As shown, the control module includes an incident voltage error adder 101, an incident voltage PI controller 102, an incident voltage limiter 103, a reflected voltage error adder 104, a reflected voltage PI controller 105, a reflected voltage limiter 106, and a dual-loop cross-limiting unit 107; the incident voltage error adder 101, the incident voltage PI controller 102, and the incident voltage limiter 103 are connected sequentially to form the incident control branch; the reflected voltage error adder 104 and the reflected voltage PI controller 105 are connected in a dual-loop cross-limiting unit 107. The incident voltage limiter 103 and the reflected voltage limiter 106 are connected in sequence to form a reflection control branch. The output terminals of both the incident voltage limiter 103 and the reflected voltage limiter 106 are connected to the input terminal of the dual-loop cross-limiting unit 107, which is used to output the final control signal. The output terminal of the incident voltage limiter 103 is connected to the input terminal of the reflected voltage limiter 106, and the output terminal of the reflected voltage limiter 106 is connected to the input terminal of the incident voltage limiter 103, forming a dual-loop hardware cross-limiting interlock architecture. During operation, the incident voltage error adder 101 receives the incident voltage setpoint Pg-F from the given reference value and the incident voltage feedback value RF-F from the two standard differential sampling signals. The adder calculates the error difference between the two values ​​and sends the error signal to the incident voltage PI controller 102 for proportional-integral regulation. The proportional element rapidly tracks error changes, improving dynamic response speed, while the integral element gradually eliminates steady-state error, ensuring the accuracy of steady-state control. The regulated signal is then sent to the incident voltage limiter 103 to constrain the upper and lower limits of the output amplitude of the incident control signal. The working principle of the reflection control branch is the same as that of the incident branch. The reflection voltage error adder 104 receives the reflection voltage setpoint Pg-R and the reflection voltage feedback value RF-R, which are then regulated by the reflection voltage PI controller 105 and sent to the reflection voltage limiter 106. Under normal load matching conditions, the reflected voltage is far below the protection threshold. The limiting signal output by the reflection control branch is in a non-triggered state, and the incident control branch dominates the output of the entire control loop. The dual-loop cross-limiting unit 107 outputs the corresponding control signal for the incident control, achieving precise closed-loop control of steady-state power. When abnormal situations such as load mismatch or arcing occur, and the reflected voltage spikes instantaneously above the threshold, the output signal of the reflection control branch triggers the limiting mechanism. Through the cross-connected hardware link, the output signal of the incident branch is instantaneously clamped, forcibly pulling down the final output control signal of the dual-loop cross-limiting unit 107, rapidly reducing the output power to suppress the reflected voltage. The entire switching process is implemented by pure hardware circuitry, requiring no software logic judgment and eliminating algorithm delay, achieving instantaneous limiting protection at the μs level. The cross-limiting interlock structure ensures that the switching process of the two branches is continuous and uninterrupted, without power jumps or control oscillations, achieving a smooth transition between steady-state power control and overload protection.This embodiment can achieve the coordinated operation of steady-state precise power control and rapid reflection overload protection through a hardware architecture with dual independent PI control branches for incident and reflection and cross-limiting interlock. It ensures power control accuracy under normal operating conditions and provides μs-level rapid limiting protection for power amplifier devices under abnormal operating conditions. The switching process is smooth without oscillation or power jump, balancing control accuracy and protection response speed, and improving the working reliability and continuous operation capability of the RF power supply.

[0037] Optionally, the control module includes multiple high-speed operational amplifiers, high-speed switching transistors, and Schottky diodes.

[0038] Specifically, the control module is constructed from multiple high-speed operational amplifiers, high-speed switching transistors, and Schottky diodes. All control functions are implemented using purely analog hardware circuitry, without the involvement of digital processing devices or software algorithms. The incident voltage error adder, reflected voltage error adder, and two PI controllers are all built using high-speed operational amplifiers paired with external passive resistor-capacitor components. The high-speed operational amplifiers possess extremely high unity-gain bandwidth and slew rate, enabling real-time, high-speed processing of error signals. This ensures the PI regulation loop achieves a response speed in the μs range while maintaining a loop control bandwidth in the hundreds of kHz range. This allows the entire control loop to quickly track changes in the given signal, adapting to the control requirements of rapidly changing process waveforms such as stepped waves, without exhibiting waveform lag or distortion. The incident voltage limiter, reflected voltage limiter, and cross-limiting interlock structure are constructed using high-speed switching transistors and Schottky diodes. The high-speed switching transistors have extremely short turn-on and turn-off times, enabling them to quickly switch on and off states instantly when the reflected voltage exceeds the limit, triggering the limiting mechanism. The Schottky diodes have low on-state voltage drop and extremely short reverse recovery time, allowing them to quickly conduct and form a clamping path during the limiting clamping process. This reduces signal deviation caused by the on-state voltage drop, ensuring the accuracy of the limiting threshold and preventing protection failure or power control deviation due to limiting level offset. The control module is built using fully discrete high-speed analog devices, enabling continuous-time signal modulation. It eliminates the sampling period discretization problem found in digital control schemes, transmitting and processing signals as continuous analog quantities throughout. The control link only has the inherent minute transmission delay of the devices, completely eliminating millisecond-level delays caused by AD conversion, digital computation, and DA output, achieving high-speed dynamic response of the loop from the root of the architecture. Meanwhile, the pure analog hardware architecture eliminates the need for expensive digital components such as high-speed AD sampling chips and embedded main controllers, as well as complex peripheral auxiliary circuits and software algorithms. This results in a simpler circuit structure, lower hardware costs, a lower failure rate, and easier maintenance. Furthermore, the all-analog hardware control link is unaffected by the susceptibility of digital signals to interference in high-frequency electromagnetic environments. Combined with differential sampling transmission at the front end, it can operate stably in complex RF electromagnetic environments, avoiding problems such as sampled data distortion, algorithm inaccuracies, and waveform distortion found in digital control schemes, thus improving the anti-interference capability and operational stability of the control loop. This embodiment can build a pure analog control module using high-speed operational amplifiers, high-speed switching transistors, and Schottky diodes, achieving μs-level ultrafast control response and hundreds of kHz-level loop bandwidth. It also boasts advantages such as simple structure, low cost, and strong anti-interference capability, ensuring both control accuracy and response speed while improving circuit reliability and ease of maintenance, making it suitable for industrial applications of high-frequency RF power supplies.

[0039] For example, the control module may consist of an incident voltage signal conditioning and error amplification unit, a reflected voltage signal conditioning and error amplification unit, a dual-loop cross-limiting and PI regulation unit, a PI regulator limiting unit, and a loop control signal proportional unit, to realize the functions of the incident voltage error adder 101, the incident voltage PI controller 102, the incident voltage limiter 103, the reflected voltage error adder 104, the reflected voltage PI controller 105, the reflected voltage limiter 106, and the dual-loop cross-limiting unit 107.

[0040] Among them, the incident voltage signal conditioning and error amplification unit is as follows: Figure 3 As shown, its inputs are RF-FFp and RF-FFn from the incident voltage feedback values, and the output is a single-ended signal RF-FF. This output includes resistors R16, R20, R13, and R26, capacitors C13, C18, C20, and C22, and the A-channel operational amplifier U1A in the LM6172IMX chip. One end of resistor R16 is connected to the input signal RF-FFp, and the other end is connected to the positive input pin of U1A. One end of R13 is connected to the positive input pin of U1A, and the other end is grounded. C13 is connected in parallel across R13. The positive power supply pin of U1A is connected to a positive 15V power supply and is connected to one end of C18. The other end of C18 is grounded. One end of resistor R20 is connected to the input signal RF-FF. The circuit consists of two terminals: one connected to the inverting input pin of U1A, and the other connected to the output pin of U1A. C22 is connected in parallel across R26. The negative power supply pin of U1A is connected to a -15V power supply and to one end of C20, while the other end of C20 is grounded. The incident voltage signal conditioning and error amplification unit performs error calculations on the given and feedback signals. Based on this, it provides front-end conditioning functionality for converting the differential feedback signal to a single-ended signal, ultimately completing the entire chain from differential incident feedback signal → single-ended signal → error amplification with the given signal.

[0041] The reflected voltage signal conditioning and error amplification unit, such as Figure 4As shown, its inputs are RF-RFp and RF-RFn from the reflected voltage feedback values, and the output is a single-ended signal RF-RF. This output includes resistors R41, R44, R39, and R47, capacitors C26, C28, C31, and C33, and the A-channel operational amplifier U3A in the LM6172IMX chip. One end of resistor R41 is connected to the input signal RF-RFp, and the other end is connected to the positive input pin of U3A. One end of R39 is connected to the positive input pin of U3A, and the other end is grounded. C26 is connected in parallel across R39. The positive power supply pin of U3A is connected to a positive 15V power supply and is connected to one end of C28. The other end of C28 is grounded. One end of resistor R44 is connected to the input signal RF-RF. The circuit consists of two terminals: one connected to the inverting input pin of U3A, and the other connected to the output pin of U3A. A capacitor C33 is connected in parallel across the two terminals of R47. The negative power supply pin of U3A is connected to a -15V power supply and to one end of a capacitor C31, with the other end of C31 grounded. The reflected voltage signal conditioning and error amplification unit performs error calculations on the given and feedback signals. Based on this, it provides front-end conditioning functionality for converting the differential feedback signal to a single-ended signal, ultimately completing the complete link from differential reflected feedback signal → single-ended signal → error amplification with the given signal.

[0042] Dual-loop cross-limiting and PI control unit, such as Figure 5As shown, it includes a first loop and a second loop. The input of the first loop is RF-FF and the incident setpoint, and the output is connected to the input of the loop control signal proportional unit. The input of the second loop is RF-RF and the reflection setpoint, and the output is connected to the first loop. The first circuit includes resistors R15, R19, R21, R24, R14, R29, R30, R35, R31, R32, and R34; capacitors C16, C14, C15, C19, and C21; the A-channel operational amplifier U2A, high-speed PNP transistors QP1 and QP2, and Schottky diode D1 from the LM6172IMX chip; the second circuit includes resistors R40, R43, R45, R46, R42, R50, R51, R57, R52, R53, and R54; capacitors C29, C27, and C30; the B-channel operational amplifier U3B, high-speed PNP transistors QP3 and QP4, and Schottky diode D2 from the LM6172IMX chip. One end of R19 is connected to the input signal RF-RF, and the other end is connected to the negative input pin of U2A. R15 and C16 are connected in series and in parallel across R19. One end of R21 is used to receive the incident setpoint, and the other end is connected to the negative input pin of U2A. The positive input pin of U2A is grounded. One end of R24 is connected to a positive 8V power supply, and the other end is connected to the negative input pin of U2A. One end of C14 and C15 are both connected to the negative input pin of U2A. The other end of C15 is connected to one end of R14. The other end of C14 and the other end of R14 are connected together to the output pin of U2A, i.e., C15 and R14 are connected in series. C13 is connected in parallel across C15 and R14. The negative power supply pin of U2A is connected to a negative 8V power supply and is connected to one end of C19. The other end of C19 is grounded. The positive power supply pin of U2A is connected to a positive 8V power supply and is connected to one end of C21. The connection is as follows: the other end of C21 is grounded; the E pin of QP1 is connected to the negative input pin of U2A; the C pin is connected to one end of R30 at the same point to the negative 8V power supply; the other end of R30 is connected to the B pin of QP1; one end of R29 is connected to the B pin of QP1; the other end is connected to the E pin of QP2 at the same point to the output pin of U2A; one end of R35 is connected to the negative input pin of U2A; the other end is connected to the C pin of QP2; one end of R31 is connected to the B pin of QP2; the other end is connected to one end of R32, one end of R34, and the input terminal of D1; the other end of R32 is connected to the output pin of U3B; the other end of R34 is connected to the negative 8V power supply; the output terminal of D1 and the output terminal of D2 are connected at the same point to the output pin of U4A of the PI regulator limiting unit; the output pin of U2A and R53 of the second loop are connected at the same point to one end of R22 of the loop control signal proportional unit.One end of R43 is connected to the input signal RF-RF, and the other end is connected to the negative input pin of U3B. R40 and C29 are connected in series and in parallel across R43. One end of R45 is used to receive the reflected setpoint, and the other end is connected to the negative input pin of U3B. The positive input pin of U3B is grounded. One end of R46 is connected to the positive 8V power supply, and the other end is connected to the negative input pin of U3B. One end of C27 and C30 are both connected to the negative input pin of U3B. The other end of C30 is connected to one end of R42. The other end of C27 and the other end of R42 are connected together to the output pin of U3B, i.e., C30 and R42 are connected in series, and C27 is connected in parallel across C30 and R42. The E pin of QP3 is connected to the negative input pin of U3B. The circuit is structured as follows: pin C is connected to one end of R51, which is then connected to a negative 8V power supply. The other end of R51 is connected to pin B of QP3. One end of R50 is connected to pin B of QP3, and the other end is connected to pin E of QP4, which is then connected to the output pin of U3B. One end of R57 is connected to the negative input pin of U3B, and the other end is connected to pin C of QP4. One end of R52 is connected to pin B of QP4, and the other end is connected to one end of R53, one end of R54, and the input of D2. The other end of R53 is connected to one end of R22 of the loop control signal proportional unit, which is then connected to the output pin of U2A. The other end of R54 is connected to a negative 8V power supply. The output of D2 and the output of D1 are connected to the output pin of U4A of the PI regulator limiting unit. Based on this structure, the dual-loop cross-limiting and PI regulation unit integrates an incident voltage PI controller, a reflected voltage PI controller, and hardware cross-limiting interlock logic. The error difference between the incident voltage feedback signal and the incident given signal is sent to a pure analog PI controller composed of U2A to precisely set the loop proportional adjustment coefficient and integral time constant. This ensures both steady-state power control with no steady-state error and constant power over long-term operation, as well as fast response speed and minimal overshoot under dynamic load disturbances. The main control signal after PI regulation is limited by a hard limiting circuit composed of high-speed PNP transistors QP1 and QP2 and Schottky diode D1. The reflected voltage error signal is sent to a matched analog PI controller composed of U3B to adjust the parameters to precisely match the incident branch, ensuring consistent dynamic response characteristics of the dual loops. The regulated signal is then limited by a hard limiting circuit composed of QP3, QP4 and Schottky diode D1. D1 and D2 form a pure hardware cross-limiting interlock structure. Under normal load matching conditions, the incident voltage control signal is forward-conducting and dominates the regulation, while the reflected voltage loop is on standby for monitoring. When the reflected voltage exceeds the limit abnormally, the reflected voltage control signal is instantly forced low by the diode hardware clamping action, achieving μs-level instantaneous limiting protection without software logic judgment or algorithm delay. The switching process is continuous and uninterrupted, without power jumps or waveform distortion.

[0043] PI regulator limiting unit such as Figure 6As shown, it includes resistors R49, R55, R48, R58, R61, and R62, capacitors C32, C35, C36, and C37, and the A-channel operational amplifier U4A in the LM6172IMX chip. One end of R49 is grounded, one end of R55 is connected to signal RF-PIO-G, and the other ends of R49, R55, and R48 are connected to the positive input pin of U4A. The other end of R48 is grounded, and C32 is connected in parallel across R48. The positive power supply pin of amplifier A is connected to a positive 8V power supply and is connected to one end of C35. The other end of C35 is grounded. One end of resistor R58 is grounded. One end of resistor R61 is connected to a positive 8V power supply. The other ends of R58, R61, and R62 are connected to the negative input pin of U4A. The other end of R62 is connected to the output pin of U4A. C37 is connected in parallel across R62. The negative power supply pin of U4A is connected to a negative 8V power supply and is connected to one end of C36. The other end of C36 is grounded. The PI regulator limiting unit conditions the limiting sub-signal through operational amplifier U4A to compensate for the voltage difference generated in the transistor clamping circuit, directly mapping the limiting command signal to the loop output. Loop control signal proportional unit such as Figure 7 As shown, it includes R17, R18, R22, R23, R25, R27 and R28, capacitors C17 and C23, and the B-channel operational amplifier U1B in the LM6172IMX chip. One end of R17 is grounded, one end of R22 is connected to the output pin of U2A and R53 of the second circuit at the same point, the other ends of R17, R22 and one end of R18 are connected to the positive input pin of U1B at the same point, the other end of R18 is grounded, C17 is connected in parallel across R18, one end of R25 is grounded, one end of R27 is connected to the positive 8V power supply, the other ends of R25, R27 and one end of R28 are connected to the negative input pin of U1B at the same point, the other end of R28 is connected to the output pin of U1B, C23 is connected in parallel across R28, one end of R23 is connected to the output pin of U1B, and the other end outputs the control signal DDS-REF. The output conditioning stage after the proportional unit of the loop control signal cross-limits performs proportional scaling and level matching on the signal to adapt to the input requirements of the subsequent multiplier.

[0044] For example, the control module further includes an incident given signal buffer conditioning circuit and a reflected given signal buffer conditioning circuit, the incident given signal buffer conditioning circuit being as follows: Figure 8As shown, it includes resistors R36, R33, R37, and R38, capacitors C24 and C25, and the B-channel operational amplifier U2B in the LM6172IMX chip. One end of R36 is grounded, and the other end of R36 and one end of R33 are connected to the positive input pin of U2B. The other end of R33 is grounded. C24 is connected in parallel across R33. One end of R37 receives the incident given signal Pg-F, i.e., the incident voltage given value. The other end of R37 and one end of R38 are connected to the negative input pin of U2B. The other end of R38 is connected to the output pin of U2B. C25 is connected in parallel across R38. The output pin of U2B is connected to one end of R21 in the first loop of the dual-loop cross-limiting and PI adjustment unit. The reflected given signal buffer conditioning circuit is as follows: Figure 9 As shown, it includes resistors R59, R56, R60 and R63, capacitors C34 and C38, and the B-channel operational amplifier U4B in the LM6172IMX chip. One end of R59 is grounded, and the other end of R59 and one end of R56 are connected to the positive input pin of U4B. The other end of R56 is grounded. C34 is connected in parallel across R56. One end of R60 receives the reflected reference signal Pg-R, i.e., the reflected voltage reference value. The other end of R60 and one end of R63 are connected to the negative input pin of U4B. The other end of R63 is connected to the output pin of U4B. C38 is connected in parallel across R63. The output pin of U4B is connected to one end of R45 in the second loop of the dual-loop cross-limiting and PI regulation unit. The incident and reflected input signal buffer conditioning circuits employ an inverting follower topology. Their main function is to perform impedance transformation and drive enhancement on the incident input signal Pg-F and the reflected input signal Pg-R, preventing distortion of the input value due to load on subsequent circuits and ensuring the accuracy and stability of the input signal. Simultaneously, through symmetrical device parameter design with the feedback conditioning branch, the gain, phase, and delay characteristics of the input and feedback signals are matched to ensure consistency, eliminating hardware characteristic deviations between channels, and adapting to the input phase requirements of the subsequent PI controller, providing a stable and accurate input reference for subsequent error summation calculations.

[0045] Optionally, the RF power supply sampling and control circuit further includes a multiplier unit, a DDS unit, and a power amplifier unit. The input terminal of the multiplier unit is connected to the control module and the DDS unit, respectively. The output terminal of the multiplier unit is connected to the input terminal of the power amplifier unit, and the output terminal of the power amplifier unit is connected to the directional coupler sampling module.

[0046] Specifically, such as Figure 1As shown, the RF power supply sampling and control circuit also includes a multiplier unit 108, a DDS unit, and a power amplifier unit 109. The input terminals of the multiplier unit 108 are connected to the control module and the DDS unit, respectively. The output terminal of the multiplier unit 108 is connected to the input terminal of the power amplifier unit 109, and the output terminal of the power amplifier unit 109 is connected to the directional coupler sampling module, forming a complete negative feedback closed-loop control link. The DDS unit, or Direct Digital Synthesis unit, is used to generate a stable, low-distortion standard sinusoidal reference signal (sine). The frequency and phase of this sinusoidal signal are precisely controllable, serving as the carrier reference signal for the entire RF power supply and providing a stable frequency reference for the output RF signal. The control signal output by the control module is a DC modulation level, representing the amplitude command for power modulation. After both are input to the multiplier unit 108, the multiplier applies the modulation level to the sinusoidal reference signal through analog multiplication, achieving amplitude modulation of the sinusoidal signal. The output is an RF modulated signal whose amplitude dynamically changes with the control signal, completing the coupling conversion from control signal to RF carrier. The modulated RF small signal is sent to the power amplifier unit 109 for power amplification. The power amplifier unit 109 amplifies the RF modulation signal of the small signal to the rated power level and outputs a high-power RF signal to the load end, providing the required RF energy for industrial processing. At the same time, the main output circuit of the power amplifier unit 109 is connected to the directional coupler sampling module, which samples the output RF signal in real time to obtain two standard differential sampling signals and feeds them back to the control module, forming a complete negative feedback closed-loop control link. The entire closed-loop link works as follows: the DDS unit outputs a standard sine wave signal of fixed frequency, the control module outputs the adjustment level according to the given reference value and the sampled feedback value, the two are multiplied and amplitude-modulated before being sent to the power amplifier unit 109 for amplification, the RF signal output by the power amplifier is sampled by the directional coupler and fed back to the control module, the control module adjusts the output adjustment level in real time to make the output power stably track the given reference value. When the given reference value is a dynamic waveform such as a stepped wave, the high-speed closed-loop link can quickly follow the waveform changes, achieving the control effect of rapid stabilization of the stepped rising edge, precise amplitude locking of the stepped flat top, and smooth fallback of the stepped falling edge. This architecture organically combines carrier generation, amplitude modulation, power amplification, and sampling closed-loop to form a fully analog RF power control link. There are no digital signal processing stages throughout, ensuring the system's response speed and control bandwidth. In this embodiment, the multiplier unit 108, DDS unit, and power amplifier unit 109, in conjunction with the sampling control module, form a complete fully analog RF power closed-loop link. This enables continuous analog control from carrier generation to power output, ensuring both frequency stability and low distortion of the output RF signal. Furthermore, the high-speed closed-loop system achieves precise power control and rapid dynamic response, enabling stable output of high-precision steady-state power and process waveforms such as stepped waves.

[0047] Optionally, the RF power supply sampling and control circuit also includes a constant temperature control unit. The constant temperature control unit includes a temperature detection and sensing subunit and a constant temperature drive control subunit. The temperature detection and sensing subunit is used to collect the real-time operating temperature of the directional coupler sampling module, and the constant temperature drive control subunit is used to dynamically adjust the working state of the temperature actuator according to the real-time operating temperature.

[0048] Specifically, such as Figure 1 As shown, the RF power supply sampling and control circuit also includes a temperature control unit. This unit is located at the directional coupler sampling module and encloses it. Internally, it integrates a temperature detection sensing subunit and a temperature control drive subunit. The temperature detection sensing subunit collects the real-time operating temperature of the directional coupler sampling module, while the temperature control drive subunit dynamically adjusts the operating state of the temperature-sensitive actuator based on the real-time operating temperature. In actual operation, the temperature detection sensing subunit uses a high-precision temperature sensor to collect the surface temperature of the core temperature-sensitive components in the directional coupler sampling module in real time, covering key components such as the current transformer magnetic ring, sampling capacitor, and detector diode, whose parameters are easily affected by temperature. The temperature signal is converted into an electrical signal and transmitted to the temperature control drive subunit. The temperature control drive subunit has a built-in standard temperature reference and closed-loop control logic. It compares the real-time collected temperature with the set standard operating temperature. When the real-time temperature is lower than the standard temperature, it drives the heating actuator to raise the sampling module temperature; when the real-time temperature is higher than the standard temperature, it drives the cooling actuator to lower the sampling module temperature. Through dynamic closed-loop control, the core components of the directional coupler sampling module are kept constant within a fixed standard operating temperature range over a long period. During long-term continuous operation of the RF power supply, power loss leads to an increase in the temperature of the sampling module. Changes in ambient temperature also affect the operating temperature of the devices. Parameters such as the permeability of the nickel-zinc magnetic ring, the capacitance of the sampling capacitor, and the forward voltage drop of the detector diode all drift with temperature, resulting in deviations in the sampling amplitude and phase, leading to decreased power sampling accuracy and reduced control stability. This embodiment uses a constant-temperature control unit to suppress the impact of temperature changes on the parameters of the sampling devices at the hardware level, eliminating sampling errors caused by temperature drift. This achieves drift-free sampling and deviation-free control across the entire temperature range, ensuring that the power control accuracy and waveform output stability do not degrade during long-term continuous operation. This embodiment uses a constant-temperature control unit to manage the temperature of the directional coupler sampling module, effectively suppressing the temperature drift of the core sampling device parameters, eliminating sampling errors caused by temperature changes, improving the long-term stability of sampling accuracy, and ensuring that the RF power supply maintains stable power control accuracy under different ambient temperatures and operating durations, making it suitable for long-term continuous industrial production applications.

[0049] Those skilled in the art will understand that all or part of the processes in the above embodiments can be implemented by a computer program instructing related hardware. The program can be stored in a computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. The storage medium can be a magnetic disk, optical disk, read-only memory (ROM), or random access memory (RAM), etc. In this application, the units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of the embodiments of the present invention according to actual needs. Furthermore, the functional units in the various embodiments of the present invention can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated units described above can be implemented in hardware or as software functional units.

[0050] While the present invention has been disclosed above, its scope of protection is not limited thereto. Those skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention, and all such changes and modifications will fall within the scope of protection of the present invention.

Claims

1. A radio frequency power supply sampling and control circuit, characterized in that, The system includes a directional coupler sampling module and a control module. The directional coupler sampling module includes a nickel-zinc magnetic ring current transformer, a multi-stage capacitive voltage divider sampling network, and a sampling signal processing unit. The nickel-zinc magnetic ring current transformer and the multi-stage capacitive voltage divider sampling network are both connected to the sampling signal processing unit. The nickel-zinc magnetic ring current transformer is used to acquire two differential current sampling signals of the main output circuit of the RF power amplifier. The multi-stage capacitor voltage divider sampling network is used to acquire the RF high voltage operating voltage sampling signal of the main output circuit of the power amplifier. The sampling signal processing unit is used to perform phase calibration compensation, load effect elimination, high-frequency peak detection, and low-pass smoothing filtering on the two differential current sampling signals and the RF high voltage operating voltage sampling signals according to the built-in circuit to obtain two standard differential sampling signals. The control module is used to compare the given reference value with the two standard differential sampling signals, perform proportional-integral adjustment through PI control, and perform cross-limiting interlocking to obtain the control signal.

2. The radio frequency power supply sampling and control circuit according to claim 1, characterized in that, The built-in circuit of the sampling signal processing unit includes a phase lead compensation capacitor, two processing branches, an incident voltage differential amplifier unit, and a reflected voltage differential amplifier unit. The two ends of the phase lead compensation capacitor are respectively connected to the input terminals of the two processing branches. The output terminals of the two processing branches are respectively connected to the input terminals of the incident voltage differential amplifier unit and the reflected voltage differential amplifier unit. The output terminals of the incident voltage differential amplifier unit and the reflected voltage differential amplifier unit are respectively connected to the input terminal of the control module. The two processing branches are used to receive the corresponding two differential current sampling signals and the radio frequency high voltage operating voltage sampling signal. Each processing branch includes a phase lag calibration network, a high-frequency Schottky diode, and a low-pass smoothing filter network connected in sequence. The phase lag calibration network includes a fixed capacitor, an adjustable phase lag calibration capacitor, and a fixed resistor. One end of the fixed capacitor, the adjustable phase lag calibration capacitor, and the fixed resistor are connected together and then connected to the processing branch, and the other end is grounded at a common point.

3. The radio frequency power supply sampling and control circuit according to claim 2, characterized in that, The low-pass smoothing filter network includes a filter inductor, a first conditioning resistor, a second conditioning resistor, a third conditioning resistor, a fourth conditioning resistor, and a filter capacitor. The filter inductor, the first conditioning resistor, and the second conditioning resistor are connected in series to the processing branch. One end of the third conditioning resistor and one end of the filter capacitor are connected between the first conditioning resistor and the second conditioning resistor. The other end of the third conditioning resistor, the other end of the filter capacitor, and one end of the fourth conditioning resistor are all grounded at the same point. The output terminal of the second conditioning resistor in one of the processing branches is connected to the first pin of the incident voltage differential amplifier unit, and the other end of the fourth conditioning resistor is connected to the second pin of the incident voltage differential amplifier unit. The output of the second conditioning resistor in another processing branch is connected to the first pin of the reflected voltage differential amplifier unit, and the other end of the fourth conditioning resistor is connected to the second pin of the reflected voltage differential amplifier unit.

4. The radio frequency power supply sampling and control circuit according to claim 2, characterized in that, The multi-level capacitive voltage divider sampling network includes a first capacitive voltage divider sampling sub-network and a second capacitive voltage divider sampling sub-network, and the first capacitive voltage divider sampling sub-network and the second capacitive voltage divider sampling sub-network are respectively connected to the corresponding processing branch; The first capacitor voltage divider sampling sub-network includes a first voltage divider capacitor and a second voltage divider capacitor. One end of the first voltage divider capacitor is connected to the main output circuit of the power amplifier, and the other end is connected between the corresponding high-frequency Schottky diode and the low-pass smoothing filter network. One end of the second voltage divider capacitor is connected between the corresponding high-frequency Schottky diode and the low-pass smoothing filter network, and the other end is grounded. The second capacitor voltage divider sampling sub-network includes a third voltage divider capacitor and a fourth voltage divider capacitor. One end of the third voltage divider capacitor is connected to the main output circuit of the power amplifier, and the other end is connected between the corresponding high-frequency Schottky diode and the low-pass smoothing filter network. One end of the fourth voltage divider capacitor is connected between the corresponding high-frequency Schottky diode and the low-pass smoothing filter network, and the other end is grounded.

5. The radio frequency power supply sampling and control circuit according to claim 4, characterized in that, The sampling signal processing unit further includes a first load effect elimination isolation resistor and a second load effect elimination isolation resistor. The first load effect elimination isolation resistor is connected in parallel across the first voltage divider capacitor, and the second load effect elimination isolation resistor is connected in series between the third voltage divider capacitor and the fourth voltage divider capacitor.

6. The radio frequency power supply sampling and control circuit according to claim 4, characterized in that, The sampling signal processing unit further includes a first voltage sampling voltage division ratio adjustment capacitor and a second voltage sampling voltage division ratio adjustment capacitor. The first voltage sampling voltage division ratio adjustment capacitor is connected in parallel across the second voltage division capacitor, and the second voltage sampling voltage division ratio adjustment capacitor is connected in parallel across the fourth voltage division capacitor.

7. The radio frequency power supply sampling and control circuit according to claim 1, characterized in that, The control module includes an incident voltage error adder, an incident voltage PI controller, an incident voltage limiter, a reflected voltage error adder, a reflected voltage PI controller, a reflected voltage limiter, and a dual-loop cross-limiting unit. The incident voltage error adder, the incident voltage PI controller, and the incident voltage limiter are connected in sequence. The reflected voltage error adder, the reflected voltage PI controller, and the reflected voltage limiter are also connected in sequence. The incident voltage error adder receives the incident voltage setpoint from the given reference value and the incident voltage feedback value from the two standard differential sampling signals. The reflected voltage error adder receives the reflected voltage setpoint from the given reference value and the reflected voltage feedback value from the two standard differential sampling signals. The outputs of both the incident voltage limiter and the reflected voltage limiter are connected to the input of the dual-loop cross-limiting unit. The dual-loop cross-limiting unit outputs the control signal, and the output of the incident voltage limiter is connected to the input of the reflected voltage limiter. The output of the reflected voltage limiter is also connected to the input of the incident voltage limiter.

8. The radio frequency power supply sampling and control circuit according to claim 7, characterized in that, The control module includes multiple high-speed operational amplifiers, high-speed switching transistors, and Schottky diodes.

9. The radio frequency power supply sampling and control circuit according to claim 1, characterized in that, It also includes a multiplier unit, a DDS unit, and a power amplifier unit. The input terminal of the multiplier unit is connected to the control module and the DDS unit, respectively. The output terminal of the multiplier unit is connected to the input terminal of the power amplifier unit, and the output terminal of the power amplifier unit is connected to the directional coupler sampling module.

10. The radio frequency power supply sampling and control circuit according to claim 1, characterized in that, It also includes a constant temperature control unit, which includes a temperature detection and sensing subunit and a constant temperature drive control subunit. The temperature detection and sensing subunit is used to collect the real-time operating temperature of the directional coupler sampling module, and the constant temperature drive control subunit is used to dynamically adjust the working state of the temperature actuator structure according to the real-time operating temperature.

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