A method for manufacturing temperature-compensated IDT electrodes of a surface acoustic wave device

Abstract

The application discloses a preparation method of a temperature compensation type surface acoustic wave device IDT electrode. The method forms a photoresist pattern on a wafer substrate, selects a chromium target material verified by particles to meet preset particle release requirements, performs a pre-melting or pre-stabilization treatment including a first heating stage, a second heating stage and a holding power stage on the chromium target material before formal deposition, deposits a bottom chromium film layer with a certain thickness through vacuum evaporation, and controls the X / Y direction scanning range of the heating source; then, a main conductive metal layer is deposited to form an IDT metal stack, and the IDT finger strips are formed through stripping. The application can reduce the chromium particle generation and deposition risk, improve appearance abnormalities, metal loss and broken finger defects, and improve the manufacturing yield.

Description

Technical Field

[0001] This invention relates to the field of surface acoustic wave (SAW) device manufacturing technology, and in particular to a method for preparing an IDT electrode for a temperature-compensated SAW device. Background Technology

[0002] In the manufacturing process of temperature-compensated surface acoustic wave (SAW) devices, a lift-off process is typically used to form the finger transducer (IDT) electrodes. In existing technology, such as a method for manufacturing a temperature-compensated SAW device, a dielectric material is first deposited on a piezoelectric substrate to form a dielectric layer and dielectric fingers are etched out. Then, metal is deposited on the etched dielectric layer to form an IDT metal layer with a thickness greater than the dielectric layer. Finally, a step-by-step lift-off process leaves a dielectric protective layer on the sidewalls of the IDT metal finger structure.

[0003] However, in actual mass production, as the thickness of the underlying chromium film increases, the properties of different chromium target materials vary, and conventional evaporation menus and heating source scanning paths cannot effectively control the stability of the chromium material during thermal sublimation. This easily leads to the generation of continuous filamentous chromium particles or fine powdery particles during the evaporation process. If these abnormally released chromium particles land on top of the photoresist, they will form residual marks after subsequent stripping and cause abnormal appearance in automated optical inspection (AOI). If chromium particles fall directly into the opening area of ​​the photoresist, they will block or interfere with the continuous deposition of the main conductive metal layer, resulting in metal loss or broken finger defects in the final IDT (Inductively Coupled Device) fingers, thus severely degrading the electrical performance and yield of the device.

[0004] Therefore, how to reduce the risk of chromium particle generation during the vacuum evaporation process of the underlying chromium film layer and improve the appearance abnormalities and finger breakage problems of the IDT electrode has become an urgent technical problem to be solved. Summary of the Invention

[0005] The main objective of this invention is to provide a method for preparing an IDT electrode for a temperature-compensated surface acoustic wave device, which aims to reduce the risk of chromium particle generation during the vacuum evaporation process of the underlying chromium film layer and improve the appearance abnormalities and finger breakage problems of the IDT electrode.

[0006] To achieve the above objectives, this invention proposes a method for fabricating an electrode for a temperature-compensated surface acoustic wave (IDT) device, comprising the following steps: A photoresist pattern is formed on a wafer substrate, the photoresist pattern including an opening region for depositing metal fingers and a photoresist layer region covering non-electrode regions; Chromium targets that have been verified to meet the preset particle release requirements are selected as vapor deposition materials. Before the formal deposition of the underlying chromium film layer, the chromium target material is subjected to pre-melting or pre-stabilization treatment, and the vapor deposition menu used includes at least a first heating stage, a second heating stage, and a power holding stage. Using the chromium target as the evaporation material, the bottom chromium film layer is deposited on the wafer substrate by vacuum evaporation, wherein the thickness of the bottom chromium film layer is... ; During the deposition of the underlying chromium film, the scanning path of the heating source relative to the surface of the chromium target is adjusted by controlling the scanning range settings of the heating source in the X direction and the scanning range settings in the Y direction. A main conductive metal layer is deposited on the bottom chromium film layer to form an IDT metal stack; Remove the photoresist pattern and the metal film layer located above the photoresist layer area, so that the IDT metal stack remaining in the opening area forms IDT fingers.

[0007] Preferably, the particle verification includes: under the verification evaporation conditions of the candidate chromium target, counting the number of filamentous chromium particles generated by the candidate chromium target, and when the number of filamentous chromium particles is lower than the particle threshold determined according to the preset particle verification standard, the candidate chromium target is determined as the chromium target that meets the preset particle release requirements after particle verification.

[0008] Preferably, the particle verification includes: after forming an IDT metal film layer using a candidate chromium target, performing at least one of automatic optical inspection of metal and automatic optical inspection after stripping on the wafer, and determining the candidate chromium target as the chromium target that meets the preset particle release requirements after particle verification when the detection yield is higher than the yield threshold determined according to the preset AOI detection standard, or when no continuous filamentous chromium residue is detected.

[0009] Preferably, the wafer substrate is a piezoelectric substrate for forming a temperature-compensated surface acoustic wave device, or a composite substrate for which the preceding film layer has been prepared.

[0010] Preferably, the thickness of the bottom chromium film layer satisfy: .

[0011] Preferably, the thickness of the bottom chromium film layer satisfy: .

[0012] Preferably, the photoresist used to form the photoresist pattern is a negative photoresist suitable for metal stripping processes.

[0013] Preferably, the first heating stage includes a first power ramp-up time and a first residence time, the second heating stage includes a second power ramp-up time and a second residence time, and the power holding stage is used to maintain the evaporation stability of the chromium target material before the formal deposition of the underlying chromium film layer.

[0014] Preferably, the first power ramp-up time The first stay time The second power ramp-up time The second stay time And the power setting value of the power holding phase The menu parameter for the vapor deposition equipment is 55.

[0015] Preferably, the scan range setting value in the X direction is... and the scan range setting value in the Y direction The parameters for the vapor deposition equipment menu must meet the following requirements: Or satisfy: .

[0016] The above technical solution has the following advantages: The technical solution provided in this application achieves significant technical benefits through multi-dimensional synergistic control of chromium target characteristics, chromium film thickness, evaporation temperature menu, and heating source scanning path. By introducing particle verification for chromium targets, target materials with low particle release risk can be screened at the process source. Strictly limiting the thickness of the underlying chromium film to within 30nm effectively shortens the vacuum evaporation time and reduces the total material evaporation, avoiding the risk of photoresist cracking while ensuring metal adhesion. Preheating the target with a menu including two specific temperature stages and a holding power stage before formal evaporation, combined with precise limitation of the heating source scanning range in the X and Y directions, ensures extremely uniform and stable sublimation and evaporation of the chromium material, fundamentally suppressing sudden material sputtering and the generation of filamentous particles. The closed-loop matching of these process windows greatly reduces the probability of chromium particles falling onto the wafer surface, significantly reduces foreign matter residue above the IDT fingers, and eliminates finger loss and broken finger defects caused by particle interference, thereby significantly improving the appearance inspection yield, electrical performance, and batch manufacturing consistency of IDT electrodes. Attached Figure Description

[0017] The present invention will now be described in detail with reference to specific embodiments and accompanying drawings, wherein: Figure 1 This is a flowchart illustrating a method for fabricating an IDT electrode for a temperature-compensated surface acoustic wave device, as provided in an embodiment of this application. Detailed Implementation

[0018] To make the objectives, technical solutions, and advantages of this application clearer, the technical solutions of this application will be clearly and completely described below in conjunction with the embodiments of this application. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0019] Combination Figure 1 A method for fabricating an IDT electrode for a temperature-compensated surface acoustic wave (SAW) device first includes providing a wafer substrate for fabricating the IDT electrode. Specifically, the wafer substrate can be a piezoelectric substrate for forming the SAW device, or a composite substrate with pre-fabricated films. The area on the wafer substrate where the IDT electrode is to be formed includes multiple finger regions and spacing regions between adjacent fingers. Next, a photoresist pattern is formed on the wafer substrate. The photoresist pattern includes opening regions for depositing metal fingers and a resist layer region covering non-electrode regions. In this embodiment, the photoresist used to form the photoresist pattern is a negative photoresist suitable for metal lift-off processes. By coating the wafer substrate with negative photoresist and forming the photoresist pattern corresponding to the IDT electrode pattern through exposure and development processes, the thickness, sidewall morphology, and opening width of the photoresist pattern must meet the requirements of subsequent chromium, copper, and titanium metal stacking deposition and lift-off processes.

[0020] After forming the photoresist pattern, a step of selecting a chromium target is performed, that is, selecting a chromium target that meets the preset particle release requirements after particle verification as the evaporation material. During the IDT electrode fabrication process, the increased thickness of the underlying chromium film layer can easily lead to AOI appearance anomalies in the IDT region. These anomalies may manifest as foreign matter or filamentous particle morphology located above the finger strip, or located inside the finger strip region, causing finger strip metal loss or breakage after subsequent peeling. To reduce the risk of filamentous chromium particle generation and deposition, the particle verification performed in this embodiment may specifically include, under the verification evaporation conditions of the candidate chromium target, counting the number of filamentous chromium particles generated by the candidate chromium target according to the same evaporation menu, the same detection area, and the same particle counting rules, and determining the candidate chromium target as the chromium target that meets the preset particle release requirements after particle verification when the number of filamentous chromium particles is lower than a particle threshold preset according to the same verification conditions. In another optional implementation, the particle verification may also include, after forming the IDT metal film layer using a candidate chromium target, performing at least one of Metal AOI and Liftoff AOI inspections on the wafer. If the inspection yield is higher than a pre-set yield threshold under the same AOI inspection conditions, or if no continuous filamentous chromium residue is detected, the candidate chromium target is identified as the chromium target that meets the preset particle release requirements after particle verification. This selection method uses a chromium target that reduces the risk of filamentous chromium particle release, replacing chromium targets that easily generate fine powder or filamentous particles during the evaporation process. This makes the release state of chromium vapor and chromium particles more stable during chromium evaporation, reducing the probability of chromium particles falling into the IDT pattern area.

[0021] Before the formal deposition of the underlying chromium film, the chromium target needs to undergo pre-melting or pre-stabilization treatment to bring the chromium material into a relatively stable evaporation state. The evaporation process used during this treatment includes at least a first heating stage, a second heating stage, and a power holding stage. The first heating stage is used to gradually bring the chromium target from its initial state into a heated state; the second heating stage is used to further stabilize the evaporation state of the chromium material; and the power holding stage is used to maintain the evaporation stability of the chromium target before the formal deposition of the underlying chromium film. Specifically, the first heating stage includes a first power ramp-up time and a first residence time, and the second heating stage includes a second power ramp-up time and a second residence time. In a specific example of this embodiment, the first power ramp-up time... The first dwell time can be set to 45 seconds. The second power ramp-up time can be set to 20 seconds. The second dwell time can be set to 45 seconds. It can be set to 60s, and the power setting value of the power holding phase. The above parameters are set to parameter 55 for the vapor deposition equipment. By using these parameters, the chromium target material is fully preheated and stabilized before the actual vapor deposition, which can effectively reduce the generation of sudden particle splashing or filamentous particles.

[0022] After selecting a chromium target material that meets the preset particle release requirements through particle verification and completing pre-melting or pre-stabilization treatment, the chromium target material is used as the evaporation material to deposit a bottom chromium film layer on the wafer substrate via vacuum evaporation. In this step, the thickness of the bottom chromium film layer... The thickness should be controlled within a range that minimizes the generation of large amounts of chromium particles while still satisfying the metal adhesion function; specifically, the thickness of the underlying chromium film layer should be... No larger than 30nm. To further improve the process window and surface yield, the thickness of the underlying chromium film layer... It can better meet the requirements of 10nm to 30nm, and under the condition of higher requirements for appearance yield and peel-off window, the thickness of the underlying chromium film layer is more suitable. It can also be controlled to meet the requirements of 10nm to 20nm. By controlling the thickness of the underlying chromium film layer within the above range, the problems of prolonged evaporation time, increased chromium evaporation, increased particle number, and increased risk of photoresist cracking caused by an excessively thick chromium film layer can be effectively avoided.

[0023] During the deposition of the underlying chromium film, the scanning path of the heating source relative to the chromium target surface can be adjusted by controlling the scanning range settings in the X and Y directions. Specifically, the heating source can be a deposition electron beam or a heating spot. By controlling its scanning range, a stable scanning path is formed between the heated area and the chromium target surface, effectively avoiding localized overheating, excessive localized sublimation, or abnormal release of particles from the target surface. Specifically, the X-direction scanning range setting... and the scan range setting value in the Y direction The menu parameters for the vapor deposition equipment can meet the requirements in this embodiment. Or, in another implementation, it can satisfy Under different crucible or vapor deposition equipment conditions, the scanning path that best matches the current state of the chromium target can be selected from the above scanning ranges. This allows the scanning path to cover the main evaporation area on the chromium material surface, while avoiding excessive concentration of scanning energy in a single area, further reducing the generation of filamentous chromium particles.

[0024] After the evaporation of the underlying chromium film, a main conductive metal layer is deposited on the underlying chromium film to form an IDT metal stack. The IDT metal stack deposited on the photoresist pattern and in the photolithographic opening area according to a predetermined film layer sequence includes at least a chromium layer and a main conductive metal layer. In this embodiment, the IDT metal stack specifically includes a chromium layer, a copper layer, and a titanium layer. Specifically, the chromium layer thickness can be one of 10 nm, 20 nm, or 30 nm, and the main conductive metal layer above it is composed of a copper layer with a thickness of approximately 290 nm and a titanium layer with a thickness of approximately 15 nm. While considering IDT electrode adhesion and AOI yield, the thickness of the chromium layer is controlled to be no greater than 30 nm.

[0025] After the IDT metal stack deposition is completed, a lift-off process is performed to form the final IDT electrode pattern. The lift-off process removes the photoresist pattern and the metal film layer above the photoresist layer, leaving the IDT metal stack within the opening area, thus forming discrete IDT fingers. Because the chromium target, chromium film thickness window, evaporation menu, and scanning range are coordinated and controlled in the preceding steps, the deposition probability of chromium particles on the top of the photoresist and in the photolithographic opening area is significantly reduced, effectively lowering the risk of foreign matter, chromium residue, metal loss, and broken fingers above the IDT fingers after lift-off. After the lift-off process, AOI inspection can be performed on the post-metal or post-lifted wafer to determine if there are filamentous particles, broken fingers, dirt, resist peeling, or other appearance abnormalities in the IDT area. When the number of filamentous chromium particles detected exceeds a preset threshold, process feedback adjustments can be prioritized in the following order: First, confirm whether the chromium target meets the particle verification requirements; second, confirm whether the chromium film thickness exceeds the preset thickness window; third, confirm whether the heating time, dwell time, holding power, deposition rate, and scanning range in the chromium evaporation menu match the current chromium target; fourth, confirm whether there are photoresist cracks or insufficient peel-off windows. Through the above feedback adjustments, a closed-loop matching is formed between chromium target selection, chromium thickness control, evaporation menu control, and photoresist window, thereby greatly improving the appearance quality and continuity of IDT fingers, reducing performance anomalies caused by IDT defects, and improving the overall device yield and batch consistency.

[0026] In another optional embodiment, this application provides an application scenario based on a composite substrate to further improve appearance yield and lift-off window. In this embodiment, the wafer substrate for fabricating the IDT electrode of the temperature-compensated surface acoustic wave device is specifically selected as a composite substrate with completed pre-film preparation. The area on the composite substrate where the IDT electrode is to be formed also includes multiple finger strip regions and spacing regions located between adjacent fingers. First, a layer of negative photoresist suitable for metal lift-off processes is coated on the composite substrate, and a corresponding photoresist pattern is formed through exposure and development processes. The photoresist pattern includes opening regions for depositing IDT metal fingers and adhesive layer regions covering non-electrode regions.

[0027] To address the extremely high requirements for appearance yield and peel-off window of the composite substrate, in this embodiment, the thickness of the bottom chromium film layer is... The wavelength is strictly controlled between 10nm and 20nm, specifically 15nm. Before metal film deposition, a chromium target that meets the preset particle release requirements after particle verification is selected as the evaporation material. This particle verification involves counting the number of filamentous chromium particles generated by the candidate chromium target under the same evaporation conditions, using the same evaporation menu, detection area, and particle statistics rules. If the number of filamentous chromium particles is lower than the preset particle threshold under the same verification conditions, the candidate chromium target is determined to be a compliant evaporation material. Before the formal deposition of the 15nm underlying chromium film, the selected chromium target undergoes pre-melting treatment. The evaporation menu includes a first heating stage, a second heating stage, and a holding power stage. Specific parameter configurations are as follows: the first power ramp-up time is set to 45s, the first residence time to 20s, the second power ramp-up time to 45s, the second residence time to 60s, and the power setting for the holding power stage (maintaining the evaporation stability of the chromium target before formal deposition) is set to 55.

[0028] During the deposition of the underlying chromium film, the scanning path of the heating source is precisely adjusted by controlling the scanning range settings in the X and Y directions. Considering the requirement for uniform release of thermal stress on the composite substrate surface, in this embodiment, the scanning range settings in both the X and Y directions are set to parameter 50 in the vapor deposition equipment menu. After the underlying chromium film is deposited, a main conductive metal layer is deposited on top to form an IDT metal stack. Specifically, a copper layer with a thickness of approximately 290 nm and a titanium layer with a thickness of approximately 15 nm are sequentially deposited on the chromium layer. Subsequently, a wet stripping process is performed to remove the negative photoresist pattern and the metal film layer located above the photoresist layer area, so that the IDT metal stack remaining in the opening area ultimately forms the IDT fingers.

[0029] To ensure process consistency and stability, this embodiment incorporates a closed-loop control mechanism that adjusts the process window based on AOI inspection feedback. Specifically, after the stripping process is completed, the wafer undergoes Metal AOI and Liftoff AOI inspections. If, during the inspection, the number of filamentous chromium particles in the IDT region exceeds the preset particle threshold, or if broken fingers or missing metal strips due to particle interference occur, a closed-loop adjustment procedure will be initiated. The current process window will be optimized and adjusted in the following order: First, check whether the currently used chromium target has degraded or mutated, confirming whether it still meets the initial particle verification requirements; Second, confirm whether the actual thickness of the underlying chromium film layer exceeds the preset 10nm to 20nm thickness window due to evaporation rate drift; Third, confirm whether the first power ramp-up time, first dwell time, second power ramp-up time, second dwell time, holding power, and scan range settings in the evaporation menu still match the actual state of the current chromium target; Fourth, confirm whether there are cracks in the preceding negative photoresist pattern, or whether the stripping window is insufficient due to lithography process fluctuations. Through such dynamic feedback and collaborative control, the selection of chromium target material, control of chromium thickness, control of vapor deposition menu, and control of photoresist window form an organic closed loop. This effectively solves the problems of electrode appearance abnormalities and finger breakage caused by filamentous chromium particles, even under thick chromium film layers or high-requirement process conditions, and significantly improves the electrical performance of RF devices and the overall manufacturing yield.

[0030] It should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and not to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A method for fabricating an electrode for a temperature-compensated surface acoustic wave (IDT) device, characterized in that, Includes the following steps: A photoresist pattern is formed on a wafer substrate, the photoresist pattern including an opening region for depositing metal fingers and a photoresist layer region covering non-electrode regions; Chromium targets that have been verified to meet the preset particle release requirements are selected as vapor deposition materials. Before the formal deposition of the underlying chromium film layer, the chromium target material is subjected to pre-melting or pre-stabilization treatment, and the vapor deposition menu used includes at least a first heating stage, a second heating stage, and a power holding stage. Using the chromium target as the evaporation material, the bottom chromium film layer is deposited on the wafer substrate by vacuum evaporation, wherein the thickness of the bottom chromium film layer is... ; During the deposition of the underlying chromium film, the scanning path of the heating source relative to the surface of the chromium target is adjusted by controlling the scanning range settings of the heating source in the X direction and the scanning range settings in the Y direction. A main conductive metal layer is deposited on the bottom chromium film layer to form an IDT metal stack; Remove the photoresist pattern and the metal film layer located above the photoresist layer area, so that the IDT metal stack remaining in the opening area forms IDT fingers.

2. The method for fabricating the temperature-compensated surface acoustic wave (IAW) device electrode according to claim 1, characterized in that, The particle verification includes: under the verification evaporation conditions of the candidate chromium target, counting the number of filamentous chromium particles generated by the candidate chromium target, and when the number of filamentous chromium particles is lower than the particle threshold determined according to the preset particle verification standard, the candidate chromium target is determined as the chromium target that meets the preset particle release requirements after particle verification.

3. The method for fabricating the temperature-compensated surface acoustic wave (IAW) electrode according to claim 1, characterized in that, The particle verification includes: after forming an IDT metal film layer using a candidate chromium target, performing at least one of automatic optical inspection of metal and automatic optical inspection after stripping on the wafer, and determining the candidate chromium target as the chromium target that meets the preset particle release requirements after particle verification when the detection yield is higher than the yield threshold determined according to the preset AOI detection standard, or when no continuous filamentous chromium residue is detected.

4. The method for fabricating the temperature-compensated surface acoustic wave (IAW) device electrode according to claim 1, characterized in that, The wafer substrate is a piezoelectric substrate used to form a temperature-compensated surface acoustic wave device, or a composite substrate for which the preceding film layer has been prepared.

5. The method for fabricating the temperature-compensated surface acoustic wave (IAW) device electrode according to claim 1, characterized in that, The thickness of the bottom chromium film layer satisfy: .

6. The method for fabricating the temperature-compensated surface acoustic wave (IAW) electrode according to claim 5, characterized in that, The thickness of the bottom chromium film layer satisfy: .

7. The method for fabricating the temperature-compensated surface acoustic wave (IAW) device electrode according to claim 1, characterized in that, The photoresist used to form the photoresist pattern is a negative photoresist suitable for metal stripping processes.

8. The method for fabricating the temperature-compensated surface acoustic wave (IAW) electrode according to claim 1, characterized in that, The first heating stage includes a first power ramp-up time and a first residence time, the second heating stage includes a second power ramp-up time and a second residence time, and the power holding stage is used to maintain the evaporation stability of the chromium target material before the formal deposition of the underlying chromium film layer.

9. The method for fabricating the temperature-compensated surface acoustic wave (IAW) electrode according to claim 8, characterized in that, First power ramp-up time The first stay time The second power ramp-up time The second stay time And the power setting value of the power holding phase The menu parameter for the vapor deposition equipment is 55.

10. The method for fabricating the temperature-compensated surface acoustic wave (IAW) electrode according to claim 1, characterized in that, The scan range setting value in the X direction and the scan range setting value in the Y direction The parameters for the vapor deposition equipment menu must meet the following requirements: Or satisfy: .

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