Filter circuit and digital isolator against single event effects

Abstract

The disclosure provides an anti-single event effect filter circuit and a digital isolator, comprising a low-pass filter module, an RS latch module and a C cell module. When the low-pass filter module generates a SET pulse at the input end of the filter circuit, the SET pulse in the input signal and its inverse signal is filtered out to obtain a first filtered signal and a second filtered signal. When the RS latch module inverts the first filtered signal and the second filtered signal, it determines a first hardened latch signal and a second hardened latch signal based on the target edges of the first filtered signal and the second filtered signal to restore the signal duty cycle. When the C cell module inverts the inverse signal of the first hardened latch signal and the second hardened latch signal, it maintains the output of the inverse signal of the first hardened latch signal and the second hardened latch signal in the previous same phase state to obtain an output signal. The circuit can suppress the propagation of the SET pulse, eliminate the influence of the filtering process on the output duty cycle, and reduce the area overhead.

Description

Technical Field

[0001] Embodiments of this disclosure relate to the field of integrated circuit technology, and more particularly to filter circuits and digital isolators resistant to single-event effects. Background Technology

[0002] As core components of aerospace equipment, integrated circuits are exposed to harsh space radiation environments for extended periods. High-energy particles can penetrate semiconductor materials, causing ionization and generating radiation effects, including total dose effects, single-event effects, and displacement damage effects. The charges generated by single-event effects, once collected by sensitive nodes in the circuit, can lead to single-event transients in combinational logic circuits and single-event flips in sequential logic circuits. In severe cases, this can even cause irreversible and permanent damage to the circuit. Therefore, as the size of integrated circuit manufacturing processes continues to shrink, single-event effects are gradually becoming a significant factor affecting the reliability of integrated circuits.

[0003] In the existing technology, the three common methods for resisting single-event transient pulses are triple mode redundancy, temporal redundancy, and pulse filtering. However, triple mode redundancy has a large area overhead, while temporal redundancy and pulse filtering methods change the output duty cycle. Summary of the Invention

[0004] This disclosure provides a filter circuit and digital isolator that resist single-event effects, which can suppress the propagation of single-event transient pulses, eliminate the influence of filtering on the output duty cycle, and reduce area overhead.

[0005] In a first aspect, this disclosure provides a filter circuit for resisting single-event effects, including a low-pass filter module, an RS latch module, and a C-cell module. The input terminal of the filter circuit is connected to the input terminal of the RS latch module through the low-pass filter module, and the output terminal of the RS latch module is connected to the output terminal of the filter circuit through the C-cell module.

[0006] The low-pass filter module is configured to filter out the single-particle transient pulse in the input signal and its inverted signal when a single-particle transient pulse is generated at the input terminal of the filter circuit, thereby obtaining a first filtered signal and a second filtered signal.

[0007] The RS latch module is configured to, when the first filtered signal and the second filtered signal are out of phase, determine a first hardened latch signal and a second hardened latch signal based on the target edge of the first filtered signal and the target edge of the second filtered signal, so as to restore the signal duty cycle, and output the inverted signal of the first hardened latch signal and the second hardened latch signal.

[0008] The C unit module is configured to maintain the output of the first hardened latch signal and the second hardened latch signal when they are in the previous co-phase state, so as to obtain the output signal, when the inverted signal of the first hardened latch signal and the second hardened latch signal are in the same phase.

[0009] In some embodiments of this disclosure, the low-pass filter module includes a first low-pass filter module and a second low-pass filter module. The first low-pass filter module is connected between the input terminal of the filter circuit and the first input terminal of the RS latch module, and the second low-pass filter module is connected between the input terminal of the filter circuit and the second input terminal of the RS latch module.

[0010] The first low-pass filter module is configured to filter out the single-particle transient pulse in the input signal and shape the filtered input signal to obtain the first filtered signal.

[0011] The second low-pass filter module is configured to filter out the single-particle transient pulse in the inverted signal of the input signal and shape the filtered inverted signal to obtain the second filtered signal.

[0012] In some embodiments of this disclosure, the first low-pass filter module includes a first RC filter and a first Schmitt trigger, and the second low-pass filter module includes a first inverter, a second RC filter, and a second Schmitt trigger. The input terminal of the filter circuit is connected to the first input terminal of the RS latch module in sequence through the first RC filter and the first Schmitt trigger, and the input terminal of the filter circuit is connected to the second input terminal of the RS latch module in sequence through the first inverter, the second RC filter, and the second Schmitt trigger.

[0013] In some embodiments of this disclosure, the RS latch module includes an RS latch and a second inverter. The two input terminals of the RS latch are connected one-to-one with the two output terminals of the low-pass filter module. One output terminal of the RS latch is connected to the first input terminal of the C unit module, and the other output terminal of the RS latch is connected to the second input terminal of the C unit module through the second inverter.

[0014] The RS latch is further configured to maintain the first hardened latch signal and the second hardened latch signal unchanged when a single-particle transient pulse in the first direction is generated at one input of the RS latch module; and to determine that one of the first hardened latch signal and the second hardened latch signal is the inverted signal of the second-direction single-particle transient pulse when a single-particle transient pulse in the second direction is generated at one input of the RS latch module, while the other signal remains unchanged.

[0015] The second inverter is configured to invert the first hardened latch signal.

[0016] In some embodiments of this disclosure, the RS latch is further configured to attenuate the single-event transient pulse of one of the first hardened latch signal and the second hardened latch signal when one of the outputs of the RS latch generates the single-event transient pulse, so as to keep the other signal unchanged.

[0017] In some embodiments of this disclosure, the C unit module includes a first MOSFET, a second MOSFET, a third MOSFET, and a fourth MOSFET. The first terminal of the first MOSFET is connected to the power supply voltage, and the second terminal of the first MOSFET is connected to the output terminal of the filter circuit through the second MOSFET. The first terminal of the fourth MOSFET is grounded, and the second terminal of the fourth MOSFET is connected to the output terminal of the filter circuit through the third MOSFET. The control terminals of the first MOSFET and the third MOSFET are connected to the first output terminal of the RS latch module, and the control terminals of the second MOSFET and the fourth MOSFET are connected to the second output terminal of the RS latch module.

[0018] The first and second MOS transistors are PMOS transistors, and the third and fourth MOS transistors are NMOS transistors.

[0019] In some embodiments of this disclosure, the C unit module further includes a third inverter, and the connection point of the second MOS transistor and the third MOS transistor is connected to the output terminal of the filter circuit through the third inverter.

[0020] In some embodiments of this disclosure, the filtering circuit further includes a hold connected to the output of the filtering circuit. The hold is configured to hold the previous valid logic level at the output of the filtering circuit.

[0021] In some embodiments of this disclosure, the hold includes a fourth inverter and a fifth inverter, the input of the fourth inverter and the output of the fifth inverter are connected to the output of the filter circuit, and the output of the fourth inverter is connected to the input of the fifth inverter.

[0022] In a second aspect, this disclosure provides a digital isolator, including any of the filtering circuits provided in the first aspect.

[0023] The technical solution disclosed herein provides a filter circuit for resisting single-event effects, including a low-pass filter module, an RS latch module, and a C-cell module. When a single-event transient pulse is generated at the input terminal of the filter circuit through the low-pass filter module, the single-event transient pulse in the input signal and its inverted signal is filtered out to obtain a first filter signal and a second filter signal. This can suppress the propagation of the single-event transient pulse and achieve the characteristic of resisting single-event transient effects.

[0024] When the first and second filtered signals are inverted, the RS latch module determines the first and second hardened latch signals based on the target edges of the first and second filtered signals to restore the signal duty cycle. It then outputs the inverted first and second hardened latch signals. This, combined with the set / reset function of the RS latch, ensures that the first and second hardened latch signals have a duty cycle close to the input signal. Furthermore, it prevents double flipping of the first and second hardened latch signals during single-event transients, thus avoiding single-event upsets.

[0025] By using the C-unit module to maintain the output of the first and second hardened latch signals when they are in phase (as they were in the previous in-phase state), the output signal can be obtained. This can be achieved by combining the C-unit module with the two complementary outputs of the RS latch to ensure that the output signal has a duty cycle close to the effective signal of the input signal, thus eliminating the influence of filtering on the output duty cycle. Since at least one of the first and second hardened latch signals remains unchanged during a single-event transient (SET), the C-unit module can maintain the output before an SET occurs, thereby suppressing error propagation.

[0026] Furthermore, the single-event filtering circuit provided in this disclosure does not require the replication of the same circuit, which can reduce circuit complexity and thus reduce area overhead. Attached Figure Description

[0027] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. It should be understood that the drawings described below only relate to some embodiments of this disclosure and are not intended to limit this disclosure, wherein: Figure 1 This is a schematic diagram of a filter circuit structure provided in an embodiment of the present disclosure.

[0028] Figure 2 This is a schematic diagram of another filtering circuit provided in an embodiment of the present disclosure.

[0029] Figure 3This is a circuit diagram of a filter circuit provided in an embodiment of the present disclosure.

[0030] Figure 4 This is a schematic diagram of the voltage waveform of a key node in the filter circuit when a SET occurs at the input of the filter circuit provided in the embodiments of this disclosure.

[0031] Figure 5 A schematic diagram of the voltage waveform of a key node in the filter circuit when no SET occurs, provided in an embodiment of this disclosure.

[0032] Figure 6 A circuit diagram of another filtering circuit provided in an embodiment of this disclosure.

[0033] Figure 7 A schematic diagram of the voltage waveform of a key node in the filter circuit when a SET occurs at the input of the RS latch module provided in this embodiment of the disclosure.

[0034] Figure 8 This is a schematic diagram of the voltage waveform of a key node in the filter circuit when a SET occurs at the output of the RS latch provided in this embodiment of the disclosure.

[0035] Figure 9 This is a circuit diagram of yet another filtering circuit provided in an embodiment of the present disclosure. Detailed Implementation

[0036] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are also within the scope of protection of this disclosure.

[0037] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this subject matter pertains. It will be further understood that terms such as those defined in commonly used dictionaries shall be interpreted as having the meaning consistent with their meaning in the context of the specification and in the relevant art, and shall not be interpreted in an idealized or overly formal form unless otherwise explicitly defined herein. As used herein, the statement “connecting” two or more parts together shall mean that the parts are joined directly together or joined through one or more intermediate components.

[0038] In this disclosure, the reference to "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of the phrase "embodiment" in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a mutually exclusive, independent, or alternative embodiment. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described in this disclosure can be combined with other embodiments.

[0039] Furthermore, the terms "first," "second," etc., in the specification, claims, or the accompanying drawings are used to distinguish different objects rather than to describe a specific order, and may explicitly or implicitly include one or more of the features.

[0040] In this disclosure, the term "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent three possibilities: A exists, A and B exist simultaneously, and B exists. Additionally, the character " / " in this document generally indicates that the preceding and following related objects have an "or" relationship.

[0041] In the description of this disclosure, unless otherwise stated, "multiple" and "at least two" mean two or more (including two), and similarly, "multiple groups" and "at least two groups" mean two or more (including two groups).

[0042] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings.

[0043] The Single Event Effect (SEE) in this disclosure refers to the energy deposition through ionization of semiconductor materials after high-energy particles irradiate them, generating electron-hole pairs. These charges are collected by sensitive nodes in the circuit, forming transient currents or voltage pulses. Specifically, SEE may generate Single Event Transients (SETs) at sensitive nodes of combinational logic circuits and Single Event Upsets (SEUs) at sensitive nodes of sequential logic circuits.

[0044] In this disclosure, SET refers to a temporary transient flip caused by a transient current or voltage pulse at a sensitive node of a combinational logic circuit, which returns to its original state after the transient pulse passes. SEU refers to a final steady-state flip caused by SET at a sensitive node of a sequential logic circuit, where the circuit maintains a new steady state different from the original state after the transient pulse passes.

[0045] In the triple-modal redundancy anti-SET pulse scheme of this disclosure, the same circuit is copied three times, and the three outputs are determined by majority vote to produce the final output. Although this scheme can shield errors, it has a large area overhead. In the time-redundancy anti-SET pulse scheme of this disclosure, a time window is formed by comparing the original signal and the delayed signal, and a holding circuit (such as a C unit) is used to filter out narrow pulses with a pulse width smaller than the design value. However, if the SET pulse happens to appear in the delay path, the delayed signal will produce pulse width distortion or additional jumps, causing the time window to change unexpectedly. This distorted window will cause the C unit output to produce unexpected transient pulses, resulting in distortion of the output signal duty cycle. In the pulse filtering anti-SET pulse scheme of this disclosure, the hysteresis characteristic of the level is used to suppress low-amplitude glitches by means of a Schmitt trigger. However, the threshold hysteresis of the Schmitt trigger will inherently change the output duty cycle.

[0046] In view of this, the present disclosure provides a filtering circuit, including a low-pass filter module, an RS latch module, and a C unit module. When the low-pass filter module generates a SET pulse at the input terminal of the filtering circuit, it filters out the SET pulse in the input signal and its inverted signal to obtain a first filtered signal and a second filtered signal. This can suppress the propagation of the SET pulse and achieve SEE resistance.

[0047] When the first and second filtered signals are inverted, the RS latch module determines the first and second hardened latch signals based on the target edges of the first and second filtered signals to restore the signal duty cycle. It then outputs the inverted first and second hardened latch signals. This, combined with the set / reset function of the RS latch on top of the low-pass filter module, ensures that the first and second hardened latch signals have a duty cycle close to the input signal. Furthermore, it prevents a double flip of the first and second hardened latch signals during a SET (Set-Off) event, thus avoiding a SEU (Sequential Activated Unstable Value) event.

[0048] By using the C-unit module to maintain the output of the first and second hardened latch signals when they are in phase (as they were in the previous in-phase state), the output signal can be obtained. This can be achieved by combining the C-unit module with the two complementary outputs of the RS latch to ensure that the output signal has a duty cycle close to the effective signal of the input signal, thus eliminating the influence of filtering on the output duty cycle. Since at least one of the first and second hardened latch signals remains unchanged during a SET (Set-Off) event, the C-unit module can maintain the output as it was before the SET event, thereby suppressing error propagation.

[0049] Furthermore, the filtering circuit provided in this disclosure does not require the replication of the same circuit, which can reduce the complexity of the circuit and thus reduce area overhead.

[0050] The technical solutions provided in this disclosure are described in detail below with reference to several specific embodiments.

[0051] Figure 1 This is a schematic diagram of a filter circuit provided in an embodiment of the present disclosure, such as... Figure 1 As shown, the filter circuit 100 includes a low-pass filter module 110, an RS latch module 120, and a C unit module 130. The input terminal of the filter circuit 100 is connected to the input terminal of the RS latch module 120 through the low-pass filter module 110, and the output terminal of the RS latch module 120 is connected to the output terminal of the filter circuit 100 through the C unit module 130.

[0052] The low-pass filter module 110 is configured to filter out the SET pulse in the input signal IN and its inverted signal INB when the input terminal of the filter circuit 100 generates a SET pulse, thereby obtaining the first filter signal FIL1 and the second filter signal FIL2.

[0053] The RS latch module 120 is configured to, when the first filtered signal FIL1 and the second filtered signal FIL2 are out of phase, determine the first hardened latch signal LA1 and the second hardened latch signal LA2 based on the target edge of the first filtered signal FIL1 and the target edge of the second filtered signal FIL2, so as to restore the signal duty cycle, and output the inverted signal LA1_B of the first hardened latch signal and the second hardened latch signal LA2. The target edge is either a rising edge or a falling edge.

[0054] The C unit module 130 is configured to maintain the output of the first hardened latch signal LA1_B and the second hardened latch signal LA2 in the previous co-phase state when the inverted signals of the first hardened latch signal LA1_B and the second hardened latch signal LA2 are inverted, so as to obtain the output signal OUT.

[0055] For example, Figure 2 A schematic diagram of another filtering circuit provided in an embodiment of this disclosure is shown below. Figure 2 As shown, the low-pass filter module 110 includes a first low-pass filter module 111 and a second low-pass filter module 112. The first low-pass filter module 111 is connected between the input terminal of the filter circuit 100 and the first input terminal of the RS latch module 120, and the second low-pass filter module 112 is connected between the input terminal of the filter circuit 100 and the second input terminal of the RS latch module 120.

[0056] The first low-pass filter module 111 includes a first RC filter and a first Schmitt trigger ST1. The input terminal of the filter circuit 100 is connected to the first input terminal of the RS latch module 120 in sequence through the first RC filter and the first Schmitt trigger ST1. The second low-pass filter module 112 includes a first inverter INV1, a second RC filter, and a second Schmitt trigger ST2. The input terminal of the filter circuit 100 is connected to the second input terminal of the RS latch module 120 in sequence through the first inverter INV1, the second RC filter, and the second Schmitt trigger ST2.

[0057] The first and second RC filters can be passive RC filters. The first RC filter includes a filter capacitor C1 and a filter resistor R1, and the second RC filter includes a filter capacitor C2 and a filter resistor R2. The input terminal of the filter circuit 100 is connected to the first plate of the filter capacitor C1 and the input terminal of the first Schmitt trigger ST1 through the filter resistor R1. The output terminal of the first inverter INV1 is connected to the first plate of the filter capacitor C2 and the input terminal of the second Schmitt trigger ST2 through the filter resistor R2. The second plates of the filter capacitors C1 and C2 are grounded. Figure 3 As shown, Figure 3 This is a circuit diagram of a filter circuit provided in an embodiment of the present disclosure.

[0058] Since the first RC filter and the second RC filter are composed of passive components, and passive components are not sensitive to SEE, the output terminals of the first RC filter and the second RC filter will not directly generate SET pulses due to single-particle incident, thus reducing the number of fault nodes inside the filter circuit 100.

[0059] It should be noted that the RC passive filter is only a preferred option for the first RC filter and the second RC filter. As an alternative, the first RC filter and the second RC filter can also be RC active filters. The first Schmitt trigger ST1 and the second Schmitt trigger ST2 can be non-inverting Schmitt triggers or inverting Schmitt triggers; this disclosure does not impose any specific restrictions on this.

[0060] Figure 4 A schematic diagram of the voltage waveform of a key node in the filter circuit when a SET occurs at the input terminal of the filter circuit provided in this embodiment of the present disclosure is shown below. Figure 4As shown, if a SET occurs at the input of the filter circuit 100, that is, an external input SET pulse is generated at the input of the filter circuit 100, then a SET pulse appears in the input signal IN. That is, a negative SET pulse appears when the input signal IN is high and / or a positive SET pulse appears when it is low. The first RC filter can significantly reduce the amplitude of the SET pulse in the input signal IN, resulting in the third filter signal FIL3. As long as the peak value of the third filter signal FIL3 is lower than the threshold of the first Schmitt trigger ST1, the hysteresis characteristic of the first Schmitt trigger ST1 can be used to shield the SET pulse in the third filter signal FIL3. That is, the first filter signal FIL1 shields the SET pulse generated at the input of the filter circuit 100, so that the output signal OUT shields the SET pulse generated at the input of the filter circuit 100, thereby ensuring that the output signal OUT is normal.

[0061] At this time, there is also a SET pulse in the inverted signal INB of the input signal. The second RC filter can significantly reduce the amplitude of the SET pulse in the inverted signal INB of the input signal, resulting in the fourth filtered signal FIL4. As long as the peak value of the fourth filtered signal FIL4 is lower than the threshold of the second Schmitt trigger ST2, the hysteresis characteristic of the second Schmitt trigger ST2 can be used to shield the SET pulse in the fourth filtered signal FIL4. That is, the second filtered signal FIL2 shields the SET pulse generated at the input of the filter circuit 100, so that the output signal OUT shields the SET pulse generated at the input of the filter circuit 100, thereby ensuring that the output signal OUT is normal.

[0062] Thus, the first low-pass filter module 111 can filter out the SET pulse in the input signal IN and shape the filtered input signal to obtain the first filtered signal FIL1. The second low-pass filter module 112 can filter out the SET pulse in the inverted signal INB of the input signal and shape the filtered inverted signal to obtain the second filtered signal FIL2.

[0063] If there are external input glitches in the received input signal IN, that is, negative glitches appearing when the input signal IN is high and / or positive glitches appearing when the input signal IN is low, the glitches in the input signal IN are significantly attenuated by the first RC filter and then shaped by the first Schmitt trigger ST1 to effectively filter them out. In other words, the first filter signal FIL1 shields the glitches in the input signal IN so that the output signal OUT shields the glitches in the input signal IN, thereby ensuring that the output signal OUT is normal.

[0064] At this time, there are also glitches in the inverted input signal INB. The glitches in the inverted input signal INB are greatly attenuated by the second RC filter and then shaped by the second Schmitt trigger ST2 to effectively filter them out. That is, the second filter signal FIL2 shields the glitches in the input signal IN so that the output signal OUT shields the glitches in the input signal IN, thereby ensuring that the output signal OUT is normal.

[0065] It should be noted that both externally input SET pulses and externally input glitches appear as unexpected transient pulses on the voltage waveform, but their generation mechanisms and propagation paths differ. Externally input glitches typically refer to electrical interference caused by switching noise, crosstalk, and power / ground fluctuations during normal operation of the preceding circuit. Their energy is limited and their width is variable, lacking the random particle incident characteristics of space radiation environments. If directly fed into subsequent digital logic circuits, they may cause false triggering. Externally input SET pulses refer to SET pulses generated by the preceding circuit itself due to single-particle incident when the circuit is applied in aerospace or radiation environments, propagating along the signal path to the subsequent stage. The low-pass filter module 110 of this disclosure is configured to suppress both conventional electrical glitches and filter SET pulses propagated from the preceding circuit due to SEE (Sequencing Emissions).

[0066] If a SET occurs at the output of the first inverter INV1, an internal interference SET pulse is generated at the output of the first inverter INV1. This SET pulse will then appear in the inverted signal INB of the input signal. That is, a negative SET pulse appears when the inverted signal INB of the input signal is high and / or a positive SET pulse appears when it is low. The SET pulse is significantly attenuated by the second RC filter and then shaped by the second Schmitt trigger ST2 to effectively filter it out. In other words, the second filter signal FIL2 shields the SET pulse generated at the output of the first inverter INV1, so that the output signal OUT shields the SET pulse generated at the output of the first inverter INV1, thereby ensuring that the output signal OUT is normal.

[0067] In summary, the low-pass filter module 110 can effectively filter out external input glitches, external input SET pulses, and internal interference SET pulses generated by sensitive nodes of the low-pass filter module 110 through the low-pass filtering characteristics of the RC filter and the hysteresis characteristics of the Schmitt trigger, ensuring that there are no glitches or SET pulses in the first filtered signal FIL1 and the second filtered signal FIL2 provided to the RS latch module 120. Furthermore, by setting the RC filter in the low-pass filter module 110 as a passive filter, the number of faulty nodes inside the filter circuit 100 can be reduced.

[0068] Figure 5 A schematic diagram of the voltage waveform of a key node in the filter circuit when no SET occurs, provided in an embodiment of this disclosure, is shown below. Figure 5As shown, at the valid signal (non-interference signal) of the input signal IN, the first filter signal FIL1 and the second filter signal FIL2 are inverted signals. When the valid signal (non-interference signal) in the input signal IN flips from low to high, the second filter signal FIL2 first flips from high to low, and then the first filter signal FIL1 flips from low to high. When the valid signal (non-interference signal) in the input signal IN flips from high to low, the first filter signal FIL1 first flips from high to low, and then the second filter signal FIL2 flips from low to high. Clearly, the low-pass filter module 110 affects the signal duty cycle, causing the duty cycles of the first filter signal FIL1 and the second filter signal FIL2 to differ from the duty cycle of the input signal IN.

[0069] Figure 6 A circuit diagram of another filtering circuit provided in an embodiment of this disclosure is shown below. Figure 2 , Figure 3 and Figure 6 As shown, the RS latch module 120 includes an RS latch 121 and a second inverter INV2. The two input terminals of the RS latch 121 are connected to the two output terminals of the low-pass filter module 110 in a one-to-one correspondence. One output terminal of the RS latch 121 is connected to the first input terminal of the C unit module 130, and the other output terminal of the RS latch 121 is connected to the second input terminal of the C unit module 130 through the second inverter INV2.

[0070] For example, RS latch 121 can be implemented using NOR gates, such as... Figure 3 and Figure 6 As shown; alternatively, it can be implemented using NAND gates. Taking NAND gates as an example, as... Figure 3 and Figure 6 As shown, the RS latch 121 includes a first NOR gate NOR1 and a second NOR gate NOR2. The first input of the first NOR gate NOR1 is connected to the first output of the low-pass filter module 110 to receive the first filtered signal FIL1. The second input of the first NOR gate NOR1 is connected to the output of the second NOR gate NOR2. The first input of the second NOR gate NOR2 is connected to the second output of the low-pass filter module 110 to receive the second filtered signal FIL2. The second input of the second NOR gate NOR2 is connected to the output of the first NOR gate NOR1.

[0071] The input of the second inverter INV2 can be connected to the output of the second NOR gate NOR2, such as... Figure 3As shown; or, connect the output of the first NOR gate NOR1, and define the signal received by the second inverter INV2 as the first hardened latch signal LA1, and the second inverter INV2 inverts the first hardened latch signal LA1. Taking the input of the second inverter INV2 connected to the output of the second NOR gate NOR2 as an example, when FIL1=0 and FIL2=1, LA1=0 and LA2=1 (assuming a reset state); when FIL1=1 and FIL2=0, LA1=1 and LA2=0 (assuming a set state); when FIL1=1 and FIL2=1, LA1=0 and LA2=0 (disabled state, which will not occur in this circuit); when FIL1=0 and FIL2=0, LA1 and LA2 maintain the previous state (hold state). Here, 1 represents a logic high level, and 0 represents a logic low level.

[0072] In this embodiment, the example given is that the rising edge of the first filter signal FIL1 lags behind the falling edge of the second filter signal FIL2 in terms of the time constants of the two RC branches. When the valid signal (non-interference signal) in the input signal IN flips from 0 to 1, the second filter signal FIL2 generates a falling edge, followed by a rising edge of the first filter signal FIL1, triggering the RS latch 121 to perform a set operation at this rising edge, causing LA1 to flip to 1 and LA2 to flip to 0. When the valid signal (non-interference signal) in the input signal IN flips from 1 to 0, the first filter signal FIL1 generates a falling edge, followed by a rising edge of the second filter signal FIL2, triggering the RS latch 121 to perform a reset operation at this rising edge, causing LA1 to flip to 0 and LA2 to flip to 1.

[0073] Therefore, RS latch 121 uses the edges of the first filter signal FIL1 and the second filter signal FIL2 to trigger a set / reset operation, restoring the signal with distorted duty cycle after RC filtering to a first hardened latch signal LA1 with a duty cycle close to that of the input signal IN. Since the first hardened latch signal LA1 and the second hardened latch signal LA2 are inverses of each other in steady state, the sum of the duty cycles of the first hardened latch signal LA1 and the second hardened latch signal LA2 is 1. Therefore, the sum of the duty cycles of the inverted signal LA1_B of the first hardened latch signal and the input signal IN is 1, and the sum of the duty cycles of the second hardened latch signal LA2 and the input signal IN is also 1, thus ensuring that the duty cycle of the output signal OUT is close to that of the input signal IN.

[0074] In other implementations, such as Figure 6As shown, the input of the second inverter INV2 is connected to the output of the first NOR gate NOR1. Since the RS latch 121 also uses the edges of the first filter signal FIL1 and the second filter signal FIL2 to trigger the set / reset operation, it restores the duty cycle of the second hardened latch signal LA2 to be close to the duty cycle of the input signal IN. The first hardened latch signal LA1 and the second hardened latch signal LA2 are still inversely related in steady state, and the sum of their duty cycles is 1. Therefore, the principle is the same.

[0075] In summary, the RS latch module 120 utilizes the set / reset function of the RS latch 121 and regenerates the signal by the edge triggering signals of the first filter signal FIL1 and the second filter signal FIL2. This restores the signal with distorted duty cycle after RC filtering to a reinforced latch signal with a duty cycle close to that of the input signal IN, thereby ensuring that the duty cycle of the output signal OUT is close to that of the input signal IN.

[0076] The above content describes the working process of RS latch module 120 restoring the signal duty cycle. The following discussion will cover the working process of RS latch module 120 filtering out SET pulses when the sensitive node of RS latch module 120 generates SET.

[0077] Figure 7 A schematic diagram of the voltage waveform of a key node in the filter circuit when a SET occurs at the input of the RS latch module provided in this embodiment of the disclosure is shown below. Figure 7 As shown, if a SET occurs at the first input of RS latch 121, an internal interference SET pulse is generated at the first input of RS latch 121. This results in a SET pulse appearing in the first filtered signal FIL1, specifically a positive SET pulse (0→1) when FIL1=0, and / or a negative SET pulse (1→0) when FIL1=1. Similarly, if a SET occurs at the second input of RS latch 121, an internal interference SET pulse is generated at the second input of RS latch 121. This results in a SET pulse appearing in the second filtered signal FIL2, specifically a positive SET pulse (0→1) when FIL2=0, and / or a negative SET pulse (1→0) when FIL2=1.

[0078] For example, RS latch 121 is implemented using NOR gates. When a SET occurs at the first input of RS latch 121, if a negative SET pulse is generated at the first input of RS latch 121, the second filter signal FIL2 remains 0, and the first filter signal FIL1 first flips from 1 to 0 and then to 1. Therefore, the second hardened latch signal LA2 remains 0, and the first hardened latch signal LA1 remains 1. Thus, the first hardened latch signal LA1 and the second hardened latch signal LA2 are not affected by the negative SET pulse generated at the first input of RS latch 121, and always maintain the state before the first filter signal FIL1 flips. Figure 7 As shown.

[0079] If a positive SET pulse is generated at the first input of RS latch 121, the second filter signal FIL2 remains at 1, and the first filter signal FIL1 first flips from 0 to 1. Then, the second hardened latch signal LA2 flips from 1 to 0, while the first hardened latch signal LA1 remains at 0. Subsequently, the first filter signal FIL1 flips from 1 to 0, then the second hardened latch signal LA2 flips from 0 to 1, while the first hardened latch signal LA1 remains at 0. Therefore, the second hardened latch signal LA2 flips with the positive SET pulse, while the first hardened latch signal LA1 always maintains the state before the first filter signal FIL1 flipped. Figure 7 As shown.

[0080] When a SET occurs at the second input of RS latch 121, if a negative SET pulse is generated at the second input of RS latch 121, the first filter signal FIL1 remains 0, and the second filter signal FIL2 first flips from 1 to 0 and then to 1. In this case, the second hardened latch signal LA2 remains 1, and the first hardened latch signal LA1 remains 0. Therefore, the first hardened latch signal LA1 and the second hardened latch signal LA2 are not affected by the negative SET pulse generated at the second input of RS latch 121 and always maintain the state before the second filter signal FIL2 flipped.

[0081] If a positive SET pulse is generated at the second input of RS latch 121, the first filter signal FIL1 remains at 1, and the second filter signal FIL2 first flips from 0 to 1. Then, the first hardened latch signal LA1 flips from 1 to 0, and the second hardened latch signal LA2 remains at 0. Subsequently, the second filter signal FIL2 flips from 1 to 0, then the first hardened latch signal LA1 flips from 0 to 1, and the second hardened latch signal LA2 remains at 0. Therefore, the first hardened latch signal LA1 flips with the positive SET pulse, and the second hardened latch signal LA2 always maintains the state before the second filter signal FIL2 flipped.

[0082] In other embodiments, the RS latch 121 is implemented using NAND gates. When a SET occurs at the first input of the RS latch 121, if a positive SET pulse is generated at the first input of the RS latch 121, the second filter signal FIL2 remains at 1, and the first filter signal FIL1 first flips from 0 to 1 and then to 0. In this case, the second hardened latch signal LA2 remains at 1, and the first hardened latch signal LA1 remains at 0. Therefore, the first hardened latch signal LA1 and the second hardened latch signal LA2 are not affected by the positive SET pulse generated at the first input of the RS latch 121 and always maintain the state before the first filter signal FIL1 flipped.

[0083] If a negative SET pulse is generated at the first input of RS latch 121, the second filter signal FIL2 remains 0, and the first filter signal FIL1 first flips from 1 to 0. Then, the first hardened latch signal LA1 remains 1, and the second hardened latch signal LA2 flips from 0 to 1. Subsequently, the first filter signal FIL1 flips from 0 to 1, so the first hardened latch signal LA1 remains 1, and the second hardened latch signal LA2 flips from 1 to 0. Therefore, the second hardened latch signal LA2 flips following the negative SET pulse, while the first hardened latch signal LA1 always maintains the state before the first filter signal FIL1 flipped.

[0084] When a SET occurs at the second input of RS latch 121, if a positive SET pulse is generated at the second input of RS latch 121, the first filter signal FIL1 remains at 1, and the second filter signal FIL2 first flips from 0 to 1 and then to 0. In this case, the first hardened latch signal LA1 remains at 1, and the second hardened latch signal LA2 remains at 0. Therefore, the first hardened latch signal LA1 and the second hardened latch signal LA2 are not affected by the positive SET pulse generated at the second input of RS latch 121 and always maintain the state before the second filter signal FIL2 flipped.

[0085] If a negative SET pulse is generated at the second input of RS latch 121, the first filter signal FIL1 remains 0, and the second filter signal FIL2 first flips from 1 to 0. Then, the second hardened latch signal LA2 remains 1, and the first hardened latch signal LA1 flips from 0 to 1. Subsequently, the second filter signal FIL2 flips from 0 to 1, and the second hardened latch signal LA2 remains 1, while the first hardened latch signal LA1 flips from 1 to 0. Therefore, the first hardened latch signal LA1 flips with the negative SET pulse, and the second hardened latch signal LA2 always maintains the state before the second filter signal FIL2 flips.

[0086] Thus, when a first-direction SET pulse is generated at one input of the RS latch module 120, the RS latch 121 maintains the first hardened latch signal LA1 and the second hardened latch signal LA2 unchanged, and the first hardened latch signal LA1 and the second hardened latch signal LA2 do not transiently flip. When a second-direction SET pulse is generated at one input of the RS latch module 120, the RS latch 121 determines that one of the first hardened latch signal LA1 and the second hardened latch signal LA2 is the inverted signal of the second-direction SET pulse, while the other signal remains unchanged. This allows the hardened latch signal that has flipped due to the SET pulse at the input of the RS latch module 120 to be quickly pulled back to its state before the start of the SET pulse after the SET pulse ends, thus avoiding SEU.

[0087] In summary, when a SET occurs at the input of the RS latch module 120, the RS latch module 120 utilizes the set / reset function of the RS latch 121 to ensure that at least one of the first reinforced latch signal LA1 and the second reinforced latch signal LA2 remains unchanged. This prevents the first reinforced latch signal LA1 and the second reinforced latch signal LA2 from undergoing a double flip due to the SET pulse at the input of the RS latch module 120, thereby avoiding SEU and ensuring the accuracy of the output signal OUT.

[0088] Figure 8 This is a schematic diagram of the voltage waveform of a key node in the filter circuit when a SET occurs at the output of the RS latch provided in this embodiment of the disclosure, as shown below. Figure 8 As shown, if a SET occurs at the first output of RS latch 121, an internal interference SET pulse is generated at the first output of RS latch 121. This generates a SET pulse in the second hardened latch signal LA2, specifically a positive SET pulse (0→1) when LA2=0, and / or a negative SET pulse (1→0) when LA2=1. Similarly, if a SET occurs at the second output of RS latch 121, an internal interference SET pulse is generated at the second output of RS latch 121. This generates a SET pulse in the first hardened latch signal LA1, specifically a positive SET pulse (0→1) when LA1=0, and / or a negative SET pulse (1→0) when LA1=1.

[0089] For example, RS latch 121 is implemented using NOR gates. When a SET occurs at the first output of RS latch 121, if a negative SET pulse is generated at the first output of RS latch 121, the second hardened latch signal LA2 first flips from 1 to 0 and then to 1, while the first hardened latch signal LA1 remains 0. Therefore, the first hardened latch signal LA1 is not affected by the negative SET pulse generated at the first output of RS latch 121 and always maintains the state before the second hardened latch signal LA2 flips.

[0090] When a SET occurs at the second output of RS latch 121, if a negative SET pulse is generated at the second output of RS latch 121, the first hardened latch signal LA1 first flips from 1 to 0 and then to 1, while the second hardened latch signal LA2 remains at 0. Therefore, the second hardened latch signal LA2 is not affected by the negative SET pulse generated at the second output of RS latch 121 and always maintains the state before the first hardened latch signal LA1 flipped.

[0091] In some other embodiments, the RS latch 121 is implemented using a NAND gate. When a SET occurs at the first output of the RS latch 121, if a positive SET pulse is generated at the first output of the RS latch 121, the second hardened latch signal LA2 first flips from 0 to 1 and then back to 0, while the first hardened latch signal LA1 remains at 1. Therefore, the first hardened latch signal LA1 is unaffected by the positive SET pulse generated at the first output of the RS latch 121 and always maintains the state before the second hardened latch signal LA2 flipped.

[0092] When a SET occurs at the second output of RS latch 121, if a positive SET pulse is generated at the second output of RS latch 121, the first hardened latch signal LA1 first flips from 0 to 1 and then back to 0, while the second hardened latch signal LA2 remains at 1. Therefore, the second hardened latch signal LA2 is not affected by the positive SET pulse generated at the second output of RS latch 121 and always maintains the state before the first hardened latch signal LA1 flipped.

[0093] In summary, when a SET occurs at one output of RS latch 121, its own set / reset function is used to prevent transient flipping at the other output. That is, it prevents the first reinforced latch signal LA1 and the second reinforced latch signal LA2 from double flipping due to the SET pulse at one output of RS latch 121, so as to avoid SEU and thus ensure the accuracy of the output signal OUT.

[0094] In some other embodiments, the RS latch 121 can be implemented using a single-event hardened NOR gate. When a SET occurs at the first output of the RS latch 121, if a positive SET pulse is generated at the first output of the RS latch 121, the RS latch 121 attenuates the positive SET pulse. The attenuated positive SET pulse is insufficient to cause a level flip of the first hardened latch signal LA1, thus maintaining the first hardened latch signal LA1 at 1. Therefore, the first hardened latch signal LA1 is unaffected by the positive SET pulse generated at the first output of the RS latch 121. Figure 8 As shown.

[0095] In the event of a SET at the second output of RS latch 121, if a positive SET pulse is generated at the second output of RS latch 121, RS latch 121 attenuates the positive SET pulse. The attenuated positive SET pulse is insufficient to cause the level of the second hardened latch signal LA2 to flip, thus keeping the second hardened latch signal LA2 at 1. Therefore, the second hardened latch signal LA2 is not affected by the positive SET pulse generated at the second output of RS latch 121.

[0096] In some other embodiments, the RS latch 121 is implemented using a single-event hardened NAND gate. When a SET occurs at the first output of the RS latch 121, if a negative SET pulse is generated at the first output of the RS latch 121, the RS latch 121 attenuates the negative SET pulse. The attenuated negative SET pulse is insufficient to cause a level flip of the first hardened latch signal LA1, thus keeping the first hardened latch signal LA1 at 0. Therefore, the first hardened latch signal LA1 is unaffected by the negative SET pulse generated at the first output of the RS latch 121.

[0097] In the event of a SET at the second output of RS latch 121, if a negative SET pulse is generated at the second output of RS latch 121, RS latch 121 attenuates the negative SET pulse. The attenuated negative SET pulse is insufficient to cause the second hardened latch signal LA2 to flip horizontally, thus keeping the second hardened latch signal LA2 at 0. Therefore, the second hardened latch signal LA2 is not affected by the negative SET pulse generated at the second output of RS latch 121.

[0098] Thus, when a SET pulse is generated at one output of RS latch 121, RS latch 121, which is composed of single-event hardened logic devices, attenuates the SET pulse of one of the first hardened latch signal LA1 and the second hardened latch signal LA2 in order to keep the other signal unchanged.

[0099] Single-event hardened NAND gates (or NOR gates) can employ hardening structures known in the art, such as layout-level hardening at the transistor level (e.g., adding a guard ring); or redundancy design, series current-limiting resistors, or shorting the substrate and source of the pull-down network NMOS transistor (or pull-up network PMOS transistor) at the circuit level, as long as the above-mentioned attenuation effect can be achieved. All of the above hardening methods are known technologies in the art, and their specific internal structures will not be described in detail here.

[0100] In summary, by using a single-event hardened logic device to implement the RS latch 121, when a SET occurs at one output of the RS latch 121, its own set / reset function and single-event hardening function can be used to prevent the other output from transiently flipping. That is, it prevents the first hardened latch signal LA1 and the second hardened latch signal LA2 from being caused by the SET pulse at the output of the RS latch 121 to also cause the other output to SET, thereby ensuring the accuracy of the output signal OUT.

[0101] See also Figure 3 The C-unit module 130 includes a first MOSFET M1, a second MOSFET M2, a third MOSFET M3, and a fourth MOSFET M4. The first MOSFET M1 and the second MOSFET M2 are PMOS transistors, while the third MOSFET M3 and the fourth MOSFET M4 are NMOS transistors. The first terminal of the first MOSFET M1 is connected to the power supply voltage, and the second terminal of the first MOSFET M1 is connected to the output terminal of the filter circuit 100 through the second MOSFET M2. The first terminal of the fourth MOSFET M4 is grounded, and the second terminal of the fourth MOSFET M4 is connected to the output terminal of the filter circuit 100 through the third MOSFET M3. The control terminals of the first MOSFET M1 and the third MOSFET M3 are connected to the first output terminal of the RS latch module 120, and the control terminals of the second MOSFET M2 and the fourth MOSFET M4 are connected to the second output terminal of the RS latch module 120.

[0102] For example, the first MOSFET M1 and the third MOSFET M3 receive the second hardened latch signal LA2, and the second MOSFET M2 and the fourth MOSFET M4 receive the inverted signal LA1_B of the first hardened latch signal. If no SET occurs at the output of RS latch 121, there is no SET pulse in the second hardened latch signal LA2 and the inverted signal LA1_B of the first hardened latch signal. When the valid signal in the input signal IN is 1, both the second hardened latch signal LA2 and the inverted signal LA1_B of the first hardened latch signal are 0, the first MOSFET M1 and the second MOSFET M2 are turned on, and the output signal OUT of the C unit module 130 is 1; when the valid signal in the input signal IN is 0, both the inverted signal LA1_B of the first hardened latch signal and the second hardened latch signal LA2 are 1, the third MOSFET M3 and the fourth MOSFET M4 are turned on, and the output signal OUT is 0.

[0103] If a SET occurs at the output of RS latch 121, a SET pulse will be present in the inverted signal LA1_B of the first hardened latch signal and the inverted signal LA2 of the second hardened latch signal. This means that one of the two input signals of the C unit module 130 will flip, causing the second hardened latch signal LA2 and the inverted signal LA1_B of the first hardened latch signal to switch from an in-phase state to an inverted state. At this time, the series conduction path within the C unit is cut off, meaning that the first MOSFET M1 and the second MOSFET M2 cannot be turned on simultaneously, nor can the third MOSFET M3 and the fourth MOSFET M4 be turned on simultaneously. The output node is in a high-impedance state, and the output signal OUT in this high-impedance state is maintained by a hold at the logic level of the previous in-phase state.

[0104] Therefore, when the second hardened latch signal LA2 and the inverted signal LA1_B of the first hardened latch signal are in phase, the output signal OUT is the inverted signal of the second hardened latch signal LA2 / the first hardened latch signal LA1; when the second hardened latch signal LA2 and the inverted signal LA1_B of the first hardened latch signal are out of phase, the output signal OUT maintains the logic level of the second hardened latch signal LA2 and the inverted signal LA1_B of the first hardened latch signal when they were in phase in the previous state.

[0105] In summary, when a SET occurs at the sensitive node of the filter circuit 100, at most one of the two input signals received by the C unit module 130 will flip. Therefore, the C unit module 130 can maintain the output signal OUT before the flip when the input flips, so as to filter the SET pulse, suppress error propagation, and further ensure the consistency of the effective signal between the output signal OUT and the input signal IN.

[0106] In this embodiment, the low-pass filter module 110, the RS latch module 120, and the C unit module 130 cooperate to form a complete three-stage protection circuit of "input filtering-intermediate hold-output suppression," filtering out input glitches and input SET pulses to achieve SET resistance characteristics, while simultaneously outputting an output signal with a duty cycle close to the input signal. Furthermore, the circuit structure is simple and the number of transistors is small, thus reducing area overhead, power consumption, and cost.

[0107] In some embodiments, Figure 9 A circuit diagram of another filtering circuit provided in the embodiments of this disclosure is shown below. Figure 6 and Figure 9 As shown, the C unit module 130 also includes a third inverter INV3, and the connection point of the second MOSFET M2 and the third MOSFET M3 is connected to the output terminal of the filter circuit 100 through the third inverter INV3.

[0108] For example, the first MOSFET M1 and the third MOSFET M3 receive the inverted signal LA1_B of the first hardened latch signal, and the second MOSFET M2 and the fourth MOSFET M4 receive the second hardened latch signal LA2. If no SET occurs at the output of RS latch 121, there is no SET pulse in the second hardened latch signal LA2 and the inverted signal LA1_B of the first hardened latch signal. When the valid signal in the input signal IN is 1, both the second hardened latch signal LA2 and the inverted signal LA1_B of the first hardened latch signal are 1, then the third MOSFET M3 and the fourth MOSFET M4 are turned on to output 0, and the output signal OUT of the third inverter INV3 is 1; when the valid signal in the input signal IN is 0, both the inverted signal LA1_B of the first hardened latch signal and the second hardened latch signal LA2 are 0, then the first MOSFET M1 and the second MOSFET M2 are turned on to output 1, and the output signal OUT is 0.

[0109] In some embodiments, see continue to see Figure 3 and Figure 9 The filter circuit 100 also includes a retainer 140 connected to the output terminal of the filter circuit 100.

[0110] For example, such as Figure 3 and Figure 9 As shown, the hold circuit 140 includes a fourth inverter INV4 and a fifth inverter INV5. The input terminal of the fourth inverter INV4 and the output terminal of the fifth inverter INV5 are connected to the output terminal of the filter circuit 100, and the output terminal of the fourth inverter INV4 is connected to the input terminal of the fifth inverter INV5.

[0111] A hold circuit 140 is provided at the output of the filter circuit 100. When the C unit composed of the first MOSFET M1, the second MOSFET M2, the third MOSFET M3 and the fourth MOSFET M4 is in a high impedance state, the logic level output by the C unit before the high impedance state is maintained, so as to keep the previous valid logic level at the output of the filter circuit 100 and avoid the filter circuit 100 being affected by noise when in a high impedance state.

[0112] This disclosure also provides a digital isolator, including the filter circuit 100 provided in any of the above embodiments, which has the functional modules and beneficial effects of the filter circuit 100, which will not be described in detail here.

[0113] For example, a digital isolator is an isolator that can be used in a radiation environment. It can not only effectively filter out SET pulses caused by high-energy particle incident, but also effectively filter out conventional electrical glitches. More importantly, it can accurately restore the pulse width and phase relationship of the input signal, ensuring that the signal timing passes through without distortion.

[0114] Unless otherwise expressly indicated by the context, the singular form of words used herein and in the appended claims includes the plural form, and vice versa. Thus, when referring to the singular, the plural form of the corresponding term is generally included. Similarly, the terms “comprising” and “including” are to be interpreted as including rather than exclusively. Likewise, the terms “including” and “or” should be interpreted as including unless such interpretation is expressly prohibited herein. Where the term “example” is used herein, the “example” is merely exemplary and illustrative, and should not be considered exclusive or extensive.

[0115] Several embodiments of this disclosure have been described in detail above. However, it is obvious that those skilled in the art can make various modifications and variations to the embodiments of this disclosure without departing from the spirit and scope of this disclosure. The scope of protection of this disclosure is defined by the appended claims.

Claims

1. A filter circuit resistant to single-event effects, characterized in that, It includes a low-pass filter module, an RS latch module, and a C unit module; The input terminal of the filter circuit is connected to the input terminal of the RS latch module through the low-pass filter module, and the output terminal of the RS latch module is connected to the output terminal of the filter circuit through the C unit module. The low-pass filter module is configured to filter out the single-particle transient pulse in the input signal and its inverted signal when a single-particle transient pulse is generated at the input terminal of the filter circuit, thereby obtaining a first filtered signal and a second filtered signal. The RS latch module is configured to, when the first filtered signal and the second filtered signal are out of phase, determine a first hardened latch signal and a second hardened latch signal based on the target edge of the first filtered signal and the target edge of the second filtered signal, so as to restore the signal duty cycle, and output the inverted signal of the first hardened latch signal and the second hardened latch signal. The C unit module is configured to maintain the output of the first hardened latch signal and the second hardened latch signal when they are in the previous co-phase state, so as to obtain the output signal, when the inverted signal of the first hardened latch signal and the second hardened latch signal are in the same phase.

2. The filter circuit according to claim 1, characterized in that, The low-pass filter module includes a first low-pass filter module and a second low-pass filter module; The first low-pass filter module is connected between the input terminal of the filter circuit and the first input terminal of the RS latch module, and the second low-pass filter module is connected between the input terminal of the filter circuit and the second input terminal of the RS latch module. The first low-pass filter module is configured to filter out the single-particle transient pulse in the input signal and shape the filtered input signal to obtain the first filtered signal. The second low-pass filter module is configured to filter out the single-particle transient pulse in the inverted signal of the input signal and shape the filtered inverted signal to obtain the second filtered signal.

3. The filter circuit according to claim 2, characterized in that, The first low-pass filter module includes a first RC filter and a first Schmitt trigger, and the second low-pass filter module includes a first inverter, a second RC filter, and a second Schmitt trigger; The input terminal of the filter circuit is connected to the first input terminal of the RS latch module in sequence through the first RC filter and the first Schmitt trigger, and the input terminal of the filter circuit is connected to the second input terminal of the RS latch module in sequence through the first inverter, the second RC filter and the second Schmitt trigger.

4. The filter circuit according to claim 1, characterized in that, The RS latch module includes an RS latch and a second inverter; The two input terminals of the RS latch are connected one-to-one with the two output terminals of the low-pass filter module. One output terminal of the RS latch is connected to the first input terminal of the C unit module, and the other output terminal of the RS latch is connected to the second input terminal of the C unit module through the second inverter. The RS latch is further configured to maintain the first hardened latch signal and the second hardened latch signal unchanged when a first-direction single-particle transient pulse is generated at one input terminal of the RS latch module; When a second-direction single-particle transient pulse is generated at one input of the RS latch module, one of the first reinforced latch signal and the second reinforced latch signal is determined to be the inverted signal of the second-direction single-particle transient pulse, while the other signal remains unchanged. The second inverter is configured to invert the first hardened latch signal.

5. The filter circuit according to claim 4, characterized in that, The RS latch is further configured to attenuate the single-event transient pulse of one of the first hardened latch signal and the second hardened latch signal when one of its outputs generates the single-event transient pulse, so as to keep the other signal unchanged.

6. The filter circuit according to claim 1, characterized in that, The C unit module includes a first MOS transistor, a second MOS transistor, a third MOS transistor, and a fourth MOS transistor; The first terminal of the first MOSFET is connected to the power supply voltage, and the second terminal of the first MOSFET is connected to the output terminal of the filter circuit through the second MOSFET. The first terminal of the fourth MOSFET is grounded, and the second terminal of the fourth MOSFET is connected to the output terminal of the filter circuit through the third MOSFET. The control terminals of the first MOSFET and the third MOSFET are connected to the first output terminal of the RS latch module, and the control terminals of the second MOSFET and the fourth MOSFET are connected to the second output terminal of the RS latch module. The first and second MOS transistors are PMOS transistors, and the third and fourth MOS transistors are NMOS transistors.

7. The filter circuit according to claim 6, characterized in that, The C unit module also includes a third inverter, and the connection point of the second MOS transistor and the third MOS transistor is connected to the output terminal of the filter circuit through the third inverter.

8. The filter circuit according to any one of claims 1-6, characterized in that, The filter circuit also includes a hold connected to the output terminal of the filter circuit; The hold is configured to hold the previous valid logic level at the output of the filter circuit.

9. The filter circuit according to claim 8, characterized in that, The holder includes a fourth inverter and a fifth inverter; The input terminal of the fourth inverter and the output terminal of the fifth inverter are connected to the output terminal of the filter circuit, and the output terminal of the fourth inverter is connected to the input terminal of the fifth inverter.

10. A digital isolator, characterized in that, Includes the filter circuit described in any one of claims 1-9.

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