Metallic or polymeric layer to protect semiconductor package bond pads from contamination

Abstract

The present disclosure relates to a metal or polymer layer to protect a semiconductor package bond pad from contamination. In an example, a semiconductor package (302) includes a bulk acoustic wave (BAW) resonator die (221) having a device side (202) formed with circuitry (204), a support structure (226) coupled to the device side and surrounding the circuitry, a bond pad (210) coupled to the device side and outside a perimeter of the support structure, a metal or polymer layer (224) coupled to the support structure and covering the circuitry, an etch stop layer (222) coupled to the metal or polymer layer, and a passive semiconductor structure (235) coupled to the etch stop layer such that the etch stop layer is between the semiconductor structure and the metal or polymer layer. Outer side surfaces of the metal or polymer layer, the etch stop layer, and the semiconductor structure are generally flush with one another, and all of the outer side surfaces of the semiconductor structure have a plasma etch striation (237).

Description

Technical Field

[0001] This disclosure generally relates to semiconductors, and more specifically, to metal or polymer layers used to protect semiconductor package bonding pads from contamination. Background Technology

[0002] A semiconductor wafer is a circular piece of semiconductor material, such as silicon, used to manufacture semiconductor chips. Typically, complex manufacturing processes are used to form many integrated circuits on a single wafer. Forming such circuits on a wafer is called fabrication. After wafer fabrication, the wafer is diced into multiple pieces called semiconductor dies, each containing one of the circuits. Dicing or sawing the wafer into individual dies is called dicing. The individual dies can then be coupled to a substrate or die pads. The resulting structure is then covered with molding compound to produce a package. Summary of the Invention

[0003] In one example, a semiconductor package includes: a bulk acoustic wave (BAW) resonator die having a device side on which a circuit system is formed; a support structure coupled to the device side and surrounding the circuit system; bonding pads coupled to the device side and located peripherally outside the support structure; a metal or polymer layer coupled to the support structure and covering the circuit system; an etch stop layer coupled to the metal or polymer layer; and a passive semiconductor structure coupled to the etch stop layer such that the etch stop layer is between the semiconductor structure and the metal or polymer layer. The outer surfaces of the metal or polymer layer, the etch stop layer, and the semiconductor structure are substantially flush with each other, and all of the outer surfaces of the semiconductor structure have plasma etch stripes.

[0004] In one example, a method for manufacturing a semiconductor package includes: coupling an oxide layer with a semiconductor structure coupled to a support structure on a device side of a semiconductor wafer, the semiconductor wafer having a circuit system formed in the device side, the support structure surrounding the circuit system, and the semiconductor wafer having bonding pads on the periphery of the support structure; patterning a photoresist layer on the semiconductor structure; etching the semiconductor structure using the photoresist layer to form a cavity above the bonding pads, the semiconductor structure having a thickness in a portion between the cavity and the oxide layer; removing the portion of the semiconductor structure and a portion of the oxide layer below the portion of the semiconductor structure using a water jet; sawing through the semiconductor wafer to produce a single-cut semiconductor die; coupling bonding wires to the bonding pads; and applying molding compound to the semiconductor die, the semiconductor structure, the bonding pads, and the bonding wires. Attached Figure Description

[0005] Figure 1This is a flowchart illustrating various methods for manufacturing semiconductor packages using metal or polymer layers to protect bonding pads from contamination.

[0006] Figure 2A1 , 2A2 2B1, 2B2, 2C1, 2C2, 2D1, 2D2, 2E1, 2E2, 2F1, 2F2, 2G1, 2G2, 2H1, 2H2, 2I1, 2I2, 3A, 3B, and 3C are process flows for manufacturing semiconductor packages using metal or polymer layers to protect bonding pads from contamination, according to various examples.

[0007] Figure 4A1 , 4A2 4B1, 4B2, 4C1, 4C2, 4D1, 4D2, 4E1, 4E2, 4F1, 4F2, 4G1, 4G2, 4H1, 4H2, 4I1, 4I2, 5A, 5B, and 5C are process flows for manufacturing semiconductor packages using metal or polymer layers to protect bonding pads from contamination, according to various examples.

[0008] Figure 6 This is a flowchart illustrating various methods for manufacturing semiconductor packages using selective etching and water jet techniques to protect bonding pads from contamination.

[0009] Figure 7A1 , 7A2 7B1, 7B2, 7C1, 7C2, 7D1, 7D2, 7E1, 7E2, 7F1, 7F2, 7G1, 7G2, 7H1, 7H2, 7I1, 7I2, 8A, 8B, and 8C are process flows for manufacturing semiconductor packages using selective etching and waterjet techniques, based on various examples, to protect bonding pads from contamination.

[0010] Figure 9 It is a block diagram of an example electronic device comprising a semiconductor package manufactured according to any of the technologies described herein. Detailed Implementation

[0011] In certain wafer-level manufacturing techniques, such as bulk acoustic wave (BAW) and microelectromechanical systems (MEMS), plasma etching is required to penetrate silicon to expose bonding pads, to which bonding wires are then coupled. In such cases, the silicon is directly above the bonding pads, and etching through this silicon exposes the pads to debris that can damage and / or contaminate them. To mitigate this risk of damage or contamination, an etch stop layer is coupled to the bottom surface of the silicon to prevent etching beyond the silicon. Furthermore, the etch stop layer prevents debris from falling directly onto the bonding pads. However, such etch stop layers often create cracks through which etching gases (e.g., plasma etching gases) can penetrate, accumulating on or near the bonding pads and causing contaminant formation. Therefore, etch stop layers are insufficient to protect the bonding pads.

[0012] This specification presents various examples of semiconductor packaging and semiconductor packaging manufacturing technologies, in which bonding pads are adequately protected from the damage and contamination described above, such as those associated with semiconductor etching processes. More specifically, a metal or polymer layer is coupled to an etch stop layer such that the etch stop layer is between the metal or polymer layer and silicon. Even in the event of cracks in the etch stop layer, the metal or polymer layer prevents gas flow to the bonding pads, thereby preventing contaminant formation on the bonding pads and preventing debris from damaging them. In an example, a semiconductor packaging manufacturing method includes coupling an oxide layer with a semiconductor structure coupled to a support structure on the device side of a semiconductor wafer. The semiconductor wafer has a circuit system formed on the device side. The support structure surrounds the circuit system, and the semiconductor wafer has bonding pads on the periphery of the support structure. The method also includes patterning a photoresist layer on the semiconductor structure and etching the semiconductor structure using the photoresist layer to form a cavity above the bonding pads. The portion of the semiconductor structure between the cavity and the oxide layer has thickness. The method further includes using a water jet to remove portions of the semiconductor structure and portions of the oxide layer beneath said portions of the semiconductor structure. The method includes sawing through the semiconductor wafer to produce a single-cut semiconductor die, and coupling bonding wires to bonding pads. The method also includes applying molding compound to the semiconductor die, the semiconductor structure, the bonding pads, and the bonding wires.

[0013] Figure 1 This is a flowchart of a method 100 for manufacturing a semiconductor package using a metal or polymer layer to protect bonding pads from contamination, based on various examples. Figure 2A1 , 2A22B1, 2B2, 2C1, 2C2, 2D1, 2D2, 2E1, 2E2, 2F1, 2F2, 2G1, 2G2, 2H1, 2H2, 2I1, 2I2, 3A, 3B, and 3C are process flows for fabricating semiconductor packages using metal or polymer layers to protect bonding pads from contamination, according to various examples. Therefore, they are now described in parallel. Figure 1 and 2A1 -3C.

[0014] Method 100 includes providing a semiconductor wafer having a precision circuit system and bonding pads (102) on the device side of the wafer. Figure 2A1 and 2A2 These are cross-sectional and top views of a semiconductor wafer 200 (e.g., silicon, gallium nitride) having a device side 202 and a non-device side 206 opposite to the device side 202, on which a precision circuitry 204 is formed. No circuitry is formed on the non-device side 206. A passivation layer 208 physically contacts the device side 202 of the semiconductor wafer 200. Bonding pads 210 are exposed on the top surface of the passivation layer 208 opposite to the device side 202. The bonding pads 210 are coupled to the circuitry in and / or on the device side 202 via vias and / or one or more additional metal layers, which are not explicitly shown for clarity. The passivation layer 208 includes a plurality of trenches 212, which appear as a grid pattern when viewed in the top view. A precision circuit system 204 exists between consecutive pairs of trenches 212, and bonding pads 210 exist between consecutive pairs of trenches 212, as shown. The precision circuit system 204 is any suitable type of circuit system. In an example, the semiconductor wafer 200 is a bulk acoustic wave (BAW) resonator wafer, and the precision circuit system 204 is a resonator element. In an example, an air cavity 213 is present beneath each example of the precision circuit system 204. The air cavity 213 facilitates the directional operation of the precision circuit system 204 (e.g., when the precision circuit system 204 is a resonator element) and / or provides mechanical stress isolation to the precision circuit system 204 to improve operation. Although the precision circuit system 204 is generally described herein as high precision, in this example, the precision circuit system 204 is a non-precision circuit system.

[0015] Method 100 includes etching trenches (104) surrounding a circuit system in the device side of a semiconductor wafer using patterned photoresist. Figure 2B1 and 2B2 yes Figure 2A1 and 2A2The cross-sectional and top views of the structure differ in that patterned photoresist 214 is applied to the top surface of the passivation layer 208. The patterned photoresist 214 is patterned, for example, using a suitable photolithography technique (e.g., utilizing a patterned mask, exposure, and a chemical solvent for developing the exposed areas of the photoresist to produce the patterned photoresist 214). The patterned photoresist 214 is patterned such that trenches 212 are exposed through the patterned photoresist 214, while the remainder of the passivation layer 208 is covered, as shown. Figure 2C1 and 2C2 yes Figure 2B1 and 2B2 The cross-sectional and top views of the structure differ in that trenches 218 are etched into the device side 202 of the semiconductor wafer 200 using patterned photoresist 214. Each of the trenches 218 is vertically aligned with a corresponding trench 212, and thus each trench 218 and its corresponding trench 212 can be considered as a single trench 216 / 218, where reference numeral 216 indicates the portion of the trench coplanar with the passivation layer 208, and reference numeral 218 indicates the portion of the trench within the semiconductor wafer 200. Trenches 216 / 218 surround the precision circuit system 204. Measured from the device side 202, the depth of the trenches 218 extending into the semiconductor wafer 200 is between 20 micrometers and approximately half the thickness of the semiconductor wafer 200. Depths below this range are disadvantageous because they do not adequately isolate mechanical stress, and depths above this range are disadvantageous because of the significant risk of wafer cracking.

[0016] Method 100 includes a support structure (106) that couples a metal or polymer layer having an oxide layer and a semiconductor structure coupled thereto to a device side of a semiconductor wafer. Figure 2D1 and 2D2 yes Figure 2C1 and 2C2The cross-sectional and top views of the structure differ in that the semiconductor structure 220, the metal or polymer layer 224, and the oxide layer 222 between the semiconductor structure 220 and the metal or polymer layer 224 are coupled to a support structure 226 on the device side 202, and more specifically, to a support structure 226 on the passivation layer 208. The semiconductor structure 220 is passive, meaning it has no circuitry. All oxide layers described herein (e.g., oxide layer 222) may also be referred to as etch stop layers. The oxide layer 222 has a first side physically contacting the semiconductor structure 220 and a second side physically contacting the metal or polymer layer 224 opposite the first side. The metal or polymer layer 224 physically contacts the support structure 226. The support structure 226 surrounds the trenches 216 / 218 and the precision circuitry 204. The oxide layer 222 can be any suitable type of oxide layer, such as silicon dioxide. The metal or polymer layer 224 can be any suitable type of metal or polymer layer, such as aluminum, copper, tungsten, titanium-tungsten, polyimide, benzocyclobutene, polydimethylsiloxane, SU-8, and polybenzoxazole. The support structure 226 can be any suitable type of rigid material, such as a polymer or copper / tin-silver or gold. The oxide layer 222 has a thickness in the range of 0.1 micrometers to 3 micrometers, where thicknesses below this range are disadvantageous because there is a risk that the oxide layer 222 will be completely etched away, and thicknesses above this range are disadvantageous because there is a risk that the target portion of the oxide layer 222 will become very difficult to remove during subsequent processes. The metal or polymer layer 224 has a thickness in the range of 0.05 micrometers to 5 micrometers, where thicknesses below this range are disadvantageous because there is a risk of cracking or breaking, and thicknesses above this range are disadvantageous because there is a risk that the target portion of the metal or polymer layer 222 will become very difficult to remove during subsequent processes. The support structure 226 has a thickness in the range of 5 micrometers to 40 micrometers, where a thickness below this range is unfavorable because of the risk of poor bonding performance, and a thickness above this range is unfavorable because the risk of poor bonding uniformity increases significantly.

[0017] Method 100 includes thinning the semiconductor structure by grinding (108). Figure 2E1 and 2E2 yes Figure 2D1 and 2D2The cross-sectional and top views of the structure differ in that the semiconductor structure 220 has been thinned by grinding. For example, a suitable back-side grinding technique can be useful. The resulting thickness of the semiconductor structure 220 is in the range of 50 micrometers to 300 micrometers, where thicknesses below this range are disadvantageous because there is a risk that the semiconductor wafer may crack or break during end-face grinding (i.e., if the grinding process continues beyond a thickness of 50 micrometers), and thicknesses above this range are disadvantageous because an increase in package thickness is unacceptable.

[0018] Method 100 includes patterning photoresist on a semiconductor structure (110). Figure 2F1 and 2F2 yes Figure 2E1 and 2E2 The cross-sectional view and top view of the structure differ in that patterned photoresist 228 is applied to the top side of the semiconductor structure 220 opposite to the semiconductor wafer 200. The patterned photoresist 228 can be patterned using the photolithography techniques described above. The patterned photoresist 228 includes an opening 230. The opening 230 is vertically aligned with a corresponding gap between the continuous support structures 226. For example, a vertical line may extend through both the opening 230 and the corresponding gap between the continuous support structures 226.

[0019] Method 100 includes thinning a semiconductor wafer by grinding (112). Figure 2G1 and 2G2 yes Figure 2F1 and 2F2 The cross-sectional and top views of the structure differ in that the non-device side 206 of the semiconductor wafer 200 has been ground to thin the semiconductor wafer 200, as indicated by reference numeral 232. The semiconductor wafer 200 is not ground so much that it reaches the trench 218 and is single-cut. Instead, the grinding should result in a thickness of the semiconductor wafer 200 between the non-device side 206 and the deepest point of the trench 218 in the range of 30 micrometers to 300 micrometers. Thicknesses below this range are disadvantageous because of the risk of cracking or breaking of the semiconductor wafer 200, and thicknesses above this range are disadvantageous because they significantly increase the package thickness.

[0020] Method 100 includes using patterned photoresist to etch a semiconductor structure to form an opening in the semiconductor structure above bonding pads (114). Method 100 includes removing the patterned photoresist (116). Figure 2H1 and 2H2 yes Figure 2G1 and 2G2 The cross-sectional view and top view of the structure differ in that, Figure 2G1 and 2G2The structure is coupled to a carrier or tape 234, and the semiconductor structure 220 is etched (e.g., plasma etched) using patterned photoresist 228, thereby creating openings 236 that slit the semiconductor structure 220 into individual semiconductor structures 235, which are passive structures (i.e., without circuitry). The openings 236 extend through the entire thickness of the semiconductor structure 220, as shown. The patterned photoresist 228 is then stripped. The width of each opening 236 is approximately equal to the width of the gap between the corresponding pair of consecutive support structures 226, as shown. When the semiconductor structure 220 is plasma etched, plasma etched stripes 237 are formed on the walls of the openings 236. Stripes 237 are present on all four sides of each semiconductor structure 235. Stripes 237 cover the entirety of each of the four sides of each semiconductor structure 235. Each stripe 237 is horizontally coplanar with the corresponding stripe 237 on each of the remaining three sides of the semiconductor structure 235, because the plasma etch process is performed on the entire semiconductor structure 220, and thus the various openings 236 are formed simultaneously. In other words, each stripe 237 extends across all four side surfaces of the corresponding semiconductor structure 235. Plasma etched stripes are microscale, parallel, fan-shaped grooves and ridges formed on the material surface during plasma etching due to directional ion bombardment.

[0021] The etching process used to create opening 236 may damage oxide layer 222. For example, cracks may form in oxide layer 222. Furthermore, gases used during the etching process (e.g., during plasma etching) can seep through these cracks in oxide layer 222, ultimately leading to contaminant formation on bonding pad 210. Debris associated with oxide layer 222 may also fall onto bonding pad 210. Metal or polymer layer 224 blocks any gas seeping through cracks in oxide layer 222 from reaching bonding pad 210, thereby preventing contaminant formation on bonding pad 210. Similarly, metal or polymer layer 224 blocks any debris from oxide layer 222 from falling onto bonding pad 210. Thus, metal or polymer layer 224 maintains the structural and operational integrity of bonding pad 210 during the etching process. After the etching process is complete, method 100 includes a portion (118) of removing the metal or polymer layer and oxide layer using a water jet. Figure 2I1 and 2I2 yes Figure 2H1 and 2H2 The cross-sectional view and top view of the structure differ in that the portions of oxide layer 222 and metal or polymer layer 224 that vertically overlap with opening 236 are removed, as indicated by reference numeral 238, for example by water jet removal.

[0022] Method 100 includes sawing through a semiconductor wafer to produce a semiconductor die (120), coupling bonding wires to bonding pads (122), and applying molding compound to the semiconductor die, semiconductor structure, bonding pads, and bonding wires (124). Figure 3A , 3B And 3C are Figure 2I1 and 2I2 The cross-sectional view, top view, and perspective view of the structure differ in that... Figure 2I1 and 2I2 The structure has been diced (e.g., sawn) to produce a diced structure 300 contained within a semiconductor package 302. More specifically, the diced structure 300 is coupled to a semiconductor die 304 via a die bonding layer 306. The semiconductor die 304 includes a device side that physically contacts the die bonding layer 306, in which a circuit system is formed. The semiconductor die 304 includes a non-device side opposite the device side. The semiconductor die 304 includes a circuit system on the device side configured to operate the circuit system in the diced structure 300, such as a precision circuit system 204. The semiconductor die 304 includes bonding pads 308. The semiconductor die 304 is coupled to a conductive terminal 310 via a die bonding layer 312. The bonding pads 310 are coupled to the bonding pads 308 via bonding wires 314. Bonding wires 316 couple the bonding pads 308 to the conductive terminals 310. In this example, the outer surface of semiconductor structure 235 shares a vertical plane (i.e., is substantially flush) with the corresponding outer surface of oxide layer 222 and the corresponding outer surface of metal or polymer layer 224. These vertical planes lie between the corresponding bonding pads 210 and the corresponding precision circuitry 204. BAW resonator die 221 contains precision circuitry 204. Molding plastic 318 physically contacts and covers various structures of semiconductor package 302, as shown. Semiconductor package 302 can be coupled to PCB 320, for example, by physically contacting conductive terminals 310 and solder joints 322 of metal traces on printed circuit board (PCB) 320.

[0023] In this example, the metal or polymer layer 224 is a flat sheet that physically contacts all or substantially all of the oxide layer 222. Therefore, portions of the metal or polymer layer 224 and the oxide layer 222 remain within the semiconductor package 302, as... Figures 3A-3C As shown in the diagram. However, in other instances, the metal or polymer layer is patterned such that not all oxide layers 222 physically contact the metal or polymer layer. Therefore, the resulting semiconductor package still includes portions of the metal or polymer layer, but does not present a physical contact with it. Figures 3A-3C The same configuration is shown. Now refer to the same configuration. Figure 1 Method 100 and Figure 4A1 , 4A2The manufacturing process of such instances is described by the process flow of 4B1, 4B2, 4C1, 4C2, 4D1, 4D2, 4E1, 4E2, 4F1, 4F2, 4G1, 4G2, 4H1, 4H2, 4I1, 4I2, 5A, 5B and 5C.

[0024] Method 100 includes providing a semiconductor wafer having a precision circuit system and bonding pads (102) on the device side of the wafer. Figure 4A1 and 4A2 Describe step 102. Specifically, Figure 4A1 and 4A2 Is with Figure 2A1 and 2A2 The cross-sectional view and top view of the same structure. Therefore, the above refers to... Figure 2A1 and 2A2 The provided description also applies Figure 4A1 and 4A2 And this will not be repeated here.

[0025] Method 100 includes etching trenches (104) surrounding a circuit system in the device side of a semiconductor wafer using patterned photoresist. Figure 4B1 , 4B2 Step 104 describes 4C1 and 4C2. Specifically, Figure 4B1 and 4B2 Is with Figure 2B1 and 2B2 The cross-sectional view and top view of the same structure. Therefore, the above refers to... Figure 2B1 and 2B2 The provided description also applies Figure 4B1 and 4B2 And this will not be repeated here. Similarly, Figure 4C1 and 4C2 Is with Figure 2C1 and 2C2 The cross-sectional view and top view of the same structure. Therefore, the above refers to... Figure 2C1 and 2C2 The provided description also applies Figure 4C1 and 4C2 And this will not be repeated here.

[0026] Method 100 includes a support structure (106) that couples a metal or polymer layer having an oxide layer and a semiconductor structure coupled thereto to a device side of a semiconductor wafer. Figure 4D1 and 4D2 Describe step 106. Specifically, Figure 4D1 and 4D2 yes Figure 2D1 and 2D2The cross-sectional and top views of the structure differ in that, unlike the metal or polymer layer 224 which is a flat, continuous sheet, the metal or polymer layer 400 is patterned. More specifically, the metal or polymer layer 400 is patterned such that it exists in the gaps between consecutive examples of the support structure 226. The metal or polymer layer 400 does not exist within the space enclosed by the support structure 226. The metal or polymer layer 400 can be, for example, formed by... Figure 4D1 and 4D2 The appropriate photolithography and / or etching techniques or any other suitable techniques are performed prior to the coupling steps depicted in the diagram to pattern the image.

[0027] Method 100 includes thinning the semiconductor structure by grinding (108). Figure 4E1 and 4E2 yes Figure 4D1 and 4D2 The cross-sectional view and top view of the structure differ in that the semiconductor structure 220 has been thinned by grinding, similar to... Figure 2E1 and 2E2 . Figure 2E1 and 2E2 The description applies to Figure 4D1 and 4D2 Therefore, it will not be repeated here.

[0028] Method 100 includes patterning photoresist on a semiconductor structure (110). Figure 4F1 and 4F2 Describe step 110. Specifically, Figure 4F1 and 4F2 Is with Figure 2F1 and 2F2 The cross-sectional and top views of the structure are identical, except that the metal or polymer layer 400 is patterned as described above. The above refers to... Figure 2F1 and 2F2 The remainder of the provided description also applies. Figure 4F1 and 4F2 And this will not be repeated here.

[0029] Method 100 includes thinning a semiconductor wafer by grinding (112). Figure 4G1 and 4G2 Describe step 112. Specifically, Figure 4G1 and 4G2 Is with Figure 2G1 and 2G2 The cross-sectional and top views of the structure are identical, except that the metal or polymer layer 400 is patterned as described above. The above refers to... Figure 2G1 and 2G2 The remainder of the provided description also applies. Figure 4G1 and 4G2 And this will not be repeated here.

[0030] Method 100 includes using patterned photoresist to etch a semiconductor structure to form an opening in the semiconductor structure above bonding pads (114). Method 100 includes removing the patterned photoresist (116). Figure 4H1 and 4H2 Describe steps 114 and 116. Specifically, Figure 4H1 and 4H2 Is with Figure 2H1 and 2H2 The cross-sectional and top views of the structure are identical, except that the metal or polymer layer 400 is patterned as described above. The above refers to... Figure 2H1 and 2H2 The remainder of the provided description also applies. Figure 4H1 and 4H2 And this will not be repeated here.

[0031] Method 100 includes a portion (118) of using a water jet to remove the metal or polymer layer and oxide layer. Figure 4I1 and 4I2 Describe step 118. Specifically, Figure 4I1 and 4I2 Is with Figure 2I1 and 2I2 The cross-sectional and top views of the structure are identical, except that the patterned metal or polymer layers 400 are mostly from... Figure 4I1 and 4I2 The structure is removed. A small portion of the metal or polymer layer 400 is retained, for example, represented by the metal or polymer structure 402. The metal or polymer structure 402 extends laterally away from the support structure 226. More specifically, the metal or polymer structure 402 extends away from the vertical plane defined by the outer surfaces of the semiconductor structure 235 and the oxide layer 222 in a direction away from the precision circuit system 204. All metal or polymer structures 402 are located below the respective oxide layer 222 in cross-sectional and / or sectional views, and within 500 nm of the respective oxide layer 222 in the vertical direction. The metal or polymer structure 402 is irregularly shaped. The metal or polymer structure 402 does not cover the respective precision circuit system 204 (i.e., is not vertically aligned with the respective precision circuit system).

[0032] Method 100 includes sawing through a semiconductor wafer to produce a semiconductor die (120), coupling bonding wires to bonding pads (122), and applying molding compound to the semiconductor die, semiconductor structure, bonding pads, and bonding wires (124). Figure 5A , 5B And 5C is Figure 4I1 and 4I2 The cross-sectional view, top view, and perspective view of the structure differ in that... Figure 4I1 and 4I2 The structure has been diced (e.g., sawn) to produce a diced structure 500 contained within a semiconductor package 502. More specifically, the diced structure 500 is coupled to a semiconductor die 504 via a die bonding layer 506. The semiconductor die 504 includes a device side that physically contacts the die bonding layer 506, in which circuitry is formed. The semiconductor die 504 includes a non-device side opposite the device side. The semiconductor die 504 includes circuitry on the device side configured to operate circuitry in the diced structure 500, such as precision circuitry 204. The semiconductor die 504 includes bonding pads 508. The semiconductor die 504 is coupled to conductive terminals 510 via a die bonding layer 512. Bonding pads 510 are coupled to bonding pads 508 via bonding wires 514. Bonding wires 516 couple bonding pads 508 to conductive terminals 510. BAW resonator die 221 contains a precision circuit system 204. Molding plastic 518 physically contacts and covers various structures of semiconductor package 502, as shown. Semiconductor package 502 can be coupled to PCB 520, for example, by physically contacting conductive terminals 510 and solder joints 522 of metal traces on printed circuit board (PCB) 520.

[0033] Other semiconductor packages that omit the metal or polymer layer are possible. Figure 6 This is a flowchart of a method 600 for manufacturing semiconductor packages using selective etching and water jet techniques to protect bonding pads from contamination, based on various examples. Figure 7A1 , 7A2 7B1, 7B2, 7C1, 7C2, 7D1, 7D2, 7E1, 7E2, 7F1, 7F2, 7G1, 7G2, 7H1, 7H2, 7I1, 7I2, 8A, 8B, and 8C are process flows for fabricating semiconductor packages using selective etching and water jet techniques to protect bonding pads from contamination, based on various examples. Therefore, they are now described in parallel. Figure 6 and 7A1 -8C.

[0034] Method 600 includes coupling an oxide layer with a semiconductor structure to a support structure on the device side of a semiconductor wafer, wherein the semiconductor wafer has a circuit system formed on the device side, the support structure surrounds the circuit system, and the semiconductor wafer has bonding pads (602) on the periphery of the support structure. Figure 7A1 and 7A2 Is with Figure 2A1 and 2A2The cross-sectional view and perspective view of the same structure shown above. Figure 2A1 and 2A2 The provided description also applies Figure 7A1 and 7A2 The structure shown is given, and therefore will not be repeated here. Figure 7B1 and 7B2 Is with Figure 2B1 and 2B2 The cross-sectional view and perspective view of the same structure shown above. Figure 2B1 and 2B2 The provided description also applies Figure 7B1 and 7B2 The structure shown is given, and therefore will not be repeated here. Figure 7C1 and 7C2 Is with Figure 2C1 and 2C2 The cross-sectional view and perspective view of the same structure shown above. Figure 2C1 and 2C2 The provided description also applies Figure 7C1 and 7C2 The structure shown is given, and therefore will not be repeated here. Figure 7D1 and 7D2 Is with Figure 2D1 and 2D2 The cross-sectional and perspective views of the same structure shown above (and therefore provided above) Figure 2D1 and 2D2 The description also applies to Figure 7D1 and 7D2 The difference is that the metal or polymer layer 224 is omitted. Therefore, the oxide layer 222 physically contacts the support structure 226. Figure 7E1 and 7E2 yes Figure 7D1 and 7D2 The cross-sectional view and top view of the structure differ in that the semiconductor structure 220 has been thinned by grinding in the manner described above.

[0035] Method 600 includes patterning a photoresist layer on a semiconductor structure (604). Figure 7F1 and 7F2 Is with Figure 2F1 and 2F2 The cross-sectional and top views of the same structure shown are different in that the metal or polymer layer 224 is omitted. Figure 2F1 and 2F2 The description also applies to Figure 7F1 and 7F2 .also, Figure 7G1 and 7G2 Is with Figure 2G1 and2G2 The cross-sectional and top views of the same structure shown are different in that the metal or polymer layer 224 is omitted. Figure 2G1 and 2G2 The description also applies to Figure 7G1 and 7G2 .

[0036] Method 600 includes using a photoresist layer to etch a semiconductor structure to form a cavity (606) over bonding pads. The semiconductor structure has a thickness (606) in the portion between the cavity and the oxide layer. Figure 7H1 and 7H2 yes Figure 7G1 and 7G2 The cross-sectional and top views of the structure differ in that openings 230 in the patterned photoresist 228 have been etched (e.g., plasma etching) in the semiconductor structure 220 to create openings 700. The etching is performed deep enough that a portion 702 of the semiconductor structure 220 remains between the bottom of the opening 700 and the oxide layer 222. The walls of the opening 700 contain stripes 237, similar to the stripes described above. The description of stripes 237 above also applies to... Figure 7H1 and 7H2 Stripes 237 are formed in the middle. Each of the portions 702 has a thickness in the range of 200 nm to 500 nm, where a thickness below this range is disadvantageous because there is a risk of over-etching and damaging or destroying the oxide layer, and a thickness above this range is disadvantageous because there is a risk that portion 702 will not be completely removed during subsequent manufacturing processes.

[0037] Method 600 includes using a water jet to remove portions of a semiconductor structure and portions of an oxide layer beneath said portions of the semiconductor structure (608). Figure 7I1 and 7I2 yes Figure 7H1 and 7H2 The cross-sectional and top views of the structure differ in that portions 702 and oxide layer 222 that physically contact those portions 702 are removed by a water jet process, thereby producing a single-cut semiconductor structure 235. Therefore, each semiconductor structure 235 has four side surfaces partially but not completely covered by stripes 237. Before the removal of portions 702, there are no stripes 237 in the portions of the four side surfaces that previously physically contacted portions 702 (i.e., the vertical thickness of the non-striped regions of the four side surfaces is in the range of 200 nm to 500 nm, as this is an acceptable thickness range for portions 702 before removal). The oxide layer 222 is not striped.

[0038] Method 600 includes sawing through a semiconductor wafer to produce a single-cut semiconductor die (610), coupling bonding wires to bonding pads (612), and applying molding compound to the semiconductor die, semiconductor structure, bonding pads, and bonding wires (614). Figures 8A-8C It is incorporated into semiconductor package 502 Figure 7I1 and 7I2 The cross-sectional view, top view, and perspective view of the structure. Except as described above, the metal or polymer structure 402 is omitted and the position of stripe 237 differs. Figures 8A-8C 802 semiconductor package and Figures 5A-5C The semiconductor package is the same as 502. Figures 5A-5C The 502 semiconductor package is otherwise identical to the 8A-8C package, and therefore... Figures 5A-5C The description also applies to Figures 8A-8C (Except for the exceptions described above), and therefore will not be repeated here.

[0039] Figure 9 This is a block diagram of an example electronic device 900 including a semiconductor package 902 coupled to a PCB 904. The semiconductor package 902 is manufactured according to any of the techniques described herein. For example, the semiconductor package 902 refers to the semiconductor packages 302 and 502 described above.

[0040] In this specification, the term "coupled" may encompass a connection, communication, or signaling path that enables the functional relationship to be consistent with this specification. For example, if device A generates a signal to control device B to perform an action, then: (a) in a first instance, device A is coupled to device B via a direct connection; or (b) in a second instance, device A is coupled to device B via an intermediate component C, provided that the intermediate component C does not alter the functional relationship between device A and device B, such that device B is controlled by device A via a control signal generated by device A.

[0041] A device “configured” to perform a task or function may be configured (e.g., programmed and / or hardwired) to perform the function during manufacturing by the manufacturer, and / or may be configured (or reconfigurable) by the user after manufacturing to perform the function and / or other additional or alternative functions. This configuration may be performed through firmware and / or software programming of the device, through the construction and / or layout of the device’s hardware components and interconnects, or through a combination thereof.

[0042] In this specification, unless otherwise stated, "about," "approximately," or "substantially" before a parameter means within + / - 10% of said parameter. Modifications may be made in the described examples within the scope of the claims, and other examples are possible.

[0043] As used herein, the terms “terminal,” “node,” “interconnect,” “pin,” “conductive terminal,” and “lead” are used interchangeably. Unless otherwise specified, these terms are generally used to refer to interconnects or their ends between device elements, circuit elements, integrated circuits, devices, or semiconductor assemblies.

Claims

1. A semiconductor package comprising: A bulk acoustic wave (BAW) resonator die having a device side on which a circuit system is formed; A support structure that is coupled to the device side and surrounds the circuit system; Bonding pads are coupled to the device side and are located on the periphery of the support structure; A metal or polymer layer coupled to the support structure and covering the circuit system; An etch stop layer is coupled to the metal or polymer layer; as well as A passive semiconductor structure coupled to the etch stop layer such that the etch stop layer is between the semiconductor structure and the metal or polymer layer, wherein the outer surfaces of the metal or polymer layer, the etch stop layer and the semiconductor structure are substantially flush with each other, and all of the outer surfaces of the semiconductor structure have plasma etch stripes.

2. The semiconductor package of claim 1, wherein the metal or polymer layer has a thickness between 0.5 micrometers and 5 micrometers.

3. The semiconductor package of claim 1, wherein the metal or polymer layer is selected from the group consisting of aluminum, copper, tungsten, and titanium-tungsten.

4. The semiconductor package of claim 1, wherein the metal or polymer layer is selected from the group consisting of polyimide, benzocyclobutene, polydimethylsiloxane, SU-8 and polybenzoxazole.

5. The semiconductor package of claim 1, wherein the BAW resonator die includes a trench surrounding the circuit system, and wherein the support structure surrounds the trench.

6. The semiconductor package of claim 1, wherein the etch stop layer has a thickness in the range of 0.1 micrometers to 3 micrometers.

7. A semiconductor package comprising: A bulk acoustic wave (BAW) resonator die having a device side on which a circuit system is formed; A support structure that is coupled to the device side and surrounds the circuit system; Bonding pads are coupled to the device side and are located on the periphery of the support structure; An oxide layer coupled to the support structure; A passive semiconductor structure coupled to the oxide layer such that the oxide layer is between the semiconductor structure and the support structure, wherein the outer surfaces of the oxide layer and the semiconductor structure are substantially flush with each other, and all of the outer surfaces of the semiconductor structure have stripes; as well as A metal or polymer structure that physically contacts at least one of the outer surfaces of the semiconductor structure, the metal or polymer structure extending away from the vertical plane defined by the outer surfaces of the semiconductor structure and the oxide layer in a direction away from the circuit system.

8. The semiconductor package of claim 7, wherein all of the metal or polymer structures are within 500 nm of the oxide layer in the vertical direction.

9. The semiconductor package of claim 8, wherein, when viewed in cross-sectional view, the metal or polymer structure is beneath the oxide layer.

10. The semiconductor package of claim 7, wherein the metal or polymer structure is selected from the group consisting of aluminum, copper, tungsten, and titanium-tungsten.

11. The semiconductor package of claim 7, wherein the metal or polymer structure is selected from the group consisting of polyimide, benzocyclobutene, polydimethylsiloxane, SU-8 and polybenzoxazole.

12. The semiconductor package of claim 7, wherein the metal or polymer structure does not cover the circuit system.

13. The semiconductor package of claim 7, wherein the metal or polymer structure is irregularly shaped.

14. The semiconductor package of claim 7, wherein the BAW resonator die includes a trench surrounding the circuit system, and wherein the support structure surrounds the trench.

15. The semiconductor package of claim 7, wherein the oxide layer has a thickness in the range of 0.1 micrometers to 3 micrometers.

16. A semiconductor package comprising: A bulk acoustic wave (BAW) resonator die having a device side on which a circuit system is formed; A support structure that is coupled to the device side and surrounds the circuit system; Bonding pads are coupled to the device side and are located on the periphery of the support structure; An oxide layer that physically contacts the support structure and covers the circuit system, the support structure separating the oxide layer from the BAW resonator die through a gap, the oxide layer having a first outer surface; A passive semiconductor structure that physically contacts the oxide layer and covers the circuit system, the semiconductor structure having a second outer surface that shares a vertical plane with the first outer surface and having a top surface and a bottom surface; Bonding wires coupled to the bonding pads and to conductive terminals; as well as A molding compound covering the BAW resonator die, the support structure, the bonding pads, the oxide layer, the semiconductor structure, and the bonding wires, with the conductive terminals exposed on the outer surface of the molding compound. A first portion of the second outer surface of the layer extending from the top surface of the semiconductor structure to the layer between the top surface and the bottom surface of the semiconductor structure contains stripes, while a second portion of the second outer surface extending from the layer to the bottom surface of the semiconductor structure does not contain stripes, and wherein the first outer surface does not contain stripes.

17. The semiconductor package of claim 16, wherein the stripes are plasma etched stripes.

18. The semiconductor package of claim 16, wherein the bonding pads are further away from the circuit system than the vertical plane.

19. The semiconductor package of claim 16, further comprising a trench surrounding the circuit system, wherein the support structure surrounds the trench.

20. The semiconductor package of claim 16, wherein the layer is located between 200 nm and 500 nm from the bottom surface of the semiconductor structure.

21. The semiconductor package of claim 16, wherein at least one of the stripes extends across the four outer surfaces of the semiconductor structure.

22. A method for manufacturing a semiconductor package, comprising: An oxide layer coupled with a semiconductor structure is coupled to a support structure on the device side of a semiconductor wafer, the semiconductor wafer having a circuit system formed in the device side, the support structure surrounding the circuit system, and the semiconductor wafer having bonding pads on the periphery of the support structure. Patterning the photoresist layer on the semiconductor structure; The semiconductor structure is etched using the photoresist layer to form a cavity over the bonding pads, the semiconductor structure having a thickness in the portion between the cavity and the oxide layer; The portion of the semiconductor structure and the portion of the oxide layer below the portion of the semiconductor structure are removed using a water jet. The semiconductor wafer is sawed through to produce a single-cut semiconductor die; Couple the bonding wire to the bonding pad; as well as Molding compound is applied to the semiconductor die, the semiconductor structure, the bonding pads, and the bonding wires.

23. The method of claim 22, wherein the thickness is in the range of 200 nm to 500 nm.

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