Current-based device filter

Abstract

The present disclosure relates to current-based device filters. A circuit (100a) includes a first input stage (101) having an input (106) to receive an input current and an output (109), a first amplifier (103) having an input (111) coupled to the output (109) of the first input stage (101) and an output (113), a second amplifier (105) having an input (115) coupled to the output (113) of the first amplifier (103) and an output (117), a first resistor (116) coupled between the output of the first amplifier (103) and the input of the second amplifier (105), a first capacitor (118) coupled to the first resistor (116) and to the input of the second amplifier (105), and a first output stage (132) having an input coupled to the output of the second amplifier (105) and an output configured to provide an output current.

Description

Technical Field

[0001] This disclosure generally relates to circuits, and more specifically, to current-based device filters. Background Technology

[0002] Device filters are used to attenuate certain frequency components of an input signal. Device filters can be implemented as low-pass filters, high-pass filters, or band-pass filters. An example of a low-pass filter is a basic RC circuit with a resistor (R) and a capacitor (C) in series. The capacitor attenuates (or blocks) the high-frequency components of the input signal while allowing the low-frequency components to pass through. Therefore, for example, in some audio applications, a low-pass filter can receive an input signal that mixes soothing low-frequency components with unwanted high-frequency ("screaming") components, attenuating the unwanted high-frequency components while allowing the low-frequency components to provide a more soothing output signal to the human ear. Summary of the Invention

[0003] According to an embodiment, a circuit includes: a first input stage having an input configured to receive an input current and an output; a first amplifier having an input coupled to the output of the first input stage and an output; a second amplifier having an input coupled to the output of the first amplifier and an output; a first resistor coupled between the output of the first amplifier and the input of the second amplifier; a first capacitor coupled to the first resistor and coupled to the input of the second amplifier; a first output stage having an input coupled to the output of the second amplifier and an output configured to provide an output current; and a first feedback path coupled between the second amplifier and the input of the first amplifier. The first feedback path includes: a buffer having an output coupled to the input of the first amplifier; and a second capacitor.

[0004] According to an embodiment, a circuit includes: a first input stage having an input configured to receive an input current and an output; a first transistor having a control terminal coupled to the output of the first input stage and a current path; a second transistor having a control terminal and a current path; a current mirror coupled between the current path of the first transistor and the current path of the second transistor; a first output stage having an input coupled to the control terminal of the second transistor and an output configured to provide an output current; a first resistor coupled between the output of the first input stage and the control terminal of the first transistor; a first capacitor coupled to the first resistor and coupled to the control terminal of the first transistor; and a first feedback path having an output coupled to the first resistor. The first feedback path includes: a buffer having an output coupled to the control terminal of the first transistor; and a second capacitor.

[0005] According to an embodiment, a transceiver includes: a first filter having an input and an output; a first mixer having an input and an output, the input of the first mixer being coupled to the output of the first filter; a second mixer having an input and an output; and a second filter having an input and an output, the input of the second filter being coupled to the output of the second mixer. The first filter includes: a first amplifier having an input coupled to the input of the first filter and an output; a second amplifier having an input coupled to the output of the first amplifier and an output; and a first feedback path coupled between the second amplifier and the input of the first amplifier, and including a buffer and a capacitor. Attached Figure Description

[0006] Figure 1A Examples of current-based device filters are shown.

[0007] Figure 1B This demonstrates another example of a current-based device filter.

[0008] Figure 1C This demonstrates another example of a current-based device filter.

[0009] Figure 1D This demonstrates another example of a current-based device filter.

[0010] Figure 1E This demonstrates another example of a current-based device filter.

[0011] Figure 1F This demonstrates another example of a current-based device filter.

[0012] Figure 1G This demonstrates another example of a current-based device filter.

[0013] Figure 1H This demonstrates another example of a current-based device filter.

[0014] Figure 2 An example of a cascaded filter containing two current-based device filters is shown.

[0015] Figure 3 This section demonstrates an example of a transceiver.

[0016] Figure 4 Show an example of a buffer.

[0017] Figure 5 Examples of current-based mixers are shown.

[0018] Figure 6A and 6B Two examples of current-based device filters are shown.

[0019] Figure 7 This section demonstrates an example of a differential transceiver. Detailed Implementation

[0020] Current-based device filters are an important class of electronic circuits developed to meet the needs of modern applications. These filters operate by processing signals as current rather than voltage, which offers several advantages in circuit design and implementation.

[0021] Current-mode filters are subject to certain limitations in their ability to balance die area and quality factor (Q). Specifically, some current-mode filters use cascaded amplifiers, but filters employing multiple amplifiers occupy significant die space, thus limiting their miniaturization potential. This is a particular concern in the context of modern integrated circuit design, where reducing die area is crucial for increasing device density and reducing manufacturing costs.

[0022] Furthermore, using multiple amplifiers increases power consumption and heat generation, which can compromise filter reliability and lifespan. In contrast, filters optimized for limited space may struggle to achieve sufficient Q, resulting in compromised frequency selectivity and stability. The growing demand for higher data rates and more stringent standards necessitates improved current-mode filters that offer a better balance between die area and filter quality.

[0023] Therefore, a current-based device filter is disclosed, which incorporates a buffer and a capacitor in the feedback path, enabling a double quadratic response while minimizing die area compared to other filters. The inclusion of a capacitor in this feedback path allows for improved frequency selectivity and stability, while the use of a buffer reduces out-of-band zeros and ensures a more predictable and desirable frequency response.

[0024] Figure 1A An example of an integrated circuit, a current-based device filter 100a, is shown. The current-based device filter 100a includes an input stage 101, a current source 102, a first amplifier 103, a second amplifier 105, an input 106, and various electronic components connected to them. Specifically, the input stage 101 includes a first transistor 104 and a second transistor 108. The first amplifier 103 includes a third transistor 112 and a fourth transistor 114. The second amplifier 105 includes a fifth transistor 120 and a sixth transistor 122. Additionally, the current-based device filter 100a includes a buffer 124, a first resistor 110, a second resistor 116, a first capacitor 118, a second capacitor 126, a third resistor 128, a third capacitor 130, and a seventh transistor 132. The first amplifier 103 may be configured to have unity gain, and the second amplifier 105 may be configured to have unity gain. In some cases, the first amplifier 103 may be referred to as a first buffer, and the second amplifier 105 may be referred to as a second buffer.

[0025] Input stage 101 has an input 106 configured to receive input current and an output 109 configured to provide output current. The power supply terminal of input stage 101 is a first current terminal (e.g., drain terminal) of first transistor 104. Current source 102 has a terminal coupled to the first current terminal of first transistor 104 and biases input stage 101. Input 106 of input stage 101 is coupled to a second current terminal (e.g., source terminal) of first transistor 104 and to a first current terminal (e.g., drain terminal) of second transistor 108. Output 109 of input stage 101 is coupled to the first current terminal of first transistor 104, the control terminal of second transistor 108, and a first terminal of first resistor 110. The control terminal of first transistor 104 is coupled to an input voltage bias (Vb). The second current terminal (e.g., source terminal) of second transistor 108 is coupled to a reference terminal (e.g., ground or VSS).

[0026] The first amplifier has an input 111 and an output 113. Within the first amplifier 103, the control terminal of the third transistor 112 is the input 111 of the first amplifier 103. The fourth transistor 114 has a first current terminal coupled to both the first current terminal of the third transistor 112 and the control terminal of the fourth transistor 114. The third transistor 112 has a second current terminal coupled to a reference terminal. The fourth transistor 114 has a second current terminal coupled to a power supply terminal (e.g., VDD). The first current terminal of the fourth transistor 114 is the output of the first amplifier 103. The reference terminal may alternatively be referred to as the second power supply terminal.

[0027] The second resistor 116 has a first terminal coupled to the output 113 of the first amplifier 103 and a second terminal coupled to both the first terminal of the first capacitor 118 and the input 115 of the second amplifier 105. The first capacitor 118 has a second terminal coupled to a power supply terminal. The first RC filter is formed by the second resistor 116 and the first capacitor 118.

[0028] Within the second amplifier 105, the fifth transistor 120 has a control terminal that serves as an input to the second amplifier 105. The fifth transistor 120 has a first current terminal coupled to a power supply terminal and a second current terminal coupled to a first current terminal of the sixth transistor 122. The first current terminal of the sixth transistor 122 is also coupled to a control terminal of the sixth transistor 122. The sixth transistor 122 has a second current terminal coupled to a reference terminal. The output of the second amplifier is the first current terminal and the control terminal of the sixth transistor 122.

[0029] A feedback path is provided from the control terminal of the sixth transistor 122 to the control terminal of the third transistor 112, and the feedback path includes a buffer 124 and a second capacitor 126. The buffer has an input coupled to the control terminal of the sixth transistor 122 and an output coupled to one terminal of the second capacitor 126. A second terminal of the second capacitor 126 is coupled to the control terminal of the third transistor 112.

[0030] A third resistor 128 is coupled between the control terminal of the sixth transistor 122 and the first terminal of the third capacitor 130, as well as the control terminal of the seventh transistor 132. The second terminal of the third capacitor 130 is coupled to a reference terminal. Additionally, the first current terminal of the seventh transistor 132 is coupled to an output terminal, and the second current terminal of the seventh transistor is coupled to a reference terminal.

[0031] The first transistor 104 and the second transistor 108 are both depicted as n-type transistors. The third transistor 112 and the sixth transistor 122 are both n-type transistors, while the fourth transistor 114 and the fifth transistor 120 are both p-type transistors. Alternatively, an equivalent circuit utilizing transistors of opposite polarity can be used. The seventh transistor 132 can be designated as the output stage. The resistance and capacitance values ​​of the filter can be varied to achieve the desired filter response. For example, the resistance and capacitance values ​​of the filter can be configured to provide a Butterworth response. The current-based device filter 100a is a third-order filter.

[0032] The current-based device filter 100a operates as follows: Input stage 101 receives a current input signal from input 106. A first transistor 104, configured as a common-gate amplifier, obtains the input current from a low-impedance source (e.g., input 106) and transmits the input current to an output current with high impedance (e.g., output 109), thereby effectively buffering the current. Additionally, a second transistor 108 operates similarly to a diode-connected transistor, while the first transistor 104 acts as a current buffer between the drain terminal and gate terminal of the second transistor 108.

[0033] The input 111 of the first amplifier 103 is controlled by the voltage provided by the output 109 of the input stage 101, and the output 113 of the first amplifier establishes the voltage for controlling transistors 114 and 120. The third transistor 112 is configured as a common-source amplifier, thereby generating an inverted and amplified output signal. The fourth transistor 114 is arranged in a diode configuration. The output 113 of the first amplifier 103 is determined by the transconductance characteristics of both the third transistor 112 and the fourth transistor 114, and is inverted relative to the input signal at input 111.

[0034] The second resistor 116 and the first capacitor 118 serve as a filter circuit between the output 113 of the first amplifier 103 and the input 115 of the second amplifier 105. The second resistor 116 and the first capacitor 118 can form a first low-pass filter. Because the first capacitor 118 stores charge, it can be regarded as a first memory element that provides a first pole to the system.

[0035] The second amplifier 105 has an input 115 at the gate terminal of the fifth transistor 120 and an output 117 coupled to both the drain terminal and the gate terminal of the sixth transistor 122. The fifth transistor 120 is configured as a common-source amplifier that also inverts the input signal. The inverting characteristic inherent in the fifth transistor 120 effectively cancels the inversion produced by the first amplifier 103. The sixth transistor 122 is implemented in a diode configuration. Therefore, the second amplifier 105 exhibits structural similarity to the first amplifier 103, employing a common-source amplifier and diode-connected transistors, differing only in the polarity of the respective transistors. If the transistors in the first amplifier 103 and the second amplifier 105 are identical, the gain characteristics of the amplifiers will exhibit an inverse relationship. For example, if the first amplifier 103 has a gain denoted as k1, and the second amplifier 105 exhibits a gain denoted as k2, then k1 = 1 / k2. This inverse relationship provides the unity gain at the input 111 of the first amplifier 103 to the output 117 of the second amplifier 105.

[0036] The output 117 of the second amplifier 105 is coupled to a feedback path that includes a buffer 124 and a second capacitor 126. The second capacitor 126 introduces an additional pole into the filter, thereby achieving a double quadratic response. Furthermore, the buffer 124 provides a low-impedance source for the second capacitor 126.

[0037] The output signal from the output 117 of the second amplifier 105 is further directed to a second RC filter comprising a third resistor 128 and a third capacitor 130. This second RC filter may also be implemented as a low-pass filter. In a common-source amplifier configuration, the output generated by this second RC filter at the third resistor and third capacitor 130 is coupled to the gate terminal of the seventh transistor 132. The seventh transistor 132 may also be designated as an output stage, and alternative suitable output stages may be employed.

[0038] The current-based device filter 100a offers several significant advantages. The feedback path, including the second capacitor 126, establishes a second memory element, thereby introducing an additional pole into the system. This improves the filter's frequency selectivity and quality factor (Q), resulting in a clearer frequency response and enhanced signal isolation. Additionally, the buffer 124 increases the output impedance seen from the output 117 of the second amplifier 105 by the feedback path. This operating characteristic minimizes the possibility of out-of-band zeros typically introduced by the feedback loop, ensuring a more predictable and desirable frequency response. Furthermore, the minimized footprint achieved through integrated design reduces die area requirements compared to conventional multi-amplifier filters, contributing to increased device density and reduced manufacturing costs.

[0039] Another advantage of the current-based device filter 100a is its ability to utilize device capacitors (e.g., polycrystalline silicon capacitors) instead of conventional metal capacitors. For example, capacitors 118, 126, and 130 can all be device capacitors. Device capacitors can be formed by forming a dielectric layer (e.g., semiconductor oxide) on a semiconductor substrate and then forming a polycrystalline semiconductor layer on the dielectric layer. In contrast, an interlayer dielectric (ILD) material can be used as a dielectric layer between conductor (e.g., metal) features to form a metal capacitor in the wiring layer of the device. Compared to ILD metal capacitors, device capacitors can utilize less horizontal area because the vertical thickness of the dielectric layer is smaller than the vertical thickness of the ILD material in an ILD metal capacitor. The current-based device filter 100a can utilize smaller device capacitors, even though these device capacitors are more fragile than ILD metal capacitors, because the feedback path is configured to receive the input signal with unity gain, thereby avoiding high voltage swings that could potentially damage the dielectric in the device capacitor. Although some or all of capacitors 118, 126 and 130 may be device capacitors in a given instance, the integrated circuit in which the current-based device filter 100a is integrated may also utilize ILD metal capacitors in other parts of the device.

[0040] although Figure 1A The transistor in the diagram is described as a metal-oxide-semiconductor field-effect transistor (MOSFET), but other types of transistors can be used. For example, in Figure 1A In this diagram, each MOSFET has a source / drain (an example of a first current terminal), a drain / source (an example of a second current terminal), and a gate terminal (an example of a control terminal). Bipolar junction transistors (BJTs), FinFETs, junction FETs (JFETs), and other transistors can be used instead of the illustrated MOSFETs. A BJT includes a collector / emitter (an example of a first current terminal), an emitter / collector (an example of a second current terminal), and a base (an example of a control terminal).

[0041] Figure 1B-1H This section describes alternative examples of current-based device filters 100b-100h, in which... Figure 1A The structure of the current-based device filter 100a shown is modified in various ways. Unless otherwise stated, Figure 1B-1H The components are similar to those in Figure 1A The corresponding element in.

[0042] Figure 1BA current-based device filter 100b is depicted, wherein the configuration of the feedback path has been modified by interchanging the positions of buffer 124 and second capacitor 126. Specifically, the first terminal of the second capacitor 126 is now coupled to the control terminal of the sixth transistor 122, while the second terminal of the second capacitor 126 is coupled to the input of buffer 124. The output of buffer 124 is then coupled to the control terminal of the first amplifier 103. This configuration implements an alternative embodiment of the current-based device filter 100b that retains the benefits of double secondary response and improved frequency selectivity while providing design and layout flexibility.

[0043] Figure 1C A current-based device filter 100c is depicted, wherein the feedback path originates from the input of a second amplifier 105 rather than its output. To eliminate the inversion introduced by the first amplifier 103, an inverter 134 is incorporated into the feedback path. Specifically, the inverter 134 has an input coupled to the input of the second amplifier 105 and an output coupled to a first terminal of a second capacitor 126. The second capacitor 126 has a second terminal coupled to the input of a buffer 124, while the output of the buffer 124 is coupled to the input of the first amplifier 103.

[0044] Figure 1D The diagram illustrates a current-based device filter 100d, where the feedback path originates from the input of a second amplifier 105. In this configuration, an inverter 134 has an input terminal coupled to the input of the second amplifier 105 and an output terminal coupled to the input of a buffer 124. The output of the buffer 124 is coupled to a first terminal of a second capacitor 126, while a second terminal of the second capacitor 126 is coupled to the input of a first amplifier 103. Furthermore, the inverter and buffer can be combined into a single circuit block.

[0045] Figure 1E-1H An alternative example of a current-based device filter 100e-100h is shown, wherein a second resistor 116 and a first capacitor 118 have been repositioned between the output of the feedback path and the input of the first amplifier 103.

[0046] Figure 1EA current-based device filter 100e is shown, wherein a second resistor 116 and a first capacitor 118 are positioned between the output of the feedback path and the input of a first amplifier 103. Therefore, the combination of a fourth transistor 114 and a fifth transistor now forms a current mirror 107. The current mirror 107 is coupled between the current path terminals of a third transistor 112 and a sixth transistor 122. A first resistor 110 has a terminal coupled to a first terminal of the second resistor 116, while a second terminal of the second resistor is coupled to a first terminal of the first capacitor 118 and to the input of the first amplifier 103. The first capacitor 118 also has a second terminal coupled to a reference terminal.

[0047] Figure 1F A current-based device filter 100f is shown, which is similar to the current-based device filter 100E, except that the positions of the buffer 124 and the second capacitor 126 are reversed. In this configuration, the second capacitor 126 has a first terminal coupled to the output of the second amplifier 105 and a second terminal coupled to the input of the buffer 124. The output of the buffer is coupled to the first terminal of the second resistor 116.

[0048] Figure 1G A current-based device filter 100g is shown, such that the feedback path originates from the input of a second amplifier 105. In this example, the feedback path also includes an inverter 134. The inverter 134 has an input coupled to the input of the second amplifier and an output coupled to the first terminal of a second capacitor 126. The second capacitor has a second terminal coupled to the input of a buffer 124. The buffer has an output coupled to the first terminal of a second resistor 116.

[0049] Figure 1H A current-based device filter 100h is shown, such that the feedback path originates from the input of a second amplifier 105 and includes an inverter 134. The inverter 134 has an input coupled to the input of the second amplifier 105 and an output coupled to the input of a buffer 124. The buffer 124 has an output coupled to the first terminal of a second capacitor 126. The second capacitor 126 has an output coupled to the first terminal of a second resistor 116.

[0050] exist Figure 1A-1H In this context, the terminals of a transistor may be referred to as current terminals, current path terminals, or specific to the transistor implementation. For example, each terminal may be a source terminal, a drain terminal, or a gate terminal. Alternatively, a terminal may be referred to as a current path between the source and drain terminals, and may also include a control terminal. Furthermore, the transistor shown is a metal-oxide-semiconductor field-effect transistor (MOSFET), but other transistor technologies such as junction field-effect transistors (JFETs), bipolar junction transistors (BJTs), and their corresponding terminal names may be used.

[0051] Figure 2 This illustrates an exemplary example of a cascaded filter configuration 200, in which multiple current-based device filters are coupled together to form a high-performance filtering system. Specifically, such as... Figure 2 As shown, a first current-based device filter 100a and a second current-based device filter 100a' are cascaded together, with the output of the first filter 100a coupled to the input of the second filter 100a'. In other examples, one or more of the first device filter 100a and the second device filter 100a' are replaced with any of the device filters 100b-100h. These configurations enable complex filtering functions through multi-stage combinations, thereby providing enhanced signal processing capabilities. Compared to conventional single-stage filters, using cascaded filter configurations offers several advantages, such as the ability to implement higher-order filtering functions, which are essential in many applications requiring precise signal processing.

[0052] Apart from Figure 2 Beyond the exemplary example shown, more stages of filters can be added to the cascade configuration. For example, although in Figure 2 Only two filters are described, but there can be 2-8 stages or 3-4 stages, thus enabling a wide range of filtering functions and applications.

[0053] Figure 3 This diagram illustrates an example of transceiver 300. Transceiver 300 includes a controller 302, a first filter 308, a first mixer 310, a duplexer 312, an antenna 314, a second mixer 316, a second filter 318, and a local oscillator 320. The controller includes a digital-to-analog converter (DAC) 304 and an analog-to-digital converter (ADC) 306. Transceiver 300 can be an ultra-wideband (UWB) transceiver.

[0054] DAC 304 has an output coupled to an input of a first filter 308, which may include one or more of current-based device filters 100a-100h. First filter 308 has an output coupled to a first mixer 310. The first mixer also receives an input from a local oscillator 320 and provides its output to a duplexer 312. The duplexer has an output to an antenna 314 and an output to a second mixer 316. The second mixer has another input from the local oscillator 320 and provides its output to an input of a second filter 318, which may also include one or more of current-based device filters 100a-100h. Second filter 318 has an output coupled to an ADC 306.

[0055] The transceiver 300 operates by sending a baseband signal to a first filter 308. The first filter 308 filters the signal and provides it to a first mixer 310, which multiplies the filtered signal with an input from a local oscillator 320 to produce a radio frequency (RF) output. The output signal then goes to a duplexer 312, which switches the input / output from the antenna 314. This process enables efficient signal transmission while minimizing interference.

[0056] Alternatively, when a signal is received, antenna 314 receives the signal, duplexer 312 receives the signal and sends it to second mixer 316. Second mixer 316 also receives input from local oscillator 320 and provides its output to second filter 318. After passing through second mixer 316, the signal is now in baseband. Second filter 318 then filters the signal and provides its output to ADC 306 for processing by controller 302.

[0057] The use of current-based device filters 100a-100h in the first filter 308 and the second filter 318 enables the transceiver to achieve improved filtering capabilities. These filters provide enhanced selectivity and suppression of unwanted signals, thereby allowing the system to more effectively suppress out-of-band interference and improve the system's ability to detect weak signals. This improves the overall performance and reliability of the transceiver.

[0058] Figure 4 An example of buffer 124 is illustrated. Buffer 124 includes a current source 402, a first transistor 404, a second transistor 406, and a third transistor 408. Additionally, a bias circuit 410 may be included to provide further functionality. For compatibility with... Figure 1A-1H In this configuration, the input signal is provided from the right side, while the output is obtained from the left side.

[0059] The third transistor 408 has a control terminal coupled to the output of the bias circuit 410. The bias circuit 410 has an input coupled to the input of the buffer 124. The third transistor 408 is in a common-source configuration such that the drain terminal (first current terminal) is the amplified output, and the source terminal (second current terminal) is coupled to the reference terminal. The first current terminal of the third transistor 408 is coupled to the first current terminal of the first transistor 404, the current source 402, and the control terminal of the second transistor 406. The second current terminal of the first transistor 404 is coupled to the first current terminal of the second transistor 406. The second current terminal of the first transistor 404 is the output of the buffer. The first transistor 404 has a control terminal coupled to the voltage bias (Vb) input. The second transistor 406 has a second current terminal coupled to the reference terminal.

[0060] The bias circuit 410 includes a first resistor 412, a second resistor 416, and a first capacitor 414. The first capacitor 414 has a first terminal coupled to the input of the bias circuit 410. The first capacitor 414 also has a second terminal coupled to the output of the current bias circuit, a first terminal of the first resistor 412, and a first terminal of the second resistor 416. The first resistor 412 has a second terminal coupled to a power supply terminal. The second resistor has a second terminal coupled to a reference terminal. The bias circuit 410 biases the third transistor 408 to operate in saturation mode. When used in examples 100a, 100d, 100e, and 100h, the bias circuit may be absent, where the input of the buffer 124 is coupled to the gate of the transistor, thus properly biasing the input to the buffer 124. Additionally, the first capacitor 414 can be removed because the second capacitor 126 is already in the feedback path.

[0061] Because the first transistor 404 receives a relatively stable gate voltage, it functions as a resistor in this circuit. The first transistor 404, together with the current source 402, is used to set the bias point of the transistor. The second transistor 406 operates similarly to a diode-connected transistor. The third transistor 408 is used to amplify the input signal. The advantage of this buffer configuration is that it combines biasing, current handling, and amplification into a single stage.

[0062] Figure 5 An example of a current-based mixer 500 that can be coupled to the output of a current-based device filter 100a-100h is described. The current-based mixer 500 includes a first transformer 501, a second transformer 514, a first diode 506, a second diode 508, a third diode 510, and a fourth diode 512.

[0063] The first transformer 501 includes a primary coil 502 and a secondary coil 504. The second transformer includes a primary coil 518 and a secondary coil 516. The primary coil 502 has a first terminal coupled to an input, which can be the output of a current-based device filter 100a-100h or a local oscillator. The second terminal of the primary coil 502 is coupled to a reference terminal. The secondary coil 504 is coupled between a first diode 506 and a third diode 510, and between a second diode 508 and a fourth diode 512. Additionally, the secondary coil 504 has a center tap coupled to ground.

[0064] The primary coil 518 of the second transformer 514 has a first terminal coupled to another input, which may be the output of a current-based device filter 100a-100h or a local oscillator. The second terminal of the primary coil 518 is coupled to a reference terminal. The secondary coil 516 of the second transformer 514 is coupled between a first diode 506 and a second diode 508, and between a third diode 510 and a fourth diode 512. Furthermore, the secondary coil 516 has a center tap coupled to the output of a current-based mixer.

[0065] The first diode 506 has a cathode coupled to the anode of the second diode 508. The second diode 508 has a cathode coupled to the anode of the fourth diode 512. The fourth diode 512 has a cathode coupled to the anode of the third diode 510. The third diode has a cathode coupled to the anode of the first diode 506.

[0066] The first transformer 501 and the second transformer 514 serve as baluns to magnetically couple the input at the desired impedance. Diodes are used to provide an approximate multiplicative nonlinear relationship.

[0067] Figure 6A and Figure 6B An example of a pseudo-differential filter 600 is shown, the pseudo-differential filter comprising, based on the above... Figure 1A-1H Two current-based device filters 601a and 601b are used, based on the principle of [the above]. In this example, differential signaling can be used. For example, the first current-based device filter 601a can receive a first signal at input 106a, and the second current-based device filter 601b can receive a second signal, which is an inverted version of the first signal, at input 106b. The first current-based device filter 601a is shown similarly to the current-based device filter 100c, except that the feedback path 604 comes from the input 115b of the second current-based device filter 601b. Similarly, the feedback path 603 of the second current-based device filter 601b comes from the input 115a of the first current-based device filter. This configuration is achieved by removing the previously [previous configuration]. Figure 1C The inverter shown is used to advantageously reduce the number of circuit elements. Additionally, the first current-based device filter 601a can be any of the examples 100a-100h that are modified to have the mentioned feedback path. Similarly, the second current-based device filter 601b can be any of the examples 100a-100h that are modified to have the mentioned feedback path.

[0068] Figure 7An example of a differential-based transceiver 700 is shown. The differential-based transceiver 700 includes a controller 702, a first pseudo-differential filter 714, a first mixer 708, a duplexer 710, an antenna 314, a local oscillator 320, a second mixer 712, and a second pseudo-differential filter 716. The controller 702 includes a first digital-to-analog converter (DAC) 713 and a first analog-to-digital converter (ADC) 715. The first pseudo-differential filter 714 includes a first filter 704 and a second filter 705. The second pseudo-differential filter 716 includes a third filter 706 and a fourth filter 707. Both the first pseudo-differential filter 714 and the second pseudo-differential filter 716 can be the pseudo-differential filter 600 shown in Figure 6.

[0069] The first DAC 713 has inputs coupled to the inputs of a first filter 704 and outputs coupled to the inputs of a second filter 705. The first filter 704 and the second filter 705 can be current-based device filters 601a-601b as shown in FIG. 6. Therefore, the first filter 704 can be coupled to the second filter 705 via feedback paths 720-721. The first filter 704 has an output coupled to a first mixer 708. The second filter 705 has an output coupled to the first mixer 708. The local oscillator 320 has an output coupled to the first mixer 708. The first mixer 708 has two outputs coupled to a duplexer 710. The duplexer has an output coupled to an antenna 314. The coupling between the duplexer 710 and the antenna 314 can be achieved using differential signaling. The duplexer 710 has two outputs coupled to a second mixer 712. The local oscillator 320 has a second output coupled to the second mixer 712. The second mixer 712 has a first output coupled to the third filter 706 and a second output coupled to the fourth filter 707. The third filter 706 and the fourth filter 707 can also be current-based device filters 601a-601b as shown in FIG. 6. Therefore, the third filter 706 and the fourth filter 707 can be coupled via feedback paths 722-723. The third filter 706 has an output coupled to the first ADC 715. The fourth filter 707 has an output coupled to the first ADC 715.

[0070] The differential-based transceiver 700 advantageously utilizes differential signaling throughout the transmission and reception paths. Differential signaling allows for increased common-mode rejection, thereby improving signal quality.

[0071] Examples of embodiments of this disclosure are outlined herein. Other embodiments may be understood from the entire specification and claims submitted herein.

[0072] Example 1. A circuit comprising: a first input stage having an input configured to receive an input current and an output; a first amplifier having an input coupled to the output of the first input stage and an output; a second amplifier having an input coupled to the output of the first amplifier and an output; a first resistor coupled between the output of the first amplifier and the input of the second amplifier; a first capacitor coupled to the first resistor and coupled to the input of the second amplifier; a first output stage having an input coupled to the output of the second amplifier and an output configured to provide an output current; and a first feedback path coupled between the second amplifier and the input of the first amplifier, the first feedback path comprising: a buffer having an output coupled to the input of the first amplifier; and a second capacitor.

[0073] Example 2. The circuit according to Example 1, wherein the input of the first feedback path is coupled to the output of the second amplifier.

[0074] Example 3. A circuit according to one or more of Examples 1 or 2, wherein the first resistor and the first capacitor form a first low-pass filter, wherein the input of the first feedback path is coupled to the output of the first low-pass filter.

[0075] Example 4. A circuit according to one or more of Examples 1 to 3, wherein the second capacitor is coupled between the input of the buffer and the second amplifier.

[0076] Example 5. A circuit according to one or more of Examples 1 to 4, wherein the second capacitor is coupled between the output of the buffer and the input of the first amplifier.

[0077] Example 6. A circuit according to one or more of Examples 1 to 5, wherein the first input stage comprises: a first transistor having a current path coupled between the input and a reference terminal of the first input stage, and a control terminal coupled to the input of the first amplifier; and a second transistor having a first current path terminal coupled to a power supply terminal and a second input terminal coupled to the input of the first input stage.

[0078] Example 7. A circuit according to one or more of Examples 1 to 6, wherein the first current path terminal of the second transistor is coupled to the input of the first amplifier via a second resistor.

[0079] Example 8. A circuit according to one or more of Examples 1 to 7, wherein the first output stage includes a first transistor having a current path coupled to the output of the first output stage and a control terminal coupled to the output of the second amplifier.

[0080] Example 9. A circuit according to one or more of Examples 1 to 8, further comprising a low-pass filter coupled between the output of the second amplifier and the input of the first output stage.

[0081] Example 10. A circuit according to one or more of Examples 1 to 9, wherein the low-pass filter comprises: a second resistor coupled between the output of the second amplifier and the input of the first output stage; and a third capacitor coupled to the second resistor.

[0082] Example 11. A circuit according to one or more of Examples 1 to 10, wherein the first amplifier comprises: a first transistor having a control terminal coupled to the output of the first input stage; and a second transistor having a current path terminal coupled to a current path terminal of the first transistor, and a control terminal coupled to the current path terminal of the first resistor and coupled to the second transistor.

[0083] Example 12. A circuit according to one or more of Examples 1 to 11, wherein the second amplifier comprises: a first transistor having a control terminal coupled to the first resistor and coupled to the first capacitor; and a second transistor having a current path terminal coupled to a current path terminal of the first transistor, and a control terminal coupled to the input of the first output stage and coupled to the current path terminal of the second transistor.

[0084] Example 13. A circuit according to one or more of Examples 1 to 12, wherein the buffer comprises: a first transistor having a control terminal coupled to an input of the buffer, and a first current path terminal and a second current path terminal; a second transistor having a first current path terminal coupled to the first current path terminal of the first transistor and a second current path terminal coupled to the output of the buffer; and a third transistor having a first current path terminal coupled to the output of the buffer and a control terminal coupled to the first current path terminal of the first transistor.

[0085] Example 14. A circuit according to one or more of Examples 1 to 13, wherein the buffer further includes a current source coupled to the first current path terminal of the first transistor.

[0086] Example 15. A circuit according to one or more of Examples 1 to 14, further comprising: a second input stage having an input coupled to the output of the first output stage and an output; a third amplifier having an input coupled to the output of the second input stage and an output; a fourth amplifier having an input coupled to the output of the third amplifier and an output; a second resistor coupled between the output of the third amplifier and the input of the fourth amplifier; a third capacitor coupled to the second resistor and the input of the fourth amplifier; a second output stage having an input coupled to the output of the fourth amplifier and an output; and a second feedback path coupled between the input of the fourth amplifier and the third amplifier, the second feedback path comprising: a second buffer having an output coupled to the input of the third amplifier; and a fourth capacitor.

[0087] Example 16. A circuit according to one or more of Examples 1 to 15, further comprising a mixer having an output coupled to the input of the first input stage.

[0088] Example 17. A circuit according to one or more of Examples 1 to 16, further comprising a mixer having an input coupled to the output of the first output stage.

[0089] Example 18. A circuit according to one or more of Examples 1 to 17, further comprising a filter, the filter comprising a first input stage, a first amplifier and a second amplifier, and a first output stage, wherein the filter is configured to have a Butterworth response.

[0090] Example 19. A circuit according to one or more of Examples 1 to 18, wherein the circuit is integrated in an integrated circuit.

[0091] Example 20. A circuit according to one or more of Examples 1 to 19, wherein the first capacitor and the second capacitor are device capacitors of the integrated circuit, and the integrated circuit further comprises a metal capacitor.

[0092] Example 21. A circuit comprising: a first input stage having an input configured to receive an input current and an output; a first transistor having a control terminal coupled to the output of the first input stage and a current path; a second transistor having a control terminal and a current path; a current mirror coupled between the current path of the first transistor and the current path of the second transistor; a first output stage having an input coupled to the control terminal of the second transistor and an output configured to provide an output current; a first resistor coupled between the output of the first input stage and the control terminal of the first transistor; a first capacitor coupled to the first resistor and coupled to the control terminal of the first transistor; and a first feedback path having an output coupled to the first resistor, the first feedback path comprising: a buffer having an output coupled to the control terminal of the first transistor; and a second capacitor.

[0093] Example 22. The circuit according to Example 21, wherein the input of the first feedback path is coupled to the control terminal of the second transistor.

[0094] Example 23. A circuit according to one or more of Examples 21 or 22, wherein the input of the first feedback path is coupled to the control terminal of the third transistor of the current mirror.

[0095] Example 24. A circuit according to one or more of Examples 21 to 23, wherein the second capacitor is coupled between the input of the buffer and the current mirror.

[0096] Example 25. A circuit according to one or more of Examples 21 to 24, wherein the second capacitor is coupled between the output of the buffer and the first resistor.

[0097] Example 26. A circuit according to one or more of Examples 21 to 25, wherein the first input stage comprises: a third transistor having a current path coupled between the input and a reference terminal of the first input stage, and a control terminal coupled to the control terminal of the first transistor; and a fourth transistor having a first current path terminal coupled to a power supply terminal and a second current path terminal coupled to the input of the first input stage.

[0098] Example 27. A circuit according to one or more of Examples 21 to 26, wherein the first current path terminal of the fourth transistor is coupled to the control terminal of the first transistor via the first resistor and via the second resistor.

[0099] Example 28. A circuit according to one or more of Examples 21 to 27, wherein the first output stage includes a third transistor having a current path coupled to the output of the first output stage and a control terminal coupled to the current path of the second transistor.

[0100] Example 29. A circuit according to one or more of Examples 21 to 28, further comprising a low-pass filter coupled between the current path of the second transistor and the input of the first output stage.

[0101] Example 30. A circuit according to one or more of Examples 21 to 29, wherein the low-pass filter comprises: a second resistor coupled between the current path of the second transistor and the input of the first output stage; and a third capacitor coupled to the second resistor.

[0102] Example 31. A circuit according to one or more of Examples 21 to 30, wherein the buffer comprises: a third transistor having a control terminal coupled to an input of the buffer, and a first current path terminal and a second current path terminal; a fourth transistor having a first current path terminal coupled to the first current path terminal of the third transistor and a second current path terminal coupled to the output of the buffer; and a fifth transistor having a first current path terminal coupled to the output of the buffer and a control terminal coupled to the first current path terminal of the third transistor.

[0103] Example 32. A circuit according to one or more of Examples 21 to 31, wherein the buffer further includes a current source coupled to the first current path terminal of the first transistor.

[0104] Example 33. A circuit according to one or more of Examples 21 to 32, further comprising: a second input stage having an input coupled to the output of the first output stage and an output; a third transistor having a control terminal coupled to the output of the second input stage and a current path; a fourth transistor having a control terminal and a current path; a second current mirror coupled between the current path of the third transistor and the current path of the fourth transistor; a second output stage having an input coupled to the control terminal of the fourth transistor and an output; a second resistor coupled between the output of the second input stage and the control terminal of the third transistor; a third capacitor coupled to the second resistor and coupled to the control terminal of the third transistor; and a second feedback path coupled to the control terminal of the third transistor, the second feedback path comprising: a second buffer having an output coupled to the control terminal of the third transistor; and the fourth capacitor.

[0105] Example 34. A circuit according to one or more of Examples 21 to 33, further comprising a mixer having an input coupled to the output of the first output stage.

[0106] Example 35. A circuit according to one or more of Examples 21 to 34, further comprising a filter, the filter comprising the first input stage, the first transistor and the second transistor, the current mirror, and the first output stage, wherein the filter is configured to have a Butterworth response.

[0107] Example 36. A circuit according to one or more of Examples 21 to 35, wherein the filter is a third-order filter.

[0108] Example 37. A circuit according to one or more of Examples 21 to 36, wherein the circuit is integrated in an integrated circuit.

[0109] Example 38. A circuit according to one or more of Examples 21 to 37, wherein the first capacitor and the second capacitor are device capacitors of the integrated circuit, and the integrated circuit further comprises a metal capacitor.

[0110] Example 39. A circuit according to one or more of Examples 21 to 38, further comprising a mixer having an output coupled to the input of the first input stage.

[0111] Example 40. A circuit according to one or more of Examples 21 to 39, wherein the first feedback path is coupled from the control terminal of the third transistor of the current mirror to the first resistor.

[0112] Example 41. A circuit according to one or more of Examples 21 to 40, wherein the first feedback path is coupled from the current path of the second transistor to the first resistor.

[0113] Example 42. A circuit according to one or more of Examples 21 to 41, wherein the input of the buffer is coupled to the current path of the second transistor, and wherein the second capacitor has a terminal coupled to the first resistor.

[0114] Example 43. A circuit according to one or more of Examples 21 to 42, wherein the second capacitor has terminals coupled to the current path of the second transistor, and wherein the buffer has an output coupled to the first resistor.

[0115] Example 44. A transceiver comprising: a first filter having an input and an output; a first mixer having an input and an output, the input of the first mixer being coupled to the output of the first filter; a second mixer having an input and an output; and a second filter having an input and an output, the input of the second filter being coupled to the output of the second mixer.

[0116] Example 45. The transceiver according to Example 44 further comprises: a duplexer having a first terminal and a second terminal, wherein the first terminal of the duplexer is coupled to the output of the first mixer, and wherein the input of the second mixer is coupled to the second terminal of the duplexer.

[0117] Example 46. A transceiver according to one or more of Examples 44 or 45, wherein the second filter includes a third amplifier having an input and an output, a fourth amplifier having an input and an output, and a second feedback path from the output of the fourth amplifier to the input of the third amplifier and including a second buffer and a second capacitor in series, wherein the input of the third amplifier is coupled to the output of the second filter, and wherein the output of the third amplifier is coupled to the input of the second amplifier.

[0118] Example 47. A transceiver according to one or more of Examples 44 to 46, further comprising: an analog-to-digital converter (ADC) having an input coupled to the output of the second filter; and a digital-to-analog converter (DAC) having an output coupled to the input of the first filter.

[0119] Example 48. A transceiver according to any one of Examples 44 to 47, wherein the transceiver is an ultra-wideband (UWB) transceiver.

[0120] The method described above is a series of actions or events, but the described order of these actions or events is not limiting. For example, some actions or events may occur in a different order and / or simultaneously with other actions or events besides those described and / or described herein. Furthermore, some of the described actions or events are optional for implementing one or more aspects or embodiments of this specification. Additionally, one or more actions or events depicted herein may be performed in one or more separate actions and / or stages. In some embodiments, the above method may be implemented in a computer-readable medium using instructions stored in memory.

[0121] In this specification, the term "coupled" may encompass a connection, communication, or signaling path that enables the functional relationship to be consistent with this specification. For example, if device A generates a signal to control device B to perform an action, then: (a) in a first instance, device A is coupled to device B via a direct connection; or (b) in a second instance, device A is coupled to device B via an intermediate component C, provided that the intermediate component C does not alter the functional relationship between device A and device B, such that device B is controlled by device A via a control signal generated by device A.

[0122] A device “configured” to perform a task or function may be configured (e.g., programmed and / or hardwired) to perform the function during manufacturing by the manufacturer, and / or may be configured (or reconfigurable) by the user after manufacturing to perform the function and / or other additional or alternative functions. This configuration may be performed through firmware and / or software programming of the device, through the construction and / or layout of the device’s hardware components and interconnects, or through a combination thereof.

[0123] As used herein, the terms “terminal,” “node,” “interconnect,” “pin,” and “lead” are used interchangeably. Unless otherwise specified, these terms are generally used to refer to interconnects or the ends thereof between device elements, circuit elements, integrated circuits, devices, or other electronic devices or semiconductor components.

[0124] The circuits or devices described herein as containing certain components may alternatively be adapted to be coupled to those components to form the described circuit system or device. For example, a structure described as containing one or more semiconductor elements (e.g., transistors), one or more passive elements (e.g., resistors, capacitors, and / or inductors), and / or one or more sources (e.g., voltage sources and / or current sources) may alternatively contain only semiconductor elements within a single physical device (e.g., a semiconductor die and / or integrated circuit (IC) package) and may be adapted to be coupled to at least some of the said passive elements and / or sources to form the described structure during or after manufacturing, for example, by an end user and / or a third party.

[0125] While the use of specific transistors is illustrated and / or described herein, other transistors (or equivalent switching devices) may be used alternatively with little or no change to the rest of the circuit system. For example, metal-oxide-semiconductor FETs (“MOSFETs”) (e.g., n-channel MOSFETs, nMOSFETs, or p-channel MOSFETs, pMOSFETs), bipolar junction transistors (BJTs, such as NPN or PNP), insulated-gate bipolar transistors (IGBTs), and / or junction field-effect transistors (JFETs) may be used in place of or in combination with the devices described herein. Transistors may be depletion-mode devices, drain-extended devices, enhancement-mode devices, natural transistors, or other types of device structure transistors. Furthermore, the devices may be implemented on / above a silicon (Si) substrate, a silicon carbide (SiC) substrate, a gallium nitride (GaN) substrate, or a gallium arsenide (GaAs) substrate.

[0126] While some elements of the described examples are contained within the integrated circuit and others are external to the integrated circuit, in other example embodiments, additional or fewer features may be incorporated into the integrated circuit. Additionally, some or all features described as external to the integrated circuit may be contained within the integrated circuit, and / or some features described as internal to the integrated circuit may be incorporated externally. As used herein, the term "integrated circuit" means one or more circuits that are: (i) incorporated in / above a semiconductor substrate; (ii) incorporated in a single semiconductor package; (iii) incorporated in the same module; and / or (iv) incorporated in / on the same printed circuit board.

[0127] The use of the phrase "grounding" in the foregoing description includes base grounding, wire grounding, floating grounding, virtual grounding, digital grounding, general grounding, and / or any other form of grounding connection applicable to or suited to the teachings of this specification. Unless otherwise stated, "about," "approximately," or "substantially" preceding a value indicates + / - 10% of that value, or, if the value is zero, a reasonable range of values ​​near zero. Within the scope of the claims, modifications may be made to the described examples, and other embodiments are possible.

Claims

1. A circuit comprising: The first input stage has an input configured to receive an input current, and an output; A first amplifier having an input coupled to the output of the first input stage, and an output; A second amplifier has an input coupled to the output of the first amplifier, and an output; A first resistor is coupled between the output of the first amplifier and the input of the second amplifier; A first capacitor is coupled to the first resistor and to the input of the second amplifier; A first output stage having an input coupled to the output of the second amplifier and an output configured to provide an output current; as well as A first feedback path, coupled between the second amplifier and the input of the first amplifier, comprises: A buffer having an output coupled to the input of the first amplifier, and Second capacitor.

2. The circuit of claim 1, wherein the input of the first feedback path is coupled to the output of the second amplifier.

3. The circuit of claim 1, wherein the first resistor and the first capacitor form a first low-pass filter, wherein the input of the first feedback path is coupled to the output of the first low-pass filter.

4. The circuit of claim 1, wherein the second capacitor is coupled between the input of the buffer and the second amplifier.

5. The circuit of claim 1, wherein the second capacitor is coupled between the output of the buffer and the input of the first amplifier.

6. The circuit of claim 1, wherein the first input stage comprises: A first transistor having a current path coupled between the input and a reference terminal of the first input stage, and a control terminal coupled to the input of the first amplifier; as well as The second transistor has a first current path terminal coupled to a power supply terminal and a second input terminal coupled to the input of the first input stage.

7. The circuit of claim 6, wherein the first current path terminal of the second transistor is coupled to the input of the first amplifier via a second resistor.

8. The circuit of claim 1, wherein the first output stage includes a first transistor having a current path coupled to the output of the first output stage and a control terminal coupled to the output of the second amplifier.

9. A circuit comprising: The first input stage has an input configured to receive an input current, and an output; A first transistor having a control terminal coupled to the output of the first input stage, and a current path; The second transistor has control terminals and a current path; A current mirror, coupled between the current path of the first transistor and the current path of the second transistor; A first output stage having an input coupled to the control terminal of the second transistor and an output configured to provide an output current; A first resistor is coupled between the output of the first input stage and the control terminal of the first transistor; A first capacitor, which is coupled to the first resistor and to the control terminal of the first transistor; as well as A first feedback path having an output coupled to the first resistor, the first feedback path comprising: A buffer having an output coupled to the control terminal of the first transistor, and Second capacitor.

10. The circuit of claim 9, wherein the input of the first feedback path is coupled to the control terminal of the second transistor.

11. The circuit of claim 9, wherein the input of the first feedback path is coupled to the control terminal of the third transistor of the current mirror.

12. The circuit of claim 9, wherein the second capacitor is coupled between the input of the buffer and the current mirror.

13. The circuit of claim 9, wherein the second capacitor is coupled between the output of the buffer and the first resistor.

14. The circuit of claim 9, wherein the first input stage comprises: A third transistor has a current path coupled between the input and reference terminals of the first input stage, and a control terminal coupled to the control terminal of the first transistor. as well as The fourth transistor has a first current path terminal coupled to a power supply terminal and a second current path terminal coupled to the input of the first input stage.

15. The circuit of claim 14, wherein the first current path terminal of the fourth transistor is coupled to the control terminal of the first transistor via the first resistor and via the second resistor.

16. The circuit of claim 9, wherein the first output stage includes a third transistor having a current path coupled to the output of the first output stage and a control terminal coupled to the current path of the second transistor.

17. The circuit of claim 9, further comprising a low-pass filter coupled between the current path of the second transistor and the input of the first output stage.

18. A transceiver comprising: The first filter has an input and an output; A first mixer has an input and an output, the input of the first mixer being coupled to the output of the first filter; The second mixer has inputs and outputs; as well as A second filter having an input and an output, the input of the second filter being coupled to the output of the second mixer, wherein the first filter comprises: A first amplifier has an input coupled to the input of the first filter, and an output; A second amplifier has an input coupled to the output of the first amplifier, and an output; as well as A first feedback path, coupled between the second amplifier and the input of the first amplifier, includes a buffer and a capacitor.

19. The transceiver of claim 18, further comprising: A duplexer having a first terminal and a second terminal, wherein the first terminal of the duplexer is coupled to the output of a first mixer, and wherein the input of a second mixer is coupled to the second terminal of the duplexer.

20. The transceiver of claim 18, wherein the second filter comprises a third amplifier having an input and an output, a fourth amplifier having an input and an output, and a second feedback path from the output of the fourth amplifier to the input of the third amplifier and comprising a second buffer and a second capacitor connected in series, wherein the input of the third amplifier is coupled to the output of the second filter, and wherein the output of the third amplifier is coupled to the input of the second amplifier.

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