Adaptive anti-aliasing filtering method and double-ring gate voltage bootstrap sampling switch circuit implementation

Abstract

This invention discloses a dual-ring gate voltage bootstrap sampling switch circuit, belonging to the field of integrated circuit design technology. The circuit includes a sampling switch transistor M. S The inner ring road and the outer ring road. During the rapid construction phase, the inner ring road will... S The gate-source voltage is kept at the supply voltage, so that M S The signal is in a low on-impedance state independent of the input signal, enabling rapid linear signal establishment. During the filtering phase, the outer loop uses controlled discharge to enable M... S As the gate-source voltage decreases, the on-resistance increases with the discharge time; and the discharge duration is controlled to be inversely proportional to the sampling frequency, so that M... S The on-resistance is inversely proportional to the sampling frequency. This on-resistance, together with the sampling capacitor, forms an adaptive anti-aliasing filter whose cutoff frequency scales linearly with the sampling frequency. This invention balances high sampling linearity with anti-aliasing filtering over a wide frequency range, and features small area, low power consumption, and wide applicability.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit design technology, and in particular to an adaptive anti-aliasing filtering method and a dual-ring gate voltage bootstrap sampling switch circuit. Background Technology

[0002] In analog front-end systems, to ensure rapid establishment of the input signal in the discrete-time analog-to-digital converter (ADC) sampling network, the bandwidth of the preamplifier is often higher than the ADC's sampling frequency fS. This inevitably leads to thermal noise aliasing issues caused by sampling. Inserting an anti-aliasing filter at the intermediate node between the preamplifier and the ADC can alleviate this problem. However, existing anti-aliasing filters (such as dynamic RC filters) have a fixed cutoff frequency and cannot adaptively scale with changes in the system's sampling frequency fS. Consequently, when facing wideband scaling requirements, the system consistently fails to balance the linearity of high-speed establishment with the aliasing noise suppression capability of low-speed sampling. Summary of the Invention

[0003] This invention provides an adaptive anti-aliasing filtering method and a dual-ring gate voltage bootstrap sampling switch circuit, which solves the problem that the cutoff frequency of the existing anti-aliasing filter is fixed and cannot be dynamically scaled with the system sampling frequency fS, and achieves adaptive anti-aliasing filtering that takes into account both sampling linearity and a wide frequency range.

[0004] In a first aspect, the present invention provides a dual-ring gate voltage bootstrap sampling switch circuit, comprising: Sampling switch transistor M S ; The inner loop is configured to switch the sampling switch M during the rapid setup phase of the sampling process. S The gate-source voltage is maintained at the power supply voltage so that the sampling switch M S It is in a low on-impedance state that is independent of the input signal amplitude, thus enabling rapid linear establishment of the input signal; The outer loop, configured for the filtering phase following the rapid setup phase, controls the discharge of the sampling switch M. S The gate-source voltage decreases over time, thereby causing the sampling switch M to... S The on-resistance increases with increasing discharge time; Furthermore, the outer loop control discharge duration is inversely proportional to the system sampling frequency, so that the sampling switch M... S The on-resistance is inversely proportional to the sampling frequency, and thus the on-resistance and the sampling capacitor form an adaptive anti-aliasing filter whose cutoff frequency scales linearly with the sampling frequency.

[0005] In conjunction with the first aspect, in one possible implementation, the inner loop includes: capacitor C B1Charging switch M7, auxiliary switch M8, auxiliary switch M9, auxiliary switch M 10 Lifting switch tube M 11 Lifting switch tube M 12 Reset switch transistor M 15 and reset switch M 16 ; The capacitor C B1 The first terminal is connected to the drain of the charging switch M3, the source of the auxiliary switch M9, and the auxiliary switch M... 10 The source of the lifting switch M 11 The source and capacitor C B2 The first terminal and the source of the thick gate oxide layer transistor M2; the capacitor C B1 The second end connects to the first node V T1 The lifting switch tube M 12 The source and the drain of the charging switch M7; The source of the charging switch M7 is connected to the power supply voltage V. D The gate of the charging switch M7 is connected to the lift switch M. 12 The drain of the auxiliary switch M 10 The gate of the lifting switch M 11 The gate of the reset switch transistor M 15 The drain of the outer ring lifting switch M5 and the gate of the outer ring charging switch M4; The source of the auxiliary switch M8 is connected to the power supply voltage V. D The drain of the auxiliary switch M8 is connected to the drain of the auxiliary switch M9, and the auxiliary switch M... 10 The drain of the lifting switch M 12 The gate of the auxiliary switch M8 and the gate of the boost switch M6 are connected; the gate of the auxiliary switch M8 is connected to the gate of the auxiliary switch M9 and the second clock signal Φ2. The reset switch transistor M 15 Gate connection power supply voltage V D The reset switch transistor M 15 The source of the reset switch transistor M is connected. 16 The drain electrode; The reset switch transistor M 16 The source of the reset switch transistor M is grounded; 16 The gate is connected to the first clock signal Φ1.

[0006] In conjunction with the first aspect, in one possible implementation, the outer loop includes: capacitor C B2Diode M1, Thick Gate Oxide Transistor M2, Charging Switch M3, Charging Switch M4, Lift Switch M5, Lift Switch M6, Reset Switch M 13 and reset switch M 14 ; The capacitor C B2 The second end connects to the second node V T2 The drain of the diode connecting tube M1, the drain of the charging switch tube M4, the source of the lift switch tube M6, and the drain of the lift switch tube M5; The source of the diode M1 is connected to the drain of the thick gate oxide layer transistor M2; the gate of the diode M1 is connected to the reset switch transistor M. 13 The drain of the M5, the source of the M6, the drain of the M7, and the sampling switch M8 S The gate; The gate of the thick-gate oxide layer transistor M2 is connected to a timing control signal Φ. 2_DF ; The source of the charging switch M3 is grounded; the gate of the charging switch M3 is connected to the first clock signal Φ1. The source of the charging switch M4 is connected to the power supply voltage V. D ; The reset switch transistor M 13 Gate connection power supply voltage V D The reset switch transistor M 13 The source of the reset switch transistor M is connected. 14 The drain electrode; The reset switch transistor M 14 The gate of the transistor is connected to the first clock signal Φ1; the reset switch transistor M 14 The source electrode is grounded.

[0007] In conjunction with the first aspect, in one possible implementation, the thick gate oxide layer tube M2 is a thick gate oxide layer tube.

[0008] In conjunction with the first aspect, in one possible implementation, the timing control signal Φ 2_DF The pulse width is inversely proportional to the system sampling frequency.

[0009] In conjunction with the first aspect, in one possible implementation, the sampling switch M S The sampling switch transistor M is an NMOS transistor. S The gate of the reset switch transistor M is connected. 13 The drain of the diode and the gate of the diode are connected; the sampling switch transistor M1 S The source is connected to the input signal terminal V. i The sampling switch transistor MS The drain is connected to the output terminal Vo.

[0010] In conjunction with the first aspect, in one possible implementation, the first clock signal Φ1 and the second clock signal Φ2 are non-overlapping clocks.

[0011] In conjunction with the first aspect, in one possible implementation, the timing control signal Φ 2_DF It becomes active after a preset delay during the active period of the second clock signal Φ2.

[0012] In conjunction with the first aspect, in one possible implementation, the sampling switch M S The gate-source voltage decreases logarithmically during the filtering stage due to the discharge of the diode connecting transistor M1, causing the sampling switch transistor M... S Once in the subthreshold region, the on-resistance increases approximately linearly with increasing discharge time.

[0013] Secondly, the present invention provides an adaptive anti-aliasing filtering method, comprising: The sampling process is divided into a rapid setup stage and a filtering stage in the time domain; During the rapid setup phase, the sampling switch M is... S The gate-source voltage is maintained at the power supply voltage, so that the sampling switch M S It is in a low on-impedance state to achieve rapid linear establishment of the input signal; After the rapid setup phase ends, in response to a timing control signal, the system switches to the filtering phase. During the filtering stage, the sampling switch M is reduced by controlling the discharge of the energy storage element. S The gate-source voltage causes the sampling switch transistor M to... S The on-resistance increases with increasing discharge time; Furthermore, the discharge duration is controlled to be inversely proportional to the system's sampling frequency, so that the sampling switch M... S The on-resistance is inversely proportional to the sampling frequency, and the on-resistance and the sampling capacitor together form an adaptive anti-aliasing filter whose cutoff frequency scales linearly with the sampling frequency.

[0014] One or more technical solutions provided in this invention have at least the following technical effects or advantages: This invention, through the rapid setup phase of the sampling process, connects the sampling switch transistor M in the inner loop. S The gate-source voltage is kept at the supply voltage, so that the sampling switch M SThe sampling circuit is in a low on-impedance state independent of the input signal amplitude. The beneficial effect of this stage is that, through a constant and independent low on-impedance, rapid linear establishment of the input signal is achieved, effectively suppressing harmonic distortion and ensuring high linearity of the sampling process. In the filtering stage following the rapid establishment phase, the outer loop controls the discharge of the sampling switch M... S The gate-source voltage decreases over time, thereby causing the sampling switch M to... S The on-resistance increases with the discharge time. The beneficial effect of this stage is that the gate voltage drop causes the switching transistor to enter the subthreshold region, where its on-resistance gradually increases. Together with the sampling capacitor, it forms a dynamic RC filter, achieving anti-aliasing filtering without adding extra hardware. Furthermore, the outer loop control discharge duration is inversely proportional to the system sampling frequency, making the sampling switch M... S The on-resistance is inversely proportional to the sampling frequency, and thus, this on-resistance, together with the sampling capacitor, forms an adaptive anti-aliasing filter whose cutoff frequency scales linearly with the sampling frequency. The beneficial effects of this control mechanism are: the filter's cutoff frequency can automatically follow the system's sampling frequency, maintaining optimal aliasing noise suppression over a wide frequency range, while simultaneously balancing the linear setup requirements of high-speed sampling and the noise suppression needs of low-speed sampling, significantly improving the system's frequency adaptability and overall performance. Attached Figure Description

[0015] Figure 1 The diagram and simulation results of the adaptive anti-aliasing filtering method provided in the embodiments of the present invention are shown below; Figure 2 This is a schematic diagram illustrating the connection state between the dual-ring gate voltage bootstrap sampling switch circuit and the specific working phase circuit provided in this embodiment of the invention. Detailed Implementation

[0016] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.

[0017] In a first aspect, the present invention provides a dual-ring gate voltage bootstrap sampling switch circuit, comprising: Sampling switch transistor M S The inner ring road and the outer ring road.

[0018] Specifically, sampling switch M S For NMOS transistors, sampling switch M S The gate is connected to the reset switch transistor M 13The drain and diode are connected to the gate of transistor M1; sampling switch transistor M S The source is connected to the input signal terminal V. i Sampling switch transistor M S The drain is connected to the output terminal Vo.

[0019] Inner Ring Road.

[0020] The inner loop is configured to switch the sampling switch M during the rapid setup phase of the sampling process. S The gate-source voltage is kept at the supply voltage so that the sampling switch M S It operates in a low on-impedance state, independent of the input signal amplitude, enabling rapid linear establishment of the input signal.

[0021] Specifically, the inner loop includes: capacitor C B1 Charging switch M7, auxiliary switch M8, auxiliary switch M9, auxiliary switch M 10 Lifting switch tube M 11 Lifting switch tube M 12 Reset switch transistor M 15 and reset switch M 16 ; Capacitor C B1 The first terminal is connected to the drain of charging switch M3, the source of auxiliary switch M9, and the auxiliary switch M... 10 The source of the lifting switch M 11 The source and capacitor C B2 The first terminal and the source of the thick gate oxide layer transistor M2; capacitor C B1 The second end connects to the first node V T1 Lifting switch tube M 12 The source and drain of the charging switch M7; the source of the charging switch M7 is connected to the power supply voltage V. D The gate connection of charging switch M7 raises the switching transistor M. 12 The drain and auxiliary switch M 10 Gate, lifting switch M 11 Gate, reset switch M 15 The drain of the auxiliary switch M8 is connected to the gate of the outer ring-driven switching transistor M5 and the gate of the outer ring-driven charging switching transistor M4; the source of the auxiliary switch M8 is connected to the power supply voltage V. D The drain of auxiliary switch M8 is connected to the drain of auxiliary switch M9 and auxiliary switch M... 10 Drain, lifting switch M 12 The gate of the auxiliary switch M8 is connected to the gate of the auxiliary switch M9 and the second clock signal Φ2; the gate of the reset switch M9 .... 15 Gate connection power supply voltage V D Reset switch transistor M15 The source is connected to the reset switch transistor M. 16 The drain of the reset switch transistor M; 16 The source is grounded; reset switch M 16 The gate is connected to the first clock signal Φ1.

[0022] Outer ring road.

[0023] The outer loop is configured to controllably discharge the sampling switch M during the filtering phase following the rapid setup phase. S The gate-source voltage decreases over time, thus causing the sampling switch M to... S The on-resistance increases with increasing discharge time; Specifically, the outer loop includes: capacitor C B2 Diode M1, Thick Gate Oxide Transistor M2, Charging Switch M3, Charging Switch M4, Lift Switch M5, Lift Switch M6, Reset Switch M 13 and reset switch M 14 ; Capacitor C B2 The second end connects to the second node V T2 The diode is connected to the drain of transistor M1, the drain of charging switch M4, the source of boost switch M6, and the drain of boost switch M5; the source of diode M1 is connected to the drain of thick gate oxide transistor M2; the gate of diode M1 is connected to the reset switch M6. 13 The drain of the boost switch M5, the source of the boost switch M6, and the sampling switch M S The gate of the thick gate oxide layer transistor M2 is connected to the timing control signal Φ. 2_DF The source of charging switch M3 is grounded; the gate of charging switch M3 is connected to the first clock signal Φ1; the source of charging switch M4 is connected to the power supply voltage V. D Reset switch transistor M 13 Gate connection power supply voltage V D Reset switch transistor M 13 The source is connected to the reset switch transistor M. 14 The drain of the reset switch transistor M; 14 The gate is connected to the first clock signal Φ1; the reset switch M 14 The source electrode is grounded.

[0024] Furthermore, the discharge duration of the outer loop control is inversely proportional to the system sampling frequency, so as to make the sampling switch M S The on-resistance is inversely proportional to the sampling frequency, and thus the on-resistance and the sampling capacitor form an adaptive anti-aliasing filter whose cutoff frequency scales linearly with the sampling frequency.

[0025] Here, the thick gate oxide layer tube M2 is a thick gate oxide layer tube.

[0026] Here, the timing control signal Φ 2_DF The pulse width is inversely proportional to the system sampling frequency.

[0027] Here, the first clock signal Φ1 and the second clock signal Φ2 are non-overlapping clocks.

[0028] Here, the timing control signal Φ 2_DF It becomes active after a preset delay during the active period of the second clock signal Φ2.

[0029] Here, sampling switch M S The gate-source voltage decreases logarithmically during the filtering stage due to the discharge of diode M1, causing the sampling switch M... S Once in the subthreshold region, the on-resistance increases approximately linearly with increasing discharge time.

[0030] For example, see Figure 2 , Figure 2 This is a schematic diagram of the circuit implementation and specific working phase circuit connection state of the dual-loop gate voltage bootstrap sampling switch provided in this embodiment of the invention. The circuit includes an inner loop and an outer loop: the function of the inner loop is the same as that of a traditional gate voltage bootstrap switch, mainly used to provide basic timing signals and PMOS substrate bias; The outer loop includes capacitor C B2 Diode connector M1 and thick gate oxide layer transistor M2, etc., are used for sampling switch transistor M. S Provides a frequency-controlled gate-source voltage V D The specific operation of this circuit consists of three stages: Reset stage (Φ1=1): Capacitor C B1 and capacitor C B2 Pre-charging is performed, at which time the sampling switch M... S Currently in shutdown state; rapid setup phase (Φ2=1, Φ 2_DF =0): Capacitor C B1 and capacitor C B2 Upper plate voltage V T1,2 Elevated to V D +V I At this time, M S The gate-source voltage remains at V. D The on-resistance is small and independent of the input signal amplitude, ensuring rapid linear establishment of the input signal; during the filtering stage (Φ2=1, Φ 2_DF =1): After the basic setup is completed, the thick gate oxide layer transistor M2 is controlled by the clock Φ. 2_DF Control conduction, outer loop capacitor C B2 Discharge begins through diode-connected transistor M1, which is used for sampling switch M. S Provides a time-varying gate-source voltage V DAnd control the discharge duration t to satisfy: t = k / f S Thus achieving M S Impedance with frequency f S Adaptive scaling.

[0031] At this stage, the capacitance C of the inner loop B1 The charge on the circuit remains constant, ensuring the stability of the overall timing signals of the circuit.

[0032] Secondly, the present invention provides an adaptive anti-aliasing filtering method, comprising: (1) Divide the sampling process into a fast setup stage and a filtering stage in the time domain; (2) During the rapid setup phase, the sampling switch M S The gate-source voltage is kept at the supply voltage, so that the sampling switch M S It is in a low on-impedance state to achieve rapid linear establishment of the input signal; (3) After the rapid setup phase ends, in response to the timing control signal, switch to the filtering phase; (4) During the filtering stage, the discharge of the energy storage element is controlled to reduce the sampling switch M. S The gate-source voltage causes the sampling switch M to... S The on-resistance increases with increasing discharge time; Furthermore, the discharge duration is inversely proportional to the system's sampling frequency, causing the sampling switch M to... S The on-resistance is inversely proportional to the sampling frequency, and the on-resistance and the sampling capacitor form an adaptive anti-aliasing filter whose cutoff frequency scales linearly with the sampling frequency.

[0033] For example, see Figure 1 , Figure 1 This is a schematic diagram and simulation results of the adaptive anti-aliasing filtering method provided in this embodiment of the invention. The adaptive anti-aliasing filtering method proposed in this embodiment divides the sampling process into two sub-stages: setup and filtering. The specific process is as follows: In phase Φ1, the sampling switch M... S Turn off, capacitor C BST Charged to power supply voltage V D After entering the Φ2 phase, a rapid setup is first performed, at which point the capacitor C... BST Charge retention on the sampling switch M S The gate voltage is raised to V D +V I (V I (As input signal), causing the sampling switch transistor M to... S The gate-source voltage is constant at V D This results in a low on-resistance R that is independent of the input signal amplitude. onThis ensures rapid signal establishment and suppresses harmonic distortion. Once the basic signal establishment is complete, the filtering stage begins. At this point, C... BST The capacitor is discharged through a controlled diode path, and the residual voltage on the capacitor is denoted as V. D Then the sampling switch transistor M S The gate-source voltage is the dynamically decreasing V. D Based on the characteristics of the capacitor-biased diode circuit, V D The relationship between the discharge duration t and the discharge duration t satisfies: ; in, Thermoelectric voltage, This is the diode saturation current. During the discharge process, The rapid drop prompted the sampling switch M S Entering the subthreshold region, its on-resistance and The relationship is: ; in, This is the subthreshold coefficient (typically 1~1.5). Therefore, it can be concluded that... With discharge duration They exhibit an approximately linear relationship. Figure 1 The simulation waveforms in the image verify that M... S Gate-source voltage Dynamic decrease, while M S On impedance The discharge time t increases approximately linearly with increasing discharge time t. This can be achieved by controlling the discharge duration t and the system sampling frequency f. S Satisfying the relation: t = k / f S This can be achieved. With 1 / f S Linear scaling. Combined with a fixed sampling capacitor C. S This allows us to construct a cutoff frequency f. CUT Automatically follow f S A dynamic anti-aliasing filter that varies.

[0034] Compared with the prior art, the beneficial effects of the present invention are as follows: (1) Wide-range frequency adaptive capability: It breaks through the limitation of fixed cutoff frequency of traditional filters, so that the cutoff frequency of anti-aliasing filter can dynamically and linearly follow the system sampling frequency over a wide range, and maintain the best filtering effect under different sampling rates. (2) Balancing high linearity and low hardware overhead: The time-division multiplexing mechanism balances the contradiction between sampling setup linearity and out-of-band noise suppression to a certain extent; and the filter network is directly embedded in the gate voltage bootstrap sampling switch, saving chip area and power consumption.

[0035] The various embodiments described in this specification are presented in a progressive manner. Similar or identical parts between embodiments can be referred to interchangeably. Each embodiment focuses on its differences from other embodiments. All or part of this invention can be used in numerous general-purpose or special-purpose computer system environments or configurations. Examples include: personal computers, server computers, handheld or portable devices, tablet devices, mobile communication terminals, multiprocessor systems, microprocessor-based systems, programmable electronic devices, network PCs, minicomputers, mainframe computers, and distributed computing environments including any of the above systems or devices, etc.

[0036] The above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit the present invention. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the present invention.

Claims

1. A dual-ring gate voltage bootstrap sampling switch circuit, characterized in that, include: Sampling switch transistor M S ; The inner loop is configured to switch the sampling switch M during the rapid setup phase of the sampling process. S The gate-source voltage is maintained at the power supply voltage so that the sampling switch M S It is in a low on-impedance state that is independent of the input signal amplitude, thus enabling rapid linear establishment of the input signal; The outer loop, configured for the filtering phase following the rapid setup phase, controls the discharge of the sampling switch M. S The gate-source voltage decreases over time, thereby causing the sampling switch M to... S The on-resistance increases with increasing discharge time; Furthermore, the outer loop control discharge duration is inversely proportional to the system sampling frequency, so that the sampling switch M... S The on-resistance is inversely proportional to the sampling frequency, and thus the on-resistance and the sampling capacitor form an adaptive anti-aliasing filter whose cutoff frequency scales linearly with the sampling frequency.

2. The dual-ring gate voltage bootstrap sampling switch circuit according to claim 1, characterized in that, The inner loop includes: capacitor C B1 Charging switch M7, auxiliary switch M8, auxiliary switch M9, auxiliary switch M 10 Lifting switch tube M 11 Lifting switch tube M 12 Reset switch transistor M 15 and reset switch M 16 ; The capacitor C B1 The first terminal is connected to the drain of the charging switch M3, the source of the auxiliary switch M9, and the auxiliary switch M... 10 The source of the lifting switch M 11 The source and capacitor C B2 The first terminal and the source of the thick gate oxide layer transistor M2; the capacitor C B1 The second end connects to the first node V T1 The lifting switch tube M 12 The source and the drain of the charging switch M7; The source of the charging switch M7 is connected to the power supply voltage V. D The gate of the charging switch M7 is connected to the lift switch M. 12 The drain of the auxiliary switch M 10 The gate of the lifting switch M 11 The gate of the reset switch transistor M 15 The drain of the outer ring lifting switch M5 and the gate of the outer ring charging switch M4; The source of the auxiliary switch M8 is connected to the power supply voltage V. D The drain of the auxiliary switch M8 is connected to the drain of the auxiliary switch M9, and the auxiliary switch M... 10 Drain, lifting switch M 12 The gate of the auxiliary switch M8 and the gate of the boosting switch M6; the gate of the auxiliary switch M8 is connected to the gate of the auxiliary switch M9 and the second clock signal Φ2; The reset switch transistor M 15 Gate connection power supply voltage V D The reset switch transistor M 15 The source of the reset switch transistor M is connected. 16 The drain electrode; The reset switch transistor M 16 The source of the reset switch transistor M is grounded; 16 The gate is connected to the first clock signal Φ1.

3. The dual-ring gate voltage bootstrap sampling switch circuit according to claim 1, characterized in that, The outer loop includes: capacitor C B2 Diode M1, Thick Gate Oxide Transistor M2, Charging Switch M3, Charging Switch M4, Lift Switch M5, Lift Switch M6, Reset Switch M 13 and reset switch M 14 ; The capacitor C B2 The second end connects to the second node V T2 The drain of the diode connecting tube M1, the drain of the charging switch tube M4, the source of the lift switch tube M6, and the drain of the lift switch tube M5; The source of the diode M1 is connected to the drain of the thick gate oxide layer transistor M2; the gate of the diode M1 is connected to the reset switch transistor M. 13 The drain of the M5, the source of the M6, the drain of the M7, and the sampling switch M8 S The gate; The gate of the thick-gate oxide layer transistor M2 is connected to a timing control signal Φ. 2_DF ; The source of the charging switch M3 is grounded; the gate of the charging switch M3 is connected to the first clock signal Φ1. The source of the charging switch M4 is connected to the power supply voltage V. D ; The reset switch transistor M 13 Gate connection power supply voltage V D The reset switch transistor M 13 The source of the reset switch transistor M is connected. 14 The drain electrode; The reset switch transistor M 14 The gate of the transistor is connected to the first clock signal Φ1; the reset switch transistor M 14 The source electrode is grounded.

4. The implementation of the dual-ring gate voltage bootstrap sampling switch circuit according to claim 3, characterized in that, The thick gate oxide layer tube M2 is a thick gate oxide layer tube.

5. The implementation of the dual-ring gate voltage bootstrap sampling switch circuit according to claim 3, characterized in that, The timing control signal Φ 2_DF The pulse width is inversely proportional to the system sampling frequency.

6. The dual-ring gate voltage bootstrap sampling switch circuit according to claim 3, characterized in that, The sampling switch transistor M S The sampling switch transistor M is an NMOS transistor. S The gate of the reset switch transistor M is connected. 13 The drain of the diode and the gate of the diode are connected; the sampling switch transistor M1 S The source is connected to the input signal terminal V. i The sampling switch transistor M S The drain is connected to the output terminal Vo.

7. The dual-ring gate voltage bootstrap sampling switch circuit according to claim 2, characterized in that, The first clock signal Φ1 and the second clock signal Φ2 are non-overlapping clocks.

8. The implementation of the dual-ring gate voltage bootstrap sampling switch circuit according to claim 3, characterized in that, The timing control signal Φ 2_DF It becomes active after a preset delay during the active period of the second clock signal Φ2.

9. The implementation of the dual-ring gate voltage bootstrap sampling switch circuit according to claim 3, characterized in that, The sampling switch transistor M S The gate-source voltage decreases logarithmically during the filtering stage due to the discharge of the diode connecting transistor M1, causing the sampling switch transistor M... S Once in the subthreshold region, the on-resistance increases approximately linearly with increasing discharge time.

10. An adaptive anti-aliasing filtering method, characterized in that, include: The sampling process is divided into a rapid setup stage and a filtering stage in the time domain; During the rapid setup phase, the sampling switch M is... S The gate-source voltage is maintained at the power supply voltage, so that the sampling switch M S It is in a low on-impedance state to achieve rapid linear establishment of the input signal; After the rapid setup phase ends, in response to a timing control signal, the system switches to the filtering phase. During the filtering stage, the sampling switch M is reduced by controlling the discharge of the energy storage element. S The gate-source voltage causes the sampling switch transistor M to... S The on-resistance increases with increasing discharge time; Furthermore, the discharge duration is controlled to be inversely proportional to the system's sampling frequency, so that the sampling switch M... S The on-resistance is inversely proportional to the sampling frequency, and the on-resistance and the sampling capacitor together form an adaptive anti-aliasing filter whose cutoff frequency scales linearly with the sampling frequency.

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