Ring oscillator circuit

Abstract

The present invention provides a ring oscillator circuit, characterized in that it comprises a ring oscillator, comprising a plurality of serially connected logic elements for generating an oscillation signal, and a transmission gate coupled in the signal path of the ring oscillator, wherein the transmission gate is closed to block the signal path when the ring oscillator is in a stop state, thereby reducing the leakage current of the ring oscillator. Compared to the known art, the present invention has the advantage that it can significantly reduce the standby power consumption and provide further optimization possibilities, such as dynamic control or bypass design, making it suitable for a variety of low-power scenarios.

Description

Technical Field

[0001] This invention belongs to the field of electronic circuit design, specifically relating to a ring oscillator circuit for generating oscillating signals. This invention offers advantages such as significantly reducing circuit leakage current and maintaining stable oscillation performance, making it suitable for the needs of modern electronic devices. Background Technology

[0002] With the continuous advancement of integrated circuit technology, especially in low-power applications, effectively reducing standby power consumption has become a crucial design challenge. Ring oscillators are a common type of oscillation signal generator. Their basic principle involves using an odd number of logic gates (usually inverters) connected in series to form a closed loop. When a signal passes through these gates, continuous oscillation is generated due to delay and logic inversion. This structure is simple and easy to integrate, making it widely used in clock generation, frequency modulation, and test circuits. However, as semiconductor manufacturing processes have entered the nanometer scale (e.g., 22nm or 14nm), the shrinking transistor size has led to a significant increase in subthreshold leakage current. This causes traditional ring oscillators to generate unnecessary power consumption even in the off state (i.e., when the start signal is low). This leakage current not only reduces the circuit's energy efficiency but also places an additional burden on battery-powered devices (such as mobile phones or IoT devices).

[0003] Researchers have attempted to address leakage current issues through various methods. For example, increasing the transistor's threshold voltage can reduce leakage current, but this often comes at the cost of sacrificing oscillation speed. Furthermore, traditional ring oscillator designs mostly focus on performance optimization during startup, paying insufficient attention to power consumption control during shutdown, thus failing to meet the increasingly stringent requirements of modern low-power applications. Therefore, effectively reducing leakage current without significantly impacting oscillation performance has become a pressing technical challenge. This invention is proposed against this backdrop, aiming to provide a solution that balances efficiency and performance through structural innovation. Summary of the Invention

[0004] The present invention provides a ring oscillator circuit, characterized in that it includes a ring oscillator comprising a plurality of series-connected logic elements for generating an oscillation signal, and a transmission gate coupled to the signal path of the ring oscillator, wherein when the ring oscillator is in a stopped state, the transmission gate is closed to block the signal path, thereby reducing the leakage current of the ring oscillator.

[0005] The main objective of this invention is to provide a ring oscillator circuit that solves the problem of excessive leakage current in the stopped state of traditional designs, while simultaneously ensuring the quality of the oscillation signal. To achieve this, this invention introduces a transmission gate coupled to the signal path of the ring oscillator. When the circuit is in the stopped state, the transmission gate closes to block the signal path, thereby effectively reducing leakage current. This design is not only simple and easy to implement, but also allows for flexible adjustment according to application requirements, making it widely applicable.

[0006] The present invention is characterized in that the ring oscillator circuit provided by the present invention includes a ring oscillator and a transmission gate. The ring oscillator consists of multiple logic elements connected in series, such as NAND gates and inverters, and its function is to generate a stable oscillation signal. The transmission gate acts as a controllable switch, configured at a critical position in the signal path. When the start signal is low (i.e., in a stop state), the transmission gate closes, cutting off the signal flow between logic elements, thereby suppressing the generation of sub-threshold leakage current. Compared with known technologies, the advantage of the present invention is that it can significantly reduce standby power consumption and provides the possibility of further optimization, such as dynamic control or bypass design, making it suitable for various low-power scenarios. Attached Figure Description

[0007] To facilitate understanding, reference should be made to the accompanying drawings and detailed descriptions while reading this invention. Specific embodiments of the invention are explained in detail through reference to the corresponding drawings, which illustrate the working principles of these embodiments. Furthermore, for clarity, features in the drawings may not be drawn to scale, and the dimensions of some features in certain drawings may be intentionally enlarged or reduced.

[0008] Figure 1 This is a basic structural diagram of a ring oscillator circuit, showing the configuration and connection relationship between the ring oscillator and the transmission gate.

[0009] Figure 2 This is a schematic diagram of an advanced structure of a ring oscillator circuit, further demonstrating the integrated design of the transmission gate and control unit.

[0010] Figure 3 This is a schematic diagram of an advanced structure of a ring oscillator circuit, further demonstrating the integrated design of the transmission gate, control unit, bypass circuit, and stabilization unit.

[0011] [Explanation of Key Component Symbols]

[0012] 10: Ring Oscillator

[0013] 12: NAND Gate

[0014] 14: Inverter

[0015] 20: Transmission Gate

[0016] 22: N-type transistor

[0017] 24: P-type transistor

[0018] 26: Inverter

[0019] 30: Control Unit

[0020] 40: Bypass circuit

[0021] 50: Stable Unit

[0022] C1: Circuit

[0023] C2: Circuit

[0024] C3: Circuit

[0025] E: Start signal

[0026] Vcc: Voltage source Detailed Implementation

[0027] Although specific configurations and arrangements are discussed herein, it should be understood that this is for illustrative purposes only. Those skilled in the art will recognize that other configurations and arrangements can be used without departing from the spirit and scope of this disclosure. It will be apparent to those skilled in the art that the disclosure of this application can also be used in a variety of other applications.

[0028] It should be noted that references to "an embodiment," "an embodiment," "an exemplary embodiment," "some embodiments," etc., in the specification indicate that the described embodiments may include specific features, structures, or characteristics, but each embodiment may not necessarily include those specific features, structures, or characteristics. Furthermore, such terms do not necessarily refer to the same embodiment. Additionally, when a specific feature, structure, or characteristic is described in connection with an embodiment, whether explicitly described or not, implementing such a feature, structure, or characteristic in conjunction with other embodiments is within the knowledge of those skilled in the art.

[0029] Generally, terms can be understood, at least in part, based on their usage in context. For example, the term “one or more” (at least in part, depending on context), as used herein, can be used to describe any feature, structure, or characteristic in a singular sense, or to describe multiple combinations of features, structures, or characteristics. Similarly, terms such as “a,” “an,” or “the” can again be understood to express a singular usage or convey a plural usage, at least in part, depending on context. Furthermore, the term “based on” can be understood to not necessarily convey an exclusive set of factors, and can conversely allow for additional factors that are not necessarily explicitly described, at least in part, depending on context.

[0030] It should be readily understood that the meanings of “on top of,” “above,” and “above” in the disclosure of this application should be interpreted in the broadest possible sense, such that “on top of” not only means “directly” on something, but also includes the meaning of being on something and having intermediate features or layers between them, and that “on top of” or “above” not only means being on or above something, but also includes the meaning of not having intermediate features or layers (i.e., being directly on something).

[0031] Furthermore, for ease of description, as illustrated in the accompanying drawings, spatial relative terms such as "below," "under," "lower," "above," and "higher" may be used to describe the relationship of one or more elements or features to another. In addition to the orientations depicted in the drawings, the spatial relative terms are intended to encompass different orientations of elements in use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations) and the spatial relative descriptions used herein may be interpreted accordingly.

[0032] The technical principle of this invention is based on the basic operating mechanism of a ring oscillator. Traditionally, a ring oscillator consists of an odd number of logic gates. When an input signal passes through these gates, due to accumulated delays and logic inversion, a periodic oscillation signal is generated. However, in the stationary state, the leakage current of the transistor still flows through the signal path, a phenomenon that is particularly pronounced in advanced manufacturing processes.

[0033] To address the problems of the aforementioned ring oscillators, this invention proposes an improved ring oscillator circuit, characterized by integrating the ring oscillator with a transmission gate.

[0034] To facilitate understanding of the ring oscillator circuit design in this embodiment, the basic principles and structure of the ring oscillator are briefly introduced below. A ring oscillator is a circuit that generates oscillating signals using the delay characteristics of logic gates and is widely used in integrated circuit design. Its core structure consists of a series of logic gates (usually inverters or other logic elements) connected in series to form a closed loop. When a signal passes through each logic gate, a certain delay is generated due to the switching behavior of the transistors. These delays accumulate and eventually cause the signal to periodically reverse in the loop, thus forming a stable oscillation output. To meet the oscillation conditions, a ring oscillator typically requires an odd number of inverters, because an odd number of inverters can provide a 180-degree phase shift, and combined with the additional phase change contributed by the delay, forms positive feedback. In practical applications, the frequency range of ring oscillators can range from several megahertz (MHz) to tens of gigahertz (GHz), making them suitable for scenarios such as clock generation, frequency modulation, or random number generation. For example, in digital processors, ring oscillators are often used to generate synchronous clock signals to ensure coordinated operation of various modules. Another characteristic of ring oscillators is their flexibility; the oscillation frequency can be easily changed by adjusting the number of logic gates or transistor parameters, making them particularly useful for testing circuit performance or calibrating process parameters. However, frequency stability and sensitivity to power supply noise are also factors to consider during design, especially in high-frequency applications where parasitic capacitance and inductance can affect oscillation quality. Based on these characteristics, the ring oscillator 10 of this embodiment employs a specific logic element configuration and combines it with a transmission gate structure to effectively reduce leakage current while maintaining oscillation performance.

[0035] A NAND gate is a basic logic gate that performs a NAND operation. Its output is logic low (0) only when all inputs are logic high (1), and logic high (1) otherwise. In Complementary Metal-Oxide-Semiconductor (CMOS) technology, a NAND gate consists of two parallel P-type metal-oxide-semiconductor transistors (PMOS) and two series-connected N-type metal-oxide-semiconductor transistors (NMOS). The source of the PMOS transistor is connected to the power supply (VDD), and the drain of the NMOS transistor is ultimately connected to ground (GND). The two input signals control the gates of the corresponding PMOS and NMOS, respectively. When either input is low, at least one PMOS is turned on, and the output is pulled to VDD; when both inputs are high, the two NMOS transistors are turned on in series, and the output is pulled to GND. This structure ensures low static power consumption in the steady state of the NAND gate, as there is only brief dynamic power consumption when the input changes. The logic versatility of NAND gates makes them extremely valuable in integrated circuit design, because with proper combination, NAND gates can implement any logic function, such as inversion, AND, or OR operations. In ring oscillators, NAND gates are typically used to provide control functions, such as turning the oscillation on and off by connecting one input to an enable signal. When the enable signal is high, the NAND gate is equivalent to an inverter, participating in the formation of the oscillation circuit; when the enable signal is low, the NAND gate output is fixed high, stopping the oscillation. Compared to a simple inverter, a NAND gate has more transistors (four), so its propagation time is usually slightly higher. For example, in a 22nm process, the propagation delay of a NAND gate can be 20%-30% higher than that of an inverter. Furthermore, the design of NAND gates requires consideration of transistor size matching to ensure a balance between logic threshold and switching speed. In low-power applications, leakage current of NAND gates is also an important consideration, especially in advanced process technologies, where sub-threshold leakage current of series NMOS transistors can accumulate, affecting standby power consumption. Therefore, designers may choose high-threshold transistors or optimize the layout to reduce leakage current. Another advantage of NAND gates is their relative robustness to noise, as their multi-input structure can filter out transient interference at the input to some extent.

[0036] An inverter is one of the most basic logic gates in integrated circuits. Its function is to reverse the logic state of an input signal, i.e., logic high (1) to logic low (0), and logic low (0) to logic high (1). In CMOS technology, an inverter consists of a P-type metal-oxide-semiconductor transistor (PMOS) and an N-type metal-oxide-semiconductor transistor (NMOS). Their gates are connected as the input terminal, and their drains are connected as the output terminal. The source of the PMOS is connected to the power supply (VDD), and the source of the NMOS is connected to ground (GND). When the input is low, the PMOS is turned on, the NMOS is turned off, and the output is pulled to VDD; when the input is high, the NMOS is turned on, the PMOS is turned off, and the output is pulled to GND. The advantage of this complementary structure is its extremely low static power consumption, because in steady state, only one transistor is turned on, avoiding the formation of a DC path. The delay time of the inverter depends on the switching speed of the transistor and the load capacitance at the output terminal, typically ranging from several picoseconds to tens of picoseconds, which is crucial for the oscillation frequency of the ring oscillator. In a ring oscillator, the inverter is the primary delay unit. By connecting multiple inverters in series, the signal is repeatedly reversed in the loop, forming a periodic oscillation. Inverter design requires a trade-off between speed, power consumption, and area. For example, increasing the transistor's width-to-length ratio (W / L) can improve drive capability and shorten delay, but it increases dynamic power consumption and chip area. In low-power designs, using high-threshold transistors can reduce leakage current, but may lead to a decrease in speed. In advanced process technologies (such as 14nm FinFETs), the leakage current problem of inverters is particularly prominent because the shrinking transistor size significantly increases the sub-threshold leakage current. For example, the leakage current of a standard inverter can reach tens of picoamps, which accumulates into significant standby power consumption in a ring oscillator composed of multiple inverters. Furthermore, inverter performance is also affected by variations in supply voltage and temperature. For instance, at low voltage operation (e.g., 0.8V), the switching speed may decrease by 30%, requiring compensation during design. Another important characteristic of inverters is their symmetry. An ideal inverter has symmetrical rise and fall times at the logic threshold (typically VDD / 2), which helps ensure the stability of the oscillation signal.

[0037] A transmission gate is a commonly used controllable switching element used to selectively turn on or off a signal path, and is widely used in digital and analog circuits. In CMOS technology, a transmission gate consists of an N-type metal-oxide-semiconductor transistor (NMOS) and a P-type metal-oxide-semiconductor transistor (PMOS) connected in parallel, with their gates receiving complementary control signals. When the control signal turns both the NMOS and PMOS on simultaneously, the transmission gate allows the input signal to be transmitted from one end to the other; when the control signal turns both off, the signal path is blocked. The parallel structure of the transmission gate allows it to transmit the full voltage range (from 0V to VDD) without signal loss due to transistor threshold voltage. For example, NMOS transistors are good at transmitting low-voltage signals (close to 0V), while PMOS transistors are good at transmitting high-voltage signals (close to VDD), and their combination ensures signal integrity. The on-resistance of a transmission gate is typically between tens of ohms and hundreds of ohms, depending on the transistor size and manufacturing process parameters. In ring oscillators, transmission gates can be used to control the connectivity of the signal path, for example, by turning off the transmission gate to stop oscillation, thereby reducing standby power consumption. However, the introduction of transmission gates also brings some challenges. For example, their on-resistance and parasitic capacitance can increase signal path delay, affecting oscillation frequency. In 14nm process technology, the parasitic capacitance of a typical transmission gate can reach several femtofarads (fF), which needs careful consideration in high-frequency applications. Furthermore, the leakage current of the transmission gate is also a significant design factor, especially in standby mode. Subthreshold leakage currents of NMOS and PMOS transistors can form weak paths through the closed transmission gate, impacting low-power targets. Therefore, the transistor type (e.g., high threshold or standard threshold) and size of the transmission gate need to be optimized to balance conduction performance and leakage characteristics. Another advantage of transmission gates is their fast response capability, with switching times typically in the picosecond range, making them suitable for dynamic control applications, such as the start signal synchronization control in this invention. The design of transmission gates also needs to consider the influence of supply voltage. Under low-voltage operation, the on-resistance can increase significantly, requiring compensation by increasing transistor size or using low-threshold transistors.

[0038] After introducing the basic elements mentioned in this invention, the following paragraphs will describe various embodiments of this invention.

[0039] Example 1

[0040] Figure 1A schematic diagram of a ring oscillator circuit according to a first embodiment of the present invention is shown. Circuit C1 includes a ring oscillator 10 and a transmission gate 20. The ring oscillator 10 is composed of a NAND gate 12 and a plurality of inverters 14 connected in series. The ring oscillator 10 can be applied to clock generators, random number generators (RNGs), or other high-performance, low-power applications. It is worth noting that in this embodiment, the ring oscillator 10 has one NAND gate 12 and an even number of inverters 14. As mentioned above, a conventional ring oscillator contains an odd number of inverters, while in this embodiment, the NAND gate 12 acts as one of the inverters, meaning that the number of the remaining inverters 14 is even. The entire ring oscillator 10 (containing one NAND gate 12 and an even number of inverters 14) has the same effect as a conventional ring oscillator (containing an odd number of inverters). In addition, with Figure 1 As shown in the embodiment, the ring oscillator 10 includes one NAND gate 12 and four inverters 14. Therefore, the ring oscillator 10 is equivalent to a ring oscillator with five inverters, and its number of stages is, for example, five. It is understood that the number of inverters 14 can be adjusted as needed, and the present invention is not limited thereto.

[0041] Transmission gate 20 is coupled between NAND gate 12 and inverters 14. One end of the transmission gate is connected to a voltage source Vcc, and the other end is connected to NAND gate 12 and the four inverters 14. When transmission gate 20 is open, the voltage source Vcc passes through the transmission gate to provide the start-up voltage for NAND gate 12 and the four inverters 14. Transmission gate 20 includes an N-type transistor 22 and a P-type transistor 24 connected in parallel, and its control signal is synchronized with the enable signal (labeled E in the figure) of the ring oscillator. Figure 1As shown in the circuit diagram, when the start signal is low (E=0), the ring oscillator stops oscillating. Simultaneously, when the start signal is low (or a 0 signal, E=0), the N-type transistor 22 receives a signal of 0, causing it to turn off (the N-type transistor 22 turns off when it receives a signal of 0 and turns on when it receives a signal of 1). Furthermore, an inverter 26 is connected to the gate of the P-type transistor 24. When the signal 0 passes through the inverter 26, it is converted into a signal of 1. This signal 1 then enters the P-type transistor 24, also causing it to turn off (the N-type transistor 22 turns off when it receives a signal of 1 and turns on when it receives a signal of 0). Therefore, for the entire transmission gate 20, when the start signal is low or 0, the transmission gate 20 is in a closed state. In other words, when the ring oscillator 10 stops oscillating, the transmission gate 20 also closes at the same time. At this time, the voltage source Vcc cannot provide the start-up voltage of the NAND gate 12 and the inverter 14 through the transmission gate 20. That is, the NAND gate 12 and the inverter 14 will be turned off. In this way, the signal path can be blocked, thereby greatly reducing the sub-threshold leakage current.

[0042] In one preferred embodiment of the invention, transmission gate 20 employs a high threshold voltage (HVT) transistor configuration. Simulation results show that the HVT configuration significantly reduces leakage current compared to using a standard threshold voltage (SVT) transistor. For example, in a 22nm process, the standby current (IDDQ) decreases from 1.00X to 0.07X (a substantial reduction of 93%); in a 14nm process, the standby current decreases further from 1.00X to 0.04X (a substantial reduction of 96%). Although the HVT configuration reduces the oscillation speed by approximately 5% (e.g., from 10.66GHz to 10.06GHz), considering both the reduction in standby current (leakage current) and the decrease in oscillation speed, the overall performance of the ring oscillator is still improved, demonstrating a better trade-off between leakage current and speed. Therefore, HVT is the preferred choice.

[0043] In some embodiments of the present invention, the size design of the transmission gate 20 has also been optimized. In the 22nm process, the aspect ratio (W / L) of the transmission gate 20 is 3*2 / 0.03 micrometers; in the 14nm process, a FinFET structure is used with an aspect ratio of 20 / 0.016 micrometers and 20 fins. This size design ensures an optimal balance between reduced leakage current and oscillation performance. Experiments conducted by the applicant have shown a significant performance improvement based on the above data. In other words, although the present invention does not limit the actual size of the transmission gate 20, designing it according to the above aspect ratio can result in optimized performance improvement.

[0044] The following description will focus on different embodiments of the present invention. For the sake of simplicity, the description will mainly focus on the differences between the embodiments, and will not repeat the same points. In addition, the same elements in the embodiments of the present invention are identified by the same reference numerals to facilitate comparison between the embodiments.

[0045] Example 2

[0046] Figure 2 A circuit diagram illustrating a second embodiment of the present invention is shown. In this second embodiment, the transmission gate 20 of circuit C2 is coupled to a control unit 30. The control unit 30 dynamically adjusts the conduction state of the transmission gate according to the operating conditions of the ring oscillator 10 (such as frequency or temperature). The purpose of the control unit 30 is to dynamically adjust the conduction state of the transmission gate 20 according to the operating conditions of the ring oscillator (such as oscillation frequency, temperature, power supply voltage, or load changes), thereby achieving an optimal balance between reducing leakage current and oscillation performance. The transmission gate of a conventional ring oscillator is typically only synchronized with the start signal E, lacking flexible adjustment capabilities. The control unit 30 generates adaptive control signals by sensing environmental or operating parameters, dynamically adjusting the on-resistance or switching timing of the transmission gate, thereby optimizing circuit performance. The control unit 30 can be a digital, analog, or hybrid circuit, with the specific structure depending on the application scenario. The control unit 30 can be a digital control unit, an analog control unit, or a hybrid control unit.

[0047] For example, assuming a ring oscillator is used in a 5G communication module, the control unit 30 can be designed as a temperature-based analog control circuit. This circuit includes a thermistor and a low-power comparator to monitor the ambient temperature (range -40°C to 85°C). When the temperature is below 0°C, the control unit outputs a high voltage (e.g., 1.2V) to fully conduct the transmission gate 20 to ensure oscillation speed; when the temperature is above 50°C, it outputs a low voltage (e.g., 0.6V) to partially turn off the transmission gate to reduce leakage current. Furthermore, the control unit can integrate an 8-bit DAC, providing 256 levels of on-state, allowing fine adjustment of the transmission gate's on-resistance (range from 10Ω to 10kΩ).

[0048] The advantages of adding control unit 30 are as follows: First, control unit 30 can adjust the transmission gate state according to operating conditions, such as maximizing leakage current blocking in low-frequency mode and prioritizing oscillation speed in high-frequency mode. Simulations show that this dynamic control can further reduce standby power consumption (lower than 0.07X without control unit). Furthermore, it enhances adaptability to variations in temperature, voltage, or process technology. For example, at high temperatures (85°C), leakage current can be reduced by 95%, while at low temperatures (-40°C), the oscillation frequency decreases by only 2%. Additionally, control unit 30 is suitable for various scenarios, such as IoT sensors (low frequency, low power consumption) or 5G base stations (high frequency, high performance). The control unit can be configured via software or hardware to meet different needs. Moreover, by finely controlling leakage current, the operating time of battery-powered devices can be extended. For example, in IoT applications, standby time can be extended from 100 hours to 120 hours.

[0049] Example 3

[0050] Figure 3 A circuit diagram illustrating a third embodiment of the present invention is shown. In this third embodiment, the transmission gate 20 of circuit C3 may include a bypass circuit 40 to provide an alternative signal path in the startup state, avoiding the influence of the transmission gate on the oscillation frequency. More specifically, the purpose of adding the bypass circuit 40 is to provide an alternative signal path bypassing the transmission gate 20 when the ring oscillator 10 is in the startup state, thereby reducing the influence of the transmission gate 20 on the oscillation frequency. Although the transmission gate 20 can effectively reduce leakage current in the shutdown state, its on-resistance (Ron) and parasitic capacitance may increase the delay of the signal path in the startup state, causing the oscillation frequency to drop (e.g., 5%). The bypass circuit 40 ensures that the signal is transmitted with minimal delay by conducting a low-impedance path in the startup state, maintaining the high-frequency performance of the ring oscillator.

[0051] like Figure 3As shown, the bypass circuit 40 is composed of a switching element or a low-impedance path and is connected in parallel with the transmission gate 20. In this embodiment, the bypass circuit 40 uses an NMOS transistor connected in parallel with the transmission gate 20, and the control signal is synchronized with the start signal E. However, in other embodiments of the present invention, the bypass circuit 40 may include a PMOS transistor, another transmission gate, or a wire (without a switching element, etc.). These are all possible variations.

[0052] Based on the applicant's experimental results, adding a bypass circuit has the following advantages. First, the bypass circuit 40 can effectively eliminate the influence of the on-resistance of the transmission gate, making the oscillation frequency closer to the ideal value (e.g., reducing the frequency loss from 5% to 0.5%, but not limited to this). Furthermore, by selectively enabling the bypass circuit 40, multi-frequency operation can be supported. For example, the main path (i.e., the path through transmission gate 20) can be used in low-frequency mode, while switching to the bypass circuit 40 in high-frequency mode. The bypass circuit 40 has a simple structure (e.g., a single transistor) and is easy to integrate into existing layouts.

[0053] In addition to the bypass circuit 40, circuit C3 also includes a stabilization unit 50 (such as a capacitor) in this embodiment to stabilize the signal path voltage when the transmission gate is closed, preventing floating. The main function of the stabilization unit 50 is to stabilize the voltage of the signal path of the ring oscillator 10 when the transmission gate 20 is closed, preventing instability caused by node voltage floating. When the transmission gate 20 is closed to block the signal path, some nodes in the ring oscillator 10 may be in an undefined state due to the lack of a clear voltage reference, which may lead to parasitic capacitance charging, unexpected leakage current, or unstable initial oscillation behavior when the circuit restarts. The stabilization unit 50 ensures that the voltage of the signal path remains within the expected range by providing a voltage reference or charge storage mechanism, thereby improving the reliability and stability of the circuit.

[0054] Generally, the stabilization unit 50 is typically composed of passive components (such as capacitors) or active components (such as voltage regulator circuits), with the specific structure depending on the application requirements. In this embodiment, the stabilization unit 50 can be implemented as a 100fF MIM capacitor connected between the output node of the transmission gate 20 and ground to ensure that the node voltage remains stable in the off state and prevent floating. Simulations show that after adding the stabilization unit, the node voltage fluctuation is reduced from ±200mV to ±10mV, and the startup time is shortened by approximately 40%. In advanced designs, a weak pull-up PMOS transistor (W / L=1 / 0.03μm) can be added to fix the node voltage at VDD, suitable for high-reliability applications.

[0055] Based on the applicant's experimental results, the advantages of adding the stabilizing unit 50 include the following: First, it improves circuit stability, prevents unexpected leakage current or signal interference caused by floating nodes, and ensures the low-power characteristics of the ring oscillator in the stopped state. Simulation results show that after adding the stabilizing unit 50, node voltage fluctuations can be reduced from ±200mV to ±10mV, improving circuit reliability. Secondly, the stabilizing unit 50 improves startup behavior. Specifically, when the circuit restarts, the stabilizing unit 50 ensures that the node voltage starts from a known initial state, reducing oscillation setup time. For example, the startup time can be shortened from 5ns to 3ns. Furthermore, the stabilizing unit 50 has a simple structure, thus exhibiting strong compatibility with existing components and easy integration into existing process technologies (such as 14nm FinFET) without significant modifications to the core design of the ring oscillator. Finally, the stabilizing unit 50 can absorb power supply or substrate noise, reducing its impact on the signal path, especially at high-frequency operations (such as above 10GHz), significantly reducing noise sensitivity.

[0056] It is worth noting that, in Figure 3 In the illustrated embodiment, circuit C3 incorporates both the control unit 30 from the second embodiment described above, as well as the newly added bypass circuit 40 and stabilizing unit 50. Adding these components simultaneously achieves the aforementioned advantages. However, in actual manufacturing processes, adding components also increases the cost and complexity of the process. Therefore, in other embodiments of the present invention, a system based on... Figure 1 The circuit C1 shown can be further modified by adding a control unit 30, a bypass circuit 40, and a stabilizing unit 50, or by adding any two of the three. All of the above combinations are also within the scope of this invention.

[0057] In summary, the present invention, compared to the conventional ring oscillator, has the following characteristics: Conventional ring oscillators may still generate leakage current in standby mode, thereby increasing the power consumption of the components. The present invention solves this problem by introducing a transmission gate 20 (e.g., Figure 1 (As shown in the embodiment). The transmission gate 20 is a switching element composed of an N-type transistor 22 and a P-type transistor 24 connected in parallel, and its conduction state is determined by a control signal. When the ring oscillator 10 stops operating, the start signal E also turns off the transmission gate 20, thus cutting off the power supply to the NAND gate 12 and each inverter 14, more effectively blocking the signal path, preventing leakage current from passing through, and thus significantly reducing standby power consumption.

[0058] Several other advanced embodiments of the present invention (such as) Figure 2 Or Figure 3This design further enhances the circuit's flexibility. In this design, transmission gate 20 is coupled to a control unit 30, which dynamically adjusts the transmission gate's conduction state based on the ring oscillator's operating conditions (such as frequency, temperature, or power supply voltage). For example, during low-frequency operation, the control unit can completely close the transmission gate to maximize leakage current blocking; during high-frequency operation, the transmission gate can be partially turned on to maintain the stability of the oscillation signal. This dynamic control mechanism not only improves the circuit's adaptability but also enables it to meet different application requirements. Furthermore, to avoid potential impacts on the oscillation frequency from transmission gate 20 during startup, a bypass circuit 40 can be added. The bypass circuit 40 is connected in parallel with transmission gate 20, providing an alternative signal path during startup to ensure unimpaired oscillation performance. Simultaneously, a stabilizing unit 50 (e.g., a capacitor) can be coupled to the output of transmission gate 20 to stabilize the signal path voltage during shutdown, preventing a floating state.

[0059] Based on the above description and accompanying drawings, the present invention provides a ring oscillator circuit C1, characterized in that it includes a ring oscillator 10, which includes a plurality of series-connected logic elements (including NAND gate 12 and a plurality of inverters 14) for generating an oscillation signal, and a transmission gate 20 coupled in the signal path of the ring oscillator 10, wherein when the ring oscillator 10 is in a stopped state, the transmission gate 20 is closed to block the signal path, thereby reducing the leakage current of the ring oscillator 10.

[0060] In some embodiments of the present invention, the ring oscillator 10 includes at least one NAND gate 12 and a plurality of inverters 14, with a transmission gate 20 coupled between the NAND gate 12 and the inverters 14.

[0061] In some embodiments of the present invention, the transmission gate 20 includes an N-type transistor and a P-type transistor 24 connected in parallel, and the control signal of the transmission gate 20 is synchronized with the start signal E of the ring oscillator 10.

[0062] In some embodiments of the invention, the transmission gate 20 is designed with a width-to-length ratio (W / L) of 3*2 / 0.03 micrometers or 20 / 0.016 micrometers to optimize the balance between leakage current reduction and circuit speed.

[0063] In some embodiments of the present invention, the standby current of the ring oscillator 10 in steady state is reduced to less than 0.07 times compared to a conventional ring oscillator without a transmission gate (as mentioned earlier, in a 22nm process, the standby current is reduced from 1.00X to 0.07X, which is a significant reduction of 93%; in a 14nm process, the standby current is further reduced from 1.00X to 0.04X, which is a significant reduction of 96%).

[0064] In some embodiments of the invention, the transmission gate 20 employs a high threshold voltage (HVt) or standard threshold voltage (SVt) transistor to further reduce subthreshold leakage current.

[0065] In some embodiments of the present invention, the operating frequency of the ring oscillator 10, after the addition of the transmission gate 20, decreases by a rate of 5.1% to 5.9% compared to the case without the transmission gate.

[0066] In some embodiments of the present invention, the transmission gate 20 is further coupled to a control unit 30, which dynamically adjusts the conduction state of the transmission gate 20 according to the operating conditions of the ring oscillator 10 to optimize the balance between leakage current reduction and oscillation performance.

[0067] In some embodiments of the invention, the transmission gate 20 may be selectively partially turned on when the ring oscillator 10 is in the start-up state to adjust the oscillation frequency of the ring oscillator 10.

[0068] In some embodiments of the present invention, the transmission gate 20 is coupled to a stabilization unit 50, which includes a capacitor element or an active voltage regulator circuit, and the stabilization unit 50 is used to stabilize the signal path voltage of the ring oscillator 10 when the transmission gate 20 is closed.

[0069] In some embodiments of the invention, the transmission gate configuration further includes a bypass circuit 40 for providing an alternative signal path to maintain oscillation performance when the ring oscillator 10 is in the start-up state.

[0070] In some embodiments of the present invention, the ring oscillator circuit C1 is applied in a low-power electronic device to improve the overall energy efficiency of the circuit.

[0071] The advantages of the ring oscillator circuit of this invention are obvious. Simulation results show that its standby current can be reduced to 0.07 times or less of conventional circuits, significantly improving energy efficiency. This characteristic makes it particularly suitable for low-power electronic devices, such as mobile devices, wearable devices, and IoT nodes. By reducing standby power consumption, this invention not only extends battery life but also provides new possibilities for circuit design in advanced process technologies. In the future, with further optimization of the control unit or bypass circuitry, this invention can play a role in a wider range of fields.

[0072] In summary, the key feature of this invention is that the ring oscillator circuit provided by this invention includes a ring oscillator and a transmission gate. The ring oscillator consists of multiple logic elements connected in series, such as NAND gates and inverters, and its function is to generate a stable oscillation signal. The transmission gate acts as a controllable switch, configured at a critical position in the signal path. When the start signal is low (i.e., in a stop state), the transmission gate closes, cutting off the signal flow between logic elements, thereby suppressing the generation of sub-threshold leakage current. Compared with known technologies, the advantage of this invention is that it can significantly reduce standby power consumption and provides the possibility for further optimization, such as dynamic control or bypass design, making it suitable for various low-power scenarios.

[0073] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made in accordance with the claims of the present invention shall be within the scope of the present invention.

Claims

1. A ring oscillator circuit, characterized in that, Include: A ring oscillator contains multiple logic elements connected in series to generate an oscillating signal; as well as A transmission gate is coupled in the signal path of the ring oscillator, wherein when the ring oscillator is in a stopped state, the transmission gate is closed to block the signal path, thereby reducing the leakage current of the ring oscillator.

2. The ring oscillator circuit as described in claim 1, characterized in that, The ring oscillator includes at least one NAND gate and multiple inverters, with the transmission gate coupled between the NAND gate and the inverters.

3. The ring oscillator circuit as described in claim 1, characterized in that, The transmission gate comprises a P-type transistor and an N-type transistor connected in parallel, and the control signal of the transmission gate is synchronized with the start signal of the ring oscillator.

4. The ring oscillator circuit as described in claim 1, characterized in that, The transmission gate is designed with a width-to-length ratio (W / L) of 3*2 / 0.03 micrometers or 20 / 0.016 micrometers to optimize the balance between reducing leakage current and circuit speed.

5. The ring oscillator circuit as described in claim 1, characterized in that, The standby current (Istandby) of this ring oscillator in steady state is reduced to less than 0.07 times compared to a conventional ring oscillator without a transmission gate.

6. The ring oscillator circuit as described in claim 1, characterized in that, The transmission gate employs a high threshold voltage (HVt) transistor or a standard threshold voltage (SVt) transistor to further reduce subthreshold leakage current.

7. The ring oscillator circuit as described in claim 1, characterized in that, The operating frequency of the ring oscillator, after the addition of the transmission gate, decreases by 5.1% to 5.9% compared to the case without the transmission gate.

8. The ring oscillator circuit as described in claim 1, characterized in that, The transmission gate is further coupled to a control unit, which dynamically adjusts the conduction state of the transmission gate according to the operating conditions of the ring oscillator to optimize the balance between leakage current reduction and oscillation performance.

9. The ring oscillator circuit as described in claim 1, characterized in that, The transmission gate can be selectively partially turned on when the ring oscillator is in the start-up state to adjust the oscillation frequency of the ring oscillator.

10. The ring oscillator circuit as described in claim 1, characterized in that, The transmission gate is coupled to a stabilization unit, which includes a capacitor or an active voltage regulator circuit. The stabilization unit is used to stabilize the signal path voltage of the ring oscillator when the transmission gate is closed.

11. The ring oscillator circuit as described in claim 1, characterized in that, The transmission gate configuration further includes a bypass circuit to provide an alternative signal path to maintain oscillation performance when the ring oscillator is in the start-up state.

12. The ring oscillator circuit as described in claim 1, characterized in that, This ring oscillator circuit is used in low-power electronic devices to improve the overall energy efficiency of the circuit.

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