Signal generation method for direct digital frequency synthesizer based on parallel multi-channel architecture

Abstract

The application discloses a signal generation method of a direct digital frequency synthesizer based on a parallel multi-channel architecture, comprising: constructing n phase control word generation channels; globally resetting and setting phase initial values of each channel; configuring a starting frequency, a terminal frequency and a frequency change rate of a chirp effective period of each channel in a single period based on a configuration signal; determining a delay, a chirp effective and suspension period length of each channel; in each period, at a starting time of each period, accumulating a frequency control word according to a frequency change rate with a time step, and inputting the phase control word generation channel in parallel to update a phase word; performing phase-amplitude conversion on the phase word to output an amplitude signal; performing time-interleaved digital-to-analog conversion on the multiple amplitude signals, and then integrating in sequence to generate a single-period target chirp digital signal. The application significantly improves internal waveform synthesis efficiency, reduces signal delay, and obtains higher spectral purity.

Description

Technical Field

[0001] This invention belongs to the field of frequency synthesis technology, and specifically provides a signal generation method and system based on a direct digital frequency synthesizer with a parallel multi-channel architecture. Background Technology

[0002] The Direct Digital Frequency Synthesizer (DDFS) is a core component of frequency synthesis technology. Due to its advantages such as high frequency resolution, fast frequency switching speed, and continuously adjustable phase, it has been widely used in conventional single-channel signal generation scenarios.

[0003] However, in high-performance applications such as phased array radar, high-frequency instruments, and multi-channel communication systems that require multi-channel synchronous output and the generation of complex waveforms, such as linear frequency modulation / chirped signals and frequency shift keying signals, the traditional single-core direct digital frequency synthesizer design has the following shortcomings:

[0004] Single-core designs are limited by the processing power of a single arithmetic unit. To ensure signal accuracy and output rate, existing technologies typically employ one of two methods: relying on large-capacity look-up tables (LUTs) to store waveform data, causing storage resources to become a system bottleneck; or adopting a complex real-time computing architecture, resulting in a significant increase in the utilization of hardware resources such as multipliers, adders, and registers.

[0005] The single-core architecture requires a redesign of the external configuration link to meet the needs of various working modes such as fixed-frequency signals, chirped signals, and frequency shift keying (FSK) signals, making it difficult to achieve fast and seamless switching between different modes.

[0006] Single-core direct digital frequency synthesizers only have single-channel waveform synthesis capabilities. In scenarios requiring parallel processing of multiple internal waveforms, only serial time-division processing can be used to process multiple waveform data segments one by one, and then complex external logic circuits are needed to integrate and output the processing results. This approach not only significantly increases system control complexity and signal delay, but also easily leads to a decrease in the consistency of waveform synthesis across channels due to timing deviations introduced by time-division processing. Summary of the Invention

[0007] The technical problem to be solved by the present invention is to overcome the shortcomings of existing single-core direct digital frequency synthesizers in multi-channel synchronous output and complex waveform generation scenarios, such as rate bottleneck, high resource consumption, low multi-channel processing efficiency and poor mode switching flexibility, and to provide a signal generation method and system for a multi-channel parallel direct digital frequency synthesizer.

[0008] To solve the above technical problems, the present invention adopts the following technical solution: a signal generation method based on a direct digital frequency synthesizer with a parallel multi-channel architecture, which executes corresponding steps according to the target configuration signal, calculates the phase control word in parallel through multiple channels, performs amplitude conversion by the basis function phase amplitude conversion module, and performs gating and conversion by the subsequent time-interleaved digital-to-analog converter with multiple times low-speed clock to obtain the target chirped digital periodic signal.

[0009] Specifically, it includes:

[0010] Step A: Construct n phase control word generation channels in a predetermined order, where n is a positive integer ≥ 2; perform a global reset operation to bring each channel into its initial state and set the initial value of the phase control word for each channel;

[0011] Step B: Obtain the target configuration signal, and configure the start frequency control word, end frequency control word, and corresponding signal change rate control word for the effective chirp period of each channel within a single cycle based on the target configuration signal; wherein, a single cycle is the chirp signal scanning cycle; the target configuration signal includes at least a channel selection field, a start frequency control word, an end frequency control word, a signal frequency change rate control word, a delay duration control word, and a pause duration control word.

[0012] Step C: Based on the delay duration control word and pause duration control word contained in the target configuration signal, determine the duration of the delay period, chirp signal effective period, and pause period for each channel within a single cycle; within each cycle, experience the following in chronological order: delay period, chirp signal effective period, and pause period; at the beginning of each period, perform the following operations synchronously:

[0013] Based on the signal frequency change rate control word for the corresponding time period, the frequency control word is updated by accumulating it step by step over time. The updated frequency control word is then input in parallel to each phase control word generation channel. By accumulating the frequency control word step by step over time, the phase control word of the corresponding channel is updated. Each updated phase control word is then converted from phase to amplitude to obtain the corresponding amplitude value and output the amplitude signal.

[0014] The multi-amplitude signals are time-interleaved digital-to-analog conversioned and converted into corresponding time period signals. Then, the time period signals are integrated according to the time sequence corresponding to the predetermined order of the phase control word channels to generate a single-cycle target chirped digital signal.

[0015] Furthermore, in step A above, initial values ​​are assigned to the initial variables of each module according to the system architecture. Generally, the initial variables of each module are assigned to the initial value of zero. However, in the multi-channel architecture, the phase control word (PCW) in the phase control word generation module cannot all be assigned to zero. The structure and internal logic operation of each phase control word generation channel are the same, but there are requirements for the logical order. In the same clock cycle of multiple channels, the same phase control word (PCW) is not generated. Instead, multiple consecutive phase control words with a logical order are generated. In this way, more consecutive phase control words can be generated in the same clock cycle, enabling the system to achieve a higher operating frequency.

[0016] Furthermore, in step B above, the start frequency control word and the end frequency control word of each chirped signal segment in the target configuration signal are first used as the basis for configuring the enable signal of the linear frequency modulation signal used to configure the effective or ineffective state of each chirped signal segment. The preset start frequency control word is used as the initial value. The start frequency control word and the end frequency control word are configured one by one according to the effective time period of each chirped signal that appears in a single cycle through the serial peripheral interface.

[0017] Based on the signal frequency change rate control word in the target configuration signal, and in conjunction with the above-mentioned linear frequency modulation signal configuration enable signal, the signal frequency change rate control word is used as the reference value to complete the setting of the signal change rate control word corresponding to the effective time period of each chirped signal within a single cycle. Alternatively, the signal frequency change rate can be set to zero to obtain a stable frequency sine wave signal.

[0018] Furthermore, in step C above, since the signal change rate control word corresponding to the preset delay period and pause period in a general system is 0, the following steps C1 to C2 are executed sequentially for each period within a single cycle:

[0019] Step C1: Update the frequency control word according to the current time period type, then proceed to step C2:

[0020] If the current time period is a delayed time period, then update the frequency control word FCW with the starting frequency control word of its subsequent time period;

[0021] If the current time period is a pause period, then update the frequency control word FCW with the termination frequency control word of its preceding time period;

[0022] If the current time period is a valid chirp signal period, then the frequency control word FCW is updated with the start frequency control word of that valid time period.

[0023] Step C2: For the current processing time period, execute steps C2-1 to C2-3 sequentially according to the time step to complete the construction of the signal for that time period;

[0024] Step C2-1: Based on the signal change rate control word corresponding to the current time period, incrementally update the frequency control word FCW after the current time period update, and output the frequency control word accumulation result;

[0025] Step C2-2: Input the accumulated result of the frequency control word into each phase control sub-PCW generation channel, accumulate and update the phase control word to obtain the phase control word corresponding to each channel that is logically continuous in phase;

[0026] In practical applications, n phase control word generation channels with identical structure and logic are generated in parallel, operating independently of each other without affecting each other.

[0027] Each channel receives the updated Frequency Control Word (FCW) and updates the corresponding Phase Control Word by accumulating the FCW. The updated Phase Control Word for each cycle is represented as follows:

[0028] ,

[0029] Therefore, the chirp signal can be simplified to its corresponding value. The expression is:

[0030]

[0031] Where k is the number of accumulated cycles of the initial frequency control word; For frequency control word step size, This is the updated phase control word.

[0032] In this process, the initial value of the phase control word (PCW) of each phase control word generation channel is different. The initial values ​​of the phase control word of each channel are set in an arithmetic sequence. The frequency control word step is divided into multiple binary multiple sub-steps. The sub-steps are obtained through shift operations. Each channel accumulates the corresponding sub-steps to update the phase control word, so that n channels generate a phase-continuous phase control word sequence in the same clock cycle, and output multiple phase control words at the same time.

[0033] Step C2-3: Truncate the phase control word output in step C2-2 to match its bit count with the input requirements of the subsequent phase-to-amplitude conversion; input the truncated high-bit phase control word (PCW) data into the phase-to-amplitude conversion module based on a finite orthogonal basis function system to calculate the amplitude value of the corresponding phase.

[0034] Furthermore, in practical applications, the phase-to-amplitude conversion module in steps C2-3 above does not use a traditional ROM structure, but instead adopts a calculation mode based on a finite orthogonal basis function system, specifically executing the following steps:

[0035] Step C2-3-1: First, select the finite-order Maclaurin expansion of the cosine function at x=0 and perform amplitude approximation synthesis. Use Horner's rule to decompose the high-order basis functions in the original formula. Reduce the use of multipliers by iteratively performing "multiplication-summation" operations to save hardware area. Then proceed to step C2-3-2.

[0036] Step C2-3-2: Utilizing the axial and central symmetry of the cosine function in the [0, 2π] phase interval, the input unsigned phase control word PCW is divided into four quadrants based on the values ​​of the high 2 bits. According to the principle of equal absolute amplitude values, the phase values ​​of the second, third, and fourth quadrants are mapped to the first quadrant to generate a signed positive phase control word a. At the same time, a sign judgment flag is generated from the high 2 bits of PCW for subsequent sign judgment of the calculation results. Then proceed to step C2-3-3.

[0037] Step C2-3-3: Input the phase control word a into the calculation module composed of alternating multiplier and adder groups. First, perform linear mapping on a to make it fall into the interval [0, π / 2] and form a variable x. Then, based on x, perform multiple operations of multiplying the calculation results with the corresponding coefficients and accumulating them to complete the conversion calculation from phase a to the absolute value of amplitude. Then proceed to step C2-3-4.

[0038] Step C2-3-4: Input the calculation results into the limiting module to limit the overflow results that exceed the range; finally, based on the sign judgment flag generated by the quadrant control word, determine the sign of the calculation results after limiting, and then perform unsigned processing to finally generate unsigned direct frequency synthesis results.

[0039] Step C3: Increment the current cumulative time step by 1, and determine whether the current time period is a delayed period or a pause period. If it is, further determine whether the current cumulative time step has reached the corresponding delay duration control word or pause duration control word in the target configuration signal. If it has reached the target, immediately terminate the processing flow of the current time period. If it has not reached the target, proceed to the next time step and return to step C2 to continue the process.

[0040] If the current time period is a valid chirp signal period, then check whether the frequency control word FCW is consistent with the termination frequency control word of the valid time period; if they are consistent, the processing flow of the time period is terminated; if they are inconsistent, proceed to the next time step and return to step C2.

[0041] Based on the same inventive concept, this invention also provides a signal generation system based on a parallel multi-channel architecture direct digital frequency synthesizer, which can adapt to better operating frequencies, can input high-precision and high-bandwidth signals, and has complete and rich mode switching functions to improve the applicability of the module.

[0042] Specifically, a signal generation system based on a parallel multi-channel architecture direct digital frequency synthesizer is used to implement the above method. The system includes a system reset module, a configuration signal receiving and processing module, a frequency control word update module, n phase control word generation channels, a phase-to-amplitude conversion module, and a time-interleaved digital-to-analog converter. The system reset module is communicatively connected to each of the other modules in the system and is used to perform system reset.

[0043] The configuration signal receiving and processing module includes a multiplexer. The multiplexer is used to receive the linear frequency modulation signal configuration enable signal in the target configuration signal, as well as the start frequency control word and end frequency control word of each chirped signal segment, and to configure the start frequency control word, end frequency control word and signal frequency change rate control word of each chirped signal effective time period arranged sequentially in a single cycle.

[0044] The frequency control word update module is used to receive the signal change rate control word output by the configuration signal receiving and processing module, and update the frequency control word by accumulating it step by step according to the signal change rate control word of the corresponding time period.

[0045] Each phase control word generation channel is implemented by a phase control word synthesis module. The phase control word synthesis module is used to receive the updated frequency control word output by the frequency control word update module, and accumulate it with time step to update the phase control word of the corresponding channel.

[0046] The phase-to-amplitude conversion module receives the updated phase control word output by the phase control word synthesis module, converts the phase control word into the corresponding amplitude value, and outputs the amplitude signal corresponding to each channel.

[0047] The time-interleaved digital-to-analog converter is used to receive the amplitude signal output from the phase-to-amplitude conversion module, and to perform gating conversion on the amplitude signal to output the target chirped digital signal.

[0048] Furthermore, the aforementioned configuration signal receiving and processing module integrates a serial peripheral interface (SPI). The input of the SPI is used to receive the target configuration signal from an external source, and its output is divided into two paths to complete data transmission. One path is connected to the input of the multiplexer in the configuration signal receiving and processing module, sending part of the target configuration signal data processed by SPI to the multiplexer. The other path is connected to the signal control module, sending the other part of the target configuration signal data processed by SPI to the chirp signal control module.

[0049] Furthermore, each of the aforementioned phase control word synthesis modules includes a multiplexer, an adder group, and a register group. The multiplexer decomposes the multiplication term in the phase difference operation of this module into a binary shift operation; the adder group performs a step-by-step accumulation operation between the shifted output terms and the current phase control word; and the register group is synchronously driven by the same clock and outputs one phase control word per clock cycle.

[0050] All phase control word synthesis modules operate in parallel under the same clock drive, outputting n adjacent and phase-continuous phase control words and sending them to the phase-to-amplitude conversion module.

[0051] Furthermore, the phase-to-amplitude conversion module processes the generated multi-channel continuous phase control word in two ways. Both methods are applicable to the parallel multi-channel direct frequency synthesizer architecture, specifically:

[0052] The first method involves a one-to-one correspondence between the phase control word (PCW) synthesis module and the basis function phase-to-amplitude conversion module, both operating at a low clock speed. A multiplier generates m consecutive amplitude values ​​in parallel, treating the fixed-frequency signal output as a linear chirped signal with a slope of 0. The final DAC sequentially scans and converts the four digital amplitude values ​​using a high-speed clock, ultimately outputting the amplitude value at a frequency m times the low-speed clock. This method requires two clocks: a high-speed low-speed clock and a high-speed clock that is strictly m times the low-speed clock. Frequency division for the high-speed clock is achieved through analog circuitry, and sufficient charging and discharging current ensures load-carrying capacity. Here, m is the same as the number of phase control word generation channels.

[0053] The second approach involves a PCW (Programmable Logic Controller) synthesis module with c phase control words corresponding to one basis function phase-to-amplitude conversion module. A medium-speed clock, c times the low-speed clock, is input to the basis function phase-to-amplitude conversion module, causing its input to scan across the c PCWs. The result is then input to the DAC via a p-to-1 clock. This method requires three clocks: one low-speed clock, a medium-speed clock strictly c times the low-speed clock, and a high-speed clock strictly p times the low-speed clock. This scheme involves relatively complex timing arrangements and MUX gating logic; its only advantage is that it saves area and reduces some power consumption.

[0054] Furthermore, the aforementioned phase-to-amplitude conversion module is based on a finite orthogonal basis function system and includes a quadrant mapping module, a multiplier group module, an adder group module, and a limiting module. The phase control word output from the phase control word synthesis module is input to the quadrant mapping module, where it is compressed in the quadrant. The low-order part of the phase control word is then sent to the multiplier group module and the adder group module to complete the operation and obtain an unsigned amplitude value. The unsigned amplitude value is then input to the limiting module to limit the maximum output value.

[0055] Meanwhile, based on the same inventive concept, the present invention also discloses a direct digital frequency synthesizer based on a parallel multi-channel architecture, which executes the above-described method process to generate a single-cycle target chirped digital signal.

[0056] The present invention adopts the above-mentioned technical solution, and compared with the prior art, the technology and system have the following technical effects:

[0057] 1) This invention significantly improves the efficiency of internal waveform synthesis, reduces signal delay, and achieves higher spectral purity by using multi-channel parallel generation of phase control words and phase-amplitude conversion based on a finite orthogonal basis function system, combined with time-interleaved digital-to-analog conversion.

[0058] 2) This invention adopts a parallel multi-channel architecture and time-interleaved digital-to-analog conversion technology, which effectively breaks through the rate limitation of a single-channel DDS and can achieve higher frequency and higher quality signal output under existing processes.

[0059] 3) The multi-channel parallel and high-efficiency conversion structure of this invention reduces the requirements for single-channel operation speed and storage depth, optimizes hardware resource utilization, and is conducive to system miniaturization and low-cost design.

[0060] 4) By assigning continuous non-zero initial values ​​to the phase control words of each channel and combining them with a successively accumulated frequency control word update mechanism, this invention ensures the continuity of the initial phase of the chirped signal, thereby improving the overall accuracy of signal synthesis and the highest operating frequency of the system. Attached Figure Description

[0061] Figure 1 This is a block diagram of the parallel phase control word generation module in this invention.

[0062] Figure 2 This is a system block diagram of the direct digital frequency synthesizer with a parallel multi-channel architecture in this invention.

[0063] Figure 3 These are schematic diagrams illustrating two structural relationships between the parallel phase control word generation multi-channel and the subsequent basis function phase-amplitude conversion module in this invention. Detailed Implementation

[0064] The specific embodiments of the present invention will be further described in detail below with reference to the accompanying drawings.

[0065] The method of this invention first resets the system. Then, based on the target configuration signal and using the system's unified clock as a reference, the initial variables of each module are reset. In particular, the phase control word generation module assigns continuous non-zero initial values ​​to different channels in phase. Then, according to the target configuration signal, the start and end frequency control words and the signal change rate control words for the effective time periods of the target signal are configured for each time period. The frequency control word FCW is accumulated sequentially with each time step and input to the phase control word generation module to generate continuous phase control words. Finally, the phase amplitude conversion module based on the expansion of the finite orthogonal basis function system and the time-interleaved digital-to-analog converter are used for gating and conversion to form the time period signal. Then, the time period signals are spliced ​​together to finally obtain the target chirped digital periodic signal.

[0066] This invention is applicable not only to generating chirped signals whose frequency changes linearly with time, but also to generating sinusoidal signals with a constant frequency. By simply configuring the above-mentioned signal frequency change rate parameter to zero, the chirped signal generator can be used as a direct digital frequency synthesizer (DDS), outputting a stable sine wave with the starting frequency.

[0067] The example uses a parallel four-channel architecture, and the specific steps are as follows:

[0068] Step A: Construct four phase control word generation channels, calculate four adjacent phase control words in parallel, and input them into the subsequent phase-to-amplitude conversion module for conversion.

[0069] The formulas for generating the phase control word for the four channels are as follows:

[0070]

[0071]

[0072]

[0073]

[0074] Where P is the phase control word. Here, k represents the initial frequency control word, and k is the cumulative number of cycles of the initial frequency control word. This is the frequency control word step size.

[0075] In the next clock cycle, the phase control word generation module for each channel will calculate as follows:

[0076]

[0077]

[0078]

[0079]

[0080] The phase control words generated in two clock cycles are adjacent to each other. Compared with a single core, more phase control words are generated for amplitude conversion within the same cycle, which increases the operating frequency of the system. Similarly, this structure can be extended to more channels.

[0081] From these two sets of formulas, we can also see that:

[0082]

[0083]

[0084]

[0085]

[0086] As can be seen from the phase control word difference between the preceding and following cycles of each calculation channel, the calculation of each difference requires three multipliers of corresponding bit lengths, namely... This requires more hardware resources and a larger area overhead. Shifters and adders can be used to replace multipliers to simplify calculations, reduce hardware resource consumption and area costs, and simultaneously reduce chip power consumption. By means of Shifting left by two bits yields the result. This can be obtained by shifting k four bits to the left. Shift left by four bits , , It can be split into Then they are added together to obtain the result. This way, only the phase control word generation module needs to calculate and generate the result. and Therefore, as Figure 1 As shown, the phase control word calculation can be expressed as: ,in All can be decomposed into a summation of powers of 2, and then the phase control word is obtained through shift and addition operations. The computational structure of each channel PCW can be simplified from a multi-stage accumulator structure based on line multipliers to a structure mainly composed of shifters and adders. The three multipliers are converted into shifters and adders, reducing the hardware resources of the original scheme. It can be considered as The current solution, i.e., the hardware resources of the technical solution of this invention, is... As can be seen, the generation of phase control words for four channels is achieved through accumulation and shift operations, which significantly reduces the consumption of hardware resources and reduces the area and power consumption.

[0087] The off-chip signals of this architecture only require configuration via the SPI module; all other signals are generated and synthesized on-chip. Through an innovatively designed low-speed multi-core computing and high-speed serial output structure, it executes corresponding steps based on the target configuration signal to obtain high-frequency, high-quality fixed-frequency sine wave signals and chirped digital signals.

[0088] The system is reset. The four phase control word channels are distinguished by their order, corresponding to the order in which the DAC selects and converts the subsequent phase control words into amplitude signals. The initial values ​​for the four channels are as follows:

[0089]

[0090]

[0091]

[0092]

[0093] Bundle Substituting, we can get According to the formula, we can get Similarly, during the initial value calculation of the four channels, multiplication operations can be converted into shift and addition operations, saving hardware resources. , Coefficients with a power of 2 can be obtained through shift operations. Other coefficients can be obtained by decomposing them into multiple coefficients with a power of 2, and then by shifting and adding them. This greatly reduces the use of multipliers and saves area costs.

[0094] Step B: Based on the start frequency control word and end frequency control word of each target signal segment in the target configuration signal, and in conjunction with the linear frequency modulation signal configuration enable signal used to set each target signal segment to an effective or ineffective state, using the preset start frequency control word as the initial reference, sequentially set the start frequency control word and end frequency control word of each effective time period of the target signal appearing in a single cycle; at the same time, based on the target signal change rate control word in the target configuration signal, and in conjunction with the linear frequency modulation signal configuration enable signal, set the signal change rate control word of each effective time period of the target signal in a single cycle, using the target signal change rate control word as the basis; after completion, proceed to step C.

[0095] Step C: Based on the delay duration control word and pause duration control word contained in the target configuration signal, determine the duration of the delay period, chirp signal effective period, and pause period for each channel within a single cycle; within each cycle, experience the following in chronological order: delay period, chirp signal effective period, and pause period; at the beginning of each period, perform the following operations synchronously:

[0096] Based on the signal change rate control word for the corresponding time period, the frequency control word is updated by accumulating it step by step over time. The updated frequency control word is then input in parallel to each phase control word generation channel. By accumulating the frequency control word step by step over time, the phase control word of the corresponding channel is updated. Each updated phase control word is then converted from phase to amplitude to obtain the corresponding amplitude value and output the amplitude signal.

[0097] The multi-amplitude signals are time-interleaved digital-to-analog conversioned and converted into corresponding time period signals. Then, the time period signals are integrated according to the time sequence corresponding to the predetermined order of the phase control word channels to generate a single-cycle target chirped digital signal.

[0098] In practical applications, since the signal change rate control word corresponding to the preset delay period and pause period in a typical system is 0, the following steps are executed sequentially for each period within a single cycle:

[0099] Step C1: Update the frequency control word according to the current time period type: If the current time period is a delayed time period, update the frequency control word with the starting frequency control word of its subsequent time period, and then proceed to step C2;

[0100] If the current time period is a pause period, the frequency control word FCW is updated with the termination frequency control word of the preceding time period, and then the process proceeds to step C2.

[0101] If the current time period is a valid chirp signal period, the frequency control word is updated with the start frequency control word of that valid time period, and then the process proceeds to step C2.

[0102] Step C2: For the current processing period, execute steps C2-1 to C2-3 sequentially according to the time step to complete the construction of the signal for that period.

[0103] Step C2-1: Based on the signal change rate control word corresponding to the current time period, incrementally update the frequency control word FCW updated in step C1, output the frequency control word accumulation result, and then proceed to step C2-2.

[0104] Step C2-2: The update result of the frequency control word is input into the PCW generation channel of each phase control sub to update the phase control word, resulting in multiple phase control words that are logically continuous in phase, and then proceed to step C2-3.

[0105] In practical applications, step C2-2 above, such as... Figure 2As shown, n phase control word generation modules with identical structure and logic operate in parallel, but are independent of each other and do not affect each other. Each channel receives the frequency control word (FCW) input from the upper level and generates the corresponding phase control word by accumulating the frequency control word. In each cycle, the phase control word generation module (PCW) needs to go through the updated frequency control word (FCW) input from the upper level. Therefore, the chirped signal can be simplified to its corresponding value. The expression is: .

[0106] The initial value of the phase control word (PCW) of each phase control word generation channel is different. A continuous phase control word sequence is generated in the same clock cycle. Multiple phase control words are simultaneously output to the phase-to-amplitude conversion module, and then the process proceeds to step C2-3.

[0107] Step C2-3. Truncate each phase control word input from the upper level to match the number of bits required for subsequent phase-to-amplitude conversion; input the truncated high-bit PCW data into the phase-to-amplitude conversion module based on a finite orthogonal basis function system to calculate the amplitude value of the corresponding phase.

[0108] In practical applications, the phase-to-amplitude conversion module in steps C2-3 above processes the generated multi-channel continuous phase control word in two ways. Both methods are applicable to parallel multi-channel direct frequency synthesizer architectures, such as... Figure 3 As shown, taking a four-channel architecture as an example:

[0109] like Figure 3 As shown in (a), the phase control word (PCW) synthesis module and the basis function phase-to-amplitude conversion module correspond one-to-one and both operate under a low-speed clock. They generate four consecutive amplitude values ​​in parallel through multipliers, treating the fixed-frequency signal output as a linear chirped signal with a slope of 0. The final DAC scans and converts the four digital amplitude values ​​sequentially using a high-speed clock, ultimately outputting the amplitude value at a frequency four times that of the low-speed clock. This method requires two clocks: a high-speed low-speed clock and a high-speed clock that is strictly four times the low-speed clock. Frequency division for the high-speed clock is achieved through analog circuitry, and sufficient charging and discharging current ensures load-carrying capacity.

[0110] like Figure 3As shown in (b), two phase control word (PCW) synthesis modules correspond to one basis function phase-to-amplitude conversion module. A medium-speed clock, twice the speed of the low-speed clock, is input to the basis function synthesis module, causing its input to scan between the two PCWs. The back-end then uses a 4-to-1 clock selector to input the result to the DAC. This method requires three clocks: one low-speed clock, a medium-speed clock strictly twice the speed of the low-speed clock, and a high-speed clock strictly four times the speed of the low-speed clock. This scheme involves relatively complex timing arrangements and MUX gating logic; its only advantage is that it can save area and reduce some power consumption.

[0111] In addition, in practical applications, the phase-amplitude conversion module in step C2-3 above does not adopt the traditional ROM structure, but adopts a calculation mode based on a finite orthogonal basis function system. It selects the finite order Maclaurin expansion of the cosine function at x=0 to perform amplitude approximate synthesis, and then obtains the amplitude value by passing through a multiplier group, an adder group, and reasonable truncation.

[0112] Step C3: Increment the current cumulative time step by 1, and determine whether the current time period is a delayed period or a pause period. If it is, further determine whether the current cumulative time step has reached the corresponding delay duration control word or pause duration control word in the target configuration signal. If it has reached the target, immediately terminate the processing flow of the current time period. If it has not reached the target, proceed to the next time step and return to step C2 to continue the process.

[0113] If the current time period is a valid chirp signal period, then check whether the frequency control word FCW is consistent with the termination frequency control word of the valid time period; if they are consistent, the processing flow of the time period is terminated; if they are inconsistent, proceed to the next time step and return to step C2.

[0114] This invention also discloses a signal generation system based on a parallel multi-channel architecture direct digital frequency synthesizer, such as... Figure 2 As shown, this system can generate high-rate-of-change chirped digital signals and output high-frequency, high-precision fixed-frequency sine waves, while also featuring mode switching functionality. The system includes a system reset module, a configuration signal receiving and processing module, a frequency control word update module, four phase control word synthesis modules, a phase-to-amplitude conversion module, and a time-interleaved digital-to-analog converter. The system reset module is communicatively connected to all other modules and is used for system reset. The phase control word synthesis module assigns corresponding logical values.

[0115] The configuration signal receiving and processing module includes a multiplexer. The multiplexer is used to receive the linear frequency modulation signal configuration enable signal in the target configuration signal, as well as the start frequency control word and end frequency control word of each chirped signal segment, and to configure the start frequency control word, end frequency control word and signal frequency change rate control word of each chirped signal effective time period arranged sequentially in a single cycle.

[0116] The frequency control word update module is used to receive the signal change rate control word output by the configuration signal receiving and processing module, and update the frequency control word by accumulating it step by step according to the signal change rate control word of the corresponding time period.

[0117] The phase control word synthesis module is used to receive the updated frequency control word output by the frequency control word update module, and to update the phase control word of the corresponding channel by accumulating it step by step over time.

[0118] The phase-to-amplitude conversion module receives the updated phase control word output by the phase control word synthesis module, converts the phase control word into the corresponding amplitude value, and outputs the amplitude signal corresponding to each channel.

[0119] The time-interleaved digital-to-analog converter is used to receive the amplitude signal output from the phase-to-amplitude conversion module, and to perform gating conversion on the amplitude signal to output the target chirped digital signal.

[0120] The specific design application is as follows: the configuration signal receiving and processing module also integrates a serial peripheral interface (SPI); the input of the SPI is used to receive the target configuration signal from the outside, and its output is divided into two paths to complete the data transmission. One path is connected to the input of the multiplexer in the configuration signal receiving and processing module to send part of the target configuration signal data processed by SPI to the multiplexer, and the other path is connected to the signal control module to send the other part of the target configuration signal data processed by SPI to the chirp signal control module.

[0121] Each phase control word synthesis module includes a multiplexer, an adder group, and a register group. The multiplexer decomposes the multiplication term in the phase difference operation into a binary shift operation. Each adder performs a step-by-step accumulation operation between the shifted output terms and the current phase control word. The register group is driven synchronously by the same clock and outputs one phase control word per clock cycle. All phase control word synthesis modules work in parallel under the same clock drive, outputting four adjacent and phase-continuous phase control words and sending them to the phase-to-amplitude conversion module.

[0122] The phase-amplitude conversion module is based on the expansion of a finite orthogonal basis function system. It mainly consists of a quadrant mapping module, a multiplier group module, an adder group module, and a limiting module. The phase control word (PCW) generated by the previous stage is superimposed with a phase jitter random number of the same bit length generated by the nonlinear feedback shift register and then input to the quadrant mapping module for processing. After quadrant compression, the low-order part of the phase control word is taken and sent to the multiplier group module and the adder group module to complete the operation and obtain an unsigned amplitude value. The result of this operation is input to the subsequent limiting module, which limits the maximum output value to prevent the output amplitude value from exceeding the theoretical maximum value.

[0123] In practical applications, when the DDFS system adopts a parallel multi-channel phase control word generation module architecture, the spurious-free dynamic range and signal synthesis efficiency of this invention are significantly improved. Thanks to the high synchronous parallel generation capability, independent channel collaborative operation characteristics, and excellent timing consistency of this parallel architecture, this invention not only minimizes phase timing deviations and computational congestion interference caused by single-core serial generation, but also more accurately suppresses additional spurious signals caused by multi-channel phase incoordination compared to traditional single-core structures, ensuring high accuracy in phase-amplitude conversion. Simultaneously, it further improves the spectral purity and multi-mode adaptation flexibility of the output signal, stably maintaining excellent signal quality over a wide bandwidth. Furthermore, it breaks through the single-core rate bottleneck, expands the Nyquist bandwidth and signal output rate, and adapts to the needs of high-frequency, high-performance scenarios.

[0124] The signal generation method and system based on a parallel multi-channel architecture direct digital frequency synthesizer proposed above has the following process: First, the initial variables of each module are reset, especially the phase control word generation module, which assigns continuous non-zero initial values ​​in phase to different channels. Then, according to the target configuration signal, the start and end frequency control words and the signal change rate control words for the effective time period of the target signal in each time period are configured. The frequency control word FCW is successively accumulated with each time step and input to the phase control word generation module to generate continuous phase control words. Finally, the phase amplitude conversion module based on the expansion of the finite orthogonal basis function system and the time-interleaved digital-to-analog converter are used for gating and conversion to form the time period signal, and then the target chirp signal is efficiently constructed from the signals of each time period.

[0125] The above design leverages the high parallelism, high synchronization, and high throughput advantages of parallel multi-channel phase control word synthesis, comprehensively improving the overall computational efficiency and signal synthesis accuracy of DDFS. This multi-core parallel generation method overcomes the speed bottleneck of single-core serial processing, achieving synchronous parallel output of multi-channel phase control words, eliminating phase timing deviations caused by time-division generation, ensuring the synchronization consistency of each channel's phase control word, and enabling superior accuracy in phase synthesis of key frequency bands. Simultaneously, it significantly improves the generation efficiency of phase control words in multiple time periods within a single cycle, reduces computational delays in complex waveform construction, and enhances the overall signal synthesis rate and reliability. Furthermore, its independent multi-core configuration and collaborative operation create a highly efficient synergistic effect with the two ratio schemes of the subsequent basis function synthesis module, more accurately adapting to the timing requirements of multi-clock systems. Combined with high-precision clock management and synchronization mechanisms, it effectively suppresses phase errors caused by single-module computational congestion.

[0126] This design scheme, without significantly increasing overall hardware resources, combines two operating modes of the subsequent basis function synthesis module and relies on the high synchronization and high throughput phase control word synthesis capability of the parallel multi-core architecture to efficiently complete the parallel generation and synchronous distribution of multi-time period and multi-channel phase control words within a single cycle. This allows the system to have better spurious-free dynamic range (SFDR) spectrum performance over a wide frequency range, while breaking through the rate bottleneck of single-core phase synthesis, improving the synchronization consistency and computational efficiency of phase generation, achieving higher signal output rate and wider Nyquist bandwidth, and adapting to the complex signal generation requirements of high-frequency and high-performance scenarios such as phased array radar.

[0127] Although specific embodiments of the present invention have been described in detail with reference to the accompanying drawings, the scope of protection of the present invention is not limited to the embodiments disclosed above. Within the scope of conventional technical knowledge possessed by those skilled in the art, various adjustments and changes can be made to the present invention as long as they do not depart from the core spirit of the present invention and the scope of protection defined by the claims.

Claims

1. A signal generation method based on a direct digital frequency synthesizer with a parallel multi-channel architecture, characterized in that, include Step A: Construct n phase control word generation channels in a predetermined order, where n is a positive integer ≥ 2; Perform a global reset to bring each channel to its initial state and set the initial value of the phase control word for each channel; Step B: Obtain the target configuration signal, and configure the start frequency control word, end frequency control word, and corresponding signal frequency change rate control word for the effective period of the chirp signal of each channel within a single cycle based on the target configuration signal. Step C: Determine the duration of the delay period, chirp signal effective period, and pause period for each channel within a single cycle based on the target configuration signal; within each cycle, experience the following in chronological order: delay period, chirp signal effective period, and pause period; at the beginning of each period, perform the following operations synchronously: Based on the signal frequency change rate control word for the corresponding time period, the frequency control word is updated by accumulating it step by step over time. The updated frequency control word is then input in parallel to each phase control word generation channel. By accumulating the frequency control word step by step over time, the phase control word of the corresponding channel is updated. Perform a phase-to-amplitude conversion on each updated phase control word, obtain the corresponding amplitude value, and output the amplitude signal. The multi-amplitude signals are time-interleaved digital-to-analog conversioned and converted into corresponding time period signals. Then, the time period signals are integrated according to the time sequence corresponding to the predetermined order of the phase control word channels to generate a single-cycle target chirped digital signal.

2. The method according to claim 1, characterized in that, Step C specifically includes: Step C1: Update the frequency control word according to the current time period type, then proceed to step C2; Step C2: Perform the following steps for the current processing time period according to the time step: Step C2-1: Based on the signal frequency change rate control word corresponding to the current time period, incrementally update the frequency control word after the current time period update, and output the frequency control word accumulation result; Step C2-2: Input the accumulated result of the frequency control word into each phase control generation channel, accumulate the frequency control word to update the phase control word, and obtain the phase control word corresponding to each channel that is logically continuous in phase. Step C2-3: Truncate the phase control word output in step C2-2 to match its bit length with the input requirements of the subsequent phase-to-amplitude conversion; perform phase-to-amplitude conversion on the truncated phase control word based on the finite orthogonal basis function system to obtain the amplitude value of the corresponding phase; Step C3: Increment the current cumulative time step by 1 and determine the current time period type: If it is a delayed time period or a paused time period, further determine whether the current cumulative time step has reached the corresponding delay duration control word or pause duration control word in the target configuration signal. If it has reached it, immediately terminate the processing flow of the current time period; if it has not reached it, proceed to the next time step and return to step C2 to continue the process. If it is a valid chirp signal period, check whether the frequency control word is consistent with the termination frequency control word of the valid period. If they are consistent, the processing flow of the period is terminated. If they are inconsistent, proceed to the next time step and return to step C2 to continue the process.

3. The method according to claim 2, characterized in that, In step C1, the frequency control word is updated according to the current time period type. Specifically, if the current time period is a delayed time period, the frequency control word is updated with the starting frequency control word of its subsequent time period. If the current time period is a pause period, then update the frequency control word with the termination frequency control word of the preceding time period; If the current time period is a valid chirp signal period, then the frequency control word is updated with the starting frequency control word of that valid time period.

4. The method according to claim 2, characterized in that, The calculation structure for the phase control word of each channel in step C2-2 includes a shifter and an adder. The specific calculation process is as follows: Each channel receives the updated frequency control word, and updates the corresponding phase control word by accumulating the frequency control word; wherein, the updated phase control word is represented as: ， The phase control word corresponding to the chirp signal is represented as follows: ， Where k is the number of accumulated cycles of the initial frequency control word. This refers to the frequency control word step size; For phase control word; This is the frequency control word.

5. A signal generation system based on a direct digital frequency synthesizer with a parallel multi-channel architecture, characterized in that, The system is used to implement the method described in any one of claims 1-4, and specifically includes a system reset module, a configuration signal receiving and processing module, a frequency control word update module, n phase control word generation channels, a phase-amplitude conversion module, and a time-interleaved digital-to-analog converter; wherein, the system reset module is communicatively connected to each of the other modules of the system and is used to perform system reset; The configuration signal receiving and processing module includes a multiplexer. The multiplexer is used to receive the linear frequency modulation signal configuration enable signal in the target configuration signal, as well as the start frequency control word and end frequency control word of each chirped signal segment, and to configure the start frequency control word, end frequency control word and signal frequency change rate control word of each chirped signal effective time period arranged sequentially in a single cycle. The frequency control word update module is used to receive the signal frequency change rate control word output by the configuration signal receiving and processing module, and update the frequency control word by accumulating it step by step according to the signal change rate control word of the corresponding time period. Each phase control word generation channel is implemented by a phase control word synthesis module. The phase control word synthesis module is used to receive the updated frequency control word output by the frequency control word update module, and accumulate it with time step to update the phase control word of the corresponding channel. The phase-to-amplitude conversion module receives the updated phase control word output by the phase control word synthesis module, converts the phase control word into the corresponding amplitude value, and outputs the amplitude signal corresponding to each channel. The time-interleaved digital-to-analog converter is used to receive the amplitude signal output from the phase-to-amplitude conversion module, and to perform gating conversion on the amplitude signal to output the target chirped digital signal.

6. The system according to claim 5, characterized in that, Each phase control word synthesis module includes a multiplexer, an adder group, and a register group. The multiplexer decomposes the multiplication term in the phase difference operation of this module into a binary shift operation. The adder group performs a step-by-step accumulation operation between the shifted output terms and the current phase control word. The register group is driven synchronously by the same clock and outputs one phase control word per clock cycle. All phase control word synthesis modules operate in parallel under the same clock drive, outputting n adjacent and phase-continuous phase control words and sending them to the phase-to-amplitude conversion module.

7. The system according to claim 5, characterized in that, The configuration signal receiving and processing module integrates a serial peripheral interface; the input of the peripheral interface is used to receive the target configuration signal from the outside, and its output is divided into two paths to complete data transmission. One path is connected to the input of the multiplexer in the configuration signal receiving and processing module, sending part of the target configuration signal data processed by the peripheral interface to the multiplexer; the other path is connected to the frequency control word update module, sending the other part of the target configuration signal data processed by the peripheral interface to the frequency control word update module.

8. The system according to claim 5, characterized in that, The phase-to-amplitude conversion module is based on a finite orthogonal basis function system and includes a quadrant mapping module, a multiplier group module, an adder group module, and a limiting module. The phase control word output from the phase control word synthesis module is input to the quadrant mapping module, where it is compressed in the quadrant. The low-order part of the phase control word is then fed into the multiplier group module and the adder group module to complete the operation and obtain an unsigned amplitude value. The unsigned amplitude value is then input to the limiting module to limit the maximum output value.

9. A direct digital frequency synthesizer based on a parallel multi-channel architecture, characterized in that, The direct digital frequency synthesizer performs the method described in any one of claims 1-4 to generate a single-cycle target chirped digital signal.

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