A clock oscillator

Abstract

The application discloses a clock oscillator. The clock oscillator comprises an oscillation core circuit and a comparison circuit, both of which are connected with a bias circuit, and the bias circuit generates a bias current. The oscillation core circuit controls a first energy storage element to charge according to a first control signal, controls the first energy storage element to discharge according to a second control signal, and outputs a first reset ramp signal according to the charging and discharging conditions of the first energy storage element. The oscillation core circuit also controls a second energy storage element to charge according to a third control signal, controls the second energy storage element to discharge according to a fourth control signal, and outputs a second reset ramp signal according to the charging and discharging conditions of the second energy storage element. The comparison circuit compares the first reset ramp signal and the second reset ramp signal to output a trigger signal. A state control circuit reverses the states of the first control signal, the second control signal, the third control signal and the fourth control signal according to the trigger signal. The technical scheme of the application improves the clock output precision while reducing the power consumption.

Description

Technical Field

[0001] This invention relates to the field of oscillator technology, and more particularly to a clock oscillator. Background Technology

[0002] Oscillators are crucial clock generation modules in sensor systems, microcontrollers, and other integrated circuits, providing clock signals for functions such as digital logic, signal acquisition, data processing, and communication control. High-speed oscillators typically generate high-precision and stable master clock signals to support the normal operation of the sensor system; low-speed oscillators, on the other hand, generate secondary clock signals, primarily serving the low-power operating mode of the circuit.

[0003] To address varying accuracy requirements for the secondary clock signal, the mainstream implementation methods are currently divided into two categories: ring oscillators and off-chip crystal oscillators. Ring oscillators offer advantages such as small size, low power consumption, and rapid start-up, but their accuracy and stability are relatively poor, thus they are mostly used in scenarios where timing accuracy requirements are not stringent. Off-chip crystal oscillators, on the other hand, offer higher frequency accuracy and better stability, but their power consumption is relatively high, their start-up time is longer, and they require external components, occupying two chip pins, which incurs additional cost and layout area overhead.

[0004] The above-mentioned technical solutions have low oscillator output accuracy and high power consumption. Summary of the Invention

[0005] This invention provides a clock oscillator that improves the clock output accuracy of the clock oscillator while reducing power consumption.

[0006] According to one aspect of the present invention, a clock oscillator is provided. The clock oscillator provided in the embodiments of the present invention includes: a bias circuit, an oscillation core circuit, a comparator circuit, and a state control circuit. The power supply terminals of the oscillation core circuit and the comparator circuit are both connected to the output terminal of the bias circuit. The bias circuit is used to generate bias current based on the power supply voltage. The oscillation core circuit has a first input terminal connected to a first control signal and a second input terminal connected to a second control signal. The oscillation core circuit is used to control the charging of the first energy storage element according to the first control signal, to control the discharging of the first energy storage element according to the second control signal, and to output a first reset ramp signal at the first output terminal based on the charging and discharging status of the first energy storage element. The oscillation core circuit also has a third input terminal connected to a third control signal and a fourth input terminal connected to the first control signal. Furthermore, the oscillation core circuit is used to control the charging of the second energy storage element according to the third control signal, to control the discharging of the second energy storage element according to the fourth control signal, and to output a second reset ramp signal at the second output terminal based on the charging and discharging status of the second energy storage element. The first reset ramp signal and the second reset ramp signal alternately reset the energy storage element. The comparator circuit has a first input terminal connected to a first reset ramp signal and a second reset ramp signal connected to a second input terminal; the comparator circuit is used to compare the magnitudes of the first reset ramp signal and the second reset ramp signal and output a trigger signal. The input terminal of the state control circuit is connected to the output terminal of the comparator circuit. It is used to invert the state of the first control signal according to the trigger signal and output it at the first output terminal, invert the state of the second control signal and output it at the second output terminal, invert the state of the third control signal and output it at the third output terminal, and invert the state of the fourth control signal and output it at the fourth output terminal.

[0007] Optionally, the oscillation core circuit includes: a first switching unit, a second switching unit, a third switching unit, a fourth switching unit, a fifth switching unit, a sixth switching unit, a seventh switching unit, an eighth switching unit, a first energy storage element, and a second energy storage element; The power supply terminal of the first switching unit is connected to the output terminal of the bias circuit, the control terminal of the first switching unit is connected to the first input terminal of the oscillation core circuit, and the output terminal of the first switching unit is connected to the first terminal of the first energy storage element. The control terminal of the second switching unit is connected to the second input terminal of the oscillation core circuit, the output terminal of the second switching unit is connected to the first terminal of the first energy storage element, and the fixed potential terminal of the second switching unit is grounded. The control terminal of the third switching unit is connected to the third input terminal of the oscillation core circuit, the input terminal of the third switching unit is connected to the output terminal of the first switching unit, and the output terminal of the third switching unit is connected to the input terminal of the fourth switching unit. The control terminal of the fourth switching unit is connected to the first input terminal of the oscillation core circuit, and the input terminal of the fourth switching unit serves as the first output terminal of the oscillation core circuit; the fixed potential terminal of the fourth switching unit is grounded through a holding capacitor. The power supply terminal of the fifth switching unit is connected to the output terminal of the bias circuit, the control terminal of the fifth switching unit is connected to the third input terminal of the oscillation core circuit, and the output terminal of the fifth switching unit is connected to the first terminal of the second energy storage element. The control terminal of the sixth switching unit is connected to the fourth input terminal of the oscillation core circuit, the output terminal of the sixth switching unit is connected to the first terminal of the second energy storage element, and the fixed potential terminal of the sixth switching unit is grounded. The control terminal of the seventh switching unit is connected to the first input terminal of the oscillation core circuit, the input terminal of the seventh switching unit is connected to the output terminal of the sixth switching unit, and the output terminal of the seventh switching unit is connected to the input terminal of the eighth switching unit. The control terminal of the eighth switching unit is connected to the third input terminal of the oscillation core circuit, and the input terminal of the eighth switching unit serves as the second output terminal of the oscillation core circuit; the fixed potential terminal of the eighth switching unit is grounded through a holding capacitor. The second terminal of the first energy storage element is grounded, and the second terminal of the second energy storage element is also grounded.

[0008] Optionally, the first switching unit includes a first transistor, the control terminal of the first transistor serves as the control terminal of the first switching unit, the first terminal of the first transistor serves as the power supply terminal of the first switching unit, and the second terminal of the first transistor serves as the output terminal of the first switching unit. The second switching unit includes a second transistor, the control terminal of the second transistor serves as the control terminal of the second switching unit, the second terminal of the second transistor serves as the output terminal of the second switching unit, and the first terminal of the second transistor serves as the fixed potential terminal of the second switching unit. The third switching unit includes a third transistor, the control terminal of the third transistor serves as the control terminal of the third switching unit, the second terminal of the third transistor serves as the input terminal of the third switching unit, and the first terminal of the third transistor serves as the output terminal of the third switching unit. The fourth switching unit includes a fourth transistor, the control terminal of the fourth transistor serves as the control terminal of the fourth switching unit, the second terminal of the fourth transistor serves as the input terminal of the fourth switching unit, and the first terminal of the fourth transistor serves as the fixed potential terminal of the fourth switching unit. The fifth switching unit includes a fifth transistor. The control terminal of the fifth transistor serves as the control terminal of the fifth switching unit, the first terminal of the fifth transistor serves as the power supply terminal of the fifth switching unit, and the second terminal of the fifth transistor serves as the output terminal of the fifth switching unit. The sixth switching unit includes a sixth transistor. The control terminal of the sixth transistor serves as the control terminal of the sixth switching unit, the second terminal of the sixth transistor serves as the output terminal of the sixth switching unit, and the first terminal of the sixth transistor serves as the fixed potential terminal of the sixth switching unit. The seventh switching unit includes a seventh transistor. The control terminal of the seventh transistor serves as the control terminal of the seventh switching unit, the second terminal of the seventh transistor serves as the input terminal of the seventh switching unit, and the first terminal of the seventh transistor serves as the output terminal of the seventh switching unit. The eighth switching unit includes an eighth transistor. The control terminal of the eighth transistor serves as the control terminal of the eighth switching unit, the second terminal of the eighth transistor serves as the input terminal of the eighth switching unit, and the first terminal of the eighth transistor serves as the fixed potential terminal of the eighth switching unit. The first energy storage element includes a first capacitor, and the second energy storage element includes a second capacitor.

[0009] Optionally, the first transistor and the fifth transistor have the same channel type; the second transistor, the third transistor, the fourth transistor, the sixth transistor, the seventh transistor, and the eighth transistor have the same channel type; the first transistor and the second transistor have different channel types. The first control signal and the second control signal are in phase, the third control signal and the fourth control signal are in phase, and the first control signal and the third control signal are out of phase.

[0010] Optionally, the comparator circuit includes: a differential comparator unit and a ninth switch unit; The first input terminal of the differential comparator unit is the first input terminal of the comparator circuit, and the second input terminal of the differential comparator unit is the second input terminal of the comparator circuit; the power supply terminal of the differential comparator circuit is used as the power supply terminal of the comparator circuit, and the fixed potential terminal of the differential comparator circuit is grounded; the differential comparator circuit is used to compare the first reset ramp signal and the second reset ramp signal and output a comparison signal. The input terminal of the ninth switching unit is connected to the output terminal of the differential comparator unit, the power supply terminal of the ninth switching unit is connected to the bias circuit, and the power supply terminal of the ninth switching unit serves as the output terminal of the comparator circuit; the fixed potential terminal of the ninth switching unit is grounded; the ninth switching unit is used to turn on or off according to the comparison signal, and when it is on, it connects the output terminal of the comparator circuit to ground; the on or off state change of the ninth switching unit outputs a trigger signal.

[0011] Optionally, the differential comparator circuit includes a ninth transistor, a tenth transistor, a first current mirror, and a second current mirror; The first terminals of the ninth transistor and the tenth transistor are both connected to the power supply terminal of the differential comparator circuit. The control terminal of the ninth transistor is connected to the first input terminal of the differential comparator circuit, and the control terminal of the tenth transistor is connected to the second input terminal of the differential comparator circuit. The input terminal of the first current mirror and the output terminal of the second current mirror are both connected to the second terminal of the ninth transistor; the input terminal of the second current mirror and the output terminal of the first current mirror are both connected to the second terminal of the tenth transistor; the first current mirror and the second current mirror are grounded; the input terminal of the second current mirror is the output terminal of the differential comparator circuit.

[0012] Optionally, the ninth switching unit includes an eleventh transistor; The first terminal of the eleventh transistor is connected to the fixed potential terminal of the ninth switching unit, the control terminal of the eleventh transistor is connected to the input terminal of the ninth switching unit, and the second terminal of the eleventh transistor is connected to the power supply terminal of the ninth switching unit.

[0013] Optionally, the bias circuit includes: a positive temperature current generating circuit, a negative temperature current generating circuit, and an output circuit; The power supply terminal of the positive temperature coefficient current generating circuit is connected to the power supply voltage to generate positive temperature coefficient current. The power supply terminal of the negative temperature coefficient current generating circuit is connected to the power supply voltage to generate positive temperature coefficient current. The first input terminal of the output circuit is connected to the output terminal of the positive temperature coefficient current generating circuit, and the second input terminal of the output circuit is connected to the output terminal of the negative temperature coefficient current generating circuit. The output circuit is used to combine the positive temperature coefficient current and the negative temperature coefficient current to output the bias current.

[0014] Optionally, the positive temperature current generating circuit includes: a twelfth transistor, a thirteenth transistor, a fourteenth transistor, a fifteenth transistor, a sixteenth transistor, a seventeenth transistor, and a first resistor; The first terminals of the twelfth and thirteenth transistors are both connected to the power supply voltage. The control terminals of the twelfth and thirteenth transistors are connected together, and the control terminals of the thirteenth transistor and its second terminal are shared. The second terminal of the fourteenth transistor is connected to the second terminal of the twelfth transistor. The second terminal of the fifteenth transistor is connected to the second terminal of the thirteenth transistor. The control terminals of the fourteenth and fifteenth transistors are connected together, and the control terminals of the fourteenth transistor and its second terminal are shared. The first terminal of the sixteenth transistor is connected to the first terminal of the fourteenth transistor. The first terminal of the seventeenth transistor is connected to the first terminal of the fifteenth transistor through a first resistor. The control terminals of the sixteenth and seventeenth transistors are shared, and the second terminals of the sixteenth and seventeenth transistors are both grounded. The negative temperature current generating circuit includes: the eighteenth transistor, the nineteenth transistor, and the second resistor; The first terminal of the eighteenth transistor is connected to the power supply voltage, and the control terminal and the second terminal of the eighteenth transistor are connected together; the control terminal of the nineteenth transistor is connected to the control terminal of the fifteenth transistor, the first terminal of the nineteenth transistor is grounded through the second resistor, and the second terminal of the nineteenth transistor is connected to the second terminal of the eighteenth transistor. The output circuit includes: the twentieth transistor and the twenty-first transistor; The first terminal of the 20th transistor and the first terminal of the 21st transistor are both connected to the power supply voltage. The control terminal of the 20th transistor is connected to the second terminal of the 13th transistor to replicate the positive temperature coefficient current. The control terminal of the 21st transistor is connected to the second terminal of the 18th transistor to replicate the negative temperature coefficient current. The node where the second terminals of the 20th and 21st transistors are connected serves as the output terminal of the bias circuit.

[0015] Optionally, the state control circuit includes: First inverting unit, second inverting unit, third inverting unit, fourth inverting unit, first NAND gate, and second NAND gate; The input terminal of the first inverter unit serves as the input terminal of the state control circuit; the output terminal of the first inverter unit is connected to the first input terminal of the first NAND gate, the output terminal of the second NAND gate is connected to the second input terminal of the first NAND gate, and the output terminal of the first NAND gate is connected to the input terminal of the second inverter unit. The output of the first inverter unit is also connected to the input of the third inverter unit. The output of the third inverter unit is connected to the first input of the second NAND gate. The output of the first NAND gate is connected to the second input of the second NAND gate. The output of the second NAND gate is connected to the input of the fourth inverter unit. The output of the second NAND gate serves as the first output of the state control circuit, and the output of the second inverting unit serves as the second output of the state control circuit; the output of the first NAND gate serves as the third output of the state control circuit, and the output of the fourth inverting unit serves as the fourth output of the state control circuit.

[0016] The technical solution of this invention generates a bias current with a positive or negative temperature coefficient through a bias circuit, which can compensate for the temperature drift generated by the oscillation core circuit and the comparator circuit. This allows the first level of the first reset ramp signal and the second reset ramp signal to remain stable at different temperatures, thereby reducing the deviation of the oscillation frequency and improving the clock accuracy of the clock oscillator output. Simultaneously, the first and second reset ramp signals output by the oscillation core circuit have a high-level holding phase. When the first reset ramp signal is held at the first level, it can provide a comparison threshold for the comparator circuit, and output a trigger signal when the voltage of the second reset ramp signal reaches the first level. Alternatively, when the second reset ramp signal is held at the first level, it can provide a comparison threshold for the comparator circuit, and output a trigger signal when the voltage of the first reset ramp signal reaches the first level. Compared to traditional oscillators, there is no need to add an additional bandgap reference circuit to provide a comparison threshold for the comparator circuit, thus reducing the power consumption of the clock oscillator.

[0017] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1A schematic diagram of a clock oscillator provided in an embodiment of the present invention; Figure 2 A waveform diagram of a first reset ramp signal and a second reset ramp signal provided in an embodiment of the present invention; Figure 3 A circuit structure diagram of a state control circuit provided in an embodiment of the present invention; Figure 4 A circuit structure diagram of an oscillation core circuit provided in an embodiment of the present invention; Figure 5 A circuit structure diagram of a comparison circuit provided in an embodiment of the present invention; Figure 6 A circuit structure diagram of a bias circuit provided in an embodiment of the present invention; Figure 7 This is a circuit diagram of a clock oscillator provided in an embodiment of the present invention. Detailed Implementation

[0020] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0021] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0022] Figure 1 This is a schematic diagram of a clock oscillator provided as an embodiment of the present invention. The present invention is applicable to scenarios requiring accurate and reliable clock signals, such as providing accurate and reliable clock signals for sensor systems. Figure 1 As shown, the clock oscillator provided in this embodiment of the invention includes: a bias circuit 10, an oscillation core circuit 20, a comparator circuit 30, and a state control circuit 40.

[0023] The power supply terminals of the oscillation core circuit 20 and the comparator circuit 30 are both connected to the output terminal of the bias circuit 10. The bias circuit 10 generates a bias current based on the power supply voltage. The first input terminal of the oscillation core circuit 20 receives a first control signal, and the second input terminal receives a second control signal. The oscillation core circuit 20 controls the charging of the first energy storage element according to the first control signal, controls the discharging of the first energy storage element according to the second control signal, and outputs a first reset ramp signal at the first output terminal based on the charging and discharging status of the first energy storage element. The third input terminal of the oscillation core circuit 20 receives a third control signal, and the fourth input terminal receives a first control signal. The oscillation core circuit 20 also controls the charging of the second energy storage element according to the third control signal, controls the discharging of the second energy storage element according to the fourth control signal, and outputs a second reset ramp signal at the second output terminal based on the charging and discharging status of the second energy storage element. The first reset ramp signal and the second reset ramp signal alternately reset. The first input terminal of the comparator circuit 30 receives the first reset ramp signal, and the second input terminal receives the second reset ramp signal. The comparator circuit 30 compares the magnitudes of the first reset ramp signal and the second reset ramp signal and outputs a trigger signal. The input terminal of the state control circuit 40 is connected to the output terminal of the comparator circuit 30. It is used to invert the state of the first control signal according to the trigger signal and output it at the first output terminal, invert the state of the second control signal and output it at the second output terminal, invert the state of the third control signal and output it at the third output terminal, and invert the state of the fourth control signal and output it at the fourth output terminal.

[0024] According to the technical solution of the present invention, the bias circuit 10 can be connected to the power supply voltage, and the bias circuit 10 can generate a bias current with a positive temperature coefficient or a negative temperature coefficient according to the power supply voltage. The bias current is output to the oscillation core circuit 20 and the comparator circuit 30.

[0025] The first control signal and the second control signal can be high-level or low-level signals output by the state control circuit 40. For example, the first control signal can be a high-level signal or a low-level signal; the second control signal can be a low-level signal or a high-level signal. The oscillation core circuit 20 can include a first energy storage element and a second energy storage element. When the first energy storage element injects bias current and its stored energy increases, it is considered to be charging; when the first energy storage element releases the stored energy, it is considered to be discharging.

[0026] The first reset ramp signal includes a ramp rise phase, a high-level hold phase, and a rapid fall phase. When the first energy storage element is charging, the first reset ramp signal is in the ramp rise phase; when the second energy storage element is charging and the first energy storage element is discharging, the first reset ramp signal is in the high-level hold phase; when the first energy storage element has finished discharging, the first reset ramp signal is in the rapid fall phase. Similarly, the injection of bias current into the second energy storage element and the increase in stored energy are considered charging; the release of stored energy by the second energy storage element is considered discharging. The second reset ramp signal includes a ramp rise phase, a high-level hold phase, and a rapid fall phase. When the second energy storage element is charging, the second reset ramp signal is in the ramp rise phase; when the first energy storage element is charging and the second energy storage element is discharging, the second reset ramp signal is in the high-level hold phase; when the second energy storage element has finished discharging, the second reset ramp signal is in the rapid fall phase.

[0027] For example, Figure 2 Waveform diagrams of a first reset ramp signal and a second reset ramp signal provided for embodiments of the present invention. (Refer to...) Figure 2 The first reset ramp signal VON is in a high-level holding phase during the t1-t2 period, for example, maintaining a first level, which can be a high-level signal. At time t2, the first reset ramp signal VON is in a rapidly decreasing phase, for example, decreasing to a second level, which can be a low-level signal. During the t2-t3 period, the first reset ramp signal VON is in a ramp-rising phase, gradually increasing from a second level to a first level. The second reset ramp signal VOP is in a ramp-rising phase during the t1-t2 period, gradually increasing from a second level to a first level. At time t2, the second reset ramp signal VOP is in a high-level holding phase, maintaining a first level. During the t2-t3 period, the second reset ramp signal VOP is in a rapidly decreasing phase, decreasing to a second level.

[0028] The alternating reset of the first reset ramp signal VON and the second reset ramp signal VOP can be understood as follows: when the second reset ramp signal VOP is in the ramp-up phase, the first reset ramp signal VON is in the high-level holding phase; when the second reset ramp signal VOP rises to the first level, the first reset ramp signal VON will quickly fall to reset. Conversely, when the first reset ramp signal VON is in the ramp-up phase, the second reset ramp signal VOP is in the high-level holding phase; when the first reset ramp signal VON rises to the first level, the second reset ramp signal VOP will quickly fall to reset.

[0029] The comparator circuit 30 can output a trigger signal based on the relative voltage magnitudes of the first reset ramp signal VON and the second reset ramp signal VOP. For example, when the first reset ramp signal VON is in a high-level holding phase, the comparator circuit 30 outputs a trigger signal the instant the voltage of the second reset ramp signal VOP rises to the first level. Alternatively, when the second reset ramp signal VOP is in a high-level holding phase, the comparator circuit 30 outputs a trigger signal the instant the voltage of the first reset ramp signal VON rises to the first level.

[0030] The state control circuit 40 can reverse the states of the first, second, third, and fourth control signals based on the trigger signal. For example, before the comparator circuit 30 outputs the trigger signal to the state control circuit 40, the first control signal is a high-level signal, the second control signal is a low-level signal, the third control signal is a low-level signal, and the fourth control signal is a high-level signal; after the comparator circuit 30 outputs the trigger signal to the state control circuit 40, the state control circuit 40 outputs the first control signal as a low-level signal, the second control signal as a high-level signal, the third control signal as a high-level signal, and the fourth control signal as a low-level signal.

[0031] Specifically, the state control circuit 40 outputs a first control signal, a second control signal, a third control signal, and a fourth control signal to the oscillation core circuit 20. The bias circuit 10 generates a bias current with a positive or negative temperature coefficient to the oscillation core circuit 20 and the comparator circuit 30. The oscillation core circuit 20 controls the charging or discharging of the first energy storage element according to the first and second control signals, and outputs a first reset ramp signal VON to the comparator circuit 30. Simultaneously, the oscillation core circuit 20 controls the charging or discharging of the second energy storage element according to the third and fourth control signals, and outputs a second reset ramp signal VOP to the comparator circuit 30. The comparator circuit 30 outputs a trigger signal based on the relative voltage magnitudes of the first reset ramp signal VON and the second reset ramp signal VOP. The state control circuit 40 reverses the states of the first, second, third, and fourth control signals according to the trigger signal. Then, the clock oscillator enters the next oscillation cycle.

[0032] According to the technical solution of this invention, by generating a bias current with a positive or negative temperature coefficient through a bias circuit, the temperature drift generated by the oscillation core circuit and the comparator circuit can be compensated. This allows the first level of the first reset ramp signal and the second reset ramp signal to remain stable at different temperatures, thereby reducing the deviation of the oscillation frequency and improving the clock accuracy of the clock oscillator output. Simultaneously, the first reset ramp signal and the second reset ramp signal output by the oscillation core circuit have a high-level holding phase. When the first reset ramp signal is held at the first level, a comparison threshold can be provided to the comparator circuit, and a trigger signal is output when the voltage of the second reset ramp signal reaches the first level. Alternatively, when the second reset ramp signal is held at the first level, a comparison threshold can be provided to the comparator circuit, and a trigger signal is output when the voltage of the first reset ramp signal reaches the first level. Compared to conventional oscillators, there is no need to add an additional bandgap reference circuit to provide a comparison threshold for the comparator circuit, thus reducing the power consumption of the clock oscillator.

[0033] In some embodiments, the oscillation core circuit includes: a first switching unit, a second switching unit, a third switching unit, a fourth switching unit, a fifth switching unit, a sixth switching unit, a seventh switching unit, an eighth switching unit, a first energy storage element, and a second energy storage element.

[0034] The power supply terminal of the first switching unit is connected to the output terminal of the bias circuit, the control terminal of the first switching unit is connected to the first input terminal of the oscillation core circuit, and the output terminal of the first switching unit is connected to the first terminal of the first energy storage element. The control terminal of the second switching unit is connected to the second input terminal of the oscillation core circuit, the output terminal of the second switching unit is connected to the first terminal of the first energy storage element, and the fixed potential terminal of the second switching unit is grounded. The control terminal of the third switching unit is connected to the third input terminal of the oscillation core circuit, the input terminal of the third switching unit is connected to the output terminal of the first switching unit, and the output terminal of the third switching unit is connected to the input terminal of the fourth switching unit. The control terminal of the fourth switching unit is connected to the first input terminal of the oscillation core circuit, and the input terminal of the fourth switching unit serves as the first output terminal of the oscillation core circuit; the fixed potential terminal of the fourth switching unit is grounded through a holding capacitor. The power supply terminal of the fifth switching unit is connected to the output terminal of the bias circuit, the control terminal of the fifth switching unit is connected to the third input terminal of the oscillation core circuit, and the output terminal of the fifth switching unit is connected to the first terminal of the second energy storage element. The control terminal of the sixth switching unit is connected to the fourth input terminal of the oscillation core circuit, the output terminal of the sixth switching unit is connected to the first terminal of the second energy storage element, and the fixed potential terminal of the sixth switching unit is grounded. The control terminal of the seventh switching unit is connected to the first input terminal of the oscillation core circuit. The input terminal of the seventh switching unit is connected to the output terminal of the sixth switching unit, and the output terminal of the seventh switching unit is connected to the input terminal of the eighth switching unit. The control terminal of the eighth switching unit is connected to the third input terminal of the oscillation core circuit, and the input terminal of the eighth switching unit serves as the second output terminal of the oscillation core circuit. The fixed potential terminal of the eighth switching unit is grounded through a holding capacitor. The second terminal of the first energy storage element is grounded, and the second terminal of the second energy storage element is grounded.

[0035] The system can be configured such that: The first switching unit can be turned on or off according to a first control signal; when on, it connects the first terminal of the first energy storage element to the power supply voltage of the bias circuit, injecting bias current into the first energy storage element and charging it. The second switching unit can be turned on or off according to a second control signal; when on, it connects the first terminal of the first energy storage element to ground, discharging it. The third switching unit can be turned on or off according to a third control signal; when on, it connects the output terminal of the first switching unit to the input terminal of the fourth switching unit. While the first energy storage element is charging, the voltage at the input terminal of the fourth switching unit gradually increases as the voltage at the first terminal of the first energy storage element rises, until it reaches a first level. When the third switching unit is off, the voltage at the input terminal of the fourth switching unit remains constant. The fourth switching unit can be turned on or off according to a first control signal; when on, it connects the first output terminal of the oscillation core circuit to a holding capacitor, maintaining the voltage at the input terminal of the fourth switching unit at the first level. The fifth switching unit can be turned on or off according to the third control signal. When on, it connects the first terminal of the second energy storage element to the power supply voltage of the bias circuit, injecting bias current into the second energy storage element and charging it. The sixth switching unit can be turned on or off according to the fourth control signal. When on, it connects the first terminal of the second energy storage element to ground, discharging it. The seventh switching unit can be turned on or off according to the first control signal. When on, it connects the output terminal of the sixth switching unit to the input terminal of the eighth switching unit. When the second energy storage element is charging, the voltage at the input terminal of the eighth switching unit gradually increases as the voltage at the first terminal of the second energy storage element increases, until it reaches the first level. When the seventh switching unit is off, the voltage at the input terminal of the eighth switching unit remains constant. The eighth switching unit can be turned on or off according to the third control signal. When on, it connects the second output terminal of the oscillation core circuit to the holding capacitor, maintaining the voltage at the input terminal of the eighth switching unit at the first level.

[0036] The third switching unit can act as an isolation buffer, isolating the voltage at the first terminal of the first energy storage element from the voltage at the first output terminal of the oscillation core circuit. The seventh switching unit can also act as an isolation buffer, isolating the voltage at the first terminal of the second energy storage element from the voltage at the second output terminal of the oscillation core circuit.

[0037] Figure 3 This is a circuit structure diagram of a state control circuit provided in an embodiment of the present invention. Figure 3As shown, in some embodiments, the state control circuit 40 includes: a first inverter unit U1, a second inverter unit U2, a third inverter unit U3, a fourth inverter unit U4, a first NAND gate D1, and a second NAND gate D2. The input terminal of the first inverter unit U1 serves as the input terminal of the state control circuit 40. The output terminal of the first inverter unit U1 is connected to the first input terminal of the first NAND gate D1. The output terminal of the second NAND gate D2 is connected to the second input terminal of the first NAND gate D1, and the output terminal of the first NAND gate D1 is connected to the input terminal of the second inverter unit U2. The output terminal of the first inverter unit U1 is also connected to the input terminal of the third inverter unit U3. The output terminal of the third inverter unit U3 is connected to the first input terminal of the second NAND gate D2. The output terminal of the first NAND gate D1 is connected to the second input terminal of the second NAND gate D2, and the output terminal of the second NAND gate D2 is connected to the input terminal of the fourth inverter unit U4. The output of the second NAND gate D2 serves as the first output of the state control circuit 40, the output of the second inverter U2 serves as the second output of the state control circuit 40, the output of the first NAND gate D1 serves as the third output of the state control circuit 40, and the output of the fourth inverter U4 serves as the fourth output of the state control circuit 40.

[0038] For example, when the signal V5 at the input terminal of the state control circuit 40 is a high-level signal, the signal V6 output by the first inverting unit U1 is a low-level signal, and the signal at the output terminal of the third inverting unit U3 is... The signal is high. After passing through the first NAND gate D1 and the second NAND gate D2, the first control signal SA output from the second NAND gate D2 is a low-level signal, and the third control signal SB output from the first NAND gate D1 is a high-level signal. The second control signal VB output from the second inverter unit U2 is a low-level signal, and the fourth control signal VA output from the fourth inverter unit U4 is a high-level signal. When the signal V5 at the input terminal of the state control circuit 40 is a low-level signal, the signal V6 output from the first inverter unit U1 is a high-level signal, and the signal V6 output from the third inverter unit U3 is a high-level signal. The signal is at a low level. After passing through the first NAND gate D1 and the second NAND gate D2, the first control signal SA output from the second NAND gate D2 is a high-level signal, and the third control signal SB output from the first NAND gate D1 is a low-level signal. The second control signal VB output from the second inverter unit U2 is a high-level signal, and the fourth control signal VA output from the fourth inverter unit U4 is a low-level signal.

[0039] It is understandable that the first output terminal of the state control circuit 40 can be used as the output terminal of the clock oscillator. The clock signal output from the first output terminal of the state control circuit 40 is divided into four by two flip-flops, and then filtered out by one clock by the clock gate circuit module, and then a stable clock is output.

[0040] Figure 4 This is a circuit structure diagram of an oscillation core circuit provided in an embodiment of the present invention. (See diagram below.) Figure 4 As shown, in some embodiments, the first switching unit includes a first transistor MP1, the control terminal of the first transistor MP1 serves as the control terminal of the first switching unit, the first terminal of the first transistor MP1 serves as the power supply terminal of the first switching unit, and the second terminal of the first transistor MP1 serves as the output terminal of the first switching unit. The second switching unit includes a second transistor MN1, the control terminal of the second transistor MN1 serves as the control terminal of the second switching unit, the second terminal of the second transistor MN1 serves as the output terminal of the second switching unit, and the first terminal of the second transistor MN1 serves as the fixed potential terminal of the second switching unit. The third switching unit includes a third transistor MN2, the control terminal of the third transistor MN2 serves as the control terminal of the third switching unit, the second terminal of the third transistor MN2 serves as the input terminal of the third switching unit, and the first terminal of the third transistor MN2 serves as the output terminal of the third switching unit. The fourth switching unit includes a fourth transistor MN3, the control terminal of the fourth transistor MN3 serves as the control terminal of the fourth switching unit, the second terminal of the fourth transistor MN3 serves as the input terminal of the fourth switching unit, and the first terminal of the fourth transistor MN3 serves as the fixed potential terminal of the fourth switching unit. The fifth switching unit includes a fifth transistor MP2. The control terminal of the fifth transistor MP2 serves as the control terminal of the fifth switching unit, the first terminal of the fifth transistor MP2 serves as the power supply terminal of the fifth switching unit, and the second terminal of the fifth transistor MP2 serves as the output terminal of the fifth switching unit. The sixth switching unit includes a sixth transistor MN4. The control terminal of the sixth transistor MN4 serves as the control terminal of the sixth switching unit, the second terminal of the sixth transistor MN4 serves as the output terminal of the sixth switching unit, and the first terminal of the sixth transistor MN4 serves as the fixed potential terminal of the sixth switching unit. The seventh switching unit includes a seventh transistor MN5. The control terminal of the seventh transistor MN5 serves as the control terminal of the seventh switching unit, the second terminal of the seventh transistor MN5 serves as the input terminal of the seventh switching unit, and the first terminal of the seventh transistor MN5 serves as the output terminal of the seventh switching unit. The eighth switching unit includes an eighth transistor MN6. The control terminal of the eighth transistor MN6 serves as the control terminal of the eighth switching unit, the second terminal of the eighth transistor MN6 serves as the input terminal of the eighth switching unit, and the first terminal of the eighth transistor MN6 serves as the fixed potential terminal of the eighth switching unit. The first energy storage element includes a first capacitor C1, and the second energy storage element includes a second capacitor C2.

[0041] Wherein, the first transistor MP1 and the fifth transistor MP2 can be P-type MOS transistors, the first terminal of the first transistor MP1 and the first terminal of the fifth transistor MP2 are the sources of the P-type MOS transistors; the second terminal of the first transistor MP1 and the second terminal of the fifth transistor MP2 are the drains of the P-type MOS transistors; the control terminal of the first transistor MP1 and the control terminal of the fifth transistor MP2 are the gates of the P-type MOS transistors.

[0042] The second transistor MN1, the third transistor MN2, the fourth transistor MN3, the sixth transistor MN4, the seventh transistor MN5, and the eighth transistor MN6 can be N-type MOSFETs. The first terminal of the second transistor MN1, the first terminal of the third transistor MN2, the first terminal of the fourth transistor MN3, the first terminal of the sixth transistor MN4, the first terminal of the seventh transistor MN5, and the first terminal of the eighth transistor MN6 can be the source of the N-type MOSFET; the second terminal of the second transistor MN1, the second terminal of the third transistor MN2, the second terminal of the fourth transistor MN3, the second terminal of the sixth transistor MN4, the second terminal of the seventh transistor MN5, and the second terminal of the eighth transistor MN6 can be the drain of the N-type MOSFET; the control terminal of the second transistor MN1, the control terminal of the third transistor MN2, the control terminal of the fourth transistor MN3, the control terminal of the sixth transistor MN4, the control terminal of the seventh transistor MN5, and the control terminal of the eighth transistor MN6 can be the gate of the N-type MOSFET.

[0043] For example, the first terminal of the first transistor MP1 and the first terminal of the fifth transistor MP2 are both connected to a bias current Iref. When the first control signal SA is low, the second control signal VB is low, the third control signal SB is high, and the fourth control signal VA is high: the first transistor MP1 is turned on, the second transistor MN1 is turned off, and the first capacitor C1 is charged. The third transistor MN2 is turned on, the fourth transistor MN3 is turned off, and the voltage of the first recovery ramp signal VON output by the oscillation core circuit 20 can be the voltage at the connection between the second terminal of the fourth transistor MN3 and the first terminal of the third transistor MN2. As the first capacitor C1 charges, the node voltage V1 at the connection between the first terminal of the first capacitor C1 and the first transistor MP1 gradually increases, and then the voltage at the first terminal of the third transistor MN2 also gradually increases. The node voltage V1 at the connection between the first terminal of the first capacitor C1 and the first transistor MP1 eventually rises to the first level VH, for example, the first level VH can be VH = VDD - VGS. Wherein, VDD can be the power supply voltage connected to the bias circuit, and VGS can be the threshold voltage at which the first transistor MP1 is turned on. The fifth transistor MP2 is turned off, and the sixth transistor MN4 is turned on, at which time the second capacitor C2 discharges. The seventh transistor MN5 is turned off, and the eighth transistor MN6 is turned on. The voltage of the second recovery ramp signal VOP output by the oscillation core circuit 20 can be the node voltage at the connection between the first terminal of the seventh transistor MN5 and the second terminal of the eighth transistor MN6. Since the first terminal of the eighth transistor MN6 is connected to the holding capacitor C3, the voltage at the second terminal of the eighth transistor MN6 is not directly discharged, but is held at the first level VH. When the second capacitor C2 has finished discharging, the voltage at the first terminal of the second capacitor C2 is zero. When the second capacitor C2 starts charging in the next cycle, the voltage at the second terminal of the eighth transistor MN6 is pulled down to the second level by the voltage at the first terminal of the second capacitor C2, so the second recovery ramp signal VOP gradually increases from the second level in the next cycle. The second level VL can be 0.

[0044] When the first control signal SA is high, the second control signal VB is high, the third control signal SB is low, and the fourth control signal VA is low: The first transistor MP1 is off, the second transistor MN1 is on, and the first capacitor C1 discharges. The third transistor MN2 is off, and the fourth transistor MN3 is on. Since the first terminal of the fourth transistor MN3 is connected to the holding capacitor C3, the voltage at the second terminal of the fourth transistor MN3 is not directly discharged but is held at the first level VH. The fifth transistor MP2 is on, and the sixth transistor MN4 is off, and the second capacitor C2 charges. The seventh transistor MN5 is on, and the eighth transistor MN6 is off. As the second capacitor C2 charges, the node voltage V2 at the connection between the first terminal of the second capacitor C2 and the fifth transistor MP2 gradually increases, and consequently, the voltage at the first terminal of the seventh transistor MN5 also gradually increases. The node voltage V2 at the connection between the first terminal of the second capacitor C2 and the fifth transistor MP2 eventually rises to the first level VH, for example, the first level VH can be VH = VDD - VGS. Where VDD can be the power supply voltage connected to the bias circuit, and VGS can be the threshold voltage at which the fifth transistor MP2 turns on. When the first capacitor C1 has finished discharging, the voltage at the first terminal of the first capacitor C1 is zero. When the first capacitor C1 begins to charge in the next cycle, the voltage at the second terminal of the second transistor MN1 is pulled down to the second level by the voltage at the first terminal of the first capacitor C1, and thus the first recovery ramp signal VON gradually increases from the second level in the next cycle.

[0045] The comparator circuit in this embodiment of the invention maintains the voltage at the second terminal of the fourth transistor MN3 at a first level using holding capacitor C3, and also maintains the voltage at the second terminal of the eighth transistor MN6 at a first level using holding capacitor C3. Compared to conventional comparator circuits, no bandgap reference circuit is required to provide a comparison threshold, thus reducing the power consumption of the clock oscillator.

[0046] Continue to refer to Figure 4 In some embodiments, the first transistor MP1 and the fifth transistor MP5 have the same channel type, and the second transistor MN1, the third transistor MN2, the fourth transistor MN3, the sixth transistor MN4, the seventh transistor MN4, and the eighth transistor MN5 have the same channel type; the first transistor MP1 and the second transistor MN1 have different channel types. The first control signal and the second control signal are in phase, the third control signal and the fourth control signal are in phase, and the first control signal and the third control signal are out of phase.

[0047] By employing first transistor MP1 and fifth transistor MP5 with the same channel type, it can be ensured that the first and second energy storage elements are charged respectively after receiving control signals of opposite phase. By sampling first transistor MP1 and second transistor MN1 with different channel types, it is possible to control the charging or discharging of the first energy storage element after receiving control signals of the same phase. By sampling fifth transistor MP2 and sixth transistor MN4 with different channel types, it is possible to control the charging or discharging of the second energy storage element after receiving control signals of the same phase.

[0048] Figure 5 This is a circuit structure diagram of a comparison circuit provided in an embodiment of the present invention. For example... Figure 5 As shown, in some embodiments, the comparison circuit 30 includes a differential comparison unit 31 and a ninth switch unit 32. The first input terminal of the differential comparison unit 31 is the first input terminal of the comparison circuit 30, the second input terminal of the differential comparison unit 31 is the second input terminal of the comparison circuit 30, the power supply terminal of the differential comparison circuit 31 serves as the power supply terminal of the comparison circuit 30, and the fixed potential terminal of the differential comparison circuit 31 is grounded. The differential comparison circuit 31 is used to compare a first reset ramp signal and a second reset ramp signal and output a comparison signal. The input terminal of the ninth switch unit 32 is connected to the output terminal of the differential comparison unit 31, the power supply terminal of the ninth switch unit 32 is connected to a bias circuit, the power supply terminal of the ninth switch unit 32 serves as the output terminal of the comparison circuit 30, and the fixed potential terminal of the ninth switch unit 32 is grounded. The ninth switch unit 32 is used to turn on or off according to the comparison signal, and when on, connects the output terminal of the comparison circuit 30 to ground; the on / off state change of the ninth switch unit 32 outputs a trigger signal.

[0049] For example, continue to refer to Figure 2 During the t1-t2 phase, the voltage of the first reset ramp signal VON is at the first level, which is higher than the voltage of the second reset ramp signal VOP. The differential comparator circuit 31 outputs the first comparison signal. At time t2, the voltage of the second reset ramp signal VOP reaches the first level, and the differential comparator circuit 31 outputs the second comparison signal. During the t2-t3 phase, the voltage of the second reset ramp signal VOP is at the first level, which is higher than the voltage of the first reset ramp signal VON. The differential comparator circuit 31 outputs the third comparison signal. At time t3, the voltage of the first reset ramp signal VON reaches the first level, and the differential comparator circuit 31 outputs the fourth comparison signal. When the first comparison signal switches to the second comparison signal, the ninth switch unit 32 outputs a trigger signal; or, when the third comparison signal switches to the fourth comparison signal, the ninth switch unit 32 outputs a trigger signal.

[0050] In some embodiments, the differential comparator circuit 31 includes a ninth transistor MP3, a tenth transistor MP4, a first current mirror, and a second current mirror. The first terminals of both the ninth transistor MP3 and the tenth transistor MP4 are connected to the power supply terminal of the differential comparator circuit 31. The control terminal of the ninth transistor MP3 is connected to the first input terminal of the differential comparator circuit 31, and the control terminal of the tenth transistor MP4 is connected to the second input terminal of the differential comparator circuit 31. The input terminal of the first current mirror and the output terminal of the second current mirror are both connected to the second terminal of the ninth transistor MP3, and the input terminal of the second current mirror and the output terminal of the first current mirror are both connected to the second terminal of the tenth transistor MP4. The first and second current mirrors are grounded, and the input terminal of the second current mirror is the output terminal of the differential comparator circuit 31.

[0051] Continue to refer to Figure 5 In this configuration, the ninth transistor MP3 and the tenth transistor MP4 can be P-type MOS transistors. The first terminal of the ninth transistor MP3 and the first terminal of the tenth transistor MP4 can be the source of the P-type MOS transistor. The second terminal of the ninth transistor MP3 and the second terminal of the tenth transistor MP4 can be the drain of the P-type MOS transistor. The control terminal of the ninth transistor MP3 and the control terminal of the tenth transistor MP4 can be the gate of the P-type MOS transistor.

[0052] The first current mirror may include N-type MOSFETs MN7 and MN8. The drain of MOSFET MN7 serves as the input terminal of the first current mirror, and the drain of MOSFET MN8 serves as the output terminal. The gates of MOSFETs MN7 and MN8 are connected, as are their gates and drains. The sources of MOSFETs MN7 and MN8 are grounded. The second current mirror may include N-type MOSFETs MN9 and MN10. The drain of MOSFET MN9 serves as the output terminal of the second current mirror, and the drain of MOSFET MN10 serves as its input terminal. The gates of MOSFETs MN9 and MN10 are connected, as are their gates and drains. The sources of MOSFETs MN9 and MN10 are grounded.

[0053] For example, during the t1-t2 phase, the voltage of the first reset ramp signal VON is at a first level, and the voltage of the second reset ramp signal VOP gradually increases from the second level. At this time, the ninth transistor MP3 is off, the tenth transistor MP4 is on, and the node voltage V3 at the connection between the second terminal of the ninth transistor MP3 and the input terminal of the first current mirror can be low, while the node voltage V4 at the connection between the second terminal of the tenth transistor MP4 and the input terminal of the second current mirror can be high. The first comparison signal output by the differential comparator circuit 31 can be a high-level signal. At time t2, the voltage of the first reset ramp signal VON drops to the second level, and the voltage of the second reset ramp signal VOP reaches the first level. At this time, the ninth transistor MP3 is on, and the tenth transistor MP4 is off. The node voltage V3 at the connection between the second terminal of the ninth transistor MP3 and the input terminal of the first current mirror can be high, while the node voltage V4 at the connection between the second terminal of the tenth transistor MP4 and the input terminal of the second current mirror can be low. The second comparison signal output by the differential comparator circuit 31 can be a low-level signal. During the t2-t3 phase, the voltage of the second reset ramp signal VOP is at the first level, and the voltage of the first reset ramp signal VON gradually rises from the second level. At this time, the ninth transistor MP3 is turned on, and the tenth transistor MP4 is turned off. The node voltage V3 at the connection between the second terminal of the ninth transistor MP3 and the input terminal of the first current mirror can be high, and the node voltage V4 at the connection between the second terminal of the tenth transistor MP4 and the input terminal of the second current mirror can be low. The third comparison signal output by the differential comparator circuit 31 can be a low-level signal. At time t3, the voltage of the second reset ramp signal VOP drops to the second level. The voltage of the first reset ramp signal VON reaches the first level. At this time, the ninth transistor MP3 is turned off, and the tenth transistor MP4 is turned on. The node voltage V3 at the connection between the second terminal of the ninth transistor MP3 and the input terminal of the first current mirror can be low, and the node voltage V4 at the connection between the second terminal of the tenth transistor MP4 and the input terminal of the second current mirror can be high. The fourth comparison signal output by the differential comparator circuit 31 can be a high-level signal.

[0054] Continue to refer to Figure 5 In some embodiments, the ninth switching unit 32 includes an eleventh transistor MN11. The first terminal of the eleventh transistor MN11 is connected to the fixed potential terminal of the ninth switching unit 32, the control terminal of the eleventh transistor MN11 is connected to the input terminal of the ninth switching unit 32, and the second terminal of the eleventh transistor MN11 is connected to the power supply terminal of the ninth switching unit 32.

[0055] Among them, the eleventh transistor MN11 can be an N-type MOS transistor, the first terminal of the eleventh transistor MN11 can be the source of the N-type MOS transistor, the second terminal of the eleventh transistor MN11 can be the drain of the N-type MOS transistor, and the control terminal of the eleventh transistor MN11 can be the gate of the N-type MOS transistor.

[0056] For example, the drain of the eleventh transistor MN11 can serve as the output terminal of the ninth switching unit 32. When the first comparison signal input to the control terminal of the eleventh transistor MN11 is a high-level signal, the eleventh transistor MN11 is turned on, and the voltage at the output terminal of the ninth switching unit 32 is low. When the second comparison signal input to the control terminal of the eleventh transistor MN11 is a low-level signal, the eleventh transistor MN11 is turned off, and the voltage at the output terminal of the ninth switching unit 32 is high. When the third comparison signal input to the control terminal of the eleventh transistor MN11 is a low-level signal, the eleventh transistor MN11 is turned off, and the voltage at the output terminal of the ninth switching unit 32 is high. When the fourth comparison signal input to the control terminal of the eleventh transistor MN11 is a high-level signal, the eleventh transistor MN11 is turned on, and the voltage at the output terminal of the ninth switching unit 32 is low. When the voltage at the output terminal of the ninth switching unit 32 switches from low to high, or from high to low, it is considered that the ninth switching unit 32 outputs a trigger signal.

[0057] In some embodiments, the bias circuit includes: a positive temperature coefficient current generating circuit, a negative temperature coefficient current generating circuit, and an output circuit. The power supply terminal of the positive temperature coefficient current generating circuit is connected to a power supply voltage and is used to generate a positive temperature coefficient current. The power supply terminal of the negative temperature coefficient current generating circuit is also connected to a power supply voltage and is used to generate a positive temperature coefficient current. The first input terminal of the output circuit is connected to the output terminal of the positive temperature coefficient current generating circuit, and the second input terminal of the output circuit is connected to the output terminal of the negative temperature coefficient current generating circuit. The output circuit combines the positive temperature coefficient current and the negative temperature coefficient current to output a bias current.

[0058] By adjusting the ratio of the positive temperature coefficient current to the negative temperature coefficient current, the bias current can be made to be a positive temperature coefficient, negative temperature coefficient, or zero temperature coefficient current. This, in turn, can compensate for temperature drift in the oscillation core circuit and the comparator circuit.

[0059] Figure 6 This is a circuit structure diagram of a bias circuit provided in an embodiment of the present invention. For example... Figure 6As shown, in some embodiments, the positive temperature current generating circuit includes: a twelfth transistor MP5, a thirteenth transistor MP6, a fourteenth transistor MN12, a fifteenth transistor MN13, a sixteenth transistor N1, a seventeenth transistor N2, and a first resistor R1. The first terminals of both the twelfth transistor MP5 and the thirteenth transistor MP6 are connected to the power supply voltage VDD. The control terminals of the twelfth transistor MP5 and the thirteenth transistor MP6 are connected together, and the control terminal and the second terminal of the thirteenth transistor MP6 are shared. The second terminal of the fourteenth transistor MN12 is connected to the second terminal of the twelfth transistor MP5, and the second terminal of the fifteenth transistor MN13 is connected to the second terminal of the thirteenth transistor MP6. The control terminals of the fourteenth transistor MN12 and the fifteenth transistor MN13 are connected together, and the control terminal and the second terminal of the fourteenth transistor MN12 are shared. The first terminal of the sixteenth transistor MN14 is connected to the first terminal of the fourteenth transistor MN12. The first terminal of the seventeenth transistor N2 is connected to the first terminal of the fifteenth transistor MN13 through the first resistor R1. The control terminal and the second terminal of the sixteenth transistor N1 are connected together. The control terminal and the second terminal of the seventeenth transistor N2 are connected together. The second terminals of the sixteenth transistor N1 and the seventeenth transistor are both grounded.

[0060] Specifically, transistors MP5 (12th) and MP6 (13th) can be P-type MOSFETs. The first terminal of MP5 and MP6 can be the source of the P-type MOSFET; the second terminal of MP5 and MP6 can be the drain of the P-type MOSFET; and the control terminal of MP5 and MP6 can be the gate of the P-type MOSFET. Similarly, transistors MN12 (14th) and MN13 (15th) can be N-type MOSFETs. The first terminal of MN12 and MN13 can be the source of the N-type MOSFET; the second terminal of MN12 and MN13 can be the drain of the N-type MOSFET; and the control terminal of MN12 and MN13 can be the gate of the N-type MOSFET. The sixteenth transistor N1 and the seventeenth transistor N2 can be NPN transistors. The first terminal of the sixteenth transistor N1 and the first terminal of the seventeenth transistor N2 can be the emitter of the NPN transistors. The second terminal of the sixteenth transistor N1 and the second terminal of the seventeenth transistor N2 can be the collector of the NPN transistors. The control terminal of the sixteenth transistor N1 and the control terminal of the seventeenth transistor N2 can be the base of the NPN transistors.

[0061] Among them, the twelfth transistor MP5, the thirteenth transistor MP6, the fourteenth transistor MN12, and the fifteenth transistor MN13 can form a negative feedback loop, creating a self-clamping circuit. According to the principle of virtual short and virtual open circuits, the node voltage VC at the connection between the source of the fourteenth transistor MN12 and the emitter of the sixteenth transistor N1 is equal to the node voltage VD at the connection between the source of the fifteenth transistor MN13 and the first terminal of the first resistor R1. Therefore, the current I1 flowing through the branch consisting of the thirteenth transistor MP6, the fifteenth transistor MN13, the first resistor R1, and the seventeenth transistor N2 can be expressed as: .in, R1 can be the emitter and base voltage drop of the seventeenth transistor N2, and R1 can be the resistance value of the first resistor. If R1 can be a negative temperature coefficient resistor, then the current I1 can be a positive temperature coefficient current I1.

[0062] Continue to refer to Figure 6 The negative temperature current generating circuit includes: the eighteenth transistor MP7, the nineteenth transistor MN14, and the second resistor R2. The first terminal of the eighteenth transistor MP7 is connected to the power supply voltage VDD, and its control terminal and second terminal are shared. The control terminal of the nineteenth transistor MN14 is connected to the control terminal of the fifteenth transistor MN13. The first terminal of the nineteenth transistor MN14 is grounded via the second resistor R2, and its second terminal is connected to the second terminal of the eighteenth transistor MP7.

[0063] The eighteenth transistor, MP7, can be a P-type MOSFET. The first terminal of MP7 can be the source of the P-type MOSFET; the second terminal of MP7 can be the drain of the P-type MOSFET; and the control terminal of MP7 can be the gate of the P-type MOSFET. The nineteenth transistor, MN14, can be an N-type MOSFET. The first terminal of MN14 can be the source of the N-type MOSFET; the second terminal of MN14 can be the drain of the N-type MOSFET; and the control terminal of MN14 can be the gate of the N-type MOSFET.

[0064] The current I2 flowing through the eighteenth transistor MP7, the nineteenth transistor MN14, and the second resistor R2 can be: Where Vbn represents the voltage at the control terminal of the fifteenth transistor MN13, Vgs represents the voltage difference between the gate and source of the nineteenth transistor MN14, and R2 can represent the resistance value of the second resistor. The second resistor R2 can be a positive temperature coefficient resistor, therefore, the current I2 can be a negative temperature coefficient current I2.

[0065] In this embodiment of the invention, the control terminal of the nineteenth transistor MN14 in the negative temperature coefficient current generation circuit is directly connected to the control terminal of the fifteenth transistor MN13. The output terminal of the negative feedback loop formed by the twelfth transistor MP5, the thirteenth transistor MP6, the fourteenth transistor MN12, and the fifteenth transistor MN13 directly controls the conduction level of the nineteenth transistor MN14. Compared with the traditional method of generating bias current through an operational amplifier in the bias circuit, this reduces the board integration area and power consumption.

[0066] Continue to refer to Figure 6 The output circuit includes: the twentieth transistor MP8 and the twenty-first transistor MP9.

[0067] The first terminals of the twentieth transistor MP8 and the twenty-first transistor MP9 are both connected to the power supply voltage VDD. The control terminal of the twentieth transistor MP8 is connected to the second terminal of the thirteenth transistor MP6 to replicate the positive temperature coefficient current I1. The control terminal of the twenty-first transistor MP9 is connected to the second terminal of the eighteenth transistor MP7 to replicate the negative temperature coefficient current I2. The node where the second terminals of the twentieth transistor MP8 and the twenty-first transistor MP9 are connected serves as the output terminal of the bias circuit 10.

[0068] Among them, the twentieth transistor MP8 and the eleventh transistor MP9 can be N-type MOS transistors. The first terminal of the twentieth transistor MP8 and the first terminal of the eleventh transistor MP9 can be the source of the N-type MOS transistors; the second terminal of the twentieth transistor MP8 and the second terminal of the eleventh transistor MP9 can be the drain of the N-type MOS transistors; the control terminal of the twentieth transistor MP8 and the control terminal of the eleventh transistor MP9 can be the gate of the N-type MOS transistors.

[0069] A suitable bias current Iref can be obtained by adjusting the resistance values ​​of the first resistor R1 in the positive temperature coefficient current generation circuit and the second resistor R2 in the negative temperature coefficient current generation circuit. For example, generating a bias current Iref with a positive temperature coefficient can cancel the threshold voltage VGS of the first transistor MP1 and the fifth transistor MP2 in the oscillation core circuit, as well as the threshold voltage VGS of the ninth transistor MP3 and the tenth transistor MP4 in the comparator circuit. This ensures that the first energy storage element and the second energy storage element's charging level are not affected by temperature, allowing the comparator circuit to accurately output trigger signals based on the charging and discharging status of the first and second energy storage elements, ultimately improving the clock accuracy of the clock oscillator.

[0070] Figure 7 This is a circuit diagram of a clock oscillator provided as an embodiment of the present invention. Figure 7 The circuit structure shown can have the beneficial effects of any of the above embodiments. It is understood that the circuit delay time td of the technical solution in the embodiments of the present invention is: Where C can be the capacitance value of the first capacitor C1 or the capacitance value of the second capacitor C2. For oscillation amplitude, , , The oscillation frequency of the clock oscillator Therefore, the technical solution of this invention allows for adjustment of the oscillation frequency by adjusting the capacitance value of the first capacitor C1 or the second capacitor C2.

[0071] For example, through the technical solution of this embodiment of the invention, the power consumption of the clock oscillator is 0.5uA and the temperature drift is less than 4%.

[0072] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this invention can be achieved, and this is not limited herein.

[0073] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A clock oscillator, characterized in that, include: Bias circuit, oscillation core circuit, comparator circuit and state control circuit; The power supply terminal of the oscillation core circuit and the power supply terminal of the comparator circuit are both connected to the output terminal of the bias circuit, which is used to generate a bias current based on the power supply voltage. The first input terminal of the oscillation core circuit is connected to a first control signal, and the second input terminal is connected to a second control signal. The oscillation core circuit is used to control the first energy storage element to charge according to the first control signal, control the first energy storage element to discharge according to the second control signal, and output a first reset ramp signal at the first output terminal according to the charging and discharging status of the first energy storage element; the third input terminal of the oscillation core circuit is connected to a third control signal, and the fourth input terminal is connected to the first control signal; the oscillation core circuit is also used to control the second energy storage element to charge according to the third control signal, control the second energy storage element to discharge according to the fourth control signal, and output a second reset ramp signal at the second output terminal according to the charging and discharging status of the second energy storage element; the first reset ramp signal and the second reset ramp signal are used for alternating resets; The first input terminal of the comparator circuit is connected to the first reset ramp signal, and the second input terminal is connected to the second reset ramp signal; the comparator circuit is used to compare the magnitudes of the first reset ramp signal and the second reset ramp signal and output a trigger signal. The input terminal of the state control circuit is connected to the output terminal of the comparator circuit. It is used to invert the state of the first control signal according to the trigger signal and output it at the first output terminal, to invert the state of the second control signal and output it at the second output terminal, to invert the state of the third control signal and output it at the third output terminal, and to invert the state of the fourth control signal and output it at the fourth output terminal.

2. The clock oscillator according to claim 1, characterized in that, The oscillation core circuit includes: a first switching unit, a second switching unit, a third switching unit, a fourth switching unit, a fifth switching unit, a sixth switching unit, a seventh switching unit, an eighth switching unit, a first energy storage element, and a second energy storage element; The power supply terminal of the first switching unit is connected to the output terminal of the bias circuit, the control terminal of the first switching unit is connected to the first input terminal of the oscillation core circuit, and the output terminal of the first switching unit is connected to the first terminal of the first energy storage element. The control terminal of the second switching unit is connected to the second input terminal of the oscillation core circuit, the output terminal of the second switching unit is connected to the first terminal of the first energy storage element, and the fixed potential terminal of the second switching unit is grounded. The control terminal of the third switching unit is connected to the third input terminal of the oscillation core circuit, the input terminal of the third switching unit is connected to the output terminal of the first switching unit, and the output terminal of the third switching unit is connected to the input terminal of the fourth switching unit. The control terminal of the fourth switching unit is connected to the first input terminal of the oscillation core circuit, and the input terminal of the fourth switching unit serves as the first output terminal of the oscillation core circuit; the fixed potential terminal of the fourth switching unit is grounded through a holding capacitor. The power supply terminal of the fifth switching unit is connected to the output terminal of the bias circuit, the control terminal of the fifth switching unit is connected to the third input terminal of the oscillation core circuit, and the output terminal of the fifth switching unit is connected to the first terminal of the second energy storage element. The control terminal of the sixth switching unit is connected to the fourth input terminal of the oscillation core circuit, the output terminal of the sixth switching unit is connected to the first terminal of the second energy storage element, and the fixed potential terminal of the sixth switching unit is grounded. The control terminal of the seventh switch unit is connected to the first input terminal of the oscillation core circuit, the input terminal of the seventh switch unit is connected to the output terminal of the sixth switch unit, and the output terminal of the seventh switch unit is connected to the input terminal of the eighth switch unit. The control terminal of the eighth switching unit is connected to the third input terminal of the oscillation core circuit, and the input terminal of the eighth switching unit serves as the second output terminal of the oscillation core circuit; the fixed potential terminal of the eighth switching unit is grounded through the holding capacitor. The second terminal of the first energy storage element is grounded, and the second terminal of the second energy storage element is also grounded.

3. The clock oscillator according to claim 2, characterized in that, The first switching unit includes a first transistor, the control terminal of the first transistor serves as the control terminal of the first switching unit, the first terminal of the first transistor serves as the power supply terminal of the first switching unit, and the second terminal of the first transistor serves as the output terminal of the first switching unit. The second switching unit includes a second transistor, the control terminal of the second transistor serves as the control terminal of the second switching unit, the second terminal of the second transistor serves as the output terminal of the second switching unit, and the first terminal of the second transistor serves as the fixed potential terminal of the second switching unit. The third switching unit includes a third transistor, the control terminal of the third transistor serves as the control terminal of the third switching unit, the second terminal of the third transistor serves as the input terminal of the third switching unit, and the first terminal of the third transistor serves as the output terminal of the third switching unit. The fourth switching unit includes a fourth transistor, the control terminal of the fourth transistor serves as the control terminal of the fourth switching unit, the second terminal of the fourth transistor serves as the input terminal of the fourth switching unit, and the first terminal of the fourth transistor serves as the fixed potential terminal of the fourth switching unit. The fifth switching unit includes a fifth transistor, the control terminal of the fifth transistor serves as the control terminal of the fifth switching unit, the first terminal of the fifth transistor serves as the power supply terminal of the fifth switching unit, and the second terminal of the fifth transistor serves as the output terminal of the fifth switching unit. The sixth switching unit includes a sixth transistor, the control terminal of the sixth transistor serves as the control terminal of the sixth switching unit, the second terminal of the sixth transistor serves as the output terminal of the sixth switching unit, and the first terminal of the sixth transistor serves as the fixed potential terminal of the sixth switching unit. The seventh switching unit includes a seventh transistor, the control terminal of the seventh transistor serves as the control terminal of the seventh switching unit, the second terminal of the seventh transistor serves as the input terminal of the seventh switching unit, and the first terminal of the seventh transistor serves as the output terminal of the seventh switching unit. The eighth switching unit includes an eighth transistor, the control terminal of the eighth transistor serves as the control terminal of the eighth switching unit, the second terminal of the eighth transistor serves as the input terminal of the eighth switching unit, and the first terminal of the eighth transistor serves as the fixed potential terminal of the eighth switching unit. The first energy storage element includes a first capacitor, and the second energy storage element includes a second capacitor.

4. The clock oscillator according to claim 3, characterized in that, The first transistor and the fifth transistor have the same channel type; the second transistor, the third transistor, the fourth transistor, the sixth transistor, the seventh transistor, and the eighth transistor have the same channel type; the first transistor and the second transistor have different channel types. The first control signal and the second control signal are in phase, the third control signal and the fourth control signal are in phase, and the first control signal and the third control signal are out of phase.

5. The clock oscillator according to claim 1, characterized in that, The comparison circuit includes: a differential comparison unit and a ninth switching unit; The first input terminal of the differential comparator unit is the first input terminal of the comparator circuit, and the second input terminal of the differential comparator unit is the second input terminal of the comparator circuit; the power supply terminal of the differential comparator circuit is used as the power supply terminal of the comparator circuit, and the fixed potential terminal of the differential comparator circuit is grounded; the differential comparator circuit is used to compare the first reset ramp signal and the second reset ramp signal and output a comparison signal. The input terminal of the ninth switching unit is connected to the output terminal of the differential comparator unit, and the power supply terminal of the ninth switching unit is connected to the bias circuit. The power supply terminal of the ninth switching unit serves as the output terminal of the comparator circuit. The fixed potential terminal of the ninth switching unit is grounded. The ninth switching unit is used to turn on or off according to the comparison signal, and when it is on, it connects the output terminal of the comparator circuit to ground. The change in the on or off state of the ninth switching unit outputs a trigger signal.

6. The clock oscillator according to claim 5, characterized in that, The differential comparator circuit includes a ninth transistor, a tenth transistor, a first current mirror, and a second current mirror. The first terminal of the ninth transistor and the first terminal of the tenth transistor are both connected to the power supply terminal of the differential comparator circuit. The control terminal of the ninth transistor is connected to the first input terminal of the differential comparator circuit, and the control terminal of the tenth transistor is connected to the second input terminal of the differential comparator circuit. The input terminal of the first current mirror and the output terminal of the second current mirror are both connected to the second terminal of the ninth transistor; the input terminal of the second current mirror and the output terminal of the first current mirror are both connected to the second terminal of the tenth transistor; the first current mirror and the second current mirror are grounded; the input terminal of the second current mirror is the output terminal of the differential comparator circuit.

7. The clock oscillator according to claim 5, characterized in that, The ninth switching unit includes an eleventh transistor; The first terminal of the eleventh transistor is connected to the fixed potential terminal of the ninth switching unit, the control terminal of the eleventh transistor is connected to the input terminal of the ninth switching unit, and the second terminal of the eleventh transistor is connected to the power supply terminal of the ninth switching unit.

8. The clock oscillator according to claim 1, characterized in that, The bias circuit includes: a positive temperature current generating circuit, a negative temperature current generating circuit, and an output circuit. The power supply terminal of the positive temperature coefficient current generating circuit is connected to the power supply voltage and is used to generate positive temperature coefficient current. The power supply terminal of the negative temperature current generating circuit is connected to the power supply voltage to generate a positive temperature coefficient current. The first input terminal of the output circuit is connected to the output terminal of the positive temperature coefficient current generating circuit, and the second input terminal of the output circuit is connected to the output terminal of the negative temperature coefficient current generating circuit. The output circuit is used to combine the positive temperature coefficient current and the negative temperature coefficient current to output the bias current.

9. The clock oscillator according to claim 8, characterized in that, The positive temperature current generating circuit includes: a twelfth transistor, a thirteenth transistor, a fourteenth transistor, a fifteenth transistor, a sixteenth transistor, a seventeenth transistor, and a first resistor; The first terminals of the twelfth and thirteenth transistors are both connected to the power supply voltage. The control terminals of the twelfth and thirteenth transistors are connected together, and the control terminals and second terminals of the thirteenth transistor are shared. The second terminal of the fourteenth transistor is connected to the second terminal of the twelfth transistor. The second terminal of the fifteenth transistor is connected to the second terminal of the thirteenth transistor. The control terminals of the fourteenth and fifteenth transistors are connected together, and the control terminals and second terminals of the fourteenth transistor are shared. The first terminal of the sixteenth transistor is connected to the first terminal of the fourteenth transistor. The first terminal of the seventeenth transistor is connected to the first terminal of the fifteenth transistor through the first resistor. The control terminals and second terminals of the sixteenth and seventeenth transistors are shared. The second terminals of the sixteenth and seventeenth transistors are both grounded. The negative temperature current generating circuit includes: an eighteenth transistor, a nineteenth transistor, and a second resistor; The first terminal of the eighteenth transistor is connected to the power supply voltage, and the control terminal and the second terminal of the eighteenth transistor are connected together; the control terminal of the nineteenth transistor is connected to the control terminal of the fifteenth transistor, the first terminal of the nineteenth transistor is grounded through the second resistor, and the second terminal of the nineteenth transistor is connected to the second terminal of the eighteenth transistor. The output circuit includes: a twentieth transistor and a twenty-first transistor; The first terminals of the twentieth transistor and the twentieth transistor are both connected to the power supply voltage. The control terminal of the twentieth transistor is connected to the second terminal of the thirteenth transistor to replicate the positive temperature coefficient current. The control terminal of the twentieth transistor is connected to the second terminal of the eighteenth transistor to replicate the negative temperature coefficient current. The node where the second terminals of the twentieth transistor and the twentieth transistor are connected serves as the output terminal of the bias circuit.

10. The clock oscillator according to claim 8, characterized in that, The state control circuit includes: First inverting unit, second inverting unit, third inverting unit, fourth inverting unit, first NAND gate, and second NAND gate; The input terminal of the first inverter unit serves as the input terminal of the state control circuit; the output terminal of the first inverter unit is connected to the first input terminal of the first NAND gate, and the output terminal of the second NAND gate is connected to the second input terminal of the first NAND gate; the output terminal of the first NAND gate is connected to the input terminal of the second inverter unit. The output of the first inverter unit is also connected to the input of the third inverter unit, the output of the third inverter unit is connected to the first input of the second NAND gate, the output of the first NAND gate is connected to the second input of the second NAND gate, and the output of the second NAND gate is connected to the input of the fourth inverter unit. The output of the second NAND gate serves as the first output of the state control circuit, and the output of the second inverting unit serves as the second output of the state control circuit; the output of the first NAND gate serves as the third output of the state control circuit, and the output of the fourth inverting unit serves as the fourth output of the state control circuit.

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