A bidirectional input / output circuit, chip, method and electronic device

Abstract

The application provides a bidirectional input and output circuit, a chip, a method and an electronic device. The circuit comprises a first port, a second port and a monitoring control unit. The monitoring control unit sets the first port and the second port as input ports and monitors the first port and the second port. If any one of the ports has input data, the corresponding first sampling signal and second sampling signal are generated. The first sampling signal is used to identify whether the first port has data. If the first port has data, the first port is set as an input port and the second port is set as an output port. The second sampling signal is used to identify whether the second port has data. If the second port has data, the second port is set as an input port and the first port is set as an output port. The circuit is also used for data frame end detection and data collision detection to ensure the reliability of bidirectional data input.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and in particular to a bidirectional input / output circuit, chip, method, and electronic device. Background Technology

[0002] The existing data transmission scheme is as follows: 1. Single-wire serial cascade transmission: This chip receives serial data from the previous chip (or module) and serially outputs the data to the next chip, enabling cascaded transmission of multiple chips. If a chip fails or the line is interrupted, the effective data transmission of the entire serial line will be affected.

[0003] 2. Two-wire data transmission with a clock line: Data transmission on the data line is driven synchronously by the clock on the clock line, enabling high-speed transmission. However, this introduces a clock line, and high-speed data transmission may introduce environmental interference, requiring strong electromagnetic interference immunity from the hardware. Furthermore, high-speed data transmission is not typically needed in standard operating environments.

[0004] 3. Parallel bus data transmission with address codes: After receiving the local address, the chip receives the corresponding data. However, this transmission scheme places high demands on the controller's driving capability, and the spatial distance for data transmission is limited by the controller's driving capability of the parallel chips. Summary of the Invention

[0005] The technical problem to be solved by the embodiments of this application is to provide a bidirectional input / output circuit, method and electronic device to solve the above-mentioned technical problem.

[0006] To address the aforementioned technical problems, this application provides a bidirectional input / output circuit, comprising: a first port, a second port, and a monitoring and control unit. Both the first port and the second port are electrically connected to the monitoring and control unit. The monitoring and control unit configures both the first port and the second port as input ports. It monitors the first port and the second port, and if input data enters either port, a first sampling signal is generated. After the first sampling signal is generated, a second sampling signal is also generated. The first sampling signal is used to identify whether there is data at the first port. If there is data at the first port, the monitoring and control unit configures the first port as an input port and the second port as an output port. The second sampling signal is used to identify whether there is data at the second port. If there is data at the second port, the monitoring and control unit configures the second port as an input port and the first port as an output port.

[0007] In some embodiments, a first timer is further included, electrically connected to the monitoring and control unit, for keeping the first timer reset during the input of a data frame through the first port or the second port, and starting the timing when the last input data of the data frame ends.

[0008] In some embodiments, when the first timer finishes counting down, a first monitoring signal is output to the monitoring control unit as an active status, indicating that the last input data of the data frame has ended. The monitoring control unit sets both the first port and the second port as input ports. In some embodiments, a second timer is also included, the first monitoring signal is used to enable the second timer to start working, and the first sampling signal is used to reset the second timer.

[0009] In some embodiments, when the second timer finishes counting down, a second monitoring signal is output to indicate that output collision detection has ended.

[0010] In some embodiments, the monitoring and control unit includes a first sampling signal generation module. The first port is electrically connected to the first sampling signal generation module via a first data line for inputting first input data from the first port. The second port is electrically connected to the first sampling signal generation module via a second data line for inputting second input data from the second port. The first input data and the second input data are ORed to obtain the first sampling signal.

[0011] In some embodiments, the monitoring and control unit includes a second sampling signal generation module, wherein the first sampling signal generation module is electrically connected to the second sampling signal generation module, and is used to input a first sampling signal to the second sampling signal generation module to trigger the second sampling signal generation module to generate a second sampling signal.

[0012] In some embodiments, the monitoring and control unit includes an input data identification and enable module, which is electrically connected to the first port via a third data line and a first enable line, respectively, for receiving first input data from the first port and setting the first port as an input port or an output port; the input data identification and enable module is also electrically connected to the first sampling signal generation module, for receiving the first sampling signal and sampling and identifying whether the first input data has entered the first port; if the first input data is identified to have entered the first port, the first port is set as an input port via the first enable line.

[0013] In some embodiments, the monitoring and control unit includes an input data identification and enable module, which is electrically connected to the second port via a fourth data line and a second enable line, respectively, for receiving second input data from the second port and setting the second port as an input port or an output port; the input data identification and enable module is also electrically connected to the second sampling signal generation module, for receiving the second sampling signal and sampling and identifying whether the second input data has entered the second port; if the second input data is identified to have entered the second port, the second port is set as an input port via the second enable line.

[0014] In some embodiments, a first timer is included, which is electrically connected to the first sampling signal generation module and is used to receive the first sampling signal output from the first sampling signal generation module, reset the first timer, and start timing; the first timer is also electrically connected to the input data recognition and enabling module, and when the first timer finishes timing, it outputs a first monitoring signal to the input data recognition and enabling module to indicate that the last input data of the data frame has ended.

[0015] In some embodiments, a second timer is included, which is electrically connected to the first timer, the first sampling signal generation module, and the input data identification and enable module, respectively. When the first monitoring signal is valid, the second timer is enabled to work. The first sampling signal is used to reset and count the second timer. When the second timer finishes counting, a second monitoring signal is output to the input data identification and enable module to indicate that the data conflict detection has ended.

[0016] This application also provides a chip embodiment, including the aforementioned bidirectional input / output circuit.

[0017] This application also provides a bidirectional input / output method, comprising the steps of: setting a first port and a second port as input ports; generating a first sampling signal from initial data signals entering through the two input ports; and generating a second sampling signal from the first sampling signal; using the first sampling signal to identify whether there is input data at the first port: if data enters at the first port, the first port is set as an input port and the second port is set as an output port; using the second sampling signal to identify whether there is input data at the second port: if data enters at the second port, the second port is set as an input port and the first port is set as an output port.

[0018] In some embodiments, the input data is continuously input in the form of data frames, the input process of the data frames is monitored, and a first duration timer is started when the last input data of the data frame ends; when the first duration timer ends, a first monitoring signal is output, and both the first port and the second port are set as input terminals.

[0019] In some embodiments, conflict detection is performed on the first port and the second port. If no data is detected at either port, a second duration of timing begins. If data is detected at either port, the process waits until no data is detected at either port before starting the second duration of timing. When the second duration ends, a second monitoring signal is output, and input terminal identification of the first port and the second port is restarted.

[0020] This application also provides an electronic device including the aforementioned chip.

[0021] Implementing the embodiments of this application has the following beneficial effects: This application provides a bidirectional input / output circuit, chip, method, and electronic device. The circuit includes: a first port, a second port, and a monitoring and control unit. The monitoring and control unit sets both the first port and the second port as input ports, and monitors both ports. If input data enters either port, a first sampling signal and a second sampling signal are generated accordingly. The first sampling signal is used to identify whether there is data at the first port: if there is data at the first port, the first port is set as the input port and the second port as the output port. The second sampling signal is used to identify whether there is data at the second port: if there is data at the second port, the second port is set as the input port and the first port as the output port. This circuit is also used for data frame end detection and data collision detection to ensure the reliability of bidirectional data input. Attached Figure Description

[0022] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0023] Figure 1 This is a schematic diagram of the circuit principle of one embodiment of the bidirectional input / output circuit of this application; Figure 2 This is a schematic diagram of the circuit composition of the first sampling signal module in one embodiment of the bidirectional input / output circuit of this application; Figure 3 This is a timing diagram of the first port recognizing input data in one embodiment of the bidirectional input / output circuit of this application; Figure 4 This is a timing diagram of the second port identifying input data in one embodiment of the bidirectional input / output circuit of this application; Figure 5 This is a waveform diagram of input data in one embodiment of the bidirectional input / output circuit of this application; Figure 6 This is a schematic diagram of the data frame end timing in one embodiment of the bidirectional input / output circuit of this application; Figure 7 This is a schematic diagram of the data conflict detection timing in one embodiment of the bidirectional input / output circuit of this application; Figure 8 This is a timing diagram of data conflict detection in another embodiment of the bidirectional input / output circuit of this application; Figure 9 This is a timing diagram of data conflict detection in another embodiment of the bidirectional input / output circuit of this application; Figure 10 This is a schematic diagram of the input data recognition and enable module circuit in one embodiment of the bidirectional input / output circuit of this application; Figure 11 This is a flowchart of one embodiment of the bidirectional input / output method of this application; Figure 12 This is a flowchart of another embodiment of the bidirectional input / output method of this application; Figure 13 This is a schematic diagram of the circuit connection of an embodiment of the chip in this application; Figure 14 This is a schematic diagram of the circuit connection of an embodiment of the chip in this application. Detailed Implementation

[0024] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0025] The terms "comprising" and "having," and any variations thereof, appearing in this specification, claims, and drawings, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or apparatus that includes a series of steps or modules is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to such process, method, product, or apparatus. Furthermore, the terms "first," "second," and "third," etc., are used to distinguish different objects and are not used to describe a specific order. Figure 1As shown, this is an embodiment of a bidirectional input / output circuit according to this application. The bidirectional input / output circuit includes a first port 1, a second port 2, a monitoring and control unit 3, and a timer 4. The timer 4 includes a first timer 41 and a second timer 42. The first port 1, the second port 2, and the timer 4 are all electrically connected to the monitoring and control unit 3.

[0026] The monitoring and control unit 3 is connected to the first port 1 and the second port 2 via a first enable line 331 and a second enable line 332, respectively. When the first input enable signal din_en transmitted via the first enable line 331 is high, the first port 1 is designated as an input port; when din_en is low, the first port 1 is designated as an output port. Similarly, when the second input enable signal dou_en transmitted via the second enable line 332 is high, the second port 2 is designated as an input port; when dou_en is low, the first port 2 is designated as an output port. This correspondence between the high and low levels of these two enable signals and the corresponding input / output settings of these two ports is merely illustrative and not restrictive. It can also be adjusted so that a low level corresponds to an input port and a high level corresponds to an output port.

[0027] When the monitoring and control unit 3 is unsure which port, first port 1 or second port 2, will receive input data first, the monitoring and control unit 3 sets both first port 1 and second port 2 as input ports. Therefore, as long as input data enters at either of these two ports, it can identify which port is the input port and then set that port as the input port, while the other port is the output port.

[0028] Specifically, in combination Figure 1 As shown, the first port 1 is electrically connected to the first sampling signal generation module 31 in the monitoring and control unit 3 via the first data line 11. The input data entering the first port 1 is transmitted to the first sampling signal generation module 31 via the first data line 11, and is called the first input data, indicating that it comes from the first port 1. The first input data of the first port 1 is represented as din. The second port 2 is also electrically connected to the first sampling signal generation module 31 in the monitoring and control unit 3 via the second data line 21. The input data entering the second port 2 is transmitted to the first sampling signal generation module 31 via the second data line 21, and is called the second input data, indicating that it comes from the second port 2. The second input data of the second port 2 is represented as dou.

[0029] The first input data from port 1 and the second input data from port 2 are logically ORed by the first sampling signal generation module 31 to obtain the first sampling signal. For example, when neither port 1 nor port 2 has input data, both are at a low level. After the OR operation, the output first sampling signal is also at a low level. When either port receives input data, it changes from a low level to a high level. After the OR operation, the output first sampling signal also changes from a low level to a high level, thus generating a valid first sampling signal. Here, the first sampling signal is represented as din_dout_mux.

[0030] Furthermore, Figure 2 An embodiment of the first sampling signal generation module 31 is shown: a first AND gate 313 is electrically connected to the first port 1 via a first data line 11, and electrically connected to the first enable line 331 of the input data recognition and enable module 33, for performing an AND operation on the first input data din and the first input enable signal din_en; a second AND gate 314 is electrically connected to the second port 2 via a second data line 21, and electrically connected to the second enable line 332 of the input data recognition and enable module 33, for performing an AND operation on the second input data dou and the second input enable signal dou_en; the two input terminals of the first OR gate 315 are electrically connected to the output terminals of the first AND gate 313 and the second AND gate 314, respectively; the input terminal of the first delay unit 316 is electrically connected to the output terminal of the first OR gate 315, and electrically connected to the input data recognition and enable module 33 via a first sampling line 312, and the output of the first delay unit 316 is the first sampling signal din_dout_mux.

[0031] in addition, Figure 2 Alternatively, the two AND gates 313 and 314 can be omitted. The first data line 11 and the second data line 21 can be electrically connected to the two input terminals of the first OR gate 315 respectively. The other circuit composition remains unchanged, and the first sampling signal din_dout_mux can still be obtained.

[0032] pass Figure 2 The first sampling signal generation module 31 shown is referenced. Figure 3 When the first input data din arrives at port 1, it changes from low to high. The first input enable signal din_en is high, the first AND gate 313 outputs a high level, and the first OR gate 315 also outputs a high level. Therefore, the first sampled signal din_dout_mux after passing through the first delay unit 316 also changes from low to high. (Reference) Figure 4When the second input data dout arrives at the second port 2, it changes from low level to high level. The second input enable signal dout_en is high level, the second AND gate 314 outputs high level, and the first OR gate 315 also outputs high level. Therefore, the first sampling signal din_dout_mux after passing through the first delay unit 316 also changes from low level to high level.

[0033] Therefore, when input data arrives at either port 1 or port 2, the first sampling signal generation module 31 can output a first sampling signal din_dout_mux that changes from low to high. This change in the first sampling signal din_dout_mux from low to high indicates that input data has arrived at either port, but further identification and determination are needed to determine which port received the input data.

[0034] It should also be noted that, for example Figure 5 As shown in the embodiment of the code pattern corresponding to the input data in this application, both the "0" code and the "1" code are return-to-zero codes. The high level in the "0" code appears at the initial moment of the code element, and the high level in the "1" code also appears at the initial moment of the code element. Alternatively, the "0" code and the "1" code can be considered as return-to-zero codes with different duty cycles. For example, both codes have a code element period of 1200ns. The high level in the "0" code lasts for 300ns, and the low level lasts for 900ns. Similarly, the high level in the "1" code lasts for 900ns, and the low level lasts for 300ns. Therefore, this change from low to high level occurs as soon as the input data enters. The recognition and judgment at the input port in this application are also based on the fact that the judgment is made as soon as the input data enters. For example, recognition can be completed if the high level lasts only 100-200ns after it begins.

[0035] Furthermore, in combination Figure 1 As shown, a first driving line 311 connects the first sampling signal generation module 31 and the second sampling signal generation module 32, used to transmit the first sampling signal din_dout_mux between the two modules. The second sampling signal generation module 32 may include an oscillator. When the first sampling signal din_dout_mux changes from low to high, the oscillator is triggered to output an oscillation signal, which is used as the second sampling signal output, denoted as oscb. Therefore, the second sampling signal oscb lags slightly behind the first sampling signal din_dout_mux, as shown... Figure 3 and Figure 4 As shown. The specific circuit composition of the second sampling signal generation module 32 will not be described in detail, as long as it is a circuit that can be triggered by the first sampling signal din_dout_mux to generate the required oscillation signal.

[0036] exist Figure 1 In this circuit, the first sampling signal din_dout_mux output by the first sampling signal generation module 31 is also electrically connected to the input data recognition and enable module 33 via the first sampling line 312. This is used to sample the first input data din from the first port 1. This is because the first port 1 and the input data recognition and enable module 33 are also electrically connected via the third data line 12. Correspondingly, the first input data din from the first port 1 is input to the input data recognition and enable module 33 for sampling and recognition by the first sampling signal din_dout_mux. Sampling is performed using the rising edge of the first sampling signal din_dout_mux, i.e., sampling occurs when the level changes from low to high. If there is actual data entering the first port 1, a high voltage will be sampled; otherwise, a low voltage will be sampled. This allows identification of whether input data has entered the first port 1.

[0037] Correspondingly, when the first sampling signal din_dout_mux detects a high voltage at port 1, indicating input data, it sets port 1 as the input port and port 2 as the output port, corresponding to din_en=1 for a high level and dout_en=0 for a low level. This can also be achieved through... Figure 3 The timing diagram shown illustrates the identification of the input data at the first port.

[0038] like Figure 3 As shown, when the first input data din enters through port 1, the first input data din changes from low to high. The first sampling signal din_dout_mux changes from low to high at time t1. This rising edge is used to sample port 1. If the sampled signal shows a high level at port 1, that is, the first input data din is high, it indicates that input data has entered through port 1. Correspondingly, the second input enable signal dou_en is set to low, and port 2 is set as the output port. Thus, the determination of which of the two input ports has input data is completed. The port with incoming data is set as the input port, and the port with incoming data is set as the output port.

[0039] exist Figure 1In this process, the second sampling signal oscb output by the second sampling signal generation module 32 is also electrically connected to the input data recognition and enable module 33 via the second sampling line 322, and is used to sample the second input data dou of the second port 2. This is because the second port 2 and the input data recognition and enable module 33 are also electrically connected via the fourth data line 22, correspondingly inputting the second input data dou from the second port to the input data recognition and enable module 33 for sampling and recognition by the second sampling signal oscb. If the first sampling signal din_dout_mux samples the first port 1 and obtains a low voltage, that is, no input data enters the first port 1, then the second sampling signal oscb will sample and recognize the second input data dou of the second port 2.

[0040] Specifically, at the first falling edge of the second sampling signal oscb, i.e. the sampling moment when the voltage changes from high to low, the second input data dou of the second port 2 is sampled. If a high voltage is obtained from the sampling, it is recognized that there is input data entering the second port 2. Then, the first port 1 is set as the output port and the second port 2 is set as the input port, corresponding to din_en=0 and dou_en=1.

[0041] In this regard, it can also be done through Figure 4 The timing diagram shown illustrates the identification of the input data at the second port. For example... Figure 4 As shown, when the second input data dout enters the second port 2, dout changes from low to high, and the first sampling signal din_dout_mux changes from low to high, triggering the oscillator in the second sampling signal generation module 32 to generate the second sampling signal oscb. At time t2, the second sampling signal oscb exhibits its first falling edge (or the opposite waveform using the first rising edge). This falling edge is used to sample the second port 2. If the sampled signal shows a high level at the second port 2, i.e., the second input data dout is high, it indicates that input data has entered the second port 2. The first input enable signal din_en is then set to low, and the first port 1 is set as the output port. Thus, the identification and judgment of which of the two input ports has input data is completed. The second port with input data is set as the input port, and the first port is set as the output port.

[0042] The above describes the process of identifying and setting up the input port. Next, we will check the working status when the input data is finished. It should be noted that this is based on... Figure 5The input data format shown typically involves continuous input data, such as eight or more consecutive input data points as a single data frame. After this data frame is completed, there is usually a delay interval before another data frame is input; that is, there is usually a time interval between adjacent data frames. Therefore, in this application, input data is typically input in the form of data frames, and the number of input data points included in a data frame can be determined as needed, usually more than one input data point.

[0043] Furthermore, such as Figure 1 As shown, it also includes a first timer 41, which is electrically connected to the first sampling signal generation module 31 in the monitoring and control unit 3 via a first reset timing line 411. This timer is used to input the first sampling signal din_dout_mux to the first timer 41 as its reset timing signal; that is, each rising edge of the first sampling signal din_dout_mux resets the first timer 41 and starts timing. Therefore, when input data is continuously input, typically during the duration of a continuous data frame composed of multiple input data, the first sampling signal din_dout_mux will have multiple rising edges, continuously resetting the first timer 41. Thus, when the last input data of the data frame ends, the first timer 41 is reset, and actual timing only begins. Therefore, the first timer 41 can be used to start timing when the last input data of an input data frame ends.

[0044] A first timing threshold rst_t0 is set for the first timer 41, corresponding to a timing duration, i.e., the first duration. When the timing duration of the first timer 41 reaches the first timing threshold rst_t0, the first monitoring signal frame_rdy is output to the input data recognition and enable module 33 in the monitoring control unit 3. At this time, the first monitoring signal frame_rdy changes from low voltage to high voltage, which is used to indicate the last input data input of the data frame.

[0045] Correspondingly, in Figure 1 The first timer 41 is electrically connected to the input data recognition and enable module 33 in the monitoring and control unit 3 via the first monitoring line 412, and is used to input the first monitoring signal frame_rdy to the input data recognition and enable module 33. When the input data recognition and enable module 33 receives the first monitoring signal frame_rdy changing from low voltage to high voltage, it sets din_en=1 and dou_en=1 accordingly, thereby setting both the first port 1 and the second port 2 as input ports.

[0046] Therefore, the first timer 41 is used to monitor the input process of a data frame. When the last input data of the data frame is input, the first timer 41 starts timing. When the timing reaches the first timing threshold rst_t0, the first port 1 and the second port 2 are set to be input ports.

[0047] The corresponding timing diagram is as follows Figure 6 As shown. During the duration of the data frame, din_en=1 and dou_en=0, corresponding to port 1 as the input port and port 2 as the output port. At time t3, the last input data of the data frame ends, and the first timer starts counting. Figure 6 In the table, idle_cnt represents the timing line of the timing signal. When the first timing threshold rst_t0 is reached, at time t4, din_en=1 and dou_en=1 are set, and the first and second ports are both input ports. The first monitoring signal frame_rdy changes from low voltage to high voltage, indicating that the last input data of the data frame has been input.

[0048] The following explanation continues: after a data frame ends, data collision detection is also required. This is because when both ports are set as input ports, there may be data being transmitted on the line connected to these two ports. However, for these two ports, the data currently being transmitted is not a complete data frame. If it is directly input, the result will be an incomplete data frame. Therefore, this data needs to be discarded and cannot be received as valid input data; hence, data collision detection is necessary.

[0049] Continue to refer to Figure 6 At time t4, the first monitoring signal frame_rdy changes from low voltage to high voltage, starting the second timer. If no input data appears at either the first or second port, when the second timer reaches the second timing threshold rst_t1, the second monitoring signal frame_rst outputs a pulse signal, changing from low to high and then back to low, indicating the end of collision detection. Then, since both the first and second ports are input ports, the process restarts to identify which port the input data first appears on, as described above. Figure 3 and Figure 4 The input port identification and setup process is shown.

[0050] Correspondingly, in Figure 1The second timer 42 is electrically connected to the input data recognition and enable module 33 in the monitoring and control unit 3 via the second monitoring line 422, and is used to input the second monitoring signal frame_rst to the input data recognition and enable module 33. The second timer 42 is also electrically connected to the first sampling signal generation module 31 in the monitoring and control unit 3 via the first reset timing line 411, and can also be reset based on the first sampling signal din_dout_mux. However, this reset is only possible when the first monitoring signal frame_rdy is valid, i.e., after the first monitoring signal frame_rdy changes from low voltage to high voltage. Therefore, in Figure 1 In the middle, a first enable timing line 413 is also connected between the first timer 41 and the second timer 42, which is used to enable the second timer 42 to start working through the first monitoring signal frame_rdy.

[0051] Regarding collision detection, it can also be achieved through the following methods: Figures 7 to 9 Please provide an explanation.

[0052] Combination Figure 7 As shown, when the first timer reaches the first timing threshold rst_t0, data conflict detection begins at time t6. din_en=1 and dou_en=1, and both the first and second ports are set as input ports. The first monitoring signal frame_rdy is valid, and the second timer starts working. At this time, there is input data at the second port, and the corresponding first sampling signal din_dout_mux also appears. Therefore, for the second timer, the first sampling signal din_dout_mux will continuously reset it, and the idle_cnt timing line will display 0 until the input data at the second port ends. At this point, the first sampling signal din_dout_mux will also not appear, and the second timer will start counting continuously until it reaches its maximum at time t7. The second monitoring signal frame_rst will then output a pulse signal, indicating the end of data conflict detection and the start of the next round of input port recognition.

[0053] Combination Figure 8As shown, when the first timer reaches the first timing threshold rst_t0, i.e., at time t8, data conflict detection begins. din_en=1 and dou_en=1, and both the first and second ports are set as input ports. The first monitoring signal frame_rdy is valid, and the second timer starts working. At this time, there is input data at the first port, and the corresponding first sampling signal din_dout_mux also appears. Therefore, for the second timer, the first sampling signal din_dout_mux will continuously reset it, and the idle_cnt timing line will display 0 until the input data at the first port ends and the first sampling signal din_dout_mux no longer appears. Then, the second timer starts counting continuously until it reaches its maximum at time t9. The second monitoring signal frame_rst outputs a pulse signal, indicating that the data conflict detection has ended and the next round of input port recognition process begins.

[0054] Combination Figure 9 As shown, when the first timer reaches the first timing threshold rst_t0, data conflict detection begins at time t10. din_en=1 and dou_en=1, and both the first and second ports are set as input ports. The first monitoring signal frame_rdy is valid, and the second timer starts working. At this time, there is input data at the second port, and the corresponding first sampling signal din_dout_mux also appears. After the input data at the second port ends, input data also appears at the first port, so the first sampling signal din_dout_mux continues to exist. For the second timer, the first sampling signal din_dout_mux will be continuously reset, and the idle_cnt timing line will display 0 until the input data at the first port ends and the first sampling signal din_dout_mux no longer appears. Then, the second timer starts counting continuously until it reaches the threshold at time t11. The second monitoring signal frame_rst outputs a pulse signal, indicating the end of data conflict detection and the start of the next round of input port recognition.

[0055] Figure 10 This is a circuit embodiment corresponding to the input data recognition and enable module in this application. Here, por represents the positive power supply, and gnd represents ground. This circuit mainly consists of an upper first branch and a lower second branch. These two branches have similar circuit compositions, both including two flip-flops, an NOT gate, a three-input AND gate, and an OR gate. The difference is that the first sampling signal din_dout_mux in the first branch is directly connected to the flip-flops, while the second sampling signal oscb in the second branch is connected to the flip-flops after passing through the NOT gate. The specific circuit connections are as follows: Figure 10 As shown in the image.

[0056] The circuit's operation is described below: For each flip-flop, a low level at the CLR (reset) terminal resets the Q terminal to a low level; a high level at the SET (set) terminal sets the Q terminal to a high level. Without reset or set, the rising edge signal at the CK terminal of the flip-flop outputs the D terminal to the Q terminal. Upon power-up reset, the outputs din_latch and dout_latch of the two flip-flops on the left side of the two branches are reset low, as are the outputs a and b of the two flip-flops on the right side of these two branches. A and b, via an inverter and an OR gate, pull din_oen and dout_oen high, controlling the two input ports to input state, awaiting the arrival of din and dout input data.

[0057] When din and dou input data arrive, they are respectively set to the two flip-flops on the left side of the two branches. When din or dou inputs a high level, the two flip-flops will latch into din_latch or dou_latch respectively (din_latch or dou_latch is set to 1). The rising edge of din_dout_mux outputs din_latch to a; the falling edge of oscb outputs dou_latch to b. din_dout_mux is the delayed signal of din or dou, and the delay time of the delay unit is relatively short. oscb is the internal clock, which has a start time after being enabled. Therefore, the first port corresponding to din is checked first, and then the second port corresponding to dou is checked. When data arrives from both ends simultaneously, din takes priority.

[0058] If din_dout_mux recognizes din_latch as high, a=1. a=1 is ORed with frame_rdy(0) via an inverter, both are 0, and after passing through an OR gate dou_oen=0, dou is set as the output. At the same time, a=1 resets b, b=0, and din remains the input.

[0059] If din_dout_mux does not recognize din_latch, a=0. din and dou remain inputs. When oscb catches dou_latch high on the falling edge, b=1. b=1 is ORed with frame_rdy(0) via an inverter. Both are 0, so din_oen is set to 0 via an OR gate, and din is set to output. At the same time, b=1 resets a, a=0, and dou remains an input.

[0060] While waiting for the input data to be received (no data input within rst_t0 time), a high level in frame_rdy sets din_oen and dou_oen high (both ends are input), verifying for data conflict. If there is no data conflict at both ends (no data input within rst_t1 time), frame_rst is high. The rising edge of frame_rst sends the D terminals (gnd) of the two flip-flops on the left side of the two branches to din_latch and dou_latch, pulling din_latch and dou_latch low (clearing the latch). The high level of frame_rst resets the two flip-flops on the left side of the two branches, resetting a and b to 0. a and b are then inverted to 1, and ORed to reset din_oen and dou_oen to the input state, waiting for the next frame of data to enter.

[0061] Based on the same inventive concept, this application also provides an embodiment of a bidirectional input / output method, such as... Figure 11 As shown, the main steps include: S101: Set both the first port and the second port to be input ports, generate a first sampling signal from the initial data signals entering through these two input ports, and generate a second sampling signal from the first sampling signal; S102: Use the first sampling signal to identify whether there is input data at the first port: if data enters the first port, the first port is set as the input port and the second port is set as the output port; S103: Use the second sampling signal to identify whether there is input data at the second port: If data enters the second port, the second port is set as the input port and the first port is set as the output port.

[0062] Steps S101 to S103 above correspond to the aforementioned Figures 1 to 5 Regarding the embodiment of input port identification, steps S102 and S103 are selective. If step S102 is executed effectively, step S103 is not executed; if step S102 cannot be executed effectively, step S103 is executed. For specific details, please refer to the foregoing description, which will not be repeated here.

[0063] like Figure 11 As shown, it may further include the following steps: S104: The input data is continuously input in the form of data frames. The input process of the data frames is monitored, and the first duration timing begins when the last input data of the data frame ends. S105: The first duration timing ends, the first monitoring signal is output, and the first port and the second port are set as input ports.

[0064] These two steps S104 to S105 correspond to the aforementioned Figure 1 and Figure 6 The implementation shown will not be elaborated on the end-of-data-frame detection.

[0065] like Figure 11 As shown, it may further include the following steps: Following steps S105 and S106: perform conflict detection on the first port and the second port. If neither port has any data input, start the second duration of timing. If either port has data input, wait until neither port has any data input before starting the second duration of timing. S107: The timing of the second duration ends, the second monitoring signal is output, and the input terminal identification of the first port and the second port is restarted.

[0066] These two steps S106 to S107 correspond to the aforementioned Figure 1 and Figure 7 , Figure 8 , Figure 9 The identification and detection of data conflicts in the illustrated embodiment will not be described in detail here.

[0067] Furthermore, it can also be done through Figure 12 The relevant process steps are further reflected Figure 11 The details of each step are not repeated here.

[0068] In this application, Figure 1 The illustrated embodiment of the bidirectional input / output circuit is implemented on a single chip, meaning the entire bidirectional input / output circuit is a system-on-a-chip (SoC). SoC is a commonly used technology in the integrated circuit field, aiming to combine multiple integrated circuits with specific functions onto a single chip to form a system or product, including the completed hardware system and its embedded software. SoCs offer significant advantages in performance, cost, power consumption, reliability, lifespan, and application scope.

[0069] like Figure 13 and Figure 14 As shown, the first chip IC1 to the seventh chip IC7 are chips that contain the bidirectional input / output circuit of this application. These chips can be cascaded together, with the first and last chips connected to the controller. Figure 13 The input data can be transmitted from the first chip IC1 to the seventh chip IC7 in the first direction (counterclockwise). Figure 14The input data can be transmitted from the seventh chip IC7 to the first chip IC1 via the second direction (clockwise). Therefore, by using the bidirectional input / output circuit of this application, bidirectional data transmission can be achieved without changing the electrical connection relationship of these chips. Even if one chip malfunctions, the other chips can input data through two different directions, so the functions of the other chips can continue to be performed.

[0070] This application provides an electronic device, such as an LED light strip, an LED display screen, and consumer electronics products with LEDs. The electronic device includes... Figure 13 and Figure 14 The chip in the illustrated embodiment, and the controller electrically connected to the chip.

[0071] It should be understood that "a plurality of" as used herein refers to two or more. Other embodiments of this application will readily occur to those skilled in the art upon consideration of the specification and practice of the application disclosed herein. This application is intended to cover any variations, uses, or adaptations of this application that follow the general principles of this application and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this application are indicated by the following claims.

[0072] It should be noted that the various embodiments in this specification are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the apparatus embodiments, since they are basically similar to the method embodiments, the description is relatively simple; relevant parts can be referred to the descriptions in the method embodiments.

[0073] The above-disclosed embodiments are merely preferred embodiments of this application and should not be construed as limiting the scope of this application. Therefore, any equivalent variations made in accordance with the claims of this application shall still fall within the scope of this application.

Claims

1. A bidirectional input / output circuit, characterized in that, include: The system includes a first port, a second port, and a monitoring and control unit, wherein both the first port and the second port are electrically connected to the monitoring and control unit. The monitoring and control unit is configured such that both the first port and the second port are input ports; The system monitors the first port and the second port. If input data enters either port, a first sampling signal is generated. After the first sampling signal is generated, a second sampling signal is also generated. The first sampling signal is used to identify whether there is data input at the first port: if there is data input at the first port, the monitoring and control unit sets the first port as an input port and the second port as an output port; The second sampling signal is used to identify whether there is data input at the second port: if there is data input at the second port, the monitoring and control unit sets the second port as the input port and the first port as the output port.

2. The bidirectional input / output circuit according to claim 1, characterized in that, It also includes a first timer, electrically connected to the monitoring and control unit, for keeping the first timer reset during the input of a data frame through the first port or the second port, and starting the timing when the last input data of the data frame ends.

3. The bidirectional input / output circuit according to claim 2, characterized in that, When the first timer finishes counting down, a first monitoring signal is output to the monitoring and control unit to indicate that the last input data of the data frame has been input. The monitoring and control unit sets both the first port and the second port to be input ports.

4. The bidirectional input / output circuit according to claim 3, characterized in that, It also includes a second timer, wherein the first monitoring signal is used to enable the second timer to start working, and the first sampling signal is used to reset the second timer.

5. The bidirectional input / output circuit according to claim 4, characterized in that, When the second timer finishes counting down, it outputs a second monitoring signal, indicating that the output collision detection has ended.

6. The bidirectional input / output circuit according to claim 1, characterized in that, The monitoring and control unit includes a first sampling signal generation module. The first port is electrically connected to the first sampling signal generation module via a first data line and is used to input first input data from the first port. The second port is electrically connected to the first sampling signal generation module via a second data line and is used to input second input data from the second port. The first sampled signal is obtained by performing an OR operation on the first input data and the second input data.

7. The bidirectional input / output circuit according to claim 6, characterized in that, The monitoring and control unit includes a second sampling signal generation module. The first sampling signal generation module is electrically connected to the second sampling signal generation module and is used to input the first sampling signal to the second sampling signal generation module to trigger the second sampling signal generation module to generate a second sampling signal.

8. The bidirectional input / output circuit according to claim 6, characterized in that, The monitoring and control unit includes an input data identification and enable module, which is electrically connected to the first port via a third data line and a first enable line, respectively, for receiving first input data from the first port and setting the first port as an input port or an output port; the input data identification and enable module is also electrically connected to the first sampling signal generation module, for receiving the first sampling signal and sampling and identifying whether the first input data has entered the first port; if the first input data is identified to have entered the first port, the first port is set as an input port via the first enable line.

9. The bidirectional input / output circuit according to claim 7, characterized in that, The input data recognition and enable module is electrically connected to the second port via the fourth data line and the second enable line, respectively, and is used to receive the second input data from the second port and to set the second port as an input port or an output port. The input data recognition and enable module is also electrically connected to the second sampling signal generation module, and is used to receive the second sampling signal and to sample and recognize whether the second input data has entered the second port. If the second input data is recognized to have entered the second port, the second port is set as an input port via the second enable line.

10. The bidirectional input / output circuit according to claim 8 or 9, characterized in that, The system includes a first timer, which is electrically connected to the first sampling signal generation module and is used to receive the first sampling signal output from the first sampling signal generation module, reset the first timer, and start timing. The first timer is also electrically connected to the input data recognition and enable module. When the first timer finishes timing, it outputs a first monitoring signal to the input data recognition and enable module to indicate that the last input data of the data frame has been input.

11. The bidirectional input / output circuit according to claim 10, characterized in that, The system includes a second timer, which is electrically connected to the first timer, the first sampling signal generation module, and the input data identification and enable module. When the first monitoring signal is valid, the second timer is enabled to work. The first sampling signal is used to reset and count the second timer. When the second timer finishes counting, a second monitoring signal is output to the input data identification and enable module to indicate that the data conflict detection has ended.

12. A chip, characterized in that, The chip includes the bidirectional input / output circuit of any one of claims 1-11.

13. A bidirectional input / output method, characterized in that, Including the following steps: The first port and the second port are both input ports. The initial data signals entering from these two input ports generate a first sampling signal, and the first sampling signal generates a second sampling signal. The first sampling signal is used to identify whether there is input data at the first port: if input data enters the first port, the first port is set as the input port and the second port is set as the output port; The second sampling signal is used to identify whether there is input data at the second port: if input data enters the second port, the second port is set as the input port and the first port is set as the output port.

14. The bidirectional input / output method according to claim 13, characterized in that, The input data is continuously input in the form of data frames. The input process of the data frames is monitored, and the first duration is started when the last input data of the data frame ends. When the first duration ends, the first monitoring signal is output, and both the first and second ports are set as input terminals.

15. The bidirectional input / output method according to claim 14, characterized in that, Conflict detection is performed on the first port and the second port. If no data is input on either port, the second duration of timing begins. If data is input on either port, the process waits until no data is input on either port before starting the second duration of timing. When the second duration ends, the second monitoring signal is output, and the input terminal identification of the first port and the second port is restarted.

16. An electronic device, characterized in that, Including the chip as described in claim 12.

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