Gate drive circuit, drive chip, power converter and power supply device

Abstract

The present disclosure relates to the technical field of integrated circuits, and particularly relates to a gate drive circuit, a drive chip, a power converter and a power supply device. The gate drive circuit comprises a first transistor, a second transistor, a NAND logic circuit, a level converter and a control circuit. The control circuit is configured to output a first control signal when an input voltage signal jumps from a high level to a low level, and gradually lower the potential of an output voltage signal during the validity period of the first control signal. The control circuit is configured to output a second control signal when the potential of the output voltage signal drops to a preset voltage, and the polarities of the first control signal and the second control signal are opposite. The embodiment of the present disclosure does not need to limit the minimum pulse width of the input voltage signal, and does not need to consider the size of the load capacitance. Compared with the related art, the embodiment simplifies the system design, has higher flexibility and adaptability, and can improve the signal frequency of the input voltage signal because the minimum pulse width does not need to be limited as in the related art.

Description

Technical Field

[0001] This disclosure relates to the field of integrated circuit technology, and in particular to a gate drive circuit, a drive chip, a power converter, and a power supply device. Background Technology

[0002] Traditional power transistor driver circuits do not specifically control the pulse width of the output voltage signal; the pulse width of the output voltage signal is generally equal to that of the input voltage signal. When the input voltage signal pulse width is large or the load capacitance is small, the output voltage signal can usually quickly follow the input voltage signal, thus achieving complete turn-off. However, when the input voltage signal pulse width is small or the load capacitance is large, the output voltage signal's decline process is relatively slow. This may result in the input voltage signal becoming high again before the output voltage signal drops to 0V (i.e., not completely turned off). In this case, the output port becomes on again before being completely turned off, causing a very large di / dt current at the output port. Due to the parasitic inductance of the leads, this di / dt can induce a large oscillating voltage at the output port, thus exposing the driver chip and the driven power device to the risk of overvoltage damage.

[0003] Traditionally, to achieve complete shutdown, the minimum pulse width of the input voltage signal is usually set according to the size of the load capacitance. However, the capacitance value of the load capacitance can vary, and temperature and chip manufacturing process can also affect the output current of the driver chip. Therefore, sufficient margin needs to be left for the minimum pulse width of the input voltage signal, but this will affect the maximum frequency of the input voltage signal. Moreover, setting the minimum pulse width for different load capacitances also increases the complexity of system design. Summary of the Invention

[0004] In view of this, the present disclosure proposes a gate driving circuit, the gate driving circuit including a first transistor, a second transistor, a NAND logic circuit, a level shifter, and a control circuit, wherein,

[0005] The source of the first transistor is used to connect to the power supply voltage.

[0006] The gate of the first transistor is connected to the output of the level converter.

[0007] The drains of the first transistor and the second transistor are connected to form the output terminal of the gate driving circuit, and the output terminal of the gate driving circuit generates an output voltage signal.

[0008] The output of the NAND logic circuit is connected to the input of the level converter and the gate of the second transistor, and the source of the second transistor is grounded.

[0009] The level converter is used to convert the reference potential of the output signal of the AND-NOT logic circuit into a target potential.

[0010] The first input terminal of the control circuit and the first input terminal of the NAND logic circuit are both used to receive input voltage signals. The second input terminal of the control circuit is connected to the output terminal of the gate drive circuit, and the output terminal of the control circuit is connected to the second input terminal of the NAND logic circuit. The control circuit is used for:

[0011] When the input voltage signal changes from high level to low level, a first control signal is output. During the period when the first control signal is valid, the potential of the output voltage signal gradually decreases.

[0012] When the potential of the output voltage signal drops to a preset voltage, a second control signal is output, wherein the polarity of the first control signal and the second control signal is opposite.

[0013] In one possible implementation, the control circuit includes a voltage detection and comparison circuit, an OR logic circuit, a NOR logic circuit, a pulse generation circuit, and an RS flip-flop, wherein...

[0014] The input terminal of the voltage detection and comparison circuit serves as the second input terminal of the control circuit. The voltage detection and comparison circuit detects the output voltage signal, compares it with a comparison threshold voltage, and outputs a comparison result signal.

[0015] The output of the voltage detection and comparison circuit is connected to the first input of the OR logic circuit.

[0016] The second input terminal of the OR logic circuit is connected to the second input terminal of the NOR logic circuit, the set terminal of the RS flip-flop, and the output terminal of the pulse generation circuit.

[0017] The output of the OR logic circuit is connected to the first input of the NOR logic circuit.

[0018] The output of the NOR logic circuit is connected to the reset terminal of the RS flip-flop.

[0019] The inverse code output of the RS flip-flop serves as the output of the control circuit.

[0020] The input terminal of the pulse generation circuit serves as the first input terminal of the control circuit. The pulse generation circuit is used to output a pulse signal when the input voltage signal changes from a high level to a low level.

[0021] In one possible implementation, the voltage detection and comparison circuit includes a third transistor and a comparator.

[0022] The drain of the third transistor serves as the input terminal of the voltage detection and comparison circuit.

[0023] The gate of the third transistor is used to receive a preset bias voltage.

[0024] The source of the third transistor is connected to the positive input terminal of the comparator.

[0025] The negative input terminal of the comparator receives the comparison threshold voltage.

[0026] The output terminal of the comparator serves as the output terminal of the voltage detection and comparison circuit.

[0027] In one possible implementation, the control circuit further includes a filtering circuit disposed between the output terminal of the OR logic circuit and the first input terminal of the NOR logic circuit, the filtering circuit being used to filter the signal output by the OR logic circuit.

[0028] In one possible implementation, the first transistor is a PMOS transistor, and the second and third transistors are both NMOS transistors.

[0029] In one possible implementation, the pulse signal is a single pulse.

[0030] In one possible implementation, the level converter includes a level shifting circuit, wherein the target potential is related to the power supply voltage.

[0031] According to another aspect of this disclosure, a driver chip is provided, the chip including the aforementioned gate driving circuit.

[0032] According to another aspect of this disclosure, a power converter is provided, the power converter including the aforementioned driver chip.

[0033] According to another aspect of this disclosure, a power supply device is provided, the power supply device including the power converter described above.

[0034] The gate driving circuit of this embodiment controls the output voltage signal by setting the control circuit 20 to generate an input voltage signal at the second input terminal of the NAND logic circuit based on the input voltage signal and / or the output voltage signal, thereby controlling the potential of the output voltage signal. When the input voltage signal jumps from a high level to a low level, a first control signal is output. During the effective period of the first control signal, the potential of the output voltage signal gradually decreases until the potential of the output voltage signal drops to a preset potential. This embodiment does not require limiting the minimum pulse width of the input voltage signal, nor does it require considering the size of the load capacitance. Compared with related technologies, it simplifies the system design and has higher flexibility and adaptability. Furthermore, because it does not require limiting the minimum pulse width as in related technologies, it can increase the signal frequency of the input voltage signal.

[0035] Other features and aspects of this disclosure will become clear from the following detailed description of exemplary embodiments with reference to the accompanying drawings. Attached Figure Description

[0036] The accompanying drawings, which are included in and form part of this specification, illustrate exemplary embodiments, features, and aspects of this disclosure together with the specification and serve to explain the principles of this disclosure.

[0037] Figure 1 A schematic diagram of a gate drive circuit according to an embodiment of the present disclosure is shown.

[0038] Figure 2 A schematic diagram of a gate drive circuit according to an embodiment of the present disclosure is shown.

[0039] Figure 3 A schematic diagram of the voltage waveforms at each node is shown when the gate drive circuit according to an embodiment of the present disclosure is in operation. Detailed Implementation

[0040] Various exemplary embodiments, features, and aspects of this disclosure will now be described in detail with reference to the accompanying drawings. The same reference numerals in the drawings denote elements that have the same or similar functions. Although various aspects of the embodiments are shown in the drawings, they are not necessarily drawn to scale unless specifically indicated otherwise.

[0041] As used herein, the terms “comprising,” “including,” “having,” or variations thereof are open-ended and include one or more of the stated features, integrals, elements, steps, components, or functions, but do not exclude the presence or addition of one or more other features, integrals, elements, steps, components, functions, or groups thereof.

[0042] When an element is referred to as “connected,” “coupled,” “responding,” or a variation thereof relative to another element, it may be directly connected, coupled, or responding to another element, or there may be an intermediate element present.

[0043] Although the terms first, second, third, etc., may be used herein to describe various elements / operations, these elements / operations should not be limited by these terms. These terms are only used to distinguish one element / operation from another. Therefore, without departing from the teachings of the inventive concept, a first element / operation in some embodiments may be referred to as a second element / operation in other embodiments.

[0044] The term “exemplary” as used herein means “serving as an example, embodiment, or illustration.” Any embodiment illustrated herein as “exemplary” is not necessarily to be construed as superior to or better than other embodiments.

[0045] Furthermore, to better illustrate this disclosure, numerous specific details are set forth in the following detailed description. Those skilled in the art will understand that this disclosure can be practiced without certain specific details. In some instances, methods, means, components, and circuits well known to those skilled in the art have not been described in detail in order to highlight the main points of this disclosure.

[0046] It should be noted that the information (including but not limited to user device information, user personal information, etc.), data (including but not limited to data used for analysis, data stored, data displayed, etc.) and signals involved in this application are all authorized by the user or fully authorized by all parties, and the collection, use and processing of related data must comply with the relevant laws, regulations and standards of the relevant regions.

[0047] As described in the background section, traditional methods that limit the minimum pulse width of the input voltage signal sacrifice the highest operating frequency and require optimization based on the load capacitance, making them cumbersome to use. In addition, traditional methods are very sensitive to noise, and the input voltage signal may have a very narrow pulse width due to noise interference, thus making it impossible to achieve complete shutdown.

[0048] Therefore, this disclosure provides a gate drive circuit that overcomes the problems existing in related technologies.

[0049] Please see Figure 1 , Figure 1 A schematic diagram of a gate drive circuit according to an embodiment of the present disclosure is shown.

[0050] like Figure 1 As shown, the gate driving circuit includes a first transistor Q1, a second transistor Q2, a NAND logic circuit Anot, a level shifter 10, and a control circuit 20, wherein...

[0051] The source of the first transistor Q1 is connected to the power supply voltage VCC.

[0052] The gate of the first transistor Q1 is connected to the output of the level converter 10.

[0053] The drains of the first transistor Q1 and the second transistor Q2 are connected to form the output terminal of the gate driving circuit, and the output terminal of the gate driving circuit generates an output voltage signal Vout.

[0054] The output of the NAND logic circuit Anot is connected to the input of the level converter 10 and the gate of the second transistor Q2, and the source of the second transistor Q2 is grounded.

[0055] The level converter 10 is used to convert the reference potential of the output signal of the NAND logic circuit Anot into a target potential.

[0056] The first input terminal of the control circuit 20 and the first input terminal of the NAND logic circuit Anot are both used to receive the input voltage signal Vin. The second input terminal of the control circuit 20 is connected to the output terminal of the gate drive circuit, and the output terminal of the control circuit 20 is connected to the second input terminal of the NAND logic circuit Anot. The control circuit 20 is used for:

[0057] When the input voltage signal Vin changes from high level to low level, a first control signal is output. During the period when the first control signal is valid, the potential of the output voltage signal Vout gradually decreases.

[0058] When the potential of the output voltage signal Vout drops to a preset voltage, a second control signal is output, wherein the polarity of the first control signal and the second control signal is opposite.

[0059] The gate driving circuit of this embodiment controls the output voltage signal Vout by setting the control circuit 20 to generate an input voltage signal at the second input terminal of the NAND logic circuit Anot based on the input voltage signal Vin and / or the output voltage signal Vout, thereby controlling the output voltage signal Vout. When the input voltage signal Vin transitions from a high level to a low level, a first control signal is output. During the effective period of the first control signal, the output voltage signal Vout gradually decreases until the output voltage signal Vout drops to a preset potential. This embodiment does not require limiting the minimum pulse width of the input voltage signal Vin, nor does it require considering the size of the load capacitance. Compared with related technologies, it simplifies the system design and has higher flexibility and adaptability. Furthermore, because it does not require limiting the minimum pulse width as in related technologies, it can increase the signal frequency of the input voltage signal Vin.

[0060] In this embodiment of the present disclosure, when the input voltage signal Vin is detected to transition from a high level to a low level, the voltage at the output terminal of the gate drive circuit can be continuously reduced by a first control signal until the potential of the output voltage signal Vout drops to a preset voltage. During this process, regardless of whether the input voltage signal Vin transitions to a high level or how short its low-level time is, it will not affect the process. This avoids the rapid transition of the input voltage signal Vin from causing a large current change rate (di / dt) at the output terminal, and avoids oscillating voltage at the output terminal, thereby ensuring the safety and reliability of the circuit.

[0061] For example, the NAND logic circuit Anot can be implemented using NAND gates in related technologies.

[0062] The embodiments disclosed herein do not limit the specific implementation of the level converter 10 and the control circuit 20. Those skilled in the art can implement them according to the actual situation and needs, referring to relevant technologies, as long as the corresponding functions can be achieved.

[0063] For example, the level converter 10 can be implemented using a level shifter or a DC-DC converter. Those skilled in the art can choose the appropriate implementation method according to the actual situation and needs.

[0064] This disclosure does not limit the specific magnitude of the target potential; those skilled in the art can set it according to actual conditions and needs, for example, such as... Figure 1 As shown, assuming the reference potential of the input voltage signal Vin is a low-voltage logic level in the low-voltage domain, the first transistor Q1 is a PMOS transistor, and the second transistor Q2 is an NMOS transistor, then the input voltage signal Vin and the signal output by the control circuit after a NOT logic operation can only drive the second transistor Q2 on the low-voltage side, but cannot drive the first transistor Q1 on the high-voltage side. In this case, the embodiment of this disclosure uses a level converter 10 to perform a level conversion on the signal output by the NOT logic circuit, so as to convert the signal from the reference potential in the low-voltage domain to the target potential (power supply voltage VCC) in the high-voltage domain, thereby enabling the converted signal to drive the first transistor Q1 on the high-voltage side.

[0065] For example, the control circuit 20 can be implemented using a processing component, which in one example includes, but is not limited to, a standalone processor, discrete components, or a combination of a processor and discrete components. The processor may include a controller in an electronic device capable of executing instructions. The processor can be implemented in any suitable manner, for example, by one or more application-specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field-programmable gate arrays (FPGAs), controllers, microcontrollers, microprocessors, or other electronic components. Within the processor, the executable instructions can be executed using hardware circuitry such as logic gates, switches, ASICs, programmable logic controllers, and embedded microcontrollers.

[0066] Of course, the control circuit 20 can also be implemented using a dedicated circuit, which will be described below as an example.

[0067] Please see Figure 2 , Figure 2 A schematic diagram of a gate drive circuit according to an embodiment of the present disclosure is shown.

[0068] In one possible implementation, such as Figure 2 As shown, the control circuit 20 may include a voltage detection and comparison circuit 210, an OR logic circuit I2, an OR NOT logic circuit I4, a pulse generation circuit I5, and an RS flip-flop I6, wherein...

[0069] The input terminal of the voltage detection and comparison circuit 210 serves as the second input terminal of the control circuit 20 (connected to the output voltage signal Vout). The voltage detection and comparison circuit 210 is used to detect the output voltage signal, compare it with the comparison threshold voltage Vref, and output a comparison result signal.

[0070] The output terminal (node ​​B) of the voltage detection and comparison circuit 210 is connected to the first input terminal of the OR logic circuit I2.

[0071] The second input terminal of the OR logic circuit I2 is connected to the second input terminal of the OR NOT logic circuit I4, the set terminal (S) of the RS flip-flop I6, and the output terminal (node ​​E) of the pulse generation circuit I5.

[0072] The output terminal (node ​​C) of the OR logic circuit I2 is connected to the first input terminal (node ​​D) of the OR NOT logic circuit I4.

[0073] The output terminal (node ​​F) of the NOR logic circuit I4 is connected to the reset terminal (R) of the RS flip-flop I6.

[0074] The inverse code output terminal of the RS flip-flop I6 ( As the output terminal of the output control circuit 20,

[0075] The input terminal of the pulse generation circuit I5 serves as the first input terminal of the control circuit 20. The pulse generation circuit I5 is used to output a pulse signal when the input voltage signal Vin changes from a high level to a low level.

[0076] The embodiments disclosed herein do not limit the specific circuit implementation of the voltage detection and comparison circuit 210, the OR logic circuit I2, the OR NOT logic circuit I4, the pulse generation circuit I5, and the RS flip-flop I6. Those skilled in the art can implement them according to the actual situation and needs, referring to relevant technologies.

[0077] For example, the OR logic circuit I2 can employ an OR gate from related technologies to implement an OR logic operation on two inputs.

[0078] For example, the NOR logic circuit I4 can employ a NOR gate from related technologies to implement a two-input NOR logic operation.

[0079] For example, the pulse generation circuit I5 can be implemented using a pulse generator in related technologies. The pulse signal in this embodiment can be a single pulse signal. This embodiment does not limit the pulse width of the pulse signal, and those skilled in the art can set it according to actual conditions and needs.

[0080] For example, the pulse generation circuit I5 can be configured to output a narrow-width high-level pulse when the input voltage signal Vin flips down (from high level to low level).

[0081] The voltage detection and comparison circuit 210 of this disclosure embodiment has voltage detection function and voltage comparison function. This disclosure embodiment limits the specific implementation method of the voltage detection function and voltage comparison function. For example, the voltage detection function can be implemented by a switching device, and the voltage comparison function can be implemented by a voltage comparator. In this disclosure embodiment, the output voltage signal Vout of the gate drive circuit can be sent to the comparator by the switching device to realize voltage comparison. For example, the switching device can be set to normally open type (always in the conducting state) as needed, or it can be turned on or off as needed under the control of the switching control signal.

[0082] In one possible implementation, such as Figure 2As shown, the voltage detection and comparison circuit 210 may include a third transistor Q3 and a comparator I1.

[0083] The drain of the third transistor Q3 serves as the input terminal of the voltage detection and comparison circuit 210.

[0084] The gate of the third transistor Q3 is used to receive a preset bias voltage V1.

[0085] The source (node ​​A) of the third transistor Q3 is connected to the positive input (+) of the comparator I1.

[0086] The negative input terminal (-) of comparator I1 receives the comparison threshold voltage Vref.

[0087] The output terminal of the comparator I1 serves as the output terminal of the voltage detection and comparison circuit 210.

[0088] This embodiment of the disclosure implements voltage detection using a third transistor Q3. For example, if a preset bias voltage V1 is higher than the on-threshold voltage of the third transistor Q3 (e.g., the preset bias voltage V1 is 5V), the third transistor Q3 can be in a normally open state. Since the on-threshold voltage drop of the transistor is reduced, the source and drain voltages of the third transistor Q3 can be considered to be almost the same, thus achieving voltage detection of the output voltage signal Vout. For example, if the output voltage signal Vout is 4V, then the detection voltage at the source of the third transistor Q3 is also approximately 4V.

[0089] For example, such as Figure 2 As shown, the negative input terminal of comparator I1 is connected to the comparison threshold voltage Vref, and the positive input terminal of comparator I1 is connected to the detection voltage output by the third transistor Q3. If the detection voltage at node A is higher than the comparison threshold voltage Vref, then the output terminal of comparator I1 (node ​​B) is high; otherwise, node B is low.

[0090] The embodiments disclosed herein do not limit the specific voltage value of the comparison threshold voltage Vref, which can be set by those skilled in the art according to actual conditions and needs. For example, the comparison threshold voltage Vref can be 1V or 2V.

[0091] In one possible implementation, such as Figure 2 As shown, the control circuit 20 may further include a filter circuit I3, which is disposed between the output terminal of the OR logic circuit I2 and the first input terminal of the OR NOT logic circuit I4. The filter circuit I3 is used to filter the signal output by the OR logic circuit I2.

[0092] This disclosure does not limit the specific implementation of the filter circuit I3. Those skilled in the art can implement it according to actual conditions and needs, referring to relevant technologies. For example, the filter circuit I3 can be a glitch elimination circuit to eliminate glitch signals in the received signal. The specific implementation of the glitch elimination circuit is not limited in this disclosure, as long as it can eliminate glitch signals in the received signal. Thus, when the pulse width of the received signal is less than a certain preset pulse width, the output voltage signal Vout remains unchanged. For example, this disclosure can utilize an RC filter circuit combined with Schmitt triggering to achieve glitch elimination. An RC filter circuit composed of resistors and capacitors is used to perform RC filtering on the received signal. The output of the RC filter circuit is connected to a Schmitt trigger, which performs Schmitt triggering on the RC-filtered signal, thereby outputting a clean signal after glitch elimination. Of course, the filter circuit I3 can also be implemented using digital logic gate integrating filters, digital sampling counting filters, etc. Alternatively, a dedicated integrated filter chip can be used; this disclosure does not limit the implementation of such methods.

[0093] In one possible implementation, the first transistor Q1 can be a PMOS transistor, and the second transistor Q2 and the third transistor Q3 can both be NMOS transistors.

[0094] The following is about Figure 2 The working principle of the gate drive circuit shown is illustrated by way of example.

[0095] Please see Figure 3 , Figure 3 A schematic diagram of the voltage waveforms at each node is shown when the gate drive circuit according to an embodiment of the present disclosure is in operation.

[0096] For example, such as Figure 2 , Figure 3 As shown, assuming the input voltage signal Vin and the output voltage signal Vout are initially at low levels, the voltage at node A is lower than Vref, and the output of comparator I1 is low. Since the output of the single pulse generation circuit I5 (node ​​E) is low in steady state, nodes C and D are both low, and thus the output F of the NOR gate I4 is high. In this way, the RS flip-flop I6 is in the reset state, and its inverse output (i.e., node G) is high.

[0097] When the input voltage signal Vin goes high, the AND-NOT logic circuit Anot outputs a low level, causing the output voltage signal Vout to go high. Once the output voltage signal Vout stabilizes, the voltage at node A is higher than Vref, causing node B to go high, and nodes C and D to go high, while node F goes low. During this process, node E remains low, thus keeping the RS flip-flop I6 in its reset state.

[0098] At a certain moment, the input voltage signal Vin goes low, and the output voltage signal Vout begins to decrease. Simultaneously, node E generates a narrow-width high-level pulse. This pulse sets RS flip-flop I6, causing node G to go low and locking the output of the NOT circuit Anot to a high level. Regardless of whether the input voltage signal Vin changes state, the output voltage signal Vout will continue to be pulled low until the voltage at node A falls below Vref, causing node B to go low. When the single pulse at node E disappears, node C goes low. After a delay, node D also goes low, causing node F to go high. RS flip-flop I6 resets again, node G goes high, and the NOT circuit Anot is unlocked, allowing the output voltage signal Vout to follow the input voltage signal Vin again.

[0099] Based on the above analysis, the embodiments of this disclosure can ensure that the output voltage signal Vout is pulled down to a very low voltage before it begins to flip upwards; coupled with the delay generated by the filter circuit I3 and the single-pulse circuit, in practice, the output voltage signal Vout will be completely pulled down to 0V, thereby achieving complete shutdown. Figure 3 As shown, it can be seen that although the input voltage signal Vin has a narrow downward pulse, the output voltage signal Vout still achieves complete shutdown.

[0100] The gate drive circuit of this disclosure has the following beneficial technical effects:

[0101] There is no need to limit the minimum pulse width of the input voltage signal Vin, thus increasing the maximum operating frequency of the input voltage signal Vin.

[0102] It is insensitive to noise in the input voltage signal Vin, and can achieve complete shutdown even in the presence of narrow pulses caused by noise.

[0103] Without needing to consider the size of the load capacitance, this invention can adapt to load capacitances of different sizes, simplifying system design.

[0104] According to another aspect of this disclosure, a driver chip is provided, the chip including the aforementioned gate driving circuit.

[0105] According to another aspect of this disclosure, a power converter is provided, the power converter including the aforementioned driver chip.

[0106] According to another aspect of this disclosure, a power supply device is provided, the power supply device including the power converter described above.

[0107] The various embodiments of this disclosure have been described above. These descriptions are exemplary and not exhaustive, nor are they limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen to best explain the principles, practical application, or technical improvements to the embodiments in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. A gate driving circuit, characterized in that, The gate driving circuit includes a first transistor, a second transistor, a NAND logic circuit, a level shifter, and a control circuit, wherein... The source of the first transistor is used to connect to the power supply voltage. The gate of the first transistor is connected to the output of the level converter. The drains of the first transistor and the second transistor are connected to form the output terminal of the gate driving circuit, and the output terminal of the gate driving circuit generates an output voltage signal. The output of the NAND logic circuit is connected to the input of the level converter and the gate of the second transistor, and the source of the second transistor is grounded. The level converter is used to convert the reference potential of the output signal of the AND-NOT logic circuit into a target potential. The first input terminal of the control circuit and the first input terminal of the NAND logic circuit are both used to receive input voltage signals. The second input terminal of the control circuit is connected to the output terminal of the gate drive circuit, and the output terminal of the control circuit is connected to the second input terminal of the NAND logic circuit. The control circuit is used for: When the input voltage signal changes from high level to low level, a first control signal is output. During the period when the first control signal is valid, the potential of the output voltage signal gradually decreases. When the potential of the output voltage signal drops to a preset voltage, a second control signal is output, wherein the polarity of the first control signal and the second control signal is opposite.

2. The gate driving circuit according to claim 1, characterized in that, The control circuit includes a voltage detection and comparison circuit, an OR logic circuit, an NOR logic circuit, a pulse generation circuit, and an RS flip-flop, wherein... The input terminal of the voltage detection and comparison circuit serves as the second input terminal of the control circuit. The voltage detection and comparison circuit detects the output voltage signal, compares it with a comparison threshold voltage, and outputs a comparison result signal. The output of the voltage detection and comparison circuit is connected to the first input of the OR logic circuit. The second input terminal of the OR logic circuit is connected to the second input terminal of the NOR logic circuit, the set terminal of the RS flip-flop, and the output terminal of the pulse generation circuit. The output of the OR logic circuit is connected to the first input of the NOR logic circuit. The output of the NOR logic circuit is connected to the reset terminal of the RS flip-flop. The inverse code output of the RS flip-flop serves as the output of the control circuit. The input terminal of the pulse generation circuit serves as the first input terminal of the control circuit. The pulse generation circuit is used to output a pulse signal when the input voltage signal changes from a high level to a low level.

3. The gate driving circuit according to claim 2, characterized in that, The voltage detection and comparison circuit includes a third transistor and a comparator. The drain of the third transistor serves as the input terminal of the voltage detection and comparison circuit. The gate of the third transistor is used to receive a preset bias voltage. The source of the third transistor is connected to the positive input terminal of the comparator. The negative input terminal of the comparator receives the comparison threshold voltage. The output terminal of the comparator serves as the output terminal of the voltage detection and comparison circuit.

4. The gate driving circuit according to claim 2 or 3, characterized in that, The control circuit further includes a filtering circuit, which is disposed between the output terminal of the OR logic circuit and the first input terminal of the OR NOT logic circuit. The filtering circuit is used to filter the signal output by the OR logic circuit.

5. The gate driving circuit according to claim 3, characterized in that, The first transistor is a PMOS transistor, and the second and third transistors are all NMOS transistors.

6. The gate driving circuit according to claim 2, characterized in that, The pulse signal is a single pulse.

7. The gate driving circuit according to claim 1, characterized in that, The level converter includes a level shifting circuit, and the target potential is related to the power supply voltage.

8. A driver chip, characterized in that, The chip includes the gate driving circuit as described in any one of claims 1-7.

9. A power converter, characterized in that, The power converter includes the driver chip as described in claim 8.

10. A power supply device, characterized in that, The power supply equipment includes the power converter as described in claim 9.

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