Output drive circuit and electronic device

Abstract

The application relates to the technical field of driving circuits, and discloses an output driving circuit and electronic equipment, the output driving circuit comprising a driving circuit, the driving circuit comprising a plurality of driving modules, for each driving module, a data signal input end of the driving module being electrically connected to a signal output end of a pre-driving circuit; a pulse signal input end of the driving module being electrically connected to a pulse output end of a swing rate control circuit; and a signal output end of the driving module being used for outputting a driving sub-signal; through the driving circuit, a target data signal output by the pre-driving circuit is subjected to swing rate adjustment processing by using a pulse signal output by the swing rate control circuit, so that a driving signal composed of driving sub-signals output by all the driving modules is output; wherein the swing rate adjustment processing is used for accelerating a flip edge of the target data signal. It can be seen that the application can improve swing rate control accuracy of output driving in high-speed transmission application, thereby improving signal transmission accuracy.

Description

Technical Field

[0001] This invention relates to the field of drive circuit technology, and in particular to an output drive circuit and electronic device. Background Technology

[0002] With technological advancements, the demand for high-speed transmission is becoming increasingly prominent, and the requirements for signal integrity are becoming more stringent. Among these, achieving a high slew rate in output drive has become a key bottleneck in improving signal quality.

[0003] Currently, the industry's main technology for output-driven slew rate control is to create selectable delays using cascaded inverters. These delays are then used to sequentially turn on the output drive transistors, thereby adjusting the slew rate. However, in this method of cascaded inverters, the delay of a single-stage inverter can still meet the slew rate control requirements at a data transmission rate of 3200Mb / s. But when the data transmission rate increases to 6400Mb / s or higher, the delay of the single-stage inverter exceeds the signal flip-edge time, rendering the slew rate control ineffective and unable to meet the precise slew rate adjustment requirements of higher-speed applications.

[0004] Therefore, it is particularly important to propose a technical solution that can improve the accuracy of output drive slew rate control in high-speed transmission applications, thereby improving the accuracy of signal transmission. Summary of the Invention

[0005] This invention provides an output drive circuit and electronic device that can improve the slew rate control accuracy of the output drive in high-speed transmission applications, thereby improving the accuracy of signal transmission.

[0006] To address the aforementioned technical problems, the first aspect of this invention discloses an output driving circuit, which includes a driving circuit comprising a plurality of driving modules, wherein: For each of the drive modules, the pulse signal input terminal of the drive module is used to electrically connect to the pulse output terminal of the slew rate control circuit; the data signal input terminal of the drive module is used to electrically connect to the signal output terminal of the pre-drive circuit; and the signal output terminal of the drive module is used to output the drive sub-signal. Each of the driving modules is configured to receive the target data signal output by the pre-driving circuit and the pulse signal output by the slew rate control circuit; and to perform slew rate adjustment processing on the target data signal using the pulse signal to output the processed driving sub-signal; wherein the slew rate adjustment processing is used to accelerate the flip edge of the target data signal; and the driving signal output by the driving circuit is composed of the driving sub-signals output by all the driving modules.

[0007] As an optional implementation, in the first aspect of the present invention, the pulse signal includes a first pulse signal and a second pulse signal; And each of the driving modules includes a first driving submodule and a second driving submodule, wherein: The first data signal input terminal of the first driving submodule is used to electrically connect to the first signal output terminal of the pre-driving circuit, the second data signal input terminal of the first driving submodule is used to electrically connect to the second signal output terminal of the pre-driving circuit, and the pulse signal input terminal of the first driving submodule is used to electrically connect to the first pulse output terminal of the slew rate control circuit. The data signal input terminal of the second driving submodule is used to electrically connect to the third signal output terminal of the pre-driving circuit, and the pulse signal input terminal of the second driving submodule is used to electrically connect to the second pulse output terminal of the slew rate control circuit. The output terminal of the first driving submodule is electrically connected to the output terminal of the second driving submodule; the power supply terminal of the first driving submodule and the power supply terminal of the second driving submodule are used to electrically connect to the power supply, and the ground terminal of the first driving submodule and the ground terminal of the second driving submodule are used to electrically connect to the reference ground. The first driving submodule is used to accelerate the rising edge of the desired output driving sub-signal using the received first pulse signal; The second driving submodule is used to accelerate the falling edge of the desired output driving sub-signal using the received second pulse signal.

[0008] As an optional implementation, in a first aspect of the present invention, the first driving submodule includes a first driving unit and an auxiliary pull-up unit, wherein: The first terminal of the first driving unit is electrically connected to the first signal output terminal of the pre-driving circuit; the second terminal of the first driving unit is electrically connected to the first pulse output terminal of the slew rate control circuit; the third terminal of the first driving unit is electrically connected to the power supply; the fourth terminal of the first driving unit is electrically connected to the reference ground; the first terminal of the auxiliary pull-up unit is electrically connected to the first pulse output terminal of the slew rate control circuit, and the second terminal of the auxiliary pull-up unit is electrically connected to the power supply; the fifth terminal of the first driving unit is electrically connected to the third terminal of the auxiliary pull-up unit, and the sixth terminal of the first driving unit is electrically connected to the output terminal of the second driving submodule. The auxiliary pull-up unit is used to turn on the auxiliary pull-up unit using the first pulse signal when the driving module needs to output a high-level driving sub-signal, so as to provide a transient acceleration current to the first driving unit, thereby accelerating the rising edge of the required output driving sub-signal.

[0009] As an optional implementation, in a first aspect of the present invention, the second driving submodule includes a second driving unit and an auxiliary pull-down unit, wherein: The first end of the second driving unit is used to electrically connect to the third signal output end of the pre-driving circuit, and the second end of the second driving unit is used to electrically connect to the power supply. The first end of the auxiliary pull-down unit is used to electrically connect to the second pulse output end of the slew rate control circuit, and the second end of the auxiliary pull-down unit is used to electrically connect to the reference ground; The third end of the second driving unit is electrically connected to the third end of the auxiliary pull-down unit and the output end of the first driving submodule, respectively. The auxiliary pull-down unit is used to turn on the auxiliary pull-down unit using the second pulse signal when the driving module needs to output a low-level driving sub-signal, so as to provide a discharge path to the second driving unit and thereby accelerate the falling edge of the required output driving sub-signal.

[0010] As an optional implementation, in the first aspect of the invention, each of the driving modules further includes a protection submodule, wherein: The first terminal of the protection submodule is electrically connected to the output terminal of the first drive submodule, the second terminal of the protection submodule is electrically connected to the output terminal of the second drive submodule, and the third terminal of the protection submodule is used to output the drive sub-signal of the drive module.

[0011] As an optional implementation, in the first aspect of the invention, the output drive circuit further includes a slew rate control circuit, wherein: The signal input terminal of the slew rate control circuit is used to receive the initial data signal, and the first pulse output terminal and the second pulse output terminal of the slew rate control circuit are electrically connected to the pulse signal input terminal of each of the drive modules, respectively. The slew rate control circuit is used to perform delay gating processing on the received initial data signal to output the processed pulse signal.

[0012] As an optional implementation, in a first aspect of the present invention, the slew rate control circuit includes a first slew rate control module and a second slew rate control module, wherein: The first terminal of the first slew rate control module is used to receive the initial data signal, and the pulse output terminal of the first slew rate control module is electrically connected to the first pulse signal input terminal of each of the drive modules. The second terminal of the second slew rate control module is used to receive the initial data signal, and the pulse output terminal of the second slew rate control module is electrically connected to the second pulse signal input terminal of each of the drive modules. The first slew rate control module is used to perform delay gating processing on the initial data signal to output the processed first pulse signal; The second slew rate control module is used to perform delay gating processing on the inverted data signal corresponding to the initial data signal, so as to output the processed second pulse signal.

[0013] As an optional implementation, in a first aspect of the present invention, the first slew rate control module includes a first inverting unit, a first delay unit, a first NAND gate unit, and a second inverting unit, wherein: The input terminal of the first inverting unit and the first input terminal of the first NAND gate unit are respectively used to receive the initial data signal. The output terminal of the first inverting unit is electrically connected to the input terminal of the first delay unit. The output terminal of the first delay unit is electrically connected to the second input terminal of the first NAND gate unit. The output terminal of the first NAND gate unit is electrically connected to the input terminal of the second inverting unit. The output terminal of the second inverting unit is electrically connected to the first pulse signal input terminal of each of the driving modules. And / or, the second slew rate control module includes a third inverting unit, a fourth inverting unit, a second delay unit, a second NAND gate unit, and a fifth inverting unit, wherein: The input terminal of the third inverting unit is used to receive the initial data signal. The output terminal of the third inverting unit is electrically connected to the input terminal of the fourth inverting unit and the first input terminal of the second NAND gate unit. The output terminal of the fourth inverting unit is electrically connected to the input terminal of the second delay unit. The output terminal of the second delay unit is electrically connected to the second input terminal of the second NAND gate unit. The output terminal of the second NAND gate unit is electrically connected to the input terminal of the fifth inverting unit. The output terminal of the fifth inverting unit is electrically connected to the second pulse signal input terminal of each of the driving modules.

[0014] As an optional implementation, in the first aspect of the present invention, the output driving circuit further includes a pre-driving circuit, wherein: The signal input terminal of the pre-drive circuit is used to receive the initial data signal, and the first signal output terminal, the second signal output terminal, and the third signal output terminal of the pre-drive circuit are electrically connected to the data signal input terminal of each drive module, respectively. The pre-driving circuit is used to perform signal shaping processing on the received initial data signal to obtain a target data signal; and output the target data signal to the driving circuit; wherein the driving capability of the target data signal is better than the driving capability of the initial data signal.

[0015] A second aspect of the present invention discloses an electronic device, the electronic device comprising a device body and an output driving circuit as disclosed in any of the first aspects.

[0016] Compared with the prior art, the present invention has the following beneficial effects: Implementing this invention provides a simple and easy-to-implement output driving circuit. This output driving circuit includes a driving circuit comprising several driving modules. By utilizing the pulse signal output by the slew rate control circuit, the driving circuit accelerates the flip edge of the target data signal output by the pre-driving circuit, thereby controlling the slew rate of the data signal to output a driving signal composed of the driving sub-signals output by all driving modules. This improves the accuracy of slew rate control in high-speed transmission applications, thereby enhancing signal transmission integrity, signal quality, and ultimately, signal transmission accuracy. Furthermore, it saves space occupied by the output driving circuit, reducing driving costs. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This is a schematic diagram of the structure of an output driving circuit disclosed in an embodiment of the present invention; Figure 2 This is a schematic diagram of another output driving circuit disclosed in an embodiment of the present invention; Figure 3 This is a schematic diagram of another output driving circuit disclosed in an embodiment of the present invention; Figure 4 This is a schematic diagram of another output driving circuit disclosed in an embodiment of the present invention; Figure 5 This is a schematic diagram of the slew rate control circuit disclosed in an embodiment of the present invention; Figure 6 This is a schematic diagram of another slew rate control circuit disclosed in an embodiment of the present invention; Figure 7 This is a signal timing diagram of an output driving circuit disclosed in an embodiment of the present invention; Figure 8 This is a schematic diagram of the structure of an electronic device disclosed in an embodiment of the present invention. Detailed Implementation

[0019] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0020] It should be noted that, unless otherwise explicitly specified and limited, the term "electrical connection" in the specification, claims, and accompanying drawings of this invention should be interpreted broadly. For example, it can refer to a fixed electrical connection, a detachable electrical connection, or an integral electrical connection; it can be a mechanical electrical connection, an electrical-electrical connection, or a connection capable of communication; it can be a direct connection or an indirect connection through an intermediate medium; it can refer to the internal connection of two elements or the interaction between two elements. Furthermore, the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish different objects, not to describe a specific order. The terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0021] Example 1 Please see Figure 1 , Figure 1 This is a schematic diagram of an output driving circuit disclosed in an embodiment of the present invention. This circuit can be applied to electronic devices requiring high-speed data transmission, such as electronic devices implementing high-speed interface data transmission; however, this embodiment of the present invention does not impose limitations. Figure 1 As shown, the output drive circuit may include a drive circuit 10, which includes a plurality of drive modules 101-10N, wherein: For each drive module, the pulse signal input terminal of the drive module is used to electrically connect to the pulse output terminal of the slew rate control circuit 20; the data signal input terminal of the drive module is used to electrically connect to the signal output terminal of the pre-drive circuit 30; and the signal output terminal of the drive module is used to output the drive sub-signal.

[0022] Each drive module is used to receive the target data signal output by the pre-drive circuit 30 and the pulse signal output by the slew rate control circuit 20; and to use the pulse signal to perform slew rate adjustment processing on the target data signal to output the processed drive sub-signal; wherein, the slew rate adjustment processing is used to accelerate the flip edge of the target data signal.

[0023] The drive signal output by the drive circuit 10 is composed of the drive sub-signals output by all drive modules.

[0024] Optionally, the driving circuit 10 can output the aforementioned driving signal to the load; however, this embodiment of the invention does not impose any limitations on this.

[0025] As can be seen, the embodiments of the present invention provide an output driving circuit that is simple in structure and easy to implement. The output driving circuit includes a driving circuit and several driving modules. The driving circuit can accelerate the flip edge of the target data signal output by the pre-driving circuit by using the pulse signal output by the slew rate control circuit, thereby realizing slew rate control of the data signal to output a driving signal composed of driving sub-signals output by all driving modules. This can improve the accuracy of slew rate control of the output drive in high-speed transmission applications, thereby improving the signal transmission integrity, improving signal quality, and thus improving signal transmission accuracy. In addition, it can also save the area occupied by the output driving circuit, which is beneficial to reducing the driving cost.

[0026] In an optional embodiment, the pulse signal may include a first pulse signal and a second pulse signal; further optionally, the first pulse signal may be output from the first pulse output terminal of the slew rate control circuit 20, and the second pulse signal may be output from the second pulse output terminal of the slew rate control circuit 20, which is not limited in this embodiment. Further, the first pulse signal and the second pulse signal may each include a set of pulse sub-signals, and the number of each set of pulse sub-signals may match the number of drive sub-modules.

[0027] Optionally, the target data signal may include a first data signal, a second data signal, and a third data signal, which is not limited in this embodiment of the invention. Further, optionally, the first data signal may be output from the first signal output terminal of the pre-drive circuit 30, the second data signal may be output from the second signal output terminal of the pre-drive circuit 30, and the third data signal may be output from the third signal output terminal of the pre-drive circuit 30, which is not limited in this embodiment of the invention. Further, the first data signal, the second data signal, and the third data signal may each include a set of data sub-signals, and the number of each set of data sub-signals may match the number of drive sub-modules.

[0028] In this optional embodiment, each driver module may optionally include a first driver submodule and a second driver submodule; optionally, please refer to... Figure 2 , Figure 2 This is a schematic diagram of another output driving circuit disclosed in an embodiment of the present invention; as shown Figure 2 As shown, taking the driver module 101 as an example, the driver module 101 may include a first driver submodule 1011 and a second driver submodule 1012, wherein: The first data signal input terminal of the first driving submodule 1011 is used to electrically connect to the first signal output terminal of the pre-driving circuit 30, the second data signal input terminal of the first driving submodule 1011 is used to electrically connect to the second signal output terminal of the pre-driving circuit 30, and the pulse signal input terminal of the first driving submodule 1011 is used to electrically connect to the first pulse output terminal of the slew rate control circuit 20. The data signal input terminal of the second drive submodule 1012 is used to electrically connect to the third signal output terminal of the pre-drive circuit 30, and the pulse signal input terminal of the second drive submodule 1012 is used to electrically connect to the second pulse output terminal of the slew rate control circuit 20. The output terminal of the first driving submodule 1011 is electrically connected to the output terminal of the second driving submodule 1012; the power supply terminal of the first driving submodule 1011 and the power supply terminal of the second driving submodule 1012 are used to electrically connect to the power supply, and the ground terminal of the first driving submodule 1011 and the ground terminal of the second driving submodule 1012 are used to electrically connect to the reference ground. The first driving submodule 1011 is used to accelerate the rising edge of the required output driving sub-signal by utilizing the received first pulse signal. The second driving submodule 1012 is used to accelerate the falling edge of the desired output driving sub-signal by utilizing the received second pulse signal.

[0029] The signal output by the first driving submodule 1011 and the signal output by the second driving submodule 1012 constitute the driving sub-signal output by the driving module 101.

[0030] As can be seen, by setting a first driving submodule and a second driving submodule in each driving module, this optional embodiment can use the first pulse signal and the second pulse signal output by the slew rate control circuit to accelerate the rising edge and falling edge of the required output driving sub-signal respectively, thereby improving the accuracy of the acceleration signal flipping edge, which is conducive to further improving the accuracy and speed of the slew rate control of the output drive.

[0031] In this optional embodiment, the first drive submodule may optionally include a first drive unit and an auxiliary pull-up unit; optionally, please refer to... Figure 4 , Figure 4 This is a schematic diagram of another output drive circuit disclosed in an embodiment of the present invention; as shown below. Figure 4 As shown, taking the drive module 101 as an example, the first drive submodule 1011 may include a first drive unit 10111 and an auxiliary pull-up unit 10112, wherein: The first terminal of the first driving unit 10111 is electrically connected to the first signal output terminal of the pre-driving circuit 30; the second terminal of the first driving unit 10111 is electrically connected to the first pulse output terminal of the slew rate control circuit 20; the third terminal of the first driving unit 10111 is electrically connected to the power supply; the fourth terminal of the first driving unit 10111 is electrically connected to the reference ground; the first terminal of the auxiliary pull-up unit 10112 is electrically connected to the first pulse output terminal of the slew rate control circuit 20, and the second terminal of the auxiliary pull-up unit 10112 is electrically connected to the power supply; the fifth terminal of the first driving unit 10111 is electrically connected to the third terminal of the auxiliary pull-up unit 10112, and the sixth terminal of the first driving unit 10111 is electrically connected to the output terminal of the second driving submodule 1012; The auxiliary pull-up unit 10112 is used to turn on the auxiliary pull-up unit 10112 with the first pulse signal when the drive module needs to output a high-level drive sub-signal, so as to provide a transient acceleration current to the first drive unit 10111, thereby accelerating the rising edge of the required output drive sub-signal.

[0032] Optionally, and more specifically, the auxiliary pull-up unit 10112 is used to turn on the auxiliary pull-up unit 10112 using the first pulse signal when the first driving unit 10111 is at a low level, so as to provide a transient acceleration current to the first driving unit 10111, thereby accelerating the rising edge of the required output driving sub-signal. This embodiment of the invention does not limit the scope of the invention.

[0033] Optionally, the power supply can be a data interface power supply, and the reference ground can be a data interface ground; this embodiment of the invention is not limited thereto. For example, such as... Figure 4 As shown, the power supply can be Figure 4 The MVDDQ shown can be referenced to the ground. Figure 4 The MVSS shown in this embodiment of the invention is not limited.

[0034] For example, such as Figure 4 As shown, the first data signal can be DRUPP, the second data signal can be DRDNN, the third data signal can be DRUPN, the first pulse signal can be SLUP, and the second pulse signal can be SLDN. This embodiment of the invention does not impose any limitations.

[0035] It is evident that by setting a first driving unit and an auxiliary pull-up unit in the first driving submodule, when a high-level driving signal needs to be output, i.e. when the first driving unit is at a low level, the auxiliary pull-up unit can be turned on by the first pulse signal, thereby providing a transient acceleration current to the first driving unit and realizing the rising edge of the acceleration signal. In this way, by precisely setting the connection relationship of the auxiliary pull-up unit, the pull-up driving capability of the auxiliary pull-up unit to assist the first driving unit can be further improved, and the accuracy of the first pulse signal acting on the driving circuit can be improved by using the precisely output first pulse signal, thereby improving the acceleration accuracy of the signal rising edge, which in turn helps to further improve the accuracy and speed of the slew rate control of the output drive.

[0036] In this optional embodiment, the first driving unit may optionally include a pull-up driving subunit and a pull-down driving subunit; optionally, as... Figure 4 As shown, taking the driver module 101 as an example, the first driver unit 10111 may include a pull-up driver subunit 101111 and a pull-down driver subunit 101112, wherein: The first terminal of the pull-up drive subunit 101111 is used to electrically connect to the first signal output terminal of the pre-drive circuit 30, and the second terminal of the pull-up drive subunit 101111 is used to electrically connect to the power supply. The first terminal of the pull-down drive subunit 101112 is used to electrically connect to the second signal output terminal of the pre-drive circuit 30, and the second terminal of the pull-down drive subunit 101112 is used to electrically connect to the reference ground. The third terminal of the pull-up drive subunit 101111 is electrically connected to the third terminal of the pull-down drive subunit 101112, the third terminal of the auxiliary pull-up unit 10112, and the output terminal of the second drive submodule 1012.

[0037] The pull-up driver subunit is used to turn on when the driver module needs to output a high-level driver sub-signal, so as to provide pull-up drive. The pull-down driver subunit is used to turn on when the driver module needs to output a low-level driver sub-signal, so as to provide pull-down drive.

[0038] More specifically, the auxiliary pull-up unit 10112 is used to turn on the auxiliary pull-up unit 10112 using a first pulse signal when the pull-up drive subunit 101111 is at a low level, so as to provide a transient acceleration current to the pull-up drive subunit 101111, thereby accelerating the rising edge of the required output drive sub-signal.

[0039] Optionally, the first data signal is used to control the on / off state of the first number of pull-up driving sub-units in the driving circuit, the second data signal is used to control the on / off state of the second number of pull-down driving sub-units in the driving circuit, and the first pulse signal is used to control the on / off state of the first number of auxiliary pull-up units in the driving circuit. This embodiment of the invention does not limit the scope of the invention.

[0040] It is evident that by setting up pull-up and pull-down drive sub-units in the first drive unit, the target data signal can be converted into a signal with better drive capability and the signal can be output stably, thereby improving the output stability and reliability of the first drive sub-module.

[0041] In this optional embodiment, the second driving submodule may optionally include a second driving unit and an auxiliary pull-down unit; optionally, as... Figure 4 As shown, taking the drive module 101 as an example, the second drive submodule 1012 may include a second drive unit 10121 and an auxiliary pull-down unit 10122, wherein: The first end of the second driving unit 10121 is used to electrically connect to the third signal output end of the pre-driving circuit 30, and the second end of the second driving unit 10121 is used to electrically connect to the power supply. The first terminal of the auxiliary pull-down unit 10122 is used to electrically connect to the second pulse output terminal of the slew rate control circuit 20, and the second terminal of the auxiliary pull-down unit 10122 is used to electrically connect to the reference ground. The third terminal of the second drive unit 10121 is electrically connected to the third terminal of the auxiliary pull-down unit 10122 and the output terminal of the first drive submodule 1011, respectively. The auxiliary pull-down unit 10122 is used to turn on the auxiliary pull-down unit 10122 with the second pulse signal when the drive module needs to output a low-level drive sub-signal, so as to provide a discharge path to the second drive unit 10121, thereby accelerating the falling edge of the required output drive sub-signal.

[0042] Optionally, and more specifically, the auxiliary pull-down unit 10122 is used to turn on the auxiliary pull-down unit 10122 by using the second pulse signal when the second driving unit 10121 is at a high level, so as to provide a discharge path to the second driving unit 10121, thereby accelerating the falling edge of the required output driving sub-signal.

[0043] The second driving unit is used to turn on when the driving module needs to output a high-level driving sub-signal, so as to provide pull-up drive.

[0044] Optionally, the third data signal is used to control the on / off state of the second driving unit of the third driving quantity in the driving circuit, and the second pulse signal is used to control the on / off state of the auxiliary pull-down unit of the second pulse control quantity in the driving circuit. This embodiment of the invention does not limit the scope of the invention.

[0045] As can be seen, by setting a second driving unit and an auxiliary pull-down unit in the second driving submodule, when a low-level driving signal needs to be output, that is, when the second driving unit is at a low level, the auxiliary pull-down unit can be turned on by the second pulse signal, thereby providing a discharge path to the second driving unit and accelerating the falling edge of the signal. In this way, by precisely setting the connection relationship of the auxiliary pull-down unit, the pull-down driving capability of the auxiliary pull-down unit to assist the second driving unit can be further improved, and the accuracy of the second pulse signal acting on the driving circuit can be improved by using the precisely output second pulse signal, thereby improving the acceleration accuracy of the signal falling edge, which in turn helps to further improve the accuracy and speed of the output drive slew rate control.

[0046] In this optional embodiment, each driver module may optionally include a protection submodule; optionally, such as Figure 4 As shown, taking the drive module 101 as an example, the drive module 101 may further include a protection submodule 1013, wherein: The first terminal of the protection submodule 1013 is electrically connected to the output terminal of the first drive submodule 1011, the second terminal of the protection submodule 1013 is electrically connected to the output terminal of the second drive submodule 1012, and the third terminal of the protection submodule 1013 is used to output the drive sub-signal of the drive module 101.

[0047] The protection submodule can be used to perform impedance matching on the first drive submodule and the second drive submodule.

[0048] Optional, such as Figure 4 As shown, the protection submodule 1013 may include a first protection unit 10131 and a second protection unit 10132, wherein: The first end of the first protection unit 10131 is electrically connected to the output end of the first drive submodule 1011, the first end of the second protection unit 10132 is electrically connected to the output end of the second drive submodule 1012, the second end of the first protection unit 10131 is electrically connected to the second end of the second protection unit 10132, and the second ends of the first protection unit 10131 and the second ends of the second protection unit 10132 are used to output the drive sub-signal of the drive module 101.

[0049] Further optional, such as Figure 4 As shown, the first protection unit 10131 may include a first impedance adjustment resistor RDN, and the second protection unit 10132 may include a second impedance adjustment resistor RUP, wherein: The first end of the first resistor RDN is electrically connected to the output end of the first driving submodule 1011, the first end of the second resistor RUP is electrically connected to the output end of the second driving submodule 1012, the second end of the first resistor RDN is electrically connected to the second end of the second resistor RUP, and the second ends of the first resistor RDN and the second end of the second resistor RUP are used to output the driving sub-signal of the driving module 101.

[0050] It is evident that by setting a protection submodule in the drive module circuit, the drive signal can be prevented from being reflected back to the drive circuit, thereby improving the transmission efficiency of the drive signal and achieving maximum power output.

[0051] In this optional embodiment, optionally, such as Figure 4 As shown, the pull-up drive subunit 101111 may include a first pull-up switch device MP1, the pull-down drive subunit 101112 may include a pull-down switch device MN1, and the auxiliary pull-up unit 10112 may include an auxiliary pull-up switch device MN2, wherein: The first terminal of the first pull-up switch device MP1 is electrically connected to the first signal output terminal of the pre-drive circuit 30, and the second terminal of the first pull-up switch device MP1 is electrically connected to the power supply; the first terminal of the pull-down switch device MN1 is electrically connected to the second signal output terminal of the pre-drive circuit 30, and the second terminal of the pull-down switch device MN1 is electrically connected to the reference ground; the first terminal of the auxiliary pull-up switch device MN2 is electrically connected to the first pulse output terminal of the slew rate control circuit 20, and the second terminal of the auxiliary pull-up switch device MN2 is electrically connected to the power supply; the third terminal of the first pull-up switch device MP1 is electrically connected to the third terminal of the pull-down switch device MN1, the third terminal of the auxiliary pull-up switch device MN2, and the first terminal of the first resistor RDN, respectively.

[0052] Optionally, the pull-up drive subunit 101111 may include at least one first pull-up switch device MP1, the pull-down drive subunit 101112 may include at least one pull-down switch device MN1, and the auxiliary pull-up unit 10112 may include at least one auxiliary pull-up switch device MN2. This embodiment of the invention does not limit the scope of the invention.

[0053] Optionally, the switching devices in this embodiment (such as the first pull-up switch device MP1, the pull-down switch device MN1, and the auxiliary pull-up switch device MN2) may include, but are not limited to, any device or component that can play an equal driving role, such as N-type MOS transistors and P-type MOS transistors. This allows for the selection of appropriate driving devices based on the actual situation of the components, thereby improving the applicability of the circuit. For example, when the first pull-up switch device MP1 is a P-type MOS transistor, the first terminal of the first pull-up switch device MP1 is the gate (G), the second terminal of the first pull-up switch device MP1 is the source (S), and the third terminal of the first pull-up switch device MP1 is the drain (D); when the pull-down switch device MN1 is an N-type MOS transistor, the first terminal of the pull-down switch device MN1 is the gate (G), the second terminal of the pull-down switch device MN1 is the source (S), and the third terminal of the pull-down switch device MN1 is the drain (D); when the auxiliary pull-up switch device MN2 is an N-type MOS transistor, the first terminal of the auxiliary pull-up switch device MN2 is the gate (G), the second terminal of the auxiliary pull-up switch device MN2 is the drain (D), and the third terminal of the auxiliary pull-up switch device MN2 is the source (S). This embodiment of the invention is not limited.

[0054] It is evident that by using different types of switching devices (such as N-type MOSFETs and P-type MOSFETs) to construct the first driving unit, the switching states of each device can be controlled efficiently and accurately under low power consumption, thereby improving the driving control efficiency and accuracy of the first driving unit, which in turn helps to further improve the slew rate control efficiency and accuracy of the output drive.

[0055] In this optional embodiment, optionally, such as Figure 4 As shown, the second drive unit 10121 may include a second pull-up switch device MN3, and the auxiliary pull-down unit 10122 may include an auxiliary pull-down switch device MN4, wherein: The first terminal of the second pull-up switch MN3 is electrically connected to the third signal output terminal of the pre-drive circuit 30, and the second terminal of the second pull-up switch MN3 is electrically connected to the power supply; the first terminal of the auxiliary pull-down switch MN4 is electrically connected to the second pulse output terminal of the slew rate control circuit 20, and the second terminal of the auxiliary pull-down switch MN4 is electrically connected to the reference ground; the third terminal of the second pull-up switch MN3 is electrically connected to the third terminal of the auxiliary pull-down switch MN4 and the output terminal of the first terminal of the second resistor RUP, respectively.

[0056] Optionally, the second drive unit 10121 may include at least one second pull-up switch device MN3, and the auxiliary pull-down unit 10122 may include at least one auxiliary pull-down switch device MN4. This embodiment of the invention does not limit the scope of the invention.

[0057] Optionally, the switching devices in this embodiment (such as the second pull-up switch MN3 and the auxiliary pull-down switch MN4) can be any device or component that can play an equivalent driving role, including but not limited to N-type MOSFETs and P-type MOSFETs. This allows for the selection of appropriate driving devices based on the actual situation of the components, thereby improving the applicability of the circuit. For example, when the second pull-up switch MN3 is an N-type MOSFET, its first terminal is the gate (G), its second terminal is the drain (D), and its third terminal is the source (S). When the auxiliary pull-down switch MN4 is an N-type MOSFET, its first terminal is the gate (G), its second terminal is the source (S), and its third terminal is the drain (D). This embodiment of the invention does not impose any limitations on this.

[0058] It is evident that by using different types of switching devices (such as N-type MOSFETs and P-type MOSFETs) to construct the second driving unit, the switching states of each device can be controlled efficiently and accurately under low power consumption, thereby improving the driving control efficiency and accuracy of the second driving unit, which in turn helps to further improve the slew rate control efficiency and accuracy of the output drive.

[0059] In an optional embodiment, such as Figure 4 As shown, the output drive circuit may further include a pull-down circuit 40, wherein: The first terminal of the pull-down circuit 40 is electrically connected to the signal output terminal of each drive module, and the second terminal of the pull-down circuit 40 is used for grounding.

[0060] Optional, such as Figure 4 As shown, the pull-down circuit 40 may include a pull-down resistor Rout, wherein: The first terminal of the pull-down resistor Rout is electrically connected to the signal output terminal of each driver module, and the second terminal of the pull-down resistor Rout is used for grounding.

[0061] As can be seen, this optional embodiment achieves voltage division of the circuit structure related to the pull-up drive by setting a pull-down circuit in the output drive circuit, thereby obtaining a high-level signal for the output drive; and the pull-down circuit can further improve the output stability of the drive signal through impedance matching, thereby improving the stability of the circuit.

[0062] In an optional embodiment, please refer to Figure 3 , Figure 3 This is a schematic diagram of another output drive circuit disclosed in an embodiment of the present invention; as shown below. Figure 3 As shown, the output drive circuit may further include a slew rate control circuit 20, wherein: The signal input terminal of the slew rate control circuit 20 is used to receive the initial data signal, and the first pulse output terminal and the second pulse output terminal of the slew rate control circuit 20 are electrically connected to the pulse signal input terminal of each drive module 101, respectively. The slew rate control circuit 20 is used to perform delay gating processing on the received initial data signal to output the processed pulse signal.

[0063] As can be seen, this optional embodiment can improve the accuracy and efficiency of processing the initial data signal while improving the output accuracy of the pulse signal by setting a slew rate control circuit in the output drive circuit, thereby further improving the slew rate control accuracy of the output drive.

[0064] In this optional embodiment, the slew rate control circuit 20 may optionally include a first slew rate control module 201 and a second slew rate control module 202, wherein: The first terminal of the first slew rate control module 201 is used to receive the initial data signal, and the pulse output terminal of the first slew rate control module 201 is electrically connected to the first pulse signal input terminal of each drive module 101. The second terminal of the second slew rate control module 202 is used to receive the initial data signal, and the pulse output terminal of the second slew rate control module 202 is electrically connected to the second pulse signal input terminal of each drive module 101. The first slew rate control module 201 is used to perform delay gating processing on the initial data signal to output the processed first pulse signal; The second slew rate control module 202 is used to perform delay gating processing on the inverted data signal corresponding to the initial data signal, so as to output the processed second pulse signal.

[0065] More specifically, the second slew rate control module 202 can first invert the initial data signal to obtain the inverted data signal corresponding to the initial data signal, and then perform delay gating on the inverted data signal to output the processed second pulse signal.

[0066] It is evident that by setting a first slew rate control module and a second slew rate control module in the slew rate control circuit, the generation accuracy of pulse signals for different flip edges can be improved, thereby further improving the output accuracy of the pulse signal.

[0067] In this optional embodiment, optionally, please refer to Figure 5 , Figure 5 This is a schematic diagram of a slew rate control circuit disclosed in an embodiment of the present invention; as shown below. Figure 5As shown, the first slew rate control module 201 may include a first inverting unit 2011, a first delay unit 2012, a first NAND gate unit 2013, and a second inverting unit 2014, wherein: The input terminal of the first inverter unit 2011 and the first input terminal of the first NAND gate unit 2013 are used to receive the initial data signal. The output terminal of the first inverter unit 2011 is electrically connected to the input terminal of the first delay unit 2012. The output terminal of the first delay unit 2012 is electrically connected to the second input terminal of the first NAND gate unit 2013. The output terminal of the first NAND gate unit 2013 is electrically connected to the input terminal of the second inverter unit 2014. The output terminal of the second inverter unit 2014 is electrically connected to the first pulse signal input terminal of each driving module 101.

[0068] Optionally, the inverting units in this embodiment (such as the first inverting unit and the second inverting unit) can be inverters, and this embodiment of the invention does not limit them.

[0069] For example, such as Figure 5 As shown, the initial data signal can be DATA. After processing by the first inverting unit 2011 and the first delay unit 2012, the resulting signal can be DATAb_delay. The signal output by the second inverting unit 2014 is SLUP, which is the first pulse signal. The timing of the signals DATA, DATAb_delay, and SLUP can be found in [reference needed]. Figure 5 .

[0070] It is evident that by setting a first inverting unit, a first delay unit, a first NAND gate unit, and a second inverting unit in the first slew rate control module, the output first pulse signal can be applied to the rising edge of the data signal, thereby enhancing the signal only when it rises and flips, and not affecting the normal output high and low levels at other times. This further improves the generation accuracy of the first pulse signal for the rising edge, which in turn helps to further improve the output accuracy of the first pulse signal, and thus helps to further improve the slew rate control accuracy of the output drive.

[0071] In this optional embodiment, optionally, please refer to Figure 6 , Figure 6 This is a schematic diagram of another slew rate control circuit disclosed in an embodiment of the present invention; as shown. Figure 6 As shown, the second slew rate control module 202 includes a third inverting unit 2021, a fourth inverting unit 2022, a second delay unit 2023, a second NAND gate unit 2024, and a fifth inverting unit 2025, wherein: The input terminal of the third inverter unit 2021 is used to receive the initial data signal. The output terminal of the third inverter unit 2021 is electrically connected to the input terminal of the fourth inverter unit 2022 and the first input terminal of the second NAND gate unit 2024. The output terminal of the fourth inverter unit 2022 is electrically connected to the input terminal of the second delay unit 2023. The output terminal of the second delay unit 2023 is electrically connected to the second input terminal of the second NAND gate unit 2024. The output terminal of the second NAND gate unit 2024 is electrically connected to the input terminal of the fifth inverter unit 2025. The output terminal of the fifth inverter unit 2025 is electrically connected to the second pulse signal input terminal of each driving module 101.

[0072] For example, such as Figure 6 As shown, the initial data signal can be DATA; the signal obtained after DATA is processed by the third inverting unit 2021 can be DATAb; the signal obtained after DATAb is processed by the fourth inverting unit 2022 and the second delay unit 2023 can be DATAbb_delay; the signal output by the fifth inverting unit 2025 is SLDN, which is the second pulse signal; the timing of the signals DATAb, DATAbb_delay and SLDN can be found in [reference needed]. Figure 6 .

[0073] It is evident that by setting a third inverting unit, a fourth inverting unit, a second delay unit, a second NAND gate unit, and a fifth inverting unit in the second slew rate control module, the output second pulse signal can be applied to the falling edge of the data signal. This achieves signal enhancement only when the signal falls and flips, without affecting the normal output high and low levels at other times. This further improves the generation accuracy of the second pulse signal for the falling edge, which in turn helps to further improve the output accuracy of the second pulse signal, and consequently, helps to further improve the slew rate control accuracy of the output drive.

[0074] In an optional embodiment, such as Figure 3 As shown, the output drive circuit may further include a pre-drive circuit 30, wherein: The signal input terminal of the pre-drive circuit 30 is used to receive the initial data signal, and the first signal output terminal, the second signal output terminal, and the third signal output terminal of the pre-drive circuit 30 are electrically connected to the data signal input terminal of each drive module 101, respectively. The pre-drive circuit 30 is used to perform signal shaping processing on the received initial data signal to obtain the target data signal; and output the target data signal to the drive circuit 10; wherein the driving capability of the target data signal is better than that of the initial data signal.

[0075] Optionally, the pre-drive circuit 30 can be a logic circuit or other circuit structures that can realize the pre-drive function. This embodiment of the invention does not limit the specific circuit.

[0076] The first signal output terminal, the second signal output terminal, and the third signal output terminal of the pre-drive circuit 30 can output a first data signal, a second data signal, and a third data signal, respectively. Furthermore, the first data signal can be out of phase with the second and third data signals, and the second data signal can be in phase with the third data signal. This embodiment of the invention does not impose any limitations.

[0077] As can be seen, this optional embodiment can improve the ability of the data signal to drive the subsequent stage by setting a pre-drive circuit in the output drive circuit, which is beneficial to further improve the driving capability of the subsequent output drive signal.

[0078] Combination Figures 4-7 The working principle of the output driving circuit in this embodiment of the invention is as follows: The initial data signal DATA is processed by the pre-drive circuit and the slew rate control circuit, and the resulting signal is then input to the drive circuit to output the drive signal. Specifically: (i) Regarding the pre-drive circuit: The pre-drive circuit processes the initial data signal to improve the ability of the data signal to drive the subsequent stage, and outputs three sets of signals: the first data signal DRUPP, the second data signal DRDNN, and the third data signal DRUPN; wherein, DRUPP is used to control the switching state and number of switches of the PMOS transistor combination MP1 (i.e., the first pull-up switch device mentioned above) in the drive circuit, DRUPN is used to control the switching state and number of switches of the NMOS transistor combination MN3 (i.e., the second pull-up switch device mentioned above) in the drive circuit, and DRDNN is used to control the switching state and number of switches of the NMOS transistor combination MN1 (i.e., the pull-down switch device mentioned above) in the drive circuit.

[0079] (II) Regarding the slew rate control circuit: The slew rate control circuit processes the initial data signal to generate the pulse signal required for slew rate control of the data signal. Therefore, it outputs two sets of pulse signals: the first pulse signal SLUP and the second pulse signal SLDN. SLUP controls the switching state and number of the NMOS transistor combination MN2 (i.e., the aforementioned auxiliary pull-up switch device) in the drive circuit, accelerating the rising edge of the output signal OUT. SLDN controls the switching state and number of the NMOS combination MN4 (i.e., the aforementioned auxiliary pull-down switch device) in the drive circuit, accelerating the falling edge of the output signal OUT. That is, when the OUT signal needs to output a low level, SLDN is pulled high by the pulse to open MN4, accelerating the falling speed of the NET2 level; when the OUT signal needs to output a high level, SLUP is pulled high by the pulse to open MN2, accelerating the pull-up of NET1, thereby accelerating the rising edge of the OUT signal. For example... Figure 5 , Figure 6 The schematic diagram of the slew rate control circuit shows that the input DATA and DATAb signals are processed by NAND gates and delays, so that the output pulse is amplified only on the toggling edges of DATA and DATAb, without affecting the normal high and low levels of the output at other times. Multiple slew rate control modules control the MN2 and MN4 arrays within the drive module to adjust the slew rate intensity.

[0080] (III) Regarding the drive circuit: (1) MP1 and MN3 in the drive circuit are pull-up drive transistors with selectable number of switches and switch states. When the drive sub-signal OUT to be output by the drive module is high, it can be equivalent to a pull-up resistor, providing a fixed pull-up drive capability for the output OUT. MP1 and MN3 can be divided with the Rout pull-down resistor to obtain a high level. At this time, the channels MN1 and MN4 pulled down to ground will be closed. In the drive circuit, MN1 is a pull-down drive transistor with selectable number of switches and switch state. It is equivalent to a resistor pulled down to ground. It is turned on when the drive sub-signal OUT output by the drive module needs to be pulled low. At this time, the channels MP1, MN2, and MN3 pulled up to the power supply will be turned off. (2) The slew rate control of the output drive is achieved through MN2 and MN4 in the drive circuit. The placement of MN2 and MN4 was confirmed after simulation comparison, for the following reasons: If MN2 is connected to NET2 (i.e., the second driving submodule mentioned above), it will not be able to adjust the slew rate because MN3 will also be turned on during pull-up, providing a strong pull-up capability to NET2 when NET2 is at a low voltage. Therefore, connecting MN2 to NET2 will not have a significant effect on enhancing the slew rate. However, the Vgs of the PMOS array MP1 is fixed and cannot provide a faster pull-up speed when NET1 (i.e., the first driving submodule mentioned above) is at a low level. Therefore, by connecting the NMOS array MN2 to NET1, when NET1 is at a low level, due to the larger Vgs of MN2, a larger current can be provided to NET1, thereby providing a faster pull-up speed. Furthermore, if NET2 is not connected to MN4, there is no pull-down channel provided by MN4. In this case, the NET2 level needs to pass through two paths to be released to ground: RUP, RDN, and MN1, or through RUP and RDN. Since the resistances of RUP and RDN are both above 200Ω, and multiple driver modules share the pull-down resistor Rout, the discharge speed is slow, affecting the slew rate of the OUT signal. Also, if the drain terminal of MN4 is connected to NET1, the pull-down channel of MN1 is already open, meaning NET1 already has the MN1 pull-down channel, which does not significantly improve the pull-down slew rate of the output OUT. Therefore, connecting the NMOS array MN4 to NET2 can accelerate the pull-down of NET2 when the output OUT transitions from high to low, thereby increasing the pull-down slew rate of NET2 and consequently accelerating the pull-down slew rate of the output OUT.

[0081] Furthermore, based on this, the signal timing of the output drive circuit can be found in [reference needed]. Figure 7 , Figure 7 This is a signal timing diagram of an output driving circuit disclosed in an embodiment of the present invention; as shown below. Figure 7 As shown, Figure 7 The timing sequence of signals such as DATA, DRUPP, DRUPN, DRDNN, SLUP, SLDN, and OUT is recorded. Specifically: the DATA signal is processed by the pre-drive circuit, which shapes the signal into a control signal with sharper edges and outputs DRUPP, DRUPN, and DRDNN respectively; the DATA signal pre-drive circuit processes the signal and outputs SLUP and SLDN respectively by selecting the number of branches of MN2 and MN4 in the drive circuit, thereby selecting the strength of the slew rate and controlling the slew rate.

[0082] Therefore, the output driving circuit proposed in the embodiments of the present invention can: (1) Under the requirements of high-speed signal transmission and low power consumption, the output drive circuit can provide slew rate control in low-voltage high-speed applications, and is not limited by the delay of a single inverter compared with the prior art; (2) This output drive circuit does not require a capacitor connected in series with the output OUT to provide pulse control slew rate, which can save layout area; (3) Compared with the prior art, the output drive circuit saves the series resistance from the slew rate control MOS transistor to OUT, and reasonably combines the impedance adjustment resistor to save the layout area, while also speeding up the slew rate.

[0083] Furthermore, simulation results demonstrate that the output drive circuit proposed in this embodiment of the invention is feasible, capable of improving the slew rate of the output waveform at a rate of 6400Mb / s, and adjusting the slew rate according to different speed requirements.

[0084] Example 2 Please see Figure 8 , Figure 8 This is a schematic diagram of the structure of an electronic device disclosed in an embodiment of the present invention. The electronic device includes a device body and an output driving circuit as described in any of the embodiments in Embodiment 1. The functions that this electronic device can achieve include, but are not limited to, precise control of the slew rate of the output drive in high-speed transmission applications. It should be noted that for a detailed description of the output driving circuit, please refer to the specific description in Embodiment 1; it will not be repeated in this embodiment.

[0085] It is evident that implementation Figure 8 The described electronic device can accelerate the flip edge of the target data signal output by the pre-drive circuit by using the pulse signal output by the slew rate control circuit through the drive circuit, thereby achieving slew rate control of the data signal and outputting a drive signal composed of drive sub-signals output by all drive modules. This can improve the accuracy of slew rate control of the output drive in high-speed transmission applications, thereby improving signal transmission integrity, signal quality, and ultimately signal transmission accuracy. In addition, it can also save the area occupied by the output drive circuit, which is beneficial to reducing drive costs.

[0086] Finally, it should be noted that the output driving circuit and electronic device disclosed in the embodiments of the present invention are merely preferred embodiments of the present invention and are only used to illustrate the technical solutions of the present invention, not to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. An output driving circuit, characterized in that, The output driving circuit includes a driving circuit, which in turn includes several driving modules, wherein: For each of the drive modules, the pulse signal input terminal of the drive module is used to electrically connect to the pulse output terminal of the slew rate control circuit; the data signal input terminal of the drive module is used to electrically connect to the signal output terminal of the pre-drive circuit; and the signal output terminal of the drive module is used to output the drive sub-signal. Each of the driving modules is configured to receive the target data signal output by the pre-driving circuit and the pulse signal output by the slew rate control circuit; and to perform slew rate adjustment processing on the target data signal using the pulse signal to output the processed driving sub-signal; wherein the slew rate adjustment processing is used to accelerate the flip edge of the target data signal; and the driving signal output by the driving circuit is composed of the driving sub-signals output by all the driving modules.

2. The output driving circuit according to claim 1, characterized in that, The pulse signal includes a first pulse signal and a second pulse signal; And each of the driving modules includes a first driving submodule and a second driving submodule, wherein: The first data signal input terminal of the first driving submodule is used to electrically connect to the first signal output terminal of the pre-driving circuit, the second data signal input terminal of the first driving submodule is used to electrically connect to the second signal output terminal of the pre-driving circuit, and the pulse signal input terminal of the first driving submodule is used to electrically connect to the first pulse output terminal of the slew rate control circuit. The data signal input terminal of the second driving submodule is used to electrically connect to the third signal output terminal of the pre-driving circuit, and the pulse signal input terminal of the second driving submodule is used to electrically connect to the second pulse output terminal of the slew rate control circuit. The output terminal of the first driving submodule is electrically connected to the output terminal of the second driving submodule; the power supply terminal of the first driving submodule and the power supply terminal of the second driving submodule are used to electrically connect to the power supply, and the ground terminal of the first driving submodule and the ground terminal of the second driving submodule are used to electrically connect to the reference ground. The first driving submodule is used to accelerate the rising edge of the desired output driving sub-signal using the received first pulse signal; The second driving submodule is used to accelerate the falling edge of the desired output driving sub-signal using the received second pulse signal.

3. The output driving circuit according to claim 2, characterized in that, The first driver submodule includes a first driver unit and an auxiliary pull-up unit, wherein: The first terminal of the first driving unit is electrically connected to the first signal output terminal of the pre-driving circuit; the second terminal of the first driving unit is electrically connected to the first pulse output terminal of the slew rate control circuit; the third terminal of the first driving unit is electrically connected to the power supply; the fourth terminal of the first driving unit is electrically connected to the reference ground; the first terminal of the auxiliary pull-up unit is electrically connected to the first pulse output terminal of the slew rate control circuit, and the second terminal of the auxiliary pull-up unit is electrically connected to the power supply; the fifth terminal of the first driving unit is electrically connected to the third terminal of the auxiliary pull-up unit, and the sixth terminal of the first driving unit is electrically connected to the output terminal of the second driving submodule. The auxiliary pull-up unit is used to turn on the auxiliary pull-up unit using the first pulse signal when the driving module needs to output a high-level driving sub-signal, so as to provide a transient acceleration current to the first driving unit, thereby accelerating the rising edge of the required output driving sub-signal.

4. The output driving circuit according to claim 2, characterized in that, The second driving submodule includes a second driving unit and an auxiliary pull-down unit, wherein: The first end of the second driving unit is used to electrically connect to the third signal output end of the pre-driving circuit, and the second end of the second driving unit is used to electrically connect to the power supply. The first end of the auxiliary pull-down unit is used to electrically connect to the second pulse output end of the slew rate control circuit, and the second end of the auxiliary pull-down unit is used to electrically connect to the reference ground; The third end of the second driving unit is electrically connected to the third end of the auxiliary pull-down unit and the output end of the first driving submodule, respectively. The auxiliary pull-down unit is used to turn on the auxiliary pull-down unit using the second pulse signal when the driving module needs to output a low-level driving sub-signal, so as to provide a discharge path to the second driving unit and thereby accelerate the falling edge of the required output driving sub-signal.

5. The output driving circuit according to claim 2, characterized in that, Each of the drive modules further includes a protection submodule, wherein: The first terminal of the protection submodule is electrically connected to the output terminal of the first drive submodule, the second terminal of the protection submodule is electrically connected to the output terminal of the second drive submodule, and the third terminal of the protection submodule is used to output the drive sub-signal of the drive module.

6. The output drive circuit according to any one of claims 1-5, characterized in that, The output drive circuit further includes a slew rate control circuit, wherein: The signal input terminal of the slew rate control circuit is used to receive the initial data signal, and the first pulse output terminal and the second pulse output terminal of the slew rate control circuit are electrically connected to the pulse signal input terminal of each of the drive modules, respectively. The slew rate control circuit is used to perform delay gating processing on the received initial data signal to output the processed pulse signal.

7. The output driving circuit according to claim 6, characterized in that, The slew rate control circuit includes a first slew rate control module and a second slew rate control module, wherein: The first terminal of the first slew rate control module is used to receive the initial data signal, and the pulse output terminal of the first slew rate control module is electrically connected to the first pulse signal input terminal of each of the drive modules. The second terminal of the second slew rate control module is used to receive the initial data signal, and the pulse output terminal of the second slew rate control module is electrically connected to the second pulse signal input terminal of each of the drive modules. The first slew rate control module is used to perform delay gating processing on the initial data signal to output the processed first pulse signal; The second slew rate control module is used to perform delay gating processing on the inverted data signal corresponding to the initial data signal, so as to output the processed second pulse signal.

8. The output driving circuit according to claim 7, characterized in that, The first slew rate control module includes a first inverting unit, a first delay unit, a first NAND gate unit, and a second inverting unit, wherein: The input terminal of the first inverting unit and the first input terminal of the first NAND gate unit are respectively used to receive the initial data signal. The output terminal of the first inverting unit is electrically connected to the input terminal of the first delay unit. The output terminal of the first delay unit is electrically connected to the second input terminal of the first NAND gate unit. The output terminal of the first NAND gate unit is electrically connected to the input terminal of the second inverting unit. The output terminal of the second inverting unit is electrically connected to the first pulse signal input terminal of each of the driving modules. And / or, the second slew rate control module includes a third inverting unit, a fourth inverting unit, a second delay unit, a second NAND gate unit, and a fifth inverting unit, wherein: The input terminal of the third inverting unit is used to receive the initial data signal. The output terminal of the third inverting unit is electrically connected to the input terminal of the fourth inverting unit and the first input terminal of the second NAND gate unit. The output terminal of the fourth inverting unit is electrically connected to the input terminal of the second delay unit. The output terminal of the second delay unit is electrically connected to the second input terminal of the second NAND gate unit. The output terminal of the second NAND gate unit is electrically connected to the input terminal of the fifth inverting unit. The output terminal of the fifth inverting unit is electrically connected to the second pulse signal input terminal of each of the driving modules.

9. The output drive circuit according to any one of claims 1, 2, 3, 4, 5, 7, and 8, characterized in that, The output drive circuit further includes a pre-drive circuit, wherein: The signal input terminal of the pre-drive circuit is used to receive the initial data signal, and the first signal output terminal, the second signal output terminal, and the third signal output terminal of the pre-drive circuit are electrically connected to the data signal input terminal of each drive module, respectively. The pre-driving circuit is used to perform signal shaping processing on the received initial data signal to obtain a target data signal; and output the target data signal to the driving circuit; wherein the driving capability of the target data signal is better than the driving capability of the initial data signal.

10. An electronic device, characterized in that, The electronic device includes a device body and an output drive circuit as described in any one of claims 1-9.

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