Gate drive circuit, chip and electronic device

Abstract

The application discloses a gate drive circuit, a chip and an electronic device. The circuit comprises a first constant current source module for generating a constant charging current; a second constant current source module for generating a constant discharging current; a first switch, a first end of which is connected to an output end of the first constant current source module, and a second end of which is connected to a gate of a power device through a gate resistance; and a second switch, a first end of which is connected to an output end of the second constant current source module, and a second end of which is connected to the gate of the power device through the gate resistance. The first switch and the second switch are configured to: in a turn-on phase of the power device, the first switch is closed and the second switch is opened, so that the charging current charges the gate through the gate resistance; and in an off phase of the power device, the first switch is opened and the second switch is closed, so that the discharging current discharges from the gate through the gate resistance. The application realizes linear charging and discharging of the gate of the power device, independently optimizes the switching loss and electromagnetic interference, and improves the robustness of the switching of the power device.

Description

Technical Field

[0001] This application relates to the field of electronic circuit technology, specifically to a gate-level driver circuit, chip, and electronic device. Background Technology

[0002] In the field of power semiconductor device driving, existing power devices are often driven by traditional voltage sources. Due to the nonlinear characteristics of the gate capacitance of power devices, voltage source driving often exhibits a nonlinear voltage change curve with "fast at the beginning and slow at the end" during the switching process. Especially under the condition of large gate resistance, the turn-off delay is obvious, which is prone to generating narrow pulse interference and affecting system stability.

[0003] In existing drive schemes, there is a trade-off between losses and electromagnetic interference (EMI). Under light loads, a rapid voltage change rate can easily lead to excessive EMI, while under heavy loads, a slow voltage change rate causes a sharp increase in turn-on losses. Simultaneously, the switching process is strongly coupled with the load current, resulting in poor dynamic robustness; the voltage change rate can change by more than three times when the current increases from 10% to 100% of the rated value. Furthermore, relying solely on an external gate resistor to adjust the switching speed is crude and cannot achieve independent optimization of different stages such as pre-charge, Miller regulation, and saturation. Moreover, the Miller regulation carries a high risk of mis-enabling, and short-circuit protection relies on external circuitry, resulting in slow response and poor accuracy. Summary of the Invention

[0004] In view of the above problems, this application provides a gate-level driver circuit, chip, and electronic device to solve the above technical problems.

[0005] In a first aspect, this application provides a gate drive circuit, comprising: The first constant current source module is used to generate a constant charging current; The second constant current source module is used to generate a constant discharge current; The first switch has a first end connected to the output end of the first constant current source module and a second end connected to the gate of the power device via a gate resistor. The second switch has its first end connected to the output terminal of the second constant current source module, and its second end connected to the gate of the power device via the gate resistor. The first switch and the second switch are configured as follows: During the turn-on phase of the power device, the first switch is closed and the second switch is open, so that the charging current charges the gate through the gate resistor; During the turn-off phase of the power device, the first switch is open and the second switch is closed, causing the discharge current to discharge from the gate through the gate resistor.

[0006] In some embodiments, the first constant current source module includes a first resistor, one end of which is connected to a first power supply and the other end of which is connected to a first terminal of the first switch.

[0007] In some embodiments, the second constant current source module includes a second resistor, one end of which is connected to a reference ground and the other end of which is connected to a first terminal of the second switch.

[0008] In some embodiments, the first switch is a PMOS transistor and the second switch is an NMOS transistor.

[0009] In some embodiments, both the first switch and the second switch are NMOS transistors.

[0010] In some embodiments, the control terminal of the first switch is used to receive a first PWM signal, and the control terminal of the second switch is used to receive a second PWM signal. The first PWM signal is used to control the first switch to turn on and off, and the second PWM signal is used to control the second switch to turn on and off.

[0011] In some embodiments, the charging current is not equal to the discharging current.

[0012] In some embodiments, the power device includes IGBTs, SiC MOSFETs, and GaN power devices.

[0013] Secondly, this application also provides a chip including the gate drive circuit described in the first aspect.

[0014] Thirdly, this application also provides an electronic device, including a device body and a chip disposed on the device body as described in the second aspect above.

[0015] The gate drive circuit, chip, and electronic equipment provided in this application provide constant charging and discharging currents through a first constant current source module and a second constant current source module, respectively. By selectively turning on the first and second switches during the turn-on and turn-off phases, the gate charging and discharging are linearly controlled by the constant current source. Since the charging and discharging currents can be set independently, turn-on losses and turn-off electromagnetic interference can be optimized separately, resolving the trade-off between the two in traditional solutions. The constant current output is unaffected by the load current, ensuring a stable voltage change rate across the entire load range, improving dynamic robustness, and eliminating late-turn-off delay and narrow-pulse interference. Therefore, this application offers the technical advantages of independently optimizable switching performance, high dynamic stability, and a simple circuit structure.

[0016] The gate drive circuit, chip, and electronic device provided in this application provide constant charging current and constant discharging current by setting independent first and second constant current source modules, respectively. By using a first switch and a second switch to selectively connect the corresponding constant current source module to the gate of the power device via a gate resistor during the turn-on and turn-off phases, the charging and discharging process of the gate is linearly controlled by the constant current source. Since the charging current and discharging current are generated by independent constant current source modules and are uncoupled, the gate voltage rise rate during the turn-on phase is determined by the charging current, and the gate voltage fall rate during the turn-off phase is determined by the discharging current. Both can be set independently, allowing for independent optimization of turn-on losses and turn-off electromagnetic interference according to actual needs. This effectively solves the contradiction between losses and electromagnetic interference caused by the simultaneous influence of a single gate resistor on turn-on and turn-off performance in traditional voltage source drives. Meanwhile, the current output by the constant current source module remains unchanged regardless of gate voltage fluctuations or load current variations, ensuring a stable voltage change rate across the entire load range during switching. This significantly improves dynamic robustness and avoids issues such as excessive electromagnetic interference under light loads and drastically increased turn-on losses under heavy loads. Furthermore, the linearized gate voltage waveform eliminates the rapid initial and slow final changes caused by gate capacitance nonlinearity in traditional drives, particularly preventing delays and narrow pulse interference during the later stages of turn-off, thus enhancing system stability. The circuit structure of this application requires only two constant current source modules and two switches, eliminating the need for complex current detection or feedback networks, resulting in a simple structure and ease of integration.

[0017] These or other aspects of this application will become more apparent in the following description of the embodiments. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 A schematic diagram of the gate drive circuit provided in an embodiment of this application is shown.

[0020] Figure 2 A schematic diagram of the gate-level driving circuit provided in an embodiment of this application is shown.

[0021] Figure 3 This illustration shows another structural schematic of the gate-level drive circuit provided in an embodiment of this application.

[0022] Figure 4 A schematic diagram of a chip provided in an embodiment of this application is shown.

[0023] Figure 5 A schematic diagram of an electronic device provided in an embodiment of this application is shown. Detailed Implementation

[0024] To enable those skilled in the art to better understand the solutions of this application, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0025] In the embodiments of this application, it should be noted that, in this document, relational terms such as first and second are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations.

[0026] Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0027] Furthermore, in the embodiments of this application, "multiple" refers to two or more. Therefore, in the embodiments of this application, "multiple" can also be understood as "at least two". "At least one" can be understood as one or more, such as one, two, or more. For example, including at least one means including one, two, or more, and is not limited to which ones are included. For example, including at least one of A, B, and C, then it could include A, B, C, A and B, A and C, B and C, or A and B and C.

[0028] It should be noted that in the embodiments of this application, "connection" can be understood as electrical connection. The connection between two electrical components can be a direct or indirect connection between the two electrical components. For example, the connection between A and B can be a direct connection between A and B, or an indirect connection between A and B through one or more other electrical components.

[0029] It should be noted that in the embodiments of this application, the "first terminal" and "second terminal" of the transistor are functional definitions based on circuit connection relationships, and do not specifically refer to the source or drain. Specifically, the first terminal refers to the terminal of the transistor connected to the constant current source module, and the second terminal refers to the terminal of the transistor connected to the gate of the power device via a gate resistor. Depending on the transistor type and its position in the circuit (charging switch or discharging switch), the first terminal and the second terminal can be the source or drain, respectively, and those skilled in the art can determine the specific connection method based on the circuit function.

[0030] The gate drive circuit provided in this application is used for the drive control of power semiconductor devices. These power devices include, but are not limited to, insulated-gate bipolar transistors (IGBTs), silicon carbide metal-oxide-semiconductor field-effect transistors (SiC MOSFETs), and gallium nitride high electron mobility transistors (GaN HEMTs).

[0031] In typical applications, the gate driver circuit serves as the interface between the controller and the power device. Its input is connected to the controller (such as an MCU, DSP, or FPGA) to receive the PWM signal output by the controller; its output is connected to the gate of the power device. Based on the received PWM signal, the gate driver circuit provides charging or discharging current to the gate of the power device, thereby controlling the power device's turn-on and turn-off. The controller, gate driver circuit, and power device together constitute a complete power conversion system.

[0032] The embodiments of this application mainly focus on the structural improvement of the gate drive circuit. By cooperating with the constant current source module and the switch, the linear charging and discharging of the gate is realized, thereby optimizing the trade-off between switching losses and electromagnetic interference and improving dynamic robustness.

[0033] Figure 1 A schematic diagram of the gate drive circuit provided in an embodiment of this application is shown, as follows: Figure 1 As shown, the gate drive circuit provided in this application embodiment includes a first constant current source module, a second constant current source module, a first switch, and a second switch.

[0034] Specifically, a first constant current source module generates a constant charging current. A second constant current source module generates a constant discharging current. A first terminal of a first switch is connected to the output terminal of the first constant current source module, and its second terminal is connected to the gate of the power device via a gate resistor (Rg). A second switch has a first terminal connected to the output terminal of the second constant current source module, and its second terminal connected to the gate of the power device via a gate resistor (Rg). The first and second switches are configured such that during the power device's turn-on phase, the first switch is closed and the second switch is open, allowing the charging current to charge the gate through the gate resistor (Rg). During the power device's turn-off phase, the first switch is open and the second switch is closed, allowing the discharging current to discharge from the gate through the gate resistor (Rg).

[0035] Optionally, the first and second constant current source modules are circuit units capable of outputting a constant current. Their internal implementation is not limited; for example, they can employ a current mirror structure, a current source composed of transistors operating in the saturation region, or a current-limiting structure composed of a resistor connected in series with the power supply. Constant charging and discharging currents mean that the current magnitude remains essentially unchanged with variations in the gate voltage during gate charging or discharging. The first and second switches control the on / off state of the charging and discharging paths. When the switches are closed, the corresponding constant current source module is connected to the gate circuit; when the switches are open, the path is cut off. The gate resistor (Rg) is connected in series in the charging and discharging path to further adjust the current magnitude or limit the peak current. During the turn-on phase, only the charging current is introduced to the gate; during the turn-off phase, only the discharging current is drawn from the gate. The two phases do not interfere with each other, therefore the magnitudes of the charging and discharging currents can be set independently, without being constrained by the other.

[0036] The embodiments of this application, through the aforementioned circuit structure, enable the gate voltage to change approximately linearly during turn-on and turn-off, avoiding the rapid initial change followed by a slower change caused by the nonlinearity of the gate capacitance in traditional voltage source drives. The current output by the constant current source module is unaffected by load current fluctuations, ensuring that the voltage change rate remains stable across the entire load range during the switching process. Furthermore, since the charging current and discharging current can be set independently, turn-on losses and turn-off electromagnetic interference can be optimized separately according to actual application requirements, effectively solving the technical problem of the trade-off between these two factors in traditional solutions. The gate drive circuit structure provided in these embodiments is simple, requiring no complex current detection or feedback networks, and is easy to integrate.

[0037] In some embodiments, Figure 2 A schematic diagram of the gate-level driver circuit provided in an embodiment of this application is shown. Figure 3 This illustration shows another structural schematic of the gate-level drive circuit provided in an embodiment of this application, as shown below. Figure 2 and Figure 3As shown, the first constant current source module includes a first resistor, one end of which is connected to a first power supply, and the other end is connected to the first terminal of a first switch. Optionally, the first resistor is connected in series with the first switch. When the first switch is closed, the voltage of the first power supply is applied to the first terminal of the first switch through the first resistor. Due to the current-limiting effect of the first resistor, the current flowing through the first switch is limited to a level determined by the voltage of the first power supply and the resistance value of the first resistor. By appropriately selecting the resistance value of the first resistor, the magnitude of the charging current can be set. The first power supply is usually a positive power supply, such as +15V or +25V, and the specific value is determined according to the gate drive voltage requirements of the power device. This implementation method has a simple structure and can obtain approximate constant current characteristics without additional active components.

[0038] This application embodiment uses a first resistor to form a first constant current source module, which only requires one resistor element to set the charging current. Compared with the structure of using a current mirror or an active constant current source, it significantly reduces circuit complexity and cost. At the same time, the resistance value is easy to adjust, which makes it easy to flexibly configure the turn-on speed according to actual application.

[0039] In some embodiments, such as Figure 2 and Figure 3 As shown, the second constant current source module includes a second resistor, one end of which is connected to a reference ground, and the other end is connected to the first terminal of the second switch. Optionally, the second resistor is connected in series with the second switch. When the second switch is closed, the charge stored in the gate capacitor flows to the reference ground through the second switch and the second resistor. The resistance value of the second resistor determines the magnitude of the discharge current; the larger the resistance, the smaller the discharge current and the slower the gate voltage drops; the smaller the resistance, the larger the discharge current and the faster the gate voltage drops. By independently selecting the resistance value of the second resistor, the discharge current and charging current can be made unequal, thereby optimizing the turn-on and turn-off processes separately. The reference ground is typically 0V.

[0040] This application embodiment uses a second resistor to form a second constant current source module, making the setting of the discharge current independent of the setting of the charging current. This solves the coupling problem in traditional voltage source drive where a single gate resistor simultaneously affects the turn-on and turn-off performance, and realizes independent adjustment of the turn-off speed. This is beneficial for optimizing the turn-off process separately according to electromagnetic interference requirements.

[0041] In some embodiments, such as Figure 2As shown, in the gate drive circuit provided in this embodiment, the first switch is a PMOS transistor Q1, and the second switch is an NMOS transistor Q2. Optionally, the source of the PMOS transistor is connected as its first terminal to the output terminal (i.e., the first resistor) of the first constant current source module, and the drain is connected as its second terminal to the gate of the power device via the gate resistor Rg; the source of the NMOS transistor is connected as its first terminal to the output terminal (i.e., the second resistor) of the second constant current source module, and the drain is connected as its second terminal to the gate of the power device via the gate resistor Rg. When a PMOS is used as a charging switch, its source is connected to the positive power supply, and its drain is connected to the gate. It conducts when the gate is low and is cut off when the gate is high. When an NMOS is used as a discharging switch, its source is grounded, and its drain is connected to the gate. It conducts when the gate is high and is cut off when the gate is low.

[0042] In some embodiments, such as Figure 3 As shown, in the gate drive circuit provided in this application embodiment, both the first switch and the second switch are NMOS transistors. Optionally, the first NMOS transistor Q3 serves as a charging switch, with its drain connected as the first terminal to the output terminal (i.e., the first resistor) of the first constant current source module, and its source connected as the second terminal to the gate of the power device via the gate resistor Rg; the second NMOS transistor Q4 serves as a discharging switch, with its source connected as the first terminal to the output terminal (i.e., the second resistor) of the second constant current source module, and its drain connected as the second terminal to the gate of the power device via the gate resistor Rg. Since the first NMOS transistor Q3 serves as a charging switch, its source potential is close to the gate voltage (at most close to the power supply voltage) when it is turned on. To ensure its full conduction, its gate usually needs to be driven by a voltage higher than the power supply voltage. In this case, it can be used in conjunction with a boost circuit or a bootstrap circuit. This scheme uses all transistors of the same type, which is beneficial for process consistency.

[0043] In some embodiments, such as Figure 2 and 3 As shown in the embodiment of this application, in the gate drive circuit, the control terminal of the first switch is used to receive a first PWM signal, and the control terminal of the second switch is used to receive a second PWM signal. The first PWM signal is used to control the on and off states of the first switch, and the second PWM signal is used to control the on and off states of the second switch. Optionally, the first PWM signal and the second PWM signal are high and low levels respectively; that is, when the first PWM signal is high, the second PWM signal is low, and vice versa. Thus, during the turn-on phase, the first switch is on and the second switch is off; during the turn-off phase, the first switch is off and the second switch is on. The PWM signal can be provided by an external microcontroller or a dedicated PWM controller, and after being shaped by a buffer, it directly drives the gate of the switching transistor.

[0044] The embodiments of this application use PWM signals to directly control the first and second switches, eliminating the need for additional digital-to-analog conversion or complex timing control circuits. This allows the gate drive circuit to easily interface with a digital controller, resulting in fast response and high control precision. At the same time, the two PWM signals being high and low levels respectively ensure strict mutual exclusion of the charging and discharging paths, avoiding the risk of shoot-through.

[0045] In some embodiments, the charging current and discharging current in the gate drive circuit provided in this application are not equal. Optionally, by setting the output current values ​​of the first constant current source module and the second constant current source module respectively, the charging current and discharging current can have different magnitudes. For example, when a faster turn-on speed is needed to reduce turn-on losses, the charging current can be increased; when a slower turn-off speed is needed to suppress turn-off electromagnetic interference, the discharging current can be decreased. Conversely, the charging and discharging paths are completely independent and do not restrict each other, achieving phased independent optimization of the switching process, which is difficult to achieve with traditional voltage source type drives.

[0046] In some embodiments, the gate drive circuit provided in this application includes IGBTs, SiC MOSFETs, and GaN power devices. By selecting appropriate power supply voltages and resistance values, the gate drive circuit provided in this application can adapt to the driving requirements of different types of power devices, thus having a wide range of applications.

[0047] This application also provides a chip. Figure 4 A schematic diagram of a chip provided in an embodiment of this application is shown, such as... Figure 4 As shown, the chip 100 includes the aforementioned gate-level driver circuit 10. A chip (Integrated Circuit, IC) is also called a chip, and this chip can be, but is not limited to, a SOC (System on Chip) chip or a SIP (System in Package) chip.

[0048] This application also provides an electronic device. Figure 5 A schematic diagram of an electronic device provided in an embodiment of this application is shown, such as... Figure 5 As shown, the electronic device includes a device body and a chip, as described above, disposed within the device body.

[0049] The above description, in conjunction with specific embodiments, provides a further detailed explanation of this application and should not be construed as limiting the specific implementation of this application to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of this application, and all such modifications and substitutions should be considered within the scope of protection of this application.

Claims

1. A gate drive circuit, characterized in that, include: The first constant current source module is used to generate a constant charging current; The second constant current source module is used to generate a constant discharge current; The first switch has a first end connected to the output end of the first constant current source module and a second end connected to the gate of the power device via a gate resistor. The second switch has its first end connected to the output terminal of the second constant current source module, and its second end connected to the gate of the power device via the gate resistor. The first switch and the second switch are configured as follows: During the turn-on phase of the power device, the first switch is closed and the second switch is open, so that the charging current charges the gate through the gate resistor; During the turn-off phase of the power device, the first switch is open and the second switch is closed, causing the discharge current to discharge from the gate through the gate resistor.

2. The gate drive circuit according to claim 1, characterized in that, The first constant current source module includes a first resistor, one end of which is connected to a first power supply and the other end of which is connected to the first terminal of the first switch.

3. The gate drive circuit according to claim 2, characterized in that, The second constant current source module includes a second resistor, one end of which is connected to a reference ground and the other end of which is connected to the first terminal of the second switch.

4. The gate drive circuit according to claim 1, characterized in that, The first switch is a PMOS transistor, and the second switch is an NMOS transistor.

5. The gate drive circuit according to claim 3, characterized in that, Both the first switch and the second switch are NMOS transistors.

6. The gate drive circuit according to claim 1, characterized in that, The control terminal of the first switch is used to receive a first PWM signal, and the control terminal of the second switch is used to receive a second PWM signal. The first PWM signal is used to control the first switch to turn on and off, and the second PWM signal is used to control the second switch to turn on and off.

7. The gate drive circuit according to claim 1, characterized in that, The charging current is not equal to the discharging current.

8. The gate drive circuit according to claim 1, characterized in that, The power devices include IGBTs, SiC MOSFETs, and GaN power devices.

9. A chip, characterized in that, Includes the gate drive circuit described in any one of claims 1 to 8.

10. An electronic device, characterized in that, It includes a device body and a chip as described in claim 9 disposed on the device body.

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