A graded gate modulation method to improve the rate of change of the drain-source voltage in dynamic reverse bias testing of SiC MOSFETs

Abstract

The application relates to a grading gate regulation method for improving the voltage change rate of a DS end in SiC MOSFET dynamic reverse bias testing, which comprises the following steps: in a T1 stage, S1 and S2 are low levels, VEE reverse bias is adopted, the device can be reliably turned off, S1 is an input signal of a driving chip IC1, and S2 is an input signal of a driving chip IC2; in a T2 stage, S1 and S2 are high levels, Vadj higher than a conventional voltage is adopted to enhance the driving and accelerate the charging of an input capacitor Cgs and a Miller capacitor; in a T3 stage, S1 is a low level and S2 is a high level, the conventional voltage VON is switched to be used for power supply, so that the driving current is reduced to continue the charging of the Miller capacitor; and in a T4 stage, S1 and S2 are low levels, VEE reverse bias is switched again to turn off the device. The application has the effect of dynamically adjusting the gate driving capacity in stages, effectively improving dV / dt, and simultaneously inhibiting voltage overshoot and oscillation.

Description

Technical Field

[0001] This application relates to the technical field of power semiconductor device testing, and in particular to a graded gate control method for improving the rate of change of the DS-terminal voltage in dynamic reverse bias testing of SiC MOSFETs. Background Technology

[0002] As a representative of wide-bandgap power semiconductor devices, SiC MOSFETs are widely used in high-power-density applications such as electric vehicles, photovoltaic inverters, and rail transportation due to their high switching speed, low on-resistance, and excellent high-temperature performance.

[0003] Dynamic reverse bias testing is an important method for evaluating the reliability of SiC MOSFET devices. According to AQG324 and related standards, dynamic reverse bias testing requires the SiC MOSFET device to have a voltage change rate (dV) at the DS terminal. DS The value of dV / dt (or dV / dt for short) must be greater than 50V / ns, and for discrete devices, it is even required to reach 100V / ns.

[0004] However, SiC MOSFET devices, especially SiC modules, typically have multiple SiC chips connected in parallel, resulting in large junction capacitances and numerous technical challenges in improving dV / dt.

[0005] Traditional approaches improve dV / dt by enhancing the pull-up / sink current capability of the driver chip and reducing the gate resistance, but the actual effect is limited. dV / dt is controlled by the Miller capacitance charging stage, i.e. the Miller plateau region. The improvement of the driver chip's driving capability mainly affects the junction capacitance during the initial charging stage. However, at the Miller plateau, since the junction capacitance has already accumulated charge, the improvement effect on dV / dt is limited.

[0006] Secondly, while reducing the gate resistance helps improve the switching speed, it puts the drive circuit in an overdamped state, which can easily lead to gate voltage overshoot, affecting device reliability and test safety.

[0007] Furthermore, a single gate resistor cannot reconcile the contradiction between switching speed and system stability. Increasing the switching speed requires a larger drive capability, but excessive drive capability will cause voltage overshoot and oscillation at the end of the turn-on period, which will worsen the electromagnetic interference (EMI) characteristics. Summary of the Invention

[0008] To address the aforementioned issues, this application provides a graded gate control method for improving the rate of change of the DS-terminal voltage in dynamic reverse bias testing of SiC MOSFETs. By dynamically adjusting the gate drive capability in stages, an effective increase in dV / dt is achieved, while suppressing voltage overshoot and oscillation.

[0009] The above-mentioned inventive objective of this application is achieved through the following technical solutions:

[0010] A graded gate control method for improving the rate of change of the DS terminal voltage in dynamic reverse bias test of SiC MOSFET includes several control stages, namely the T1 stage, the T2 stage, the T3 stage and the T4 stage.

[0011] During the T1 stage, both S1 and S2 are at low level, and VEE is used for reverse bias to reliably turn off the device. S1 is the input signal of driver chip IC1, S2 is the input signal of driver chip IC2, and VEE is the reverse voltage of the gate power supply.

[0012] During the T2 phase, both S1 and S2 are at high levels, and Vadj, which is a higher voltage than the conventional voltage, is used for enhanced driving. Vadj is an adjustable gate power supply positive voltage, which accelerates the charging of the input capacitor Cgs and the Miller capacitor.

[0013] During the T3 phase, S1 is at a low level and S2 is at a high level, switching to the normal voltage VON for power supply to reduce the drive current and continue charging the Miller capacitor. VON is the positive voltage of the gate power supply.

[0014] During the T4 phase, S1 and S2 are at low levels, and the device switches back to VEE reverse bias to turn off.

[0015] Optionally, during stage T1, when both S1 and S2 are at low levels and VEE is reverse-biased to reliably turn off the device, the steps include:

[0016] Controlling S1 and S2 to maintain a low level, in the switching circuit, the third switch connected to VEE is closed, the first switch connected to Vadj and the second switch connected to VON are both open, VEE is connected to the gate, Vadj and VON are both open, and the gate current flows from the SiCMOSFET gate through the gate resistor to VEE, forming a reverse draw.

[0017] By adopting the above technical solution, the gate voltage is maintained at the VEE negative voltage in the T1 stage, ensuring that the device is in a reliable off state before turn-on. It provides a reliable reverse bias before the device is turned on, ensuring that the gate charge is completely extracted and avoiding false turn-on.

[0018] Optionally, in the T2 stage, both S1 and S2 are at high levels, using a Vadj-enhanced drive higher than the conventional voltage, where Vadj is an adjustable gate power supply forward voltage, to accelerate the charging of the input capacitor Cgs and the Miller capacitor, including:

[0019] By keeping both S1 and S2 at a high level, the gate power supply forward voltage Vadj can be adjusted and connected to the gate of the SiC MOSFET. Vadj is greater than VON, and the gate current flows from Vadj through the gate resistor to the gate of the SiC MOSFET, thus forward charging the gate capacitance of the SiC MOSFET.

[0020] By adopting the above technical solution, this stage provides an enhanced gate drive current, accelerates the charging of the input capacitor Cgs, and enables the gate voltage of the SiC MOSFET to rise rapidly to the Miller plateau voltage. At the same time, it provides a strong driving force for the Miller capacitor in the early stage of the Miller plateau, shortening the turn-on delay time and the duration of the Miller plateau.

[0021] Optionally, during stage T3, when S1 is low and S2 is high, the system switches to the normal voltage VON to reduce the drive current and continue charging the Miller capacitor. This includes:

[0022] When S1 is switched to low level and S2 is kept high level, VON is connected to the gate of the SiC MOSFET, Vadj is disconnected, and the gate current flows from VON through the gate resistor to the gate of the SiC MOSFET.

[0023] By adopting the above technical solution, the current direction in stage T3 is the same as that in stage T2, both flowing towards the gate of the SiC MOSFET, but the current amplitude is reduced because VON is less than Vadj. At this time, the Miller capacitor is almost saturated, and the required drive current is reduced. Using a lower voltage VON to power the circuit can continue to complete the charging process and avoid excessive drive current causing subsequent oscillations.

[0024] Optionally, the step of switching back to VEE reverse bias and turning off the device during the T4 stage when S1 and S2 are low includes:

[0025] When S1 is low, S2 is switched to low, VEE is connected to the gate of the SiC MOSFET, Vadj and VON are both disconnected, and the gate current of the SiC MOSFET is reversed, flowing from the gate of the SiC MOSFET through the gate resistor to VEE, thus resetting to stage T1.

[0026] By adopting the above technical solution, the gate capacitor is reverse-pumped in this stage, so that the gate voltage is turned off quickly and stably, and reset to the T1 stage.

[0027] Optionally, in the T2 stage, both S1 and S2 are at high levels, and Vadj is used to enhance the drive, which is higher than the conventional voltage. Vadj is an adjustable gate power supply forward voltage. In the step of accelerating the charging of the input capacitor Cgs and the Miller capacitor, the charging rate of the input capacitor Cgs is adjusted by adjusting the amplitude of the adjustable gate power supply forward voltage Vadj, thereby adjusting the time to reach the Miller platform.

[0028] By identifying the junction capacitance characteristics of SiC MOSFET devices, the larger the junction capacitance, the greater the required drive current, and Vadj is increased; if the junction capacitance is small, Vadj is appropriately decreased.

[0029] By adopting the above technical solution, in practical applications, the Vadj value needs to be selected comprehensively based on the junction capacitance of the SiC MOSFET device under test and the target dV / dt requirement. For SiC modules with large junction capacitance, such as multiple chips connected in parallel, Vadj should be adjusted to a higher value; for discrete devices with small junction capacitance, Vadj can be adjusted to a lower value to avoid excessive voltage overshoot and oscillation while increasing dV / dt.

[0030] The second objective of this invention is achieved through the following technical solution:

[0031] A graded gate control circuit for improving the rate of change of the DS terminal voltage in dynamic reverse bias test of SiC MOSFET is used to execute a graded gate control method for improving the rate of change of the DS terminal voltage in dynamic reverse bias test of SiC MOSFET, including driver chip IC1, driver chip IC2, first diode D1, second diode D2, gate resistor R1 and SiC MOSFET Q1.

[0032] The driver chip IC1 is connected to an adjustable gate power supply forward voltage Vadj. The input terminal of the driver chip IC1 is used to receive the switch control signal S1. The output terminal of the driver chip IC1 is connected in series with the first diode D1 and coupled to one end of the gate resistor R1. One end of the gate resistor R1 is provided with a gate resistor voltage Vdr detection point. The other end of the gate resistor R1 is coupled to the gate of the SiC MOSFET Q1. The other end of the gate resistor R1 is provided with a gate voltage Vgs detection point.

[0033] The driver chip IC2 is connected to the positive gate power supply voltage VON. The input terminal of the driver chip IC2 is used to receive the switch control signal S2. The output terminal of the driver chip IC2 is connected in series with the second diode D2 and then coupled to one end of the gate resistor R1.

[0034] By adopting the above technical solution, and through the series isolation structure of driver chips IC1 and IC2 in conjunction with the first diodes D1 and D2, hierarchical power supply and precise switching control of the gate drive circuit of SiC MOSFET Q1 are achieved. IC1 is connected to an adjustable voltage Vadj, and IC2 is connected to a conventional voltage VON. Both are driven by independent switching control signals S1 and S2, respectively. The unidirectional conduction characteristics of the first diodes D1 and D2 ensure safe isolation and seamless switching of the power supply path, avoiding crosstalk and backflow risks between different voltage sources. When executing the hierarchical gate control method, this circuit structure can provide enhanced drive current through driver chips IC1 and Vadj in stage T2, significantly accelerating Q... The charging process of the input capacitor Cgs and Miller capacitor Cgd enables the gate voltage to quickly reach the Miller plateau, effectively shortening the Miller plateau duration and thus improving the voltage change rate dV / dt at the DS terminal to meet the AQG324 standard of greater than 50V / ns, and 100V / ns for discrete devices. In stage T3, the circuit switches to IC2 and VON power supply to continue charging the Miller capacitor with a lower drive current, avoiding overshoot risks. In stages T1 and T4, the circuit switches to reverse VEE extraction to suppress voltage overshoot and high-frequency oscillation at the end of turn-on, improving electromagnetic interference characteristics. Through flexible adjustment of the Vadj amplitude, this circuit can be adapted to SiC MOSFET devices with different junction capacitance characteristics, balancing improved switching speed with system reliability, and resolving the technical contradiction of balancing speed and stability with a single gate resistor.

[0035] Optionally, the driver chip IC1 includes a first transistor and a second transistor, and the driver chip IC2 includes a third transistor and a fourth transistor. The collector of the first transistor is connected to an adjustable gate power supply forward voltage Vadj, the base of the first transistor is used to receive a switch control signal S1, and the emitter of the first transistor is coupled to the first diode D1. The base of the second transistor is used to receive the switch control signal S1, and the emitter of the second transistor is coupled to the gate power supply reverse voltage VEE.

[0036] The bases of both the third and fourth transistors are used to receive the switch control signal S2. The collector of the third transistor is coupled to the forward voltage VON of the gate power supply, and the emitter of the third transistor is coupled to the second diode D2. The emitter of the fourth transistor is coupled to the reverse voltage VEE of the gate power supply, and the collector of the fourth transistor is coupled to one end of the gate resistor R1.

[0037] By adopting the above technical solution, each driver chip uses complementary transistors to form a push-pull output stage with the first and second transistors of driver chip IC1 and the third and fourth transistors of driver chip IC2. The stage is synchronously driven by the same control signal S1 or / and S2, realizing the rapid switching between the gate charging path and the discharging path, effectively shortening the switching transition time, and enhancing the active extraction capability of gate charge. This helps to suppress voltage overshoot and oscillation, and improve system reliability.

[0038] In summary, this application includes at least one of the following beneficial technical effects:

[0039] 1. By employing enhanced drive with a higher voltage Vadj than usual in stage T2 and adaptive drive with VON in stage T3, a hierarchical control strategy dynamically adjusts the drive capability of each stage of the Miller platform. Compared with traditional fixed gate voltage drive, hierarchical control shortens the Miller platform, effectively improving dV / dt, thereby shortening the switching time and meeting the AQG324 standard requirement of dV / dt greater than 50V / ns.

[0040] 2. The current flow direction of the graded regulation is precisely controllable. In stages T2 and T3, the gate current direction is maintained as a positive current flowing from the driving power supply to the gate of the SiC MOSFET, ensuring continuous charging of the gate capacitor. In stage T2, the drive is enhanced by Vadj, and both S1 and S2 are kept at high level. In stage T3, the drive is switched to VON. The graded regulation of the drive current is achieved by changing the amplitude of the drive voltage. Stage T1 is reverse bias before turn-on, and stage T4 switches to VEE reverse extraction again to achieve bidirectional control before and after turn-on.

[0041] 3. In the T4 stage, the gate charge is extracted by the reverse voltage of VEE, which makes the gate voltage stabilize quickly and improves the electromagnetic interference characteristics.

[0042] 4. Balancing switching speed and system reliability: The hierarchical control strategy provides sufficient drive capability to ensure switching speed during the initial turn-on stage of T1 and the middle stages of T2 and T3. At the end of the turn-on stage, oscillation is suppressed by reverse extraction of VEE, which solves the contradiction between speed and stability that is difficult to balance with a single gate resistor.

[0043] 5. Vadj is an adjustable gate power supply forward voltage, which can be flexibly adjusted according to the junction capacitance characteristics of different SiC MOSFET devices. It has a wide range of applications, adjustable parameters, and strong adaptability. Attached Figure Description

[0044] Figure 1 This is a timing diagram of the T1 to T4 control stages in Embodiment 1 of this application;

[0045] Figure 2These are schematic diagrams showing the flow of the gate current in stage T1 of Embodiment 1 and the structure of the control circuit in Embodiment 2 of this application;

[0046] Figure 3 This is a schematic diagram of the gate current flow in stage T2 of Embodiment 1 of this application;

[0047] Figure 4 This is a schematic diagram of the gate current flow in stage T1 of Embodiment 1 of this application;

[0048] Figure 5 This is a schematic diagram of the gate current flow in stage T1 of Embodiment 1 of this application;

[0049] Figure 6 This is a waveform comparison diagram of Embodiment 1 of this application and the traditional fixed gate voltage drive. Detailed Implementation

[0050] To make the purpose, technical solution, and advantages of this application clearer, the following description is provided in conjunction with the appendix. Figure 1-6 The present application will be further described in detail below with reference to embodiments. It should be understood that the specific embodiments described herein are for illustrative purposes only and are not intended to limit the scope of the application.

[0051] Embodiment 1 of this application discloses a graded gate modulation method for improving the rate of change of the DS-terminal voltage during dynamic reverse bias testing of SiC MOSFETs. (Refer to...) Figure 1 The graded gate control method for improving the rate of change of the DS terminal voltage in the dynamic reverse bias test of SiC MOSFET includes four control stages, namely the T1 stage, the T2 stage, the T3 stage and the T4 stage.

[0052] S10: During the T1 stage, both S1 and S2 are at low level. VEE is used for reverse bias to reliably turn off the device. S1 is the input signal of driver chip IC1, S2 is the input signal of driver chip IC2, and VEE is the reverse voltage of the gate power supply.

[0053] Specifically, refer to Figure 1 and Figure 2 Step S10 includes controlling S1 and S2 to maintain a low level, so that the gate power supply reverse voltage VEE is connected to the gate of the SiC MOSFET, and Vadj and VON are isolated from the gate of the SiC MOSFET.

[0054] In this state, the Vdr potential at the front end of the gate resistor R1 is pulled down to the negative voltage of VEE. Since the gate voltage VGS is higher than VEE, the charge stored on the gate capacitance, i.e., the input capacitance Cgs and the Miller capacitance Cgd, flows along the discharge path Q1 from the gate to the gate resistor R1 under the voltage difference drive, then to the driver chip IC2 and to the VEE terminal, forming... Figure 2The reverse extraction current is indicated by the red dashed line.

[0055] This reverse draw process quickly and completely discharges the residual positive charge in the gate capacitance to VEE, clamping VGS at the negative voltage level of VEE, typically -3V to -5V. Under this negative bias, the SiC MOSFET Q1 has sufficient threshold voltage margin, and even under high temperature or high dv / dt interference, the gate will not be mis-turned on due to parasitic Miller effect or coupling noise, ensuring that the device is in a reliable off state before turn-on.

[0056] This stage serves as the initial preparation stage for the entire graded control cycle. By thoroughly clearing the residual charge on the gate, it provides a zero-starting-charge condition for the subsequent T2 stage Vadj enhancement drive, ensuring that each turn-on starts from a defined negative voltage reference. This guarantees the consistency of the charging rate of the input capacitor Cgs in the T2 stage, avoids switching time jitter caused by inconsistent starting voltage, and lays the foundation for precise control of dV / dt.

[0057] S20: During the T2 phase, both S1 and S2 are at high levels. Vadj, which is an adjustable gate power supply forward voltage, is used to enhance the drive, accelerating the charging of the input capacitor Cgs and the Miller capacitor.

[0058] Specifically, refer to Figure 1 and Figure 3 Step S20 includes controlling S1 and S2 to both switch to high level, and the adjustable gate power supply forward voltage Vadj is connected to the gate of SiC MOSFET Q1 after passing through the upper transistor inside the driver chip IC1, the first diode D1, and the gate resistor R1, forming Figure 3 The forward charging circuit is shown by the red dashed line in the middle.

[0059] At this point, the Vdr potential is raised to Vadj, typically 20V~30V, which is much higher than the conventional drive voltage VON. The gate drive current Ig=(Vadj-VGS) / R1. Since Vadj is much larger than VGS, which is initially a negative VEE voltage, a peak current much larger than that of the conventional drive scheme can be obtained in this stage.

[0060] Under the influence of the ultra-large drive current, the input capacitance Cgs of the SiC MOSFET Q1 is rapidly charged, and the gate voltage VGS quickly crosses the threshold voltage Vth from the VEE negative voltage with a high slope, reaching the Miller plateau voltage Vplat. During this stage, the turn-on delay time td(on) is significantly compressed to the nanosecond level. After entering the Miller plateau, due to the continuous power supply of Vadj and its high amplitude, the drive current Ig remains large. This strong current continuously provides sufficient charge to the Miller capacitance Cgd, maintaining the voltage change rate in the Miller plateau region at a high level and effectively shortening the duration of the Miller plateau.

[0061] Depending on the junction capacitance of the SiC MOSFET device, the duration of this stage can be dynamically adjusted within the range of 150ns to 400ns. Specifically, for SiC modules with large junction capacitance, such as multiple chips connected in parallel, Vadj is increased to increase the gate drive current Ig, thereby improving the charging rate and shortening the rise time. For discrete devices with small junction capacitance, Vadj is decreased to avoid gate oscillation caused by excessively fast di / dt.

[0062] This stage, through Vadj-enhanced driving, achieves rapid transition of the input capacitor Cgs charging stage and efficient charging in the early stage of the Miller plateau. On the one hand, it significantly shortens the turn-on delay time td(on) and the duration of the Miller plateau, creating conditions for improving dV / dt. On the other hand, by adjusting the Vadj amplitude, the driving capability is matched with the junction capacitance characteristics of the device under test, ensuring speed while avoiding excessive voltage overshoot and ringing due to excessive driving capability, thus achieving a balance between speed and reliability.

[0063] S30: During the T3 phase, S1 is low and S2 is high, switching to the normal voltage VON to reduce the drive current and continue charging the Miller capacitor. VON is the positive voltage of the gate power supply.

[0064] Specifically, refer to Figure 1 and Figure 4 Step S30 specifically includes controlling S1 to switch to a low level and S2 to maintain a high level. The gate power supply forward voltage VON is connected to the gate of SiC MOSFET Q1 after passing through the upper transistor inside the driver chip IC2, the second diode D2, and the gate resistor R1, forming... Figure 4 The forward charging circuit is shown by the red dashed line in the middle, with Vadj isolated from the gate.

[0065] At this time, the Vdr potential at the front end of the gate resistor switches from Vadj in stage T2 to VON, with a typical value of 15V~18V. The gate drive current switches from Ig_high=(Vadj-VGS) / R1 to Ig_low=(VON-VGS) / R1, and the current amplitude decreases.

[0066] At this stage, the Miller capacitance Cgd of the SiC MOSFET Q1 is nearly saturated, and the voltage change rate dV / dt at the DS terminal has basically reached the target value. The gate charge requirement has decreased significantly, and only a small holding current is needed to complete the residual charging of the Miller capacitance. If the enhanced drive current of stage T2 is applied during this stage, the excess drive energy will have nowhere to be released after the Miller capacitance is fully charged. This will form an LC resonance between the gate circuit inductor and capacitor, causing gate voltage overshoot and subsequent high-frequency ringing, worsening electromagnetic interference, and possibly exceeding the gate withstand voltage limit of Q1.

[0067] By switching to a lower voltage VON power supply in the T3 stage, the drive current is actively reduced to an appropriate level, so that the gate charge injection rate is precisely matched with the residual charge demand of the Miller capacitor. Under the premise of ensuring that the Miller capacitor is fully charged, the Miller platform is smoothly completed with a reduced drive current. This actively suppresses voltage overshoot and gate ringing caused by excess drive energy at the end of turn-on, and achieves a smooth current transition from the enhanced drive stage to the reverse extraction stage. This lays the initial condition for rapid stabilization at the end of turn-on without oscillation, and effectively solves the contradiction between turn-on speed and electromagnetic interference in the traditional single gate drive scheme.

[0068] S40: During the T4 phase, S1 and S2 are at low levels, and the device switches back to VEE reverse bias to turn off.

[0069] Specifically, refer to Figure 1 and Figure 5 Step S40 includes maintaining S1 at a low level and switching S2 to a low level. The reverse gate power supply voltage VEE is connected to one end of the gate resistor R1 via the third switch. Vadj and VON are both isolated from the gate. At this time, the Vdr potential is rapidly pulled down from VON in stage T3 to the negative voltage of VEE. Since the gate voltage VGS of SiC MOSFET Q1 is close to the Miller plateau voltage Vplat at the end of stage T3, which is much higher than VEE, a reverse voltage difference is formed across the gate capacitor, driving the positive charge stored in the gate to be discharged in reverse to VEE through the gate resistor R1, thereby turning off the device.

[0070] The gate current direction is completely opposite to that in stages T2 and T3. Charge flows out from the gate of SiC MOSFET Q1, through the gate resistor R1 and the third switch, into the VEE terminal, forming... Figure 5 The red dashed line shows the active reverse extraction current. The magnitude of the current changes dynamically with the difference between VGS and VEE. A large reverse peak current can be generated at the moment of initial extraction, which quickly pulls down VGS.

[0071] The gate voltage VGS drops from the Miller plateau voltage Vplat to the VEE negative voltage at an extremely fast rate. The rapid drop in gate voltage directly drives the DS terminal voltage to stabilize to the target voltage value quickly, effectively shortening the voltage stabilization time at the end of the turn-on period. Furthermore, after switching to a lower drive voltage in stage T3, although the forward drive current has been greatly reduced, the reverse extraction current introduced in stage T4 is equivalent to resetting back to stage T1.

[0072] In this embodiment, the amplitude adjustment of the adjustable gate power supply positive voltage Vadj is the core parameter adjustment method to achieve graded gate control. In the T2 stage, Vadj is connected to the gate of SiCMOSFETQ1 through the driver chip IC1, the first diode D1 and the gate resistor R1. The gate drive current Ig=(Vadj-VGS) / R1, where VGS is the VEE negative voltage in the initial stage of turn-on, so Ig is approximately proportional to Vadj.

[0073] Since the charging rate of the input capacitor Cgs is dVGS / dt=Ig / Ciss=(Vadj-VGS) / (R1×Ciss), under the condition that R1 and Ciss are fixed, the magnitude of Vadj directly determines the time required for VGS to rise from VEE to the Miller plateau voltage Vplat. That is, the higher Vadj is, the larger dVGS / dt is, the faster the speed to reach the Miller plateau, and the shorter the turn-on delay time td(on) is, and vice versa.

[0074] Therefore, by adjusting the Vadj amplitude, the arrival time at the Miller plateau can be precisely adjusted to adapt to different dV / dt requirements. In practical engineering applications, it is necessary to identify the junction capacitance characteristics of the SiC MOSFET device under test in advance. Specifically, this can be done by consulting the input capacitance Ciss and Miller capacitance Crss (Cgd parameter values) in the device datasheet, or by offline measurement using an impedance analyzer. When the device under test is a SiC module, i.e., including multiple SiC chips connected in parallel internally, its junction capacitance accumulates exponentially, with typical Ciss values ​​reaching 10nF~20nF. Such a large capacitance requires sufficient charge injection in the T2 stage to quickly cross the Miller plateau. Therefore, Vadj should be increased to provide a sufficiently large drive current Ig to ensure efficient charging of the junction capacitance within a limited time.

[0075] When the device under test is a discrete SiC MOSFET, its Ciss value is usually between 1nF and 5nF, requiring a small drive current. If a high amplitude Vadj is still used for driving, an excessive Ig will cause gate voltage overshoot and ringing. Therefore, Vadj should be appropriately reduced to match the smaller junction capacitance and avoid excessive drive energy causing voltage overshoot and electromagnetic interference.

[0076] In addition, the amplitude adjustment of Vadj must also take into account the voltage withstand capability and current carrying capacity of the driver chip IC1 and the first diode D1 to ensure that when Vadj is adjusted to the upper limit, the components of the drive circuit still operate within the safe range.

[0077] By setting Vadj as a continuously adjustable or stepped adjustable voltage source, the same set of stepped gate control circuits can cover SiC MOSFET devices with different junction capacitance specifications, such as discrete devices and multi-chip modules. The optimal dV / dt improvement effect can be achieved simply by adjusting the Vadj amplitude according to the junction capacitance characteristics of the device under test, without the need to change the driver circuit hardware. It has good versatility and engineering adaptability.

[0078] In this embodiment, refer to Figure 6 This image shows a comparison of the gate voltage waveforms using a hierarchical gate control strategy and a traditional fixed gate voltage drive. The black waveform represents the hierarchical gate control strategy, while the red waveform represents the traditional fixed gate voltage drive.

[0079] In the traditional fixed gate voltage driving method, only a single supply voltage VON is used throughout the entire turn-on process. The Miller plateau lasts for t3~t5. During this period, the gate voltage is clamped near Vplat, and dV / dt is limited by the Miller capacitor charging rate and cannot be effectively improved.

[0080] Under the hierarchical gate control strategy of this invention, the Miller platform time period is t2~t4, which is significantly shorter than the traditional method. Here, t2~t3 corresponds to the T2 stage in this embodiment, which uses Vadj enhanced drive, and the Miller capacitor charging speed is significantly faster than the traditional method. t3~t4 corresponds to the T3 stage, which switches to VON drive. Although the driving capability is reduced, the Miller capacitor is almost fully charged at this time, and a lower driving current can be maintained.

[0081] Through the aforementioned graded control, the total Miller platform time is shortened from t3-t5 in the traditional method to t2-t4, effectively improving dV / dt. Simultaneously, the T4 stage employs VEE reverse sampling, enabling the gate voltage to stabilize rapidly at the end of the turn-on period.

[0082] Embodiment 2 of this application also discloses a graded gate control circuit for improving the rate of change of the DS-terminal voltage during dynamic reverse bias testing of SiC MOSFETs, used to execute a graded gate control method for improving the rate of change of the DS-terminal voltage during dynamic reverse bias testing of SiC MOSFETs, referring to... Figure 2 It includes driver chip IC1, driver chip IC2, first diode D1, second diode D2, gate resistor R1, and SiC MOSFET Q1;

[0083] The driver chip IC1 includes a first transistor and a second transistor, and the driver chip IC2 includes a third transistor and a fourth transistor.

[0084] The collector of the first transistor is connected to the adjustable gate power supply forward voltage Vadj, the base of the first transistor is used to receive the switch control signal S1, and the emitter of the first transistor is coupled to one end of the first diode D1. The base of the second transistor is used to receive the switch control signal S1, and the emitter of the second transistor is coupled to the gate power supply reverse voltage VEE.

[0085] The bases of both the third and fourth transistors are used to receive the switch control signal S2. The collector of the third transistor is coupled to the forward voltage VON of the gate power supply, and the emitter of the third transistor is coupled to the second diode D2. The emitter of the fourth transistor is coupled to the reverse voltage VEE of the gate power supply, and the collector of the fourth transistor is coupled to one end of the gate resistor R1.

[0086] The other end of the first diode D1 is coupled to one end of the gate resistor R1. A gate resistor voltage Vdr detection point is set at one end of the gate resistor R1. The other end of the gate resistor R1 is coupled to the gate of the SiC MOSFET Q1. A gate voltage Vgs detection point is set at the other end of the gate resistor R1.

[0087] The driver chip IC2 is connected to the positive voltage VON of the gate power supply. The input terminal of the driver chip IC2 is used to receive the switch control signal S2. The output terminal of the driver chip IC2 is connected in series with the second diode D2 and then coupled to one end of the gate resistor R1.

[0088] The implementation principle of the graded gate control circuit for improving the voltage change rate of the DS terminal in the dynamic reverse bias test of SiC MOSFET in this application embodiment is as follows: the driver chip IC1 is composed of a first transistor, namely the upper transistor and the second transistor in embodiment 1, and the lower transistor in embodiment 1 to form a push-pull output stage; the driver chip IC2 is composed of a third transistor and a fourth transistor to form a push-pull output stage; the conduction and turn-off of each transistor are independently controlled by the switch control signals S1 and S2 respectively.

[0089] When S1 is high, the first transistor is turned on and the second transistor is turned off. Vadj injects positive current into the gate of Q1 through the first transistor, the first diode D1, and the gate resistor R1, forming a charging circuit. At this time, the Vdr potential is raised to Vadj.

[0090] When S2 is high, the third transistor is turned on and the fourth transistor is turned off. VON injects positive current into the gate of Q1 through the third transistor, the second diode D2, and the gate resistor R1.

[0091] When S1 and S2 are at low levels, the third transistor is cut off and the fourth transistor is turned on, and the gate charge is discharged to VEE through the fourth transistor.

[0092] The first diode D1 and the second diode D2 provide unidirectional isolation, preventing reverse current flow between the two positive voltages Vadj and VON through the gate resistor, ensuring that the two drive sources do not interfere with each other when switching between S1 and S2. At the same time, D1 and D2 block the reverse current path, preventing the gate charge of Q1 from being discharged through an unexpected path.

[0093] The collector of the fourth transistor is directly coupled to the Vdr node at one end of the gate resistor R1, so that the lower transistor of IC2 can provide an additional low-impedance discharge path for the gate charge when S2 is low, thereby enhancing the gate discharge capability.

[0094] The Vdr and VGS detection points are used to monitor the voltage waveforms before and after the gate resistor in real time, so as to accurately control the switching timing of each stage and evaluate the control effect. Through the four-state switching of the S1 and S2 level combination, the different driving sources of the four stages T1 to T4 achieve graded power supply and reverse extraction of the gate.

[0095] The above are all preferred embodiments of this application and are not intended to limit the scope of protection of this application. Any feature disclosed in this specification (including the abstract and drawings) may be replaced by other equivalent or similar features unless specifically stated otherwise. That is, unless specifically stated otherwise, each feature is only one example of a series of equivalent or similar features.

Claims

1. A graded gate control method for improving the rate of change of the DS-terminal voltage in dynamic reverse bias testing of SiC MOSFETs, characterized in that: It includes several control phases, including the TI phase, T2 phase, T3 phase and T4 phase; During the T1 stage, both S1 and S2 are at low level, and VEE is used for reverse bias to reliably turn off the device. S1 is the input signal of driver chip IC1, S2 is the input signal of driver chip IC2, and VEE is the reverse voltage of the gate power supply. During the T2 phase, both S1 and S2 are at high levels, and Vadj, which is a higher voltage than the conventional voltage, is used for enhanced driving. Vadj is an adjustable gate power supply positive voltage, which accelerates the charging of the input capacitor Cgs and the Miller capacitor. During the T3 phase, S1 is at a low level and S2 is at a high level, switching to the normal voltage VON for power supply to reduce the drive current and continue charging the Miller capacitor. VON is the positive voltage of the gate power supply. During the T4 phase, S1 and S2 are at low levels, and the device switches back to VEE reverse bias, turning off the device.

2. The graded gate control method for improving the rate of change of the DS-terminal voltage in dynamic reverse bias testing of SiC MOSFETs according to claim 1, characterized in that: During stage T1, when both S1 and S2 are at low levels and VEE is reverse biased, the steps to reliably turn off the device include: Controlling S1 and S2 to maintain a low level, in the switching circuit, the third switch connected to VEE is closed, the first switch connected to Vadj and the second switch connected to VON are both open, VEE is connected to the gate, Vadj and VON are both open, and the gate current flows from the SiC MOSFET gate through the gate resistor to VEE, forming a reverse draw.

3. The graded gate control method for improving the rate of change of the DS-terminal voltage in dynamic reverse bias testing of SiC MOSFETs according to claim 1, characterized in that: In the T2 stage, both S1 and S2 are at high levels, using a Vadj-enhanced drive higher than the conventional voltage. Vadj is an adjustable gate power supply forward voltage. This step accelerates the charging of the input capacitor Cgs and the Miller capacitor, including: By keeping both S1 and S2 at a high level, the gate power supply forward voltage Vadj can be adjusted and connected to the gate of the SiC MOSFET. Vadj is greater than VON, and the gate current flows from Vadj through the gate resistor to the gate of the SiC MOSFET, thus forward charging the gate capacitance of the SiC MOSFET.

4. The graded gate control method for improving the rate of change of the DS-terminal voltage in dynamic reverse bias testing of SiC MOSFETs according to claim 1, characterized in that: During the T3 phase, S1 is low and S2 is high, switching to the normal voltage VON for power supply to reduce the drive current and continue the Miller capacitor charging process, including: When S1 is switched to low level and S2 is kept high level, VON is connected to the gate of the SiC MOSFET, Vadj is disconnected, and the gate current flows from VON through the gate resistor to the gate of the SiC MOSFET.

5. A graded gate control method for improving the rate of change of the DS-terminal voltage in dynamic reverse bias testing of SiC MOSFETs according to claim 1, characterized in that: The steps of switching back to VEE reverse bias and turning off the device during the T4 stage when S1 and S2 are low include: When S1 is low, S2 is switched to low, VEE is connected to the gate of the SiC MOSFET, Vadj and VON are both disconnected, and the gate current of the SiC MOSFET flows in the opposite direction, from the gate of the SiC MOSFET through the gate resistor to VEE, which means resetting to stage T1.

6. The graded gate control method for improving the rate of change of the DS-terminal voltage in dynamic reverse bias testing of SiC MOSFETs according to claim 3, characterized in that: In the T2 stage, both S1 and S2 are at high levels, and Vadj, which is higher than the conventional voltage, is used for enhanced driving. Vadj is an adjustable gate power supply forward voltage. In the step of accelerating the charging of input capacitor Cgs and Miller capacitor, the charging rate of input capacitor Cgs is adjusted by adjusting the amplitude of the adjustable gate power supply forward voltage Vadj, thereby adjusting the time to reach the Miller platform. By identifying the junction capacitance characteristics of SiC MOSFET devices, the larger the junction capacitance, the larger the required drive current, and Vadj is increased accordingly. If the junction capacitance is small, adjust Vadj appropriately.

7. A graded gate control circuit for improving the rate of change of the DS-terminal voltage during dynamic reverse bias testing of SiC MOSFETs, used to execute a graded gate control method for improving the rate of change of the DS-terminal voltage during dynamic reverse bias testing of SiC MOSFETs, characterized in that: It includes driver chip IC1, driver chip IC2, first diode D1, second diode D2, gate resistor R1, and SiC MOSFET Q1; The driver chip IC1 is connected to an adjustable gate power supply forward voltage Vadj. The input terminal of the driver chip IC1 is used to receive the switch control signal S1. The output terminal of the driver chip IC1 is connected in series with the first diode D1 and coupled to one end of the gate resistor R1. One end of the gate resistor R1 is provided with a gate resistor voltage Vdr detection point. The other end of the gate resistor R1 is coupled to the gate of the SiC MOSFET Q1. The other end of the gate resistor R1 is provided with a gate voltage Vgs detection point. The driver chip IC2 is connected to the positive gate power supply voltage VON. The input terminal of the driver chip IC2 is used to receive the switch control signal S2. The output terminal of the driver chip IC2 is connected in series with the second diode D2 and then coupled to one end of the gate resistor R1.

8. A graded gate control circuit for improving the rate of change of the DS-terminal voltage in dynamic reverse bias testing of SiC MOSFETs according to claim 7, characterized in that: The driver chip IC1 includes a first transistor and a second transistor, and the driver chip IC2 includes a third transistor and a fourth transistor. The collector of the first transistor is connected to an adjustable gate power supply forward voltage Vadj, the base of the first transistor is used to receive a switch control signal S1, and the emitter of the first transistor is coupled to the first diode D1. The base of the second transistor is used to receive the switch control signal S1, and the emitter of the second transistor is coupled to the gate power supply reverse voltage VEE. The bases of both the third and fourth transistors are used to receive the switch control signal S2. The collector of the third transistor is coupled to the forward voltage VON of the gate power supply, and the emitter of the third transistor is coupled to the second diode D2. The emitter of the fourth transistor is coupled to the reverse voltage VEE of the gate power supply, and the collector of the fourth transistor is coupled to one end of the gate resistor R1.

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