High-voltage-resistant isolated analog switch circuit and integrated circuit chip

Abstract

The application discloses a high-voltage-resistance isolation analog switch circuit, which is connected between an external analog input / output terminal PAD and a chip internal analog node AY, and comprises a first analog switch, a second analog switch, a pull-up PMOS switch MPPU1, a bias circuit BIAS, an N switch driving circuit NGS and a P switch driving circuit PGS. Through adaptive adjustment of the substrate potential and the gate voltage of the PMOS switch and the NMOS switch in the first analog switch, in the state that the power supply normally supplies power and the switch is off, the high voltage and noise of the external analog input / output terminal can be effectively isolated, and the device can be protected from being damaged by the external high voltage.

Description

Technical Field

[0001] This invention relates to the field of analog switches, and more particularly to a high-voltage isolation analog switch circuit and integrated circuit chip. Background Technology

[0002] In microcontrollers (MCUs), isolation analog switches are often used as interfaces between external analog signals and internal analog circuits. Circuits such as analog-to-digital converters, operational amplifiers, and comparators all require isolation analog switches to select from multiple analog signals: a conducting isolation analog switch transmits the required analog signal into the chip; a de-converted isolation analog switch isolates unwanted signals from the chip. Figure 1 This is a circuit diagram of an isolated analog switch widely used in MCUs in existing technologies.

[0003] Figure 1 The conventional isolation analog switch shown consists of PMOS switches MPS1 and MPS2, NMOS switches MNS1 and MNS2, and a pull-down NMOS switch MNPD1. MPS1's source is connected to the external analog input / output terminal PAD, its drain is connected to intermediate node t1, and its gate is connected to the inverse enable signal enb. MNS1's source is connected to the external analog input / output terminal PAD, its drain is connected to intermediate node t1, and its gate is connected to the enable signal en. MPS1 and MNS1 form the first-stage analog switch. MPS2's source is connected to intermediate node t1, its drain is connected to internal analog node AY, and its gate is connected to the inverse enable signal enb. MNS2's source is connected to intermediate node t1, its drain is connected to internal analog node AY, and its gate is connected to the enable signal en. MPS2 and MNS2 form the second-stage analog switch. The pull-down NMOS switch MNPD1 has its source grounded, its drain connected to intermediate node t1, and its gate connected to the inverse enable signal enb. It is responsible for absorbing noise from intermediate node t1 to ground when the analog switch is off. The enable signal en is the switch conduction control signal. When en is high, the switch is on; when en is low, the switch is off. The inverse enable signal enb is the inverse of the enable signal en.

[0004] When the enable signal en is high, the inverse enable signal enb is low, and the transmission gates of the first and second stage analog switches are turned on. Under different signal levels, the PMOS branch and / or NMOS branch conduct, the pull-down NMOS switch MNPD1 is turned off, and the isolation analog switch is on. The external analog input / output terminal PAD is connected to the internal analog node AY. When the enable signal en is low, the inverse enable signal enb is high, both stage analog switches are turned off, the pull-down NMOS switch MNPD1 is turned on, and the isolation analog switch is off. When a short pulse exceeding the power supply, a short pulse below ground, or high-frequency coupled noise appears at the external analog input / output terminal PAD, the turned-off first stage analog switch reduces the noise amplitude. The reduced noise is absorbed to ground by the pull-down NMOS switch MNPD1 and cannot interfere with the internal circuit through the turned-off second stage analog switch, thus achieving internal and external isolation.

[0005] When the MCU power supply and external signal are in the same voltage domain, the aforementioned conventional isolation analog switch can function normally. However, MCUs often need to communicate with external signals in a voltage domain higher than their own power supply voltage. For example, a 1.8V powered MCU needs to support a 3.3V communication protocol, and a 3.3V powered MCU needs to support a 5V communication protocol. In this case, the conventional isolation analog switch not only cannot isolate high-voltage signals but also risks damage itself. Taking a 3.3V powered MCU facing a 5V input signal as an example: when the external analog input / output terminal PAD is 5V, the reverse enable signal enb is 3.3V in the switch-off state. The gate voltage (3.3V) of PMOS switch MPS1 is lower than its source voltage (5V), causing PMOS switch MPS1 to be mis-turned on and unable to block the external 5V signal from entering the chip. At the same time, the gate of NMOS switch MNS1 is at ground potential, and the voltage difference between its gate and source is 5V, which is much higher than the gate-source safety voltage of a 3.3V low-voltage NMOS device. MNS1's gate oxide is at risk of overvoltage damage.

[0006] Furthermore, the conventional solution uses a pull-down NMOS switch MNPD1 to pull the intermediate node t1 to ground to absorb noise. However, this pull-down node solution also has shortcomings in high-voltage scenarios: it cannot prevent high voltage from entering the chip through a mis-converted PMOS switch, nor can it solve the gate oxide overvoltage problem of the NMOS switch; and when high voltage is coupled to the intermediate node t1, the drain terminal of the pull-down NMOS switch MNPD1 itself may experience high voltage stress, and whether it exceeds the device's rated terminal voltage needs to be evaluated in conjunction with the specific process. Therefore, a simple two-stage transmission gate plus pull-down transistor structure cannot achieve high-voltage isolation and device protection.

[0007] Based on the above problems, a new high-voltage isolation analog switch circuit is needed. Summary of the Invention

[0008] The technical problem to be solved by the present invention is: the purpose of the present invention is to provide a high voltage-resistant isolated analog switch circuit that is compatible with the MCU power supply and external signal being in the same voltage domain, and the MCU power supply being one level lower than the voltage domain of the external signal.

[0009] To address the aforementioned technical problems, this invention provides a high-voltage isolated analog switch circuit connected between an external analog input / output terminal PAD and an internal analog node AY. The circuit includes a first analog switch, a second analog switch, a pull-up PMOS switch MPPU1, a bias circuit BIAS, an N-switch driver circuit NGS, and a P-switch driver circuit PGS. Specifically, the first analog switch comprises a first PMOS switch MPS1 and a first NMOS switch MNS1 connected in parallel. The source terminal of the first PMOS switch MPS1 is connected to the external analog input / output terminal PAD, the drain terminal is connected to the intermediate node t1, the gate terminal is connected to the P-switch drive voltage pgenb output by the P-switch driver circuit PGS, and the substrate is connected to the... The bias circuit BIAS outputs a substrate bias voltage vsub; the source terminal of the first NMOS switch MNS1 is connected to the external analog input / output terminal PAD, the drain terminal is connected to the intermediate node t1, the gate terminal is connected to the N-switch drive voltage ngen output by the N-switch drive circuit NGS, and the substrate is connected to the ground terminal GND; the second analog switch includes a second PMOS switch MPS2 and a second NMOS switch MNS2 connected in parallel; the second analog switch is connected between the intermediate node t1 and the internal analog node AY; the gate terminal of the second PMOS switch MPS2 is connected to the inverse enable signal enb, and the gate terminal of the second NMOS switch MNS2 is connected to the enable signal en. The signal enb is the inverse of the enable signal en; the source and substrate of the pull-up PMOS switch MPPU1 are connected to the chip power supply VDD, the drain is connected to the intermediate node t1, and the gate is connected to the enable signal en; the input of the bias circuit BIAS includes: the enable signal en, the inverse enable signal enb, and the external analog input / output terminal PAD, and outputs the substrate bias voltage vsub and the P gate bias voltage pgt, and is configured such that: when the enable signal en is low, the high-voltage isolation analog switch circuit is in the off state, and the voltage of the external analog input / output terminal PAD is higher than the voltage of the chip power supply VDD, the substrate bias voltage vsub follows the external analog input / output terminal PAD. The voltage at the output terminal PAD; the inputs of the P-switch drive circuit PGS include: an inverse enable signal enb, an external analog input / output terminal PAD, a substrate bias voltage vsub, and a P-gate bias voltage pgt, configured such that when the enable signal enb is low, the high-voltage isolation analog switch circuit is off, and the voltage at the external analog input / output terminal PAD is higher than the voltage at the chip power supply VDD, the output P-switch drive voltage pgenb follows the voltage at the external analog input / output terminal PAD to keep the first PMOS switch MPS1 off; the inputs of the N-switch drive circuit NGS include: an inverse enable signal enb and an external analog input / output terminal PAD;The N-switch driver circuit NGS includes a clamped NMOS transistor whose source terminal is connected to the external analog input / output terminal PAD. The N-switch driver circuit NGS is configured to clamp the N-switch drive voltage ngen at a potential lower than the chip power supply VDD by one turn-on threshold voltage of the clamped NMOS transistor when the enable signal en is low, the high-voltage isolated analog switch circuit is off, and the voltage of the external analog input / output terminal PAD is higher than the chip power supply VDD.

[0010] Further, the bias circuit BIAS includes a first PMOS transistor MP1, a second PMOS transistor MP2, a third PMOS transistor MP3, a first NMOS transistor MN1, a second NMOS transistor MN2, and a third NMOS transistor MN3; wherein: the drain of the first PMOS transistor MP1 is connected to the chip power supply VDD, the source and substrate are connected to the substrate bias voltage vsub output terminal, and the gate is connected to the P-gate bias voltage pgt output terminal; the source and substrate of the second PMOS transistor MP2 are connected to the substrate bias voltage vsub output terminal, the drain is connected to the external analog input / output terminal PAD, and the gate is connected to the chip power supply VDD. D; The source terminal of the third PMOS transistor MP3 is connected to the output terminal of the P-gate bias voltage pgt, the drain terminal is connected to the external analog input / output terminal PAD, the gate terminal is connected to the chip power supply VDD, and the substrate is connected to the output terminal of the substrate bias voltage vsub; The source terminal of the first NMOS transistor MN1 is connected to the external analog input / output terminal PAD, the drain terminal is connected to the output terminal of the P-gate bias voltage pgt, the gate terminal is connected to the reverse enable signal enb, and the substrate is connected to the ground terminal GND; The second NMOS transistor MN2 and the third NMOS transistor MN3 are connected in series between the output terminal of the P-gate bias voltage pgt and the ground terminal GND.

[0011] Furthermore, the drain of the second NMOS transistor MN2 is connected to the output of the P-gate bias voltage pgt, the gate is connected to the chip power supply VDD, the source is connected to the drain of the third NMOS transistor MN3, and the substrate is connected to the ground terminal GND; the source and substrate of the third NMOS transistor MN3 are connected to the ground terminal GND, and the gate is connected to the enable signal en.

[0012] Further, the P-switch driving circuit PGS includes a fifth PMOS transistor MP5, a sixth PMOS transistor MP6, and a fifth NMOS transistor MN5; wherein: the source terminal of the fifth PMOS transistor MP5 is connected to the output terminal of the P-switch driving voltage pgenb, the drain terminal is connected to the inverse enable signal enb, the gate terminal is connected to the P-gate bias voltage pgt, and the substrate is connected to the substrate bias voltage vsub; the source terminal of the sixth PMOS transistor MP6 is connected to the external analog input / output terminal PAD, the drain terminal is connected to the output terminal of the P-switch driving voltage pgenb, the gate terminal is connected to the chip power supply VDD, and the substrate is connected to the substrate bias voltage vsub; the source terminal of the fifth NMOS transistor MN5 is connected to the output terminal of the P-switch driving voltage pgenb, the drain terminal is connected to the inverse enable signal enb, the gate terminal is connected to the chip power supply VDD, and the substrate is connected to the ground terminal GND.

[0013] Furthermore, the N-switch driving circuit NGS includes a fourth PMOS transistor MP4 and a fourth NMOS transistor MN4; wherein: the source terminal and substrate of the fourth PMOS transistor MP4 are connected to the chip power supply VDD, the drain terminal is connected to the output terminal of the N-switch driving voltage ngen, and the gate terminal is connected to the inverse enable signal enb; the fourth NMOS transistor MN4 is the clamped NMOS transistor, its source terminal is connected to the external analog input / output terminal PAD, its drain terminal is connected to the output terminal of the N-switch driving voltage ngen, its gate terminal is connected to the inverse enable signal enb, and its substrate is connected to the ground terminal GND.

[0014] Furthermore, each MOS transistor in the high-voltage isolation analog switch circuit is a low-voltage MOS device with a gate oxide rated voltage not higher than the chip power supply VDD voltage.

[0015] The present invention also provides an integrated circuit chip, including the high-voltage isolation analog switch circuit described above. The integrated circuit chip is a microcontroller (MCU), and the high-voltage isolation analog switch circuit serves as the interface between the external analog input / output terminal (PAD) of the microcontroller (MCU) and its internal analog circuitry. The internal analog circuitry includes an analog-to-digital converter, an operational amplifier, or a comparator.

[0016] The present invention has the following beneficial effects: (1) When the bias circuit BIAS is in the off state and the external analog input / output terminal PAD voltage is higher than the chip power supply VDD, the substrate bias voltage vsub follows the external analog input / output terminal PAD voltage, so that the substrate potential of the first PMOS switch MPS1 and other PMOS transistors is always not lower than its source / drain potential in steady state, thus preventing latch-up effect.

[0017] (2) When the P switch drive circuit PGS is in the off state and the voltage of the external analog input / output terminal PAD is higher than the chip power supply VDD, the P switch drive voltage pgenb follows the voltage of the external analog input / output terminal PAD, and the gate-source voltage difference of MPS1 is zero, thereby keeping MPS1 reliably off and realizing true isolation of the high voltage of the external analog input / output terminal PAD.

[0018] (3) The N-switch driver circuit NGS includes a clamping NMOS transistor (fourth NMOS transistor MN4) whose source terminal is connected to the external analog input / output terminal PAD. In the off state and when the voltage of the external analog input / output terminal PAD is higher than the chip power supply VDD, the N-switch drive voltage ngen is clamped to a value one NMOS turn-on threshold voltage lower than the chip power supply VDD. The gate voltage of the first NMOS switch MNS1 no longer increases with the external analog input / output terminal PAD. Thus, MNS1 remains off, avoiding overvoltage damage.

[0019] (4) The pull-up PMOS switch MPPU1 replaces the pull-down NMOS switch MNPD1. When the enable signal en is low (off state), MPPU1 is turned on, pulling the intermediate node t1 up to the chip power supply VDD. The transient noise of the external analog input / output terminal PAD is attenuated by the first analog switch that is turned off and reaches t1. It is then discharged to the power network by the turned-on MPPU1, thereby suppressing the noise from entering the internal analog node AY through the second analog switch and providing a definite discharge path for the noise of the intermediate node t1. At the same time, since the source terminal and substrate of MPPU1 are connected to VDD and t1 is pulled up to the definite potential of VDD, the problem of the drain terminal of the pull-down NMOS tube in the prior art that may be subjected to high voltage stress is avoided.

[0020] (5) After reaching a steady state within the specified external analog input / output terminal PAD voltage range, the gate-source voltage difference and gate-drain voltage difference of each MOS transistor in the circuit do not exceed the chip power supply voltage, and the substrate voltage of each PMOS transistor is not lower than its source / drain voltage. Therefore, this invention can use low-voltage MOS devices with a gate oxide rated voltage not higher than VDD under standard low-voltage CMOS process to achieve a high voltage tolerance higher than the power supply voltage within the specified external signal voltage range, without the need for high-voltage devices or special processes. It has the advantages of simple structure, low power consumption, small area, and easy integration.

[0021] In summary, by adaptively adjusting the substrate potential and gate voltage of the PMOS and NMOS switches in the first analog switch, this invention can effectively isolate high voltage and noise from external signal terminals and protect the device from damage by external high voltage when the power supply is normal and the switches are off. Attached Figure Description

[0022] The accompanying drawings, which are included to provide a further understanding of the invention and form part of this invention, illustrate exemplary embodiments of the invention and are used to explain the invention, but do not constitute an undue limitation of the invention. In the drawings: Figure 1 This is a circuit diagram of a conventional isolation analog switch in the prior art; Figure 2 A circuit diagram of a high-voltage isolation analog switch circuit provided in an embodiment of the present invention; Figure 3 The circuit diagram of the bias circuit BIAS in the high withstand voltage isolated analog switch circuit provided in the embodiment of the present invention; Figure 4 The circuit diagram of the N-switch drive circuit NGS in the high-voltage isolation analog switch circuit provided in the embodiment of the present invention; Figure 5 The circuit diagram of the P-switch drive circuit PGS in the high-voltage isolation analog switch circuit provided in the embodiment of the present invention; Figure 6 The waveform diagram shows the switch's on-state under 3.3V / 5V conditions. Figure 7 The waveform of the external signal voltage changing slowly at 3.3V / 5V is shown. Figure 8 The waveform diagram shows the rapid rise of the external signal voltage under 3.3V / 5V conditions. Figure 9 The waveform diagram shows the rapid drop in external signal voltage under 3.3V / 5V conditions. Figure 10 The waveforms of each node as a function of the enable signal en are shown. Detailed Implementation

[0023] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0024] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention.

[0025] The general idea of ​​this invention is: by adaptively adjusting the substrate potential and gate voltage of the PMOS and NMOS switches in the first analog switch, under the condition that the power supply is normal and the switch is off, it can effectively isolate the high voltage and noise of the external analog input / output terminal, and protect the device from damage by the external high voltage.

[0026] It should be understood that the embodiments of the present invention and the specific features therein are detailed descriptions of the technical solutions of the present invention, rather than limitations thereof; where there is no conflict, the embodiments of the present invention and the technical features therein can be combined with each other.

[0027] In the attached diagram, the substrates of all PMOS transistors not labeled are connected to the chip power supply VDD, and the substrates of all NMOS transistors not labeled are connected to the ground terminal GND.

[0028] The high-voltage isolation analog switch circuit of this embodiment can be applied to integrated circuit chips such as microcontrollers (MCUs) as an isolation interface between external analog input / output terminals and internal analog circuits. The internal analog circuits are, for example, analog-to-digital converters, operational amplifiers, or comparators, with their input / output terminals corresponding to internal analog nodes. This embodiment is particularly suitable for communication scenarios where the MCU power supply voltage is lower than the external signal voltage in the first voltage domain. For example, a 1.2V powered MCU needs to support a 1.8V communication protocol, a 1.8V powered MCU needs to support a 3.3V communication protocol, and a 3.3V powered MCU supports a 5V communication protocol. In this embodiment, the typical operating voltage range of the analog switch in the on state is generally from 0 to the chip power supply VDD voltage. The device's safe voltage is generally 1.1 times the typical operating voltage (e.g., the safe voltage of a 3.3V device is 3.63V). The circuit structure consists of two voltage-rated stages (e.g., two-stage input switches, MN2 protecting MN3, etc.), so the high voltage cannot exceed 2.2 times the typical operating voltage. When the switch is in the off state, the signal on the external analog input / output terminal can be a digital signal and processed by other digital interface circuits. At this time, the voltage of the external analog input / output terminal may be higher than the voltage of the chip power supply VDD.

[0029] Figure 2 The circuit diagram is provided for a high-voltage isolation analog switch circuit according to an embodiment of the present invention. Figure 2As shown, the high-voltage isolated analog switch circuit of this embodiment is connected between the external analog input / output terminal PAD and the internal analog node AY. It includes a first analog switch, a second analog switch, a pull-up PMOS switch MPPU1, a bias circuit BIAS, an N-switch driver circuit NGS, and a P-switch driver circuit PGS. The first PMOS switch MPS1 and the first NMOS switch MNS1 are connected in parallel to form the first analog switch, which together constitute a CMOS transmission gate. The source terminal of the first PMOS switch MPS1 is connected to the external analog input / output terminal PAD, the drain terminal is connected to the intermediate node t1, the gate terminal is connected to the P-switch drive voltage pgenb output by the P-switch driver circuit PGS, and the substrate is connected to the substrate bias voltage vsub output by the bias circuit BIAS. The source terminal of the first NMOS switch MNS1 is connected to the external analog input / output terminal PAD, the drain terminal is connected to the intermediate node t1, the gate terminal is connected to the N-switch drive voltage ngen output by the N-switch driver circuit NGS, and the substrate is connected to the ground terminal GND. The second PMOS switch MPS2 and the second NMOS switch MNS2 are connected in parallel to form the second analog switch, which together constitute a CMOS transmission gate. The source of the second PMOS switch MPS2 is connected to the intermediate node t1, the drain is connected to the internal analog node AY, the gate is connected to the inverse enable signal enb, and the substrate is connected to the chip power supply VDD. The source of the second NMOS switch MNS2 is connected to the intermediate node t1, the drain is connected to the internal analog node AY, the gate is connected to the enable signal en, and the substrate is connected to ground GND. The source and substrate of the pull-up PMOS switch MPPU1 are connected to the chip power supply VDD, the drain is connected to the intermediate node t1, and the gate is connected to the enable signal en.

[0030] like Figure 2 As shown, the bias circuit BIAS takes the enable signal en, the inverse enable signal enb, and the external analog input / output terminal PAD as inputs, and outputs the substrate bias voltage vsub and the P-gate bias voltage pgt. The P-switch driver circuit PGS has four inputs: the inverse enable signal enb, the external analog input / output terminal PAD, the substrate bias voltage vsub, and the P-gate bias voltage pgt, and outputs the P-switch drive voltage pgenb to the gate terminal of the first PMOS switch MPS1. The N-switch driver circuit NGS has two inputs: the inverse enable signal enb and the external analog input / output terminal PAD, and outputs the N-switch drive voltage ngen to the gate terminal of the first NMOS switch MNS1. The inverse enable signal enb is the inverse of the enable signal en.

[0031] and Figure 1The difference from the prior art shown is that: in this embodiment, the pull-down NMOS switch MNPD1 with the drain connected to the intermediate node and the source connected to ground is eliminated, and instead, a pull-up PMOS switch MPPU1 with the source and substrate connected to the chip power supply VDD, the drain connected to the intermediate node t1, and the gate connected to the enable signal en is used; at the same time, the gate voltage of the first analog switch is no longer directly driven by the enable signal en / inverse enable signal enb, but is adaptively generated by the bias circuit BIAS, the N switch drive circuit NGS, and the P switch drive circuit PGS according to the voltage of the external analog input / output terminal PAD, resulting in the substrate bias voltage vsub, the P gate bias voltage pgt, the N switch drive voltage ngen, and the P switch drive voltage pgenb; and the substrate of the first PMOS switch MPS1 is no longer fixedly connected to the chip power supply VDD, but is connected to the substrate bias voltage vsub that can follow the high voltage of the external analog input / output terminal PAD.

[0032] Figure 3 This is a circuit diagram of the bias circuit BIAS in an embodiment of the present invention. Figure 3As shown, the bias circuit BIAS includes a first PMOS transistor MP1, a second PMOS transistor MP2, a third PMOS transistor MP3, a first NMOS transistor MN1, a second NMOS transistor MN2, and a third NMOS transistor MN3. Specifically: the drain of the first PMOS transistor MP1 is connected to the chip power supply VDD, its source and substrate are connected to the substrate bias voltage vsub output, and its gate is connected to the P-gate bias voltage pgt output; the source and substrate of the second PMOS transistor MP2 are connected to the substrate bias voltage vsub output, its drain is connected to the external analog input / output terminal PAD, and its gate is connected to the chip power supply VDD; the source of the third PMOS transistor MP3 is connected to the P-gate bias voltage pgt output, its drain is connected to the external analog input / output terminal PAD, its gate is connected to the chip power supply VDD, and its substrate is connected to the substrate bias voltage vsub output; the source of the first NMOS transistor MN1 is connected to... Connect the external analog input / output terminal PAD, with the drain connected to the P-gate bias voltage pgt output terminal, the gate connected to the inverse enable signal enb, and the substrate connected to ground GND; the second NMOS transistor MN2 and the third NMOS transistor MN3 are connected in series between the P-gate bias voltage pgt output terminal and the ground GND, forming a pull-down branch: the drain of the second NMOS transistor MN2 is connected to the P-gate bias voltage pgt output terminal, the gate is connected to the chip power supply VDD, the source is connected to the drain of the third NMOS transistor MN3, and the substrate is connected to ground GND; the source and substrate of the third NMOS transistor MN3 are connected to ground GND, and the gate is connected to the enable signal en. In the above structure, the first PMOS transistor MP1 and the second PMOS transistor MP2 constitute the selection path for the substrate bias voltage vsub: when the P gate bias voltage pgt is at a low potential (low voltage in the on-state or off-state), the first PMOS transistor MP1 is turned on, pulling the substrate bias voltage vsub up to the chip power supply VDD; when the external analog input / output terminal PAD voltage is higher than the chip power supply VDD voltage and the turn-on condition of the second PMOS transistor MP2 is met, the second PMOS transistor MP2 is turned on, making the substrate bias voltage vsub follow the external analog input / output terminal PAD voltage. The first NMOS transistor MN1 and the third PMOS transistor MP3 form the selection path for the P-gate bias voltage pgt: When the enable signal enb is high and the external analog input / output terminal PAD voltage is not higher than VDD-VthN, the first NMOS transistor MN1 is turned on, and the P-gate bias voltage pgt follows the external analog input / output terminal PAD voltage, where VthN is the turn-on threshold voltage of the NMOS transistor; when the external analog input / output terminal PAD voltage is higher than the chip power supply voltage VDD and the turn-on condition of the third PMOS transistor MP3 is met, the third PMOS transistor MP3 is turned on, causing the P-gate bias voltage pgt to follow the external analog input / output terminal PAD voltage. The series pull-down branch of the second NMOS transistor MN2 and the third NMOS transistor MN3 only pulls the P-gate bias voltage pgt to ground in the on state (when the enable signal en is high).

[0033] It should be noted that when the P-gate bias voltage pgt is higher than the chip power supply voltage VDD (in the off state and the external analog input / output terminal PAD is high voltage), the gate voltage of the second NMOS transistor MN2 is limited to the chip power supply voltage VDD. At this time, the source potential of the second NMOS transistor MN2 is clamped to a potential no higher than VDD-VthN, that is, the drain potential of the third NMOS transistor MN3 does not exceed VDD-VthN. Thus, the second NMOS transistor MN2 bears the high voltage of the P-gate bias voltage pgt, reducing the gate-drain voltage difference and other terminal voltages borne by the third NMOS transistor MN3, thus providing withstand voltage protection for the third NMOS transistor MN3. It should be pointed out that in the off state, the enable signal en is low, and the third NMOS transistor MN3 is in the off state. The above clamping relationship further ensures that the drain of the third NMOS transistor MN3 does not bear high voltage. The MN2 / MN3 cascade structure is a preferred implementation in this embodiment. In other embodiments, if the NMOS device voltage tolerance provided by the process allows, the cascade relationship between the two can also be simplified. However, the cascade structure of this embodiment can further reduce the voltage stress on the third NMOS transistor MN3.

[0034] Figure 4 This is a circuit diagram of the N-switch drive circuit NGS in an embodiment of the present invention. Figure 4 As shown, the N-switch driver circuit NGS includes a fourth PMOS transistor MP4 and a fourth NMOS transistor MN4. Specifically: the source and substrate of the fourth PMOS transistor MP4 are connected to the chip power supply VDD, the drain is connected to the output of the N-switch drive voltage ngen, and the gate is connected to the inverse enable signal enb; the source of the fourth NMOS transistor MN4 is connected to the external analog input / output terminal PAD, the drain is connected to the output of the N-switch drive voltage ngen, the gate is connected to the inverse enable signal enb, and the substrate is connected to the ground terminal GND. The fourth NMOS transistor MN4 is the clamping NMOS transistor with its source end connected to the external analog input / output terminal PAD as described in this invention: when the enable signal enb is high and the voltage of the external analog input / output terminal PAD increases, the fourth NMOS transistor MN4 pulls up the N-switch drive voltage ngen in a source-follower manner; when the voltage of the external analog input / output terminal PAD rises above VDD-VthN, the fourth NMOS transistor MN4 turns off, thereby clamping the N-switch drive voltage ngen to approximately VDD-VthN, so that the gate voltage of the first NMOS switch MNS1 no longer continues to rise with the high voltage of the external analog input / output terminal PAD.

[0035] Figure 5 This is a circuit diagram of the P-switch driving circuit PGS in an embodiment of the present invention. Figure 5As shown, the P-switch driver circuit PGS includes a fifth PMOS transistor MP5, a sixth PMOS transistor MP6, and a fifth NMOS transistor MN5. Specifically: the source of the fifth PMOS transistor MP5 is connected to the output of the P-switch drive voltage pgenb, the drain is connected to the inverse enable signal enb, the gate is connected to the P-gate bias voltage pgt, and the substrate is connected to the substrate bias voltage vsub; the source of the sixth PMOS transistor MP6 is connected to the external analog input / output terminal PAD, the drain is connected to the output of the P-switch drive voltage pgenb, the gate is connected to the chip power supply VDD, and the substrate is connected to the substrate bias voltage vsub; the source of the fifth NMOS transistor MN5 is connected to the output of the P-switch drive voltage pgenb, the drain is connected to the inverse enable signal enb, the gate is connected to the chip power supply VDD, and the substrate is connected to the ground terminal GND. The fifth PMOS transistor, MP5, has a gate voltage that follows the high voltage of the external analog input / output terminal PAD, namely the P-gate bias voltage pgt. This ensures that MP5 can be reliably turned off under high voltage conditions in the off state, preventing a leakage path between the reverse enable signal enb and the P-switch drive voltage pgenb. The sixth PMOS transistor, MP6, turns on when the voltage of the external analog input / output terminal PAD is higher than the chip power supply VDD and its conduction condition is met, causing the P-switch drive voltage pgenb to follow the voltage of the external analog input / output terminal PAD. The substrates of both the fifth PMOS transistor MP5 and the sixth PMOS transistor MP6 are connected to a substrate bias voltage vsub, ensuring that their substrate potential is not lower than the source / drain potential. It can be seen that the P-gate bias voltage pgt controls the gate of the first PMOS transistor MP1 in the bias circuit BIAS, turning off the first PMOS transistor MP1 when the high voltage is in the off state, thereby switching the substrate bias voltage vsub path from the first PMOS transistor MP1 to the second PMOS transistor MP2. On the other hand, it controls the gate of the fifth PMOS transistor MP5 in the P-switch drive circuit PGS, turning off the fifth PMOS transistor MP5 when the high voltage is in the off state, thereby switching the P-switch drive voltage pgenb path from the fifth PMOS transistor MP5 to the sixth PMOS transistor MP6. The synergistic effect of the P-gate bias voltage pgt, the substrate bias voltage vsub, and the P-switch drive voltage pgenb together ensures reliable isolation under the high voltage condition in the off state.

[0036] The following is combined with Figure 2 , Figure 3 , Figure 4 and Figure 5 The working process of the high-voltage isolation analog switch circuit in this embodiment is described in terms of its working state.

[0037] 1. On state (en signal is high level, inverse enable signal enb is low level) When the enable signal en is high (power supply voltage) and the inverse enable signal enb is low (ground voltage): refer to Figure 3The second NMOS transistor MN2 and the third NMOS transistor MN3 are in the ON state, pulling the P-gate bias voltage pgt low to ground. After the P-gate bias voltage pgt is pulled low, the first PMOS transistor MP1 is turned on, pulling the substrate bias voltage vsub high to the power supply voltage. The first NMOS transistor MN1, the second PMOS transistor MP2, and the third PMOS transistor MP3 are all turned off. The output of the bias circuit BIAS is the P-gate bias voltage pgt at ground and the substrate bias voltage vsub at the power supply voltage. (Reference) Figure 4 When the reverse enable signal enb is low, the fourth PMOS transistor MP4 is turned on, the fourth NMOS transistor MN4 is turned off, and the output N-switch drive voltage ngen is the power supply voltage. (Reference) Figure 5 When the reverse enable signal enb is low, the fifth PMOS transistor MP5 and the sixth PMOS transistor MP6 are turned off, and the fifth NMOS transistor MN5 is turned on, resulting in a low output P-switch drive voltage pgenb. (Back to...) Figure 2 The P-switch drive voltage pgenb is a low voltage, and the N-switch drive voltage ngen is the power supply voltage. The transmission gate of the first analog switch is fully turned on, and conduction is achieved through the first PMOS switch MPS1 branch and / or the first NMOS switch MNS1 branch under different signal levels. The transmission gate of the second analog switch is also fully turned on, and conduction is achieved through the second PMOS switch MPS2 branch and / or the second NMOS switch MNS2 branch under different signal levels. The pull-up PMOS switch MPPU1 is turned off. The external analog input / output terminal PAD is connected to the internal analog node AY through the turned-on first and second analog switches. When the analog switches are in the turned-on state, they transmit analog input / output signals.

[0038] like Figure 6 As shown, taking a chip power supply VDD of 3.3V and an external signal voltage of 5V as an example, when the switch is on, the voltages of the internal analog node AY and the intermediate node t1 both follow the changes of the external analog input / output terminal PAD.

[0039] 2. In the off state and the external analog input / output terminal PAD is at a low voltage (en signal is low level, and enb signal is high level). When the enable signal en is low (ground voltage) and the inverse enable signal enb is high (power supply voltage), the analog switch is in the off state. At this time, the signal on the external analog input / output terminal PAD is a digital signal, which is processed by other digital interface circuits. This high-voltage isolation analog switch circuit isolates the voltage of the external analog input / output terminal PAD, preventing it from entering the internal analog node AY.

[0040] When the external analog input / output terminal PAD input is low voltage: Reference Figure 3The third NMOS transistor MN3 is turned off, no longer pulling down the P-gate bias voltage pgt; the first NMOS transistor MN1 is turned on, the third PMOS transistor MP3 is turned off, and the P-gate bias voltage pgt equals the external analog input / output terminal PAD voltage, i.e., low voltage; the first PMOS transistor MP1 is turned on, the second PMOS transistor MP2 is turned off, and the substrate bias voltage vsub is the power supply voltage. (Reference) Figure 4 The fourth PMOS transistor MP4 is turned off, and the fourth NMOS transistor MN4 is turned on. The N-switch drive voltage ngen is equal to the external analog input / output terminal PAD voltage, i.e., the low voltage. (Reference) Figure 5 The fifth NMOS transistor MN5 is turned off, the sixth PMOS transistor MP6 is turned off, and the fifth PMOS transistor MP5 is turned on. The P-switch drive voltage pgenb is equal to the inverse enable signal enb voltage, which is the power supply voltage. (Back to...) Figure 2 When the P-switch drive voltage pgenb is high, the first PMOS switch MPS1 is turned off; when the N-switch drive voltage ngen is low, the first NMOS switch MNS1 is turned off, and the first analog switch is turned off. When the reverse enable signal enb is high, the second PMOS switch MPS2 is turned off; when the enable signal en is low, the second NMOS switch MNS2 is turned off, and the second analog switch is turned off. The pull-up PMOS switch MPPU1 is turned on, pulling the intermediate node t1 up to the power supply voltage. The low voltage at the external analog input / output terminal PAD is intercepted by the turned-off first analog switch. Even if there is a momentary low-pulse interference below ground, it will be absorbed by the turned-on pull-up PMOS switch MPPU1 into the power network without interfering with the internal analog node AY.

[0041] 3. In the off state, the voltage at the external analog input / output terminal PAD is approximately equal to the power supply voltage. When the voltage at the external analog input / output terminal PAD rises to approximately equal to the supply voltage VDD: Reference Figure 3 The first NMOS transistor MN1 tends to turn off when the external analog input / output terminal PAD voltage rises to a level lower than the supply voltage by one NMOS turn-on threshold voltage. The first PMOS transistor MP1 turns on, and the second PMOS transistor MP2 turns off. The substrate bias voltage vsub remains equal to the supply voltage. (Reference) Figure 4 Similarly, the fourth NMOS transistor MN4 tends to turn off when the voltage at the external analog input / output terminal PAD rises to a level lower than the supply voltage by one NMOS turn-on threshold voltage, and the N-switch drive voltage ngen is maintained at this voltage. (Reference) Figure 5 The operating state of the P-switch drive circuit PGS remains unchanged, and the P-switch drive voltage pgenb remains high (power supply voltage). Returning to... Figure 2With each switch state unchanged, the voltage of the external analog input / output terminal PAD is intercepted by the first analog switch that is turned off. Even if there is a momentary high pulse interference higher than the power supply, it will be absorbed by the conducting pull-up PMOS switch MPPU1 and sent to the power network.

[0042] 4. In the off state and the voltage of the external analog input / output PAD is higher than the power supply voltage. refer to Figure 3 When the external analog input / output terminal PAD voltage exceeds the chip power supply VDD by at least one PMOS turn-on threshold voltage, the third PMOS transistor MP3 turns on. The P-gate bias voltage pgt equals the external analog input / output terminal PAD voltage and is higher than the chip power supply VDD. The first PMOS transistor MP1 turns off, and the second PMOS transistor MP2 turns on. The substrate bias voltage vsub equals the external analog input / output terminal PAD voltage and is higher than the power supply voltage. That is, both the substrate bias voltage vsub and the P-gate bias voltage pgt follow the external analog input / output terminal PAD voltage. (Reference) Figure 4 The fourth NMOS transistor, MN4, has been turned off when the external analog input / output terminal PAD voltage rises to VDD-VthN. The N-switch drive voltage, ngen, remains at a level approximately one NMOS transistor turn-on threshold voltage lower than the supply voltage, i.e., approximately VDD-VthN, and no longer rises with the external analog input / output terminal PAD voltage. (Reference) Figure 5 When the P-gate bias voltage pgt is higher than the power supply voltage, the fifth PMOS transistor MP5 is turned off. When the external analog input / output terminal PAD voltage is higher than the power supply voltage by at least one PMOS transistor's turn-on threshold voltage, the sixth PMOS transistor MP6 is turned on, and the P-switch drive voltage pgenb rises to the external analog input / output terminal PAD voltage and is higher than the power supply voltage. That is, the P-switch drive voltage pgenb follows the external analog input / output terminal PAD voltage. (Back to...) Figure 2At this point, the potential relationships of the key nodes in the circuit are as follows: the substrate bias voltage vsub is equal to the external analog input / output terminal PAD voltage, the P switch drive voltage pgenb is equal to the external analog input / output terminal PAD voltage, the N switch drive voltage ngen is approximately VDD-VthN, the pull-up PMOS switch MPPU1 is turned on, and the intermediate node t1 is pulled up to the power supply voltage VDD. Since both the P switch drive voltage pgenb and the substrate bias voltage vsub are equal to the external analog input / output terminal PAD voltage, the gate-source voltage difference of the first PMOS switch MPS1 is zero, and the substrate potential is not lower than the source / drain potential, so the first PMOS switch MPS1 remains reliably off; since the N switch drive voltage ngen is lower than the external analog input / output terminal PAD voltage, the first NMOS switch MNS1 also remains off. The high voltage of the external analog input / output terminal PAD continues to be isolated by the off-state first analog switch, and the pull-up PMOS switch MPPU1 is turned on, which can absorb instantaneous noise interference.

[0043] like Figure 7 As shown, taking a chip power supply VDD of 3.3V and an external signal voltage of 5V as an example, when the switch is off, during the process of the external analog input / output terminal PAD voltage slowly changing from 0 to 5V: the substrate bias voltage vsub and the P switch drive voltage pgenb are the higher values ​​among the external analog input / output terminal PAD and the chip power supply VDD; the N switch drive voltage ngen follows the change of the external analog input / output terminal PAD, reaching its highest value of the chip power supply VDD; the P gate bias voltage pgt follows the change of the external analog input / output terminal PAD, and is cut off at VDD-Vth before the external analog input / output terminal PAD exceeds the chip power supply VDD; after the external analog input / output terminal PAD exceeds the chip power supply VDD, it continues to follow the external analog input / output terminal PAD. Throughout the process, the intermediate node t1 is pulled up, the internal analog node AY is floating and unaffected, and there is no leakage current in the circuit.

[0044] like Figure 8 , Figure 9 This is a waveform diagram showing the rapid rise and fall of the PAD voltage at the external analog input / output terminals, along with the substrate bias voltage vsub, P-gate bias voltage pgt, P-switch drive voltage pgenb, and... Figure 7 The tracking state of the external analog input / output terminal PAD is consistent with the slow change, and the maximum interference to the internal analog node AY signal under high impedance is less than 1mV. Figure 10 The waveforms of each node as a function of the enable signal en are shown. The coupling noise of nodes such as the intermediate node t1 and the substrate bias voltage vsub is less than 1mV.

[0045] After reaching a steady state within the specified external analog input / output terminal PAD voltage range, as specified above. Figure 2 , Figure 3 , Figure 4 , Figure 5 The gate-source voltage difference and gate-drain voltage difference of all MOS transistors therein are within the withstand voltage range, and no MOS transistor has the risk of gate oxide overvoltage damage; meanwhile, the substrate voltage of each PMOS transistor is not lower than its source / drain voltage. It should be noted that the above terminal voltage conclusion is valid within the specified PAD voltage range; the specified PAD voltage range not only satisfies VDD<VPAD≤2.2VDD, but also has its upper limit determined by factors such as the junction breakdown voltage, drain-source terminal voltage and reliability margin of the specific process, which can be determined by those skilled in the art in combination with the specific process. For example, when VDD=3.3V and VthN,eff is about 0.7V, PAD=5V falls within the specified PAD voltage range, at this time the magnitude of the gate-source voltage difference of MNS1 is about 5V-(3.3V-0.7V)=2.4V, which does not exceed 3.3V.

[0046] When the enable signal en is at a low level, the first analog switch and the second analog switch are turned off, and the pull-up PMOS switch MPPU1 is turned on to pull the intermediate node t1 up to the power supply voltage VDD, so that t1 has a determined potential instead of being floating. When transient noise (such as a short pulse momentarily exceeding the power supply, a short pulse below ground, or high-frequency coupling noise) appears at the external analog input / output terminal PAD, the transient noise is first attenuated by the turned-off first analog switch, and reaches the intermediate node t1 after its amplitude is reduced; the noise reaching t1 is discharged to the power supply network of the chip power supply VDD through the turned-on pull-up PMOS switch MPPU1, thereby suppressing the noise from entering the internal analog node AY through the turned-off second analog switch, and realizing isolation between the internal and external circuits. Compared with Figure 1 the scheme in the prior art shown in which a pull-down NMOS switch MNPD1 is used to absorb noise to the ground, the pull-up PMOS switch MPPU1 of this embodiment has its source terminal and substrate connected to the chip power supply VDD, its drain terminal connected to the intermediate node t1, and its gate terminal connected to the enable signal en, which also remains in a conducting state in a high withstand voltage state and provides a determined potential and a noise discharge path for the intermediate node t1; at the same time, the problem that the drain terminal of the pull-down NMOS transistor may be subjected to high voltage stress when high voltage is coupled to the intermediate node t1 is avoided.

[0047] In this embodiment of the invention, each MOS transistor in the high-voltage isolated analog switch circuit (including MPS1, MNS1, MPS2, MNS2, MPPU1, and MP1 to MP6 and MN1 to MN5 in BIAS, NGS, and PGS) is a low-voltage MOS device with a gate oxide rated voltage not exceeding the chip power supply voltage VDD. Because the circuit uses a following mechanism of substrate bias voltage vsub, P-gate bias voltage pgt, P-switch drive voltage pgenb, and a clamping mechanism of N-switch drive voltage ngen, the gate-source voltage difference and gate-drain voltage difference of each MOS transistor do not exceed the withstand voltage value within the specified external analog input / output terminal PAD voltage range. Therefore, low-voltage devices using standard low-voltage CMOS technology can achieve a high voltage tolerance higher than the power supply voltage within the specified external signal voltage range, eliminating the need for high-voltage devices. This approach offers advantages such as small area, low cost, and ease of integration with standard processes. It should be noted that the drain-source voltage and junction voltage tolerance of low-voltage MOS devices depend on the specific process. The upper limit of the specified external analog input / output terminal PAD voltage range should simultaneously meet the junction breakdown voltage, drain-source voltage and reliability margin requirements allowed by the specific process. In the embodiments of the present invention, when the chip power supply is normal and the analog switch is in the off state, the following objectives are achieved simultaneously by using low-voltage MOS devices: (1) Real isolation is achieved for high voltage signals on the external analog input / output terminal PAD that are higher than the power supply voltage, preventing them from entering the internal analog node AY; (2) Terminal voltage protection is achieved for each MOS device in the circuit, ensuring that the gate-source voltage difference, gate-drain voltage difference and other terminal voltages do not exceed their rated safe voltage, avoiding overvoltage damage; (3) The substrate of the PMOS device is correctly biased to prevent latch-up effect caused by the PMOS substrate potential being lower than its source / drain potential; (4) Transient noise on the intermediate node t1 has a definite discharge path, avoiding noise interference to the internal analog node AY.

[0048] This invention also provides an integrated circuit chip, including the high-voltage isolation analog switch circuit of any of the above embodiments. Further, the integrated circuit chip is a microcontroller (MCU), and the high-voltage isolation analog switch circuit serves as the interface between the MCU's external analog input / output terminal PAD and its internal analog circuitry. The internal analog circuitry includes an analog-to-digital converter, an operational amplifier, or a comparator, and its input / output terminals correspond to the internal analog node AY. When the MCU needs to communicate with a voltage domain higher than its own power supply voltage (e.g., a 3.3V powered MCU supports a 5V communication protocol), in the analog switch-off state, high-voltage digital signals at the external analog input / output terminal PAD, which are within a specified voltage range, are isolated by this high-voltage isolation analog switch circuit, preventing them from entering the internal analog circuitry and thus avoiding damage to the switch itself.

[0049] Numerous specific details are set forth in the specification provided herein. However, it will be understood that embodiments of the invention may be practiced without these specific details. In some instances, well-known methods, structures, and techniques have not been shown in detail so as not to obscure the understanding of this specification.

[0050] Similarly, it should be understood that, in order to streamline this disclosure and aid in understanding one or more of the various inventive aspects, in the above description of exemplary embodiments of the invention, various features of the invention are sometimes grouped together in a single embodiment, figure, or description thereof. However, this method of disclosure should not be interpreted as reflecting an intention that the claimed invention requires more features than are expressly recited in each claim. Rather, as reflected in the claims, inventive aspects lie in fewer than all features of a single foregoing disclosed embodiment. Therefore, the claims following the detailed description are hereby expressly incorporated into that detailed description, wherein each claim itself is a separate embodiment of the invention.

[0051] Furthermore, those skilled in the art will understand that although some embodiments herein include certain features included in other embodiments but not others, combinations of features from different embodiments are intended to be within the scope of the invention and form different embodiments. For example, any of the embodiments claimed in the claims can be used in any combination.

[0052] It should be noted that the above embodiments are illustrative of the invention and not restrictive, and that those skilled in the art can devise alternative embodiments without departing from the scope of the appended claims. In the claims, any reference signs placed between parentheses should not be construed as limiting the claims. The word "comprising" does not exclude the presence of elements or steps not listed in the claims. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. The use of the words first, second, and third, etc., does not indicate any order and these words can be interpreted as names.

Claims

1. A high-voltage isolation analog switch circuit, connected between the external analog input / output terminal PAD and the internal analog node AY of the chip, characterized in that, It includes a first analog switch, a second analog switch, a pull-up PMOS switch MPPU1, a bias circuit BIAS, an N-switch driver circuit NGS, and a P-switch driver circuit PGS; wherein: The first analog switch includes a first PMOS switch MPS1 and a first NMOS switch MNS1 connected in parallel; the source terminal of the first PMOS switch MPS1 is connected to the external analog input / output terminal PAD, the drain terminal is connected to the intermediate node t1, the gate terminal is connected to the P-switch driving voltage pgenb output by the P-switch driving circuit PGS, and the substrate is connected to the substrate bias voltage vsub output by the bias circuit BIAS; the source terminal of the first NMOS switch MNS1 is connected to the external analog input / output terminal PAD, the drain terminal is connected to the intermediate node t1, the gate terminal is connected to the N-switch driving voltage ngen output by the N-switch driving circuit NGS, and the substrate is connected to the ground terminal GND. The second analog switch includes a second PMOS switch MPS2 and a second NMOS switch MNS2 connected in parallel; the second analog switch is connected between the intermediate node t1 and the internal analog node AY; the gate terminal of the second PMOS switch MPS2 is connected to the inverse enable signal enb, and the gate terminal of the second NMOS switch MNS2 is connected to the enable signal en, wherein the inverse enable signal enb is the inverse signal of the enable signal en; The source and substrate of the pull-up PMOS switch MPPU1 are connected to the chip power supply VDD, the drain is connected to the intermediate node t1, and the gate is connected to the enable signal en. The inputs of the bias circuit BIAS include an enable signal en, an inverse enable signal enb, and an external analog input / output terminal PAD. It outputs the substrate bias voltage vsub and the P-gate bias voltage pgt, and is configured to: when the enable signal en is low, the high-voltage isolation analog switch circuit is off, and the voltage of the external analog input / output terminal PAD is higher than the voltage of the chip power supply VDD, make the substrate bias voltage vsub follow the voltage of the external analog input / output terminal PAD. The inputs of the P-switch driving circuit PGS include: an inverse enable signal enb, an external analog input / output terminal PAD, a substrate bias voltage vsub, and a P-gate bias voltage pgt. It is configured such that when the enable signal enb is low, the high-voltage isolation analog switch circuit is in the off state, and the voltage of the external analog input / output terminal PAD is higher than the voltage of the chip power supply VDD, the output P-switch driving voltage pgenb follows the voltage of the external analog input / output terminal PAD to keep the first PMOS switch MPS1 off. The inputs of the N-switch driver circuit NGS include: an inverse enable signal enb and an external analog input / output terminal PAD; the N-switch driver circuit NGS includes a clamped NMOS transistor whose source terminal is connected to the external analog input / output terminal PAD; the N-switch driver circuit NGS is configured to clamp the N-switch drive voltage ngen at a potential that is one conduction threshold voltage of the clamped NMOS transistor lower than the chip power supply VDD when the enable signal enb is low, the high-voltage isolation analog switch circuit is in the off state, and the voltage of the external analog input / output terminal PAD is higher than the chip power supply VDD.

2. The high-voltage isolation analog switch circuit according to claim 1, characterized in that, The bias circuit BIAS includes a first PMOS transistor MP1, a second PMOS transistor MP2, a third PMOS transistor MP3, a first NMOS transistor MN1, a second NMOS transistor MN2, and a third NMOS transistor MN3; wherein: The drain of the first PMOS transistor MP1 is connected to the chip power supply VDD, the source and substrate are connected to the substrate bias voltage vsub output, and the gate is connected to the P gate bias voltage pgt output. The source and substrate of the second PMOS transistor MP2 are connected to the substrate bias voltage vsub output terminal, the drain terminal is connected to the external analog input / output terminal PAD, and the gate terminal is connected to the chip power supply VDD. The source terminal of the third PMOS transistor MP3 is connected to the output terminal of the P gate bias voltage pgt, the drain terminal is connected to the external analog input / output terminal PAD, the gate terminal is connected to the chip power supply VDD, and the substrate is connected to the output terminal of the substrate bias voltage vsub. The source terminal of the first NMOS transistor MN1 is connected to the external analog input / output terminal PAD, the drain terminal is connected to the output terminal of the P gate bias voltage pgt, the gate terminal is connected to the reverse enable signal enb, and the substrate is connected to the ground terminal GND. The second NMOS transistor MN2 and the third NMOS transistor MN3 are connected in series between the output terminal of the P-gate bias voltage pgt and the ground terminal GND.

3. The high-voltage isolation analog switch circuit according to claim 2, characterized in that, The drain of the second NMOS transistor MN2 is connected to the output of the P-gate bias voltage pgt, the gate is connected to the chip power supply VDD, the source is connected to the drain of the third NMOS transistor MN3, and the substrate is connected to the ground terminal GND; the source and substrate of the third NMOS transistor MN3 are connected to the ground terminal GND, and the gate is connected to the enable signal en.

4. The high-voltage isolation analog switch circuit according to claim 1, characterized in that, The P-switch driving circuit PGS includes a fifth PMOS transistor MP5, a sixth PMOS transistor MP6, and a fifth NMOS transistor MN5; wherein: The source terminal of the fifth PMOS transistor MP5 is connected to the output terminal of the P switch drive voltage pgenb, the drain terminal is connected to the reverse enable signal enb, the gate terminal is connected to the P gate bias voltage pgt, and the substrate is connected to the substrate bias voltage vsub. The source terminal of the sixth PMOS transistor MP6 is connected to the external analog input / output terminal PAD, the drain terminal is connected to the output terminal of the P switch drive voltage pgenb, the gate terminal is connected to the chip power supply VDD, and the substrate is connected to the substrate bias voltage vsub. The source terminal of the fifth NMOS transistor MN5 is connected to the output terminal of the P-switch drive voltage pgenb, the drain terminal is connected to the reverse enable signal enb, the gate terminal is connected to the chip power supply VDD, and the substrate is connected to the ground terminal GND.

5. The high-voltage isolation analog switch circuit according to claim 1, characterized in that, The N-switch drive circuit NGS includes a fourth PMOS transistor MP4 and a fourth NMOS transistor MN4; wherein: The source and substrate of the fourth PMOS transistor MP4 are connected to the chip power supply VDD, the drain is connected to the output of the N-switch drive voltage ngen, and the gate is connected to the reverse enable signal enb. The fourth NMOS transistor MN4 is the clamped NMOS transistor, with its source terminal connected to the external analog input / output terminal PAD, its drain terminal connected to the output terminal of the N-switch drive voltage ngen, its gate terminal connected to the reverse enable signal enb, and its substrate connected to the ground terminal GND.

6. The high-voltage isolation analog switch circuit according to claim 1, characterized in that, Each MOS transistor in the high-voltage isolation analog switch circuit is a low-voltage MOS device with a gate oxide rated voltage not higher than the chip power supply VDD voltage.

7. An integrated circuit chip, characterized in that, Includes the high-voltage isolation analog switch circuit as described in any one of claims 1 to 6.

8. The integrated circuit chip according to claim 7, characterized in that, The integrated circuit chip is a microcontroller (MCU), and the high-voltage isolation analog switch circuit serves as the interface between the external analog input / output terminal PAD of the microcontroller (MCU) and its internal analog circuit. The internal analog circuit includes an analog-to-digital converter circuit, an operational amplifier, or a comparator.

Images