Power-on reset circuit, chip, electronic device and control method

Abstract

The application provides a power-on reset circuit, a chip, an electronic device and a control method, and belongs to the electronic field. A current source in the power-on reset circuit is used for outputting a constant total current. A proportional shunt control module in the power-on reset circuit is used for shunting the constant total current through a 1:N current mirror relationship, so that the charging current of the charging capacitor is 1 / (N+1) of the constant total current. An output module in the power-on reset circuit is used for outputting a reset signal of different levels according to the high and low of the voltage across the charging capacitor. Through the proportional shunt control module, the constant total current is shunted, the charging current of the charging capacitor can be reduced without increasing the charging capacitor, the charging time of the charging capacitor is increased, and the area and cost of the chip and the electronic device can be reduced.

Description

Technical Field

[0001] This application relates to the field of electronic technology, and in particular to a power-on reset circuit, a chip, an electronic device, and a control method. Background Technology

[0002] During chip power-up, the chip's supply voltage rises from zero to its upper limit and then stabilizes. The chip includes a power-on reset circuit and a load module. The power-on reset circuit includes a current source, a capacitor, and a Schmitt trigger. The current source outputs current to charge the capacitor, and the Schmitt trigger outputs a reset signal based on the capacitor's voltage. For example, if the supply voltage is not yet stable, the capacitor charging is not yet complete, and the capacitor voltage is less than the Schmitt trigger's toggling threshold. Therefore, the Schmitt trigger outputs a first-level reset signal, causing the load module to perform a reset operation to prevent logic errors and state instability caused by unstable supply voltage. When the supply voltage is stable, the capacitor charging is complete, and the capacitor voltage is greater than the Schmitt trigger's toggling threshold. Therefore, the Schmitt trigger outputs a second-level reset signal, causing the load module to cancel the reset operation and operate normally based on a stable supply voltage.

[0003] In related technologies, the charging time of the capacitor is extended by increasing its capacitance value, thereby ensuring that the capacitor is fully charged only after the power supply voltage has stabilized. This ensures that the logic level of the reset signal output by the Schmitt trigger is correct, so that the load module cancels the reset operation only after the power supply voltage has stabilized.

[0004] However, increasing the capacitance value of the capacitor will increase the chip area and cost. Summary of the Invention

[0005] This application provides a power-on reset circuit, a chip, an electronic device, and a control method, which can reduce the chip area and cost. The technical solution of this application is as follows.

[0006] In one aspect, a power-on reset circuit is provided, which includes a current source, a charging capacitor, a proportional shunt control module, and an output module.

[0007] The current source is used to receive the supply voltage and output a constant total current. The current output terminal of the current source, the first terminal of the charging capacitor, and the current control node of the proportional shunt control module are interconnected. The second terminal of the charging capacitor is interconnected with the current reference node of the proportional shunt control module.

[0008] The proportional shunt control module includes a first NMOS transistor and a second NMOS transistor with a width-to-length ratio of 1:N. The gates of the first NMOS transistor and the second NMOS transistor are interconnected, and their sources are grounded together. The drain of the first NMOS transistor serves as the current reference node, and the drain of the second NMOS transistor serves as the current control node.

[0009] The proportional current shunt control module is used to shunt the constant total current through a 1:N current mirror relationship, so that the charging current of the charging capacitor is 1 / (N+1) of the constant total current.

[0010] The input terminal of the output module is connected to the first terminal of the charging capacitor, and is used to output a reset signal of different levels according to the voltage across the two terminals of the charging capacitor. Specifically, when the voltage of the charging capacitor is lower than the flip threshold, a low-level active reset signal is output, and when the voltage of the charging capacitor is higher than the flip threshold, a high-level release reset signal is output.

[0011] In one implementation, the output module includes a Schmitt trigger, the toggling threshold of which is determined based on the stable upper limit of the supply voltage. This ensures that the voltage of the charging capacitor reaches the toggling threshold only after the supply voltage has stabilized, guaranteeing that the power-on reset circuit outputs a high-level release reset signal only after the supply voltage has stabilized.

[0012] In one implementation, the current source includes a reference current source and a PMOS current mirror. The PMOS current mirror includes a first PMOS transistor and a second PMOS transistor with gate interconnection. The first PMOS transistor is used to receive the reference current output from the reference current source. The second PMOS transistor is used to mirror the reference current to obtain a constant total current and output a constant total current.

[0013] In one implementation, the power-on reset circuit further includes a buffer, the input of which is connected to the output of the output module. The buffer buffers the reset signal and outputs the buffered reset signal to the load module. By buffering the reset signal, the buffer enhances the driving capability of the reset signal and isolates the load module from the power-on reset circuit, thereby improving its stability.

[0014] In one implementation, the buffer includes a first inverter and a second inverter. The input terminal of the first inverter is the input terminal of the buffer, and the output terminal of the first inverter is connected to the input terminal of the second inverter. The first inverter is used to buffer and invert the reset signal. The second inverter is used to buffer and invert the output signal of the first inverter to obtain a buffered reset signal.

[0015] In a second aspect, a display driver chip is provided, the chip including a power-on reset circuit as in any implementation of the first aspect. The display driver chip may be, for example, a power management integrated circuit (PMIC), a display driver integrated circuit (DDI), a large touch and display driver IC (LTDDI), a low dropout regulator (LDO), or a small-size display power management chip.

[0016] Thirdly, an electronic device is provided, which includes a display driver chip as described in any implementation of the second aspect.

[0017] Fourthly, a power-on reset control method is provided, applied to a power-on reset circuit as described in any implementation of the first aspect, the method comprising the following steps.

[0018] The power supply voltage is received by the current source in the power-on reset circuit, and a constant total current is output.

[0019] The proportional current shunt control module in the power-on reset circuit shunts the constant total current based on a 1:N current mirror relationship, so that the charging current of the charging capacitor is 1 / (N+1) of the constant total current.

[0020] The output module in the power-on reset circuit outputs reset signals of different levels according to the voltage across the charging capacitor. Specifically, when the voltage of the charging capacitor is lower than the flip threshold, a low-level active reset signal is output, and when the voltage of the charging capacitor is higher than the flip threshold, a high-level release reset signal is output.

[0021] In one implementation, the method further includes: adjusting the width-to-length ratio (1:N) of the first NMOS transistor and the second NMOS transistor in the proportional shunt control module to determine the equivalent amplification factor of the charging capacitor to adapt to different power-on reset delay requirements.

[0022] In one implementation, the current source includes a reference current source and a PMOS current mirror, the PMOS current mirror including a first PMOS transistor and a second PMOS transistor with gate interconnection; the method includes the following steps: receiving the supply voltage and outputting a constant total current through the current source in the power-on reset circuit.

[0023] The reference current is received from the reference current source through the first PMOS transistor.

[0024] The reference current is mirrored by the second PMOS transistor to obtain a constant total current, and then the constant total current is output.

[0025] The technical solution provided in this application has at least the following beneficial effects.

[0026] The proportional current shunt control module in the power-on reset circuit shunts the constant total current, which can reduce the charging current of the charging capacitor and increase the charging time of the charging capacitor without increasing the charging capacitor size. This ensures that the delay time of the power-on reset circuit meets the requirements, while also reducing the chip area and cost. Attached Figure Description

[0027] Figure 1 This is a schematic diagram of a power-on reset circuit provided in an embodiment of this application; Figure 2 A circuit diagram of a power-on reset circuit provided in an embodiment of this application; Figure 3 A signal timing diagram of a power-on reset circuit provided in an embodiment of this application; Figure 4 This is a flowchart of a power-on reset control method provided in an embodiment of this application. Detailed Implementation

[0028] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings. The terminology used in the embodiments section of this application is only for explaining specific embodiments and is not intended to limit this application.

[0029] When the chip is powered on, its supply voltage gradually rises from zero to an upper limit, and then remains stable after reaching the upper limit. The chip includes a power-on reset circuit and a load module. The power-on reset circuit includes a current source, a charging capacitor, and a Schmitt trigger. The current source outputs current to charge the charging capacitor, and the Schmitt trigger outputs a reset signal based on the voltage across the charging capacitor.

[0030] For example, when the power supply voltage is not yet stable, the charging capacitor has not yet finished charging, and the voltage of the charging capacitor is less than the toggling threshold of the Schmitt trigger. As a result, the Schmitt trigger outputs a first-level reset signal, causing the load module to perform a reset operation. In this way, logic errors and state instability of the load module can be avoided when the power supply voltage is unstable.

[0031] For example, after the supply voltage reaches its upper limit and remains there for a period of time, the charging capacitor completes its charging. The voltage across the charging capacitor then exceeds the Schmitt trigger's toggling threshold, causing the Schmitt trigger to output a second-level reset signal, thus canceling the reset operation of the load module. In this way, the load module can operate normally based on a stable supply voltage.

[0032] In related technologies, the charging capacitor needs to be set to a larger size to extend the charging time of the charging capacitor, thereby ensuring that the power supply voltage is stable before the Schmitt trigger outputs a second-level reset signal to improve the working stability of the load module.

[0033] For example, the voltage V when the charging capacitor is fully charged, the charging current I of the charging capacitor, the charging time t of the charging capacitor, and the charging capacitance C of the charging capacitor satisfy the following formula (1).

[0034]

[0035] Taking V as the upper limit of the power supply voltage of 1.8 volts, I as 1 microamp and t as 1 millisecond as an example, substituting the above data into formula (1) yields that C is approximately 555.5 picofarads, indicating a relatively large charging capacitor value.

[0036] However, larger charging capacitors increase the area and cost of the power-on reset circuit, which in turn increases the area and cost of the chip and electronic device.

[0037] This application provides a power-on reset circuit. See also... Figure 1 The power-on reset circuit 10 provided in this application embodiment includes a current source 11, a charging capacitor 12, a proportional current shunt control module 13, and an output module 14.

[0038] The current output terminal of the current source 11, the current control node of the proportional shunt control module 13, the first terminal of the charging capacitor 12, and the input terminal of the output module 14 are interconnected, and the second terminal of the charging capacitor 12 is connected to the current reference node of the proportional shunt control module 13.

[0039] Current source 11 is used to receive the supply voltage and output a constant total current. For example, based on the supply voltage, current source 11 obtains a constant total current and outputs the constant total current to the current control node of the proportional shunt control module 13.

[0040] The proportional current shunt control module 13 is used to shunt the constant total current through a 1:N current mirror relationship, so that the charging current of the charging capacitor 12 is 1 / (N+1) of the constant total current, where N is a positive integer.

[0041] In this way, the charging current of the charging capacitor 12 is less than the constant total current output by the current source 11. That is to say, the charging current of the charging capacitor 12 in this embodiment is lower than that in related technologies, and the charging time of the charging capacitor 12 can be extended without increasing the size of the charging capacitor 12.

[0042] In addition, the power-on reset circuit 10 in this embodiment does not need to reduce the constant total current output by the current source 11, thereby avoiding the situation where the small constant total current has low stability, poor accuracy, and low controllability, which leads to the power-on reset circuit 10 outputting an erroneous reset signal.

[0043] Output module 14 outputs reset signals of different levels based on the voltage across charging capacitor 12. These reset signals instruct the load module to perform a reset operation or cancel the reset operation. Specifically, when the voltage across charging capacitor 12 is below the toggling threshold, output module 14 outputs a low-level active reset signal, instructing the load module to perform a reset operation. Conversely, when the voltage across charging capacitor 12 is above the toggling threshold, output module 14 outputs a high-level release reset signal, instructing the load module to cancel the reset operation.

[0044] The circuit structure and corresponding function of the power-on reset circuit 10 are described below. (See reference...) Figure 2 The current source 11 includes a PMOS current mirror and a reference current source I0. The PMOS current mirror includes a first PMOS transistor M1 and a second PMOS transistor M2. The proportional shunt control module 13 includes a first N-type metal-oxide-semiconductor (MOS) transistor M3 and a second NMOS transistor M4. The output module 14 includes a Schmitt trigger U1.

[0045] The drain of the first NMOS transistor M3 is the current reference node of the proportional shunt control module 13, and the drain of the second NMOS transistor M4 is the current control node of the proportional shunt control module 13. The drain of the first PMOS transistor M1 is the reference current terminal of the PMOS current mirror. The drain of the second PMOS transistor M2 is the mirror current terminal of the PMOS current mirror, and also the output terminal of the current source 11.

[0046] The output terminal of the reference current source I0, the drain of the first PMOS transistor M1, the gate of the first PMOS transistor M1, and the gate of the second PMOS transistor M2 are interconnected. The source of the first PMOS transistor M1 is connected to the source of the second PMOS transistor M2. The drain of the second PMOS transistor M2, the first terminal of the charging capacitor 12, the input terminal of the Schmitt trigger U1, and the drain of the second NMOS transistor M4 are interconnected. The second terminal of the charging capacitor 12, the drain of the first NMOS transistor M3, the gate of the first NMOS transistor M3, and the gate of the second NMOS transistor M4 are interconnected. The sources of both the first NMOS transistor M3 and the second NMOS transistor M4 are grounded.

[0047] The reference current source I0 is used to output a reference current.

[0048] The first PMOS transistor M1 is used to receive the reference current output from the reference current source I0 and output the reference current to the gate of the second PMOS transistor M2.

[0049] The second PMOS transistor M2 is used to mirror the reference current to obtain a constant total current and output a constant total current.

[0050] For example, when the supply voltage is greater than the start-up voltage of the second PMOS transistor M2, the second PMOS transistor M2 mirrors the reference current to obtain a constant total current and outputs a constant total current.

[0051] The second NMOS transistor M4 is used to shunt the constant total current through a 1:N current mirror relationship, so that the charging current of the charging capacitor 12 is 1 / (N+1) of the constant total current.

[0052] It can be understood that the first NMOS transistor M3 and the second NMOS transistor M4 form a current mirror, and the ratio between the drain current of the first NMOS transistor M3 and the drain current of the second NMOS transistor M4 is equal to the ratio of the width to the length of the first NMOS transistor M3 and the second NMOS transistor M4.

[0053] For example, when the width-to-length ratio of the first NMOS transistor M3 to the second NMOS transistor M4 is 1:N, the ratio between the drain current of the first NMOS transistor M3 and the drain current of the second NMOS transistor M4 is also 1:N. Since the sum of the drain currents of the first NMOS transistor M3 and the second NMOS transistor M4 is a constant total current, the charging current of the charging capacitor 12 is 1 / (N+1) of the constant total current. Thus, the second NMOS transistor M4 can shunt the constant total current through a 1:N current mirror relationship, ensuring that the charging current of the charging capacitor 12 is 1 / (N+1) of the constant total current.

[0054] In this embodiment, since the drain of the first PMOS transistor M3 serves as the current reference node of the proportional current shunt control module 13, the second NMOS transistor M4 can sense the change in the charging current of the charging capacitor 12 in real time, and then dynamically adjust the charging current of the charging capacitor 12 according to the 1:N current mirror relationship, thereby enhancing the stability of the charging current of the charging capacitor 12.

[0055] The following example illustrates the situation with a constant total current of 1 microamp and a width-to-length ratio of 50 for the first NMOS transistor M3 and the second NMOS transistor M4. The second charging current of the charging capacitor 12 should be 0.02 microamp. Substituting I = 0.02 microamp, V = 1.8 volts, and t = 1 millisecond into formula (1), we can obtain that the capacitance of the charging capacitor 12 is approximately 10.9 picofarads.

[0056] As can be seen, with the upper limit of the power supply voltage and the charging time of the charging capacitor remaining unchanged, the capacitance value of the charging capacitor 12 provided in this application embodiment is one-fifty-first of the capacitance value of the capacitor in the related technology. That is, with the charging current equal to the constant total current of 1 microamp and the charging time remaining unchanged, the charging capacitor 12 provided in this application embodiment is equivalent to being magnified by 51 times, which significantly reduces the area and cost of the capacitor, thereby reducing the area and cost of the chip and electronic device.

[0057] Please refer to the function of Schmitt trigger U1. Figure 1 The functions of the output module will not be described in detail here.

[0058] For example, the toggle threshold of the Schmitt trigger U1 is determined based on the stable upper limit of the supply voltage. This ensures that the voltage of the charging capacitor reaches the toggle threshold only after the supply voltage has stabilized, and that the power-on reset circuit outputs a high-level release reset signal only after the supply voltage has stabilized.

[0059] Optionally, the power-on reset circuit 10 further includes a buffer, the input of which is connected to the output of the output module 14. This buffer buffers the reset signal and outputs the buffered reset signal to the load module. By setting a buffer after the output module 14 and buffering the reset signal, the driving capability of the reset signal can be improved, while also isolating the load module from interference to the power-on reset circuit 10, thus enhancing the stability of the power-on reset circuit 10.

[0060] For example, the buffer includes a first inverter and a second inverter. The input terminal of the first inverter is the input terminal of the buffer, and the output terminal of the first inverter is connected to the input terminal of the second inverter. The first inverter is used to buffer and invert the reset signal. The second inverter is used to buffer and invert the output signal of the first inverter to obtain a buffered reset signal.

[0061] The working principle of the power-on reset circuit 10 provided in the embodiments of this application is explained below. For example, see [reference needed]. Figure 3 At and before time t0, the supply voltage is zero, and the chip is not yet powered on. At this time, the power-on reset circuit 10 does not work, and the power-on reset circuit 10 does not output a reset signal.

[0062] At time t0, the supply voltage begins to rise from zero, and the power-on reset circuit 10 starts to operate due to the excitation of the supply voltage. The charging capacitor 12 in the power-on reset circuit 10 begins to charge. The voltage of the charging capacitor 12 begins to rise linearly. However, at this time, the voltage of the charging capacitor 12 has not yet reached the toggling threshold of the Schmitt trigger U1, and the Schmitt trigger U1 outputs a low-level reset signal. The load module performs a reset operation based on this low-level reset signal.

[0063] At time t1, the supply voltage reaches its upper limit of 1.8V. However, the charging capacitor 12 is still charging, and its voltage has not yet reached the toggling threshold of the Schmitt trigger U1. Therefore, the Schmitt trigger U1 maintains a low-level reset signal output.

[0064] At time t2, charging capacitor 12 completes charging, and its voltage reaches the toggling threshold of Schmitt trigger U1. Schmitt trigger U1 then flips, outputting a high-level reset signal. The load module cancels the reset operation based on this high-level reset signal.

[0065] It is understood that after the supply voltage reaches its upper limit, the charging capacitor 12 completes charging. That is, after the supply voltage stabilizes, the Schmitt trigger U1 outputs a high level. In this way, the power-on reset circuit 10 provided in this embodiment can instruct the load module to cancel the reset operation after the supply voltage stabilizes, thereby ensuring the correct timing and stable operation of the load module.

[0066] This application also provides a power-on reset control method. This power-on reset method is applied to... Figure 1 or Figure 2 The power-on reset circuit 10 is shown in the image. (See also...) Figure 4 The power-on reset method includes the following steps S41 to S43.

[0067] Step S41: The power supply voltage is received and a constant total current is output through the current source in the power-on reset circuit.

[0068] For example, step S41 includes steps S411 to S412.

[0069] Step S411: Output a reference current through the reference current source in the current source.

[0070] Step S412: Obtain a constant total current based on the reference current through the PMOS current mirror in the current source.

[0071] Optionally, step S412 includes: receiving a reference current through a first PMOS transistor in a PMOS current mirror; mirroring the reference current through a second PMOS transistor to obtain a constant total current; and outputting a constant total current.

[0072] In some embodiments, when the supply voltage received by the second PMOS transistor is greater than the startup voltage, the reference current is mirrored through the second PMOS transistor to obtain a constant total current, and a constant total current is output.

[0073] Step S42: The proportional current shunt control module in the power-on reset circuit shunts the constant total current based on a 1:N current mirror relationship, so that the charging current of the charging capacitor is 1 / (N+1) of the constant total current.

[0074] For example, step S42 includes: shunting the constant total current using the second NMOS transistor based on the width-to-length ratio of the first NMOS transistor to the second NMOS transistor, which is 1:N.

[0075] Step S43: The output module in the power-on reset circuit outputs reset signals of different levels according to the voltage across the charging capacitor.

[0076] Specifically, when the voltage of the charging capacitor is lower than the flip threshold, a low-level active reset signal is output through the output module; when the voltage of the charging capacitor is higher than the flip threshold, a high-level release reset signal is output through the output module.

[0077] In some embodiments, the power-on reset control method further includes: adjusting the width-to-length ratio (1:N) of the first NMOS transistor and the second NMOS transistor in the proportional shunt control module to determine the equivalent amplification factor of the charging capacitor, so as to adapt to different power-on reset delay requirements. The equivalent amplification factor of the charging capacitor is N+1. By adjusting N, the charging time of the charging capacitor can be adjusted, thereby adapting to different power-on reset delay requirements.

[0078] For the relevant descriptions of each step in the above power-on reset control method, please refer to the relevant descriptions of the power-on reset circuit 10 provided in the aforementioned embodiments of this application, which will not be repeated here.

[0079] This application also provides a display driver chip. The chip includes any of the power-on reset circuits 10 provided in the foregoing embodiments of this application. Exemplarily, the display driver chip is at least one of a power management integrated circuit (PMIC), a display driver integrated circuit (DDI), a large touch and display driver IC (LTDDI), and a small-size display power management chip among low-dropout regulators (LDOs).

[0080] This application also provides an electronic device. This electronic device includes any of the display driver chips provided in the foregoing embodiments of this application.

[0081] It should be noted that the terms "first," "second," etc. (if present) in the specification and claims of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.

[0082] It should be understood that the objects used in this way can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in a sequence other than those illustrated or described herein. The embodiments described in the above exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.

[0083] Unless otherwise expressly specified and limited, the term "connection" in the embodiments of this application should be interpreted broadly. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium; it can be a connection within two components. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0084] Furthermore, all signals involved in this application have been authorized by the user or by all parties in full, and the collection, use, and processing of these signals must comply with the relevant laws, regulations, and standards of the relevant countries and regions. For example, the signals involved in this application were all obtained under full authorization.

[0085] As can be understood, "multiple" in this article refers to two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone. The character " / " generally indicates that the preceding and following related objects have an "or" relationship.

[0086] The above description is merely an exemplary embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the principles of this application should be included within the protection scope of this application.

Claims

1. A power-on reset circuit, characterized in that, The power-on reset circuit includes a current source, a charging capacitor, a proportional shunt control module, and an output module. The current source is used to receive the supply voltage and output a constant total current. The current output terminal of the current source, the first terminal of the charging capacitor, and the current control node of the proportional shunt control module are interconnected. The second terminal of the charging capacitor is interconnected with the current reference node of the proportional shunt control module. The proportional current shunt control module includes a first NMOS transistor and a second NMOS transistor with a width-to-length ratio of 1:N. The gates of the first NMOS transistor and the second NMOS transistor are interconnected, and their sources are grounded together. The drain of the first NMOS transistor serves as the current reference node, and the drain of the second NMOS transistor serves as the current control node. The proportional current shunting control module is used to shun the constant total current through a 1:N current mirror relationship, so that the charging current of the charging capacitor is 1 / (N+1) of the constant total current. The input terminal of the output module is connected to the first terminal of the charging capacitor, and is used to output a reset signal of different levels according to the voltage across the two terminals of the charging capacitor. Specifically, when the voltage of the charging capacitor is lower than the flip threshold, a low-level active reset signal is output, and when the voltage of the charging capacitor is higher than the flip threshold, a high-level release reset signal is output.

2. The power-on reset circuit according to claim 1, characterized in that, The output module includes a Schmitt trigger; The toggling threshold of the Schmitt trigger is determined based on the stable upper limit of the supply voltage.

3. The power-on reset circuit according to claim 1, characterized in that, The current source includes a reference current source and a PMOS current mirror; The PMOS current mirror includes a first PMOS transistor and a second PMOS transistor with gate interconnection; the first PMOS transistor is used to receive the reference current output by the reference current source. The second PMOS transistor is used to mirror the reference current to obtain the constant total current and output the constant total current.

4. The power-on reset circuit according to any one of claims 1 to 3, characterized in that, The power-on reset circuit also includes a buffer, the input of which is connected to the output of the output module; The buffer is used to buffer the reset signal and output the buffered reset signal to the load module.

5. The power-on reset circuit according to claim 4, characterized in that, The buffer includes a first inverter and a second inverter, the input terminal of the first inverter is the input terminal of the buffer, and the output terminal of the first inverter is connected to the input terminal of the second inverter; The first inverter is used to buffer and invert the reset signal; The second inverter is used to buffer and invert the output signal of the first inverter to obtain a buffered reset signal.

6. A display driver chip, characterized in that, The chip includes a power-on reset circuit as described in any one of claims 1 to 5.

7. An electronic device, characterized in that, The electronic device includes the display driver chip as described in claim 6.

8. A power-on reset control method, characterized in that, The method, applied to the power-on reset circuit as described in any one of claims 1 to 5, comprises: The power supply voltage is received by the current source in the power-on reset circuit, and a constant total current is output. The proportional current shunt control module in the power-on reset circuit shunts the constant total current based on a 1:N current mirror relationship, so that the charging current of the charging capacitor is 1 / (N+1) of the constant total current. The output module in the power-on reset circuit outputs reset signals of different levels according to the voltage across the charging capacitor. When the voltage of the charging capacitor is lower than the flip threshold, a low-level active reset signal is output, and when the voltage of the charging capacitor is higher than the flip threshold, a high-level release reset signal is output.

9. The power-on reset control method according to claim 8, characterized in that, The method further includes: The width-to-length ratio of the first NMOS transistor and the second NMOS transistor in the proportional current shunt control module is adjusted to 1:N to determine the equivalent amplification factor of the charging capacitor, so as to adapt to different power-on reset delay requirements.

10. The power-on reset control method according to claim 8 or 9, characterized in that, The current source includes a reference current source and a PMOS current mirror, wherein the PMOS current mirror includes a first PMOS transistor and a second PMOS transistor with interconnected gates; the step of receiving the supply voltage and outputting a constant total current through the current source in the power-on reset circuit includes: The reference current output from the reference current source is received through the first PMOS transistor; The constant total current is obtained by mirroring the reference current through the second PMOS transistor, and then output as a constant total current.

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